LM62435APPQRJRRQ1_技术文档

LM62435-Q1

ZHCSLD0B –MAY 2020 –REVISED JUNE 2021

LM62435-Q1 汽车类3V 至36V、3.5A 低EMI 同步降压转换器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准

LM62435-Q1 是一款汽车专用的高性能直流/直流同步

降压转换器。该器件具有集成式高侧和低侧

MOSFET，能够在 3.0V 至 36V 的宽输入电压范围内

提供高达 3.5A 的输出电流；可耐受 42V 电压，支持

400ms 时长的负载突降。LM62435-Q1 可对压降进行

软恢复，因此无需对输出进行过冲。

– 温度等级1：–40°C 至+150°C，T_J

• 提供功能安全

– 可帮助进行功能安全系统设计的文档

• 针对超低EMI 要求进行了优化

– HotRod^™封装和并行输入路径可以尽可能减少

开关节点振铃

– 展频可降低峰值发射

LM62435-Q1 专门设计用于降低 EMI。该器件具有假

随机展频、可调节 SW 节点上升时间和低 EMI，并采

用具有低开关节点振铃和易于使用、优化型引脚排列的

VQFN-HR 封装。开关频率可在 200kHz 至 2.2MHz 范

围内同步，从而避开噪声敏感频段。另外，可以选择频

率，从而在低工作频率下提高效率，或在高工作频率下

缩小解决方案尺寸。

– 可调节SW 节点上升时间

– 轻负载下可通过引脚可选FPWM 模式提供恒定

频率

• 专为汽车应用而设计

– 支持42V 的汽车负载突降

– ±1% 的总输出稳压精度

自动模式可在轻负载运行时进行频率折返，实现仅

7µA（典型值）的空载电流消耗和高轻负载效率。

PWM 和 PFM 模式之间无缝转换，以及极低的

MOSFET 导通电阻和外部偏置输入，均确保在整个负

载范围内实现卓越的效率。

– V_OUT可在1V 至95% 的V_IN之间调节，出厂时

可选5V 和3.3V 固定输出电压

• 可在所有负载下进行高效电源转换

– 在13.5V_IN、3.3V_OUT下具有7µA 的无负载电流

– 在1mA、13.5V_IN、5V_OUT下PFM 效率为83%

– 具有用于提升效率的外部偏置选项

• 适用于可扩展电源

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

– 与以下器件引脚兼容：

LM62435-Q1

VQFN-HR (14)

4.00mm × 3.50mm

• LM62440-Q1（36V、4A、固定f_SW

• LM61460-Q1（36V、6A、可调节f_SW

）

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 汽车信息娱乐系统与仪表组：音响主机、媒体集线

器、USB 充电器、显示屏

• 汽车ADAS 和车身电子装置

100

95

90

85

80

75

70

V_IN= 8 V

V_IN= 13.5 V

V_IN= 24 V

65

60

YELLOW: PEAK

BLUE: AVERAGE

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2 3 45

SNVS

效率：V_OUT= 5V，F_SW= 2200kHz

传导EMI：V_OUT=5V，f_SW=2100kHz

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBP3

LM62435-Q1

ZHCSLD0B –MAY 2020 –REVISED JUNE 2021

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Table of Contents

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................25

9 Application and Implementation..................................31

9.1 Application Information............................................. 31

9.2 Typical Application.................................................... 31

10 Power Supply Recommendations..............................43

11 Layout...........................................................................44

11.1 Layout Guidelines................................................... 44

11.2 Layout Example...................................................... 46

12 Device and Documentation Support..........................47

12.1 Documentation Support.......................................... 47

12.2 接收文档更新通知................................................... 47

12.3 支持资源..................................................................47

12.4 Trademarks.............................................................47

12.5 静电放电警告.......................................................... 47

12.6 术语表..................................................................... 47

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................6

7.6 计时特性......................................................................9

7.7 Systems Characteristics .......................................... 10

7.8 Typical Characteristics.............................................. 11

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................14

Information.................................................................... 47

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (April 2021) to Revision B (June 2021)

Page

• Added EVM thermal resistance.......................................................................................................................... 6

Changes from Revision * (May 2020) to Revision A (April 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1

• Changed R_θJAfrom 59 to 58.7...........................................................................................................................6

• Changed _θJC(top)from 19 to 26.1....................................................................................................................... 6

2

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5 Device Comparison Table

DEVICE

ORDERABLE PART

NUMBER

REFERENCE PART

NUMBER

LIGHT LOAD

MODE

SPREAD

SPECTRUM

OUTPUT

VOLTAGE

SWITCHING

FREQUENCY

LM62435APPQRJRRQ1

LM62435BPPQRJRRQ1

LM62435CPPQRJRRQ1

LM62435APP-Q1

LM62435BPP-Q1

LM62435CPP-Q1

Pin Selectable Pin Selectable

Adjustable

3.3 V

2.1 MHz

LM62435-Q1

5 V

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6 Pin Configuration and Functions

PGND2

BIAS

1

11

10

VCC

AGND

FB

2

3

4

SW

5

9

PGOOD

PGND1

图6-1. RJR Package 14-Pin VQFN-HR Top View

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Input to internal LDO. Connect to output voltage point to improve efficiency. Connect an optional

high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity. If output

voltage is above 12 V, connect this pin to ground.

BIAS

1

P

Internal LDO output. Used as supply to internal control circuits. Do not connect to any external

loads. Connect a high-quality 1-µF capacitor from this pin to AGND.

VCC

2

3

O

G

Analog ground for internal circuitry. Feedback and VCC are measured with respect to this pin.

Must connect AGND to both PGND1 and PGND2 on PCB.

AGND

Output voltage feedback input to the internal control loop. Connect to output voltage sense point

for fixed 3.3 V or 5 V output voltage factory options. Connect to feedback divider tap point for

adjustable output voltage. Do not float or connect to ground.

FB

4

5

I

Open-drain power-good status output. Pull this pin up to a suitable voltage supply through a

current limiting resistor. High = power OK, low = fault. PGOOD output goes low when EN = low,

V_IN> 1 V.

PGOOD

O

This pin controls the mode of operation of the LM62435-Q1. Modes include Auto Mode

(automatic PFM / PWM operation), FPWM, and synchronization to an external clock. When

synchronized, the clock triggers on rising edge of an external clock. Also, spread spectrum

operation is controlled by this pin. See 节8.3.2. Do not float this pin.

MODE/SYNC

6

I

Precision enable input. High = on, Low = off. Can be connected to VIN. Precision enable allows

the pin to be used as an adjustable UVLO. See 节9.

EN

7

8

I

Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin

to PGND1. Low impedance connection must be provided to VIN2.

VIN1

P

Power ground to internal low-side MOSFET. Connect to system ground. Low impedance

connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors

from this pin to VIN1.

PGND1

SW

9

G

O

G

10

11

Switch node of the converter. Connect to output inductor.

Power ground to internal low-side MOSFET. Connect to system ground. Low impedance

connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors

from this pin to VIN2.

PGND2

Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin

to PGND2. Low impedance connection must be provided to VIN1.

VIN2

12

13

14

P

Connect to CBOOT through a resistor. This resistance must be between 0 Ωand open and

determines SW node rise time.

RBOOT

CBOOT

I/O

High-side driver upper supply rail. Connect a 100-nF capacitor between SW pin and CBOOT. An

internal diode connects to VCC and allows CBOOT to charge while SW node is low.

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of -40℃to +150℃(unless otherwise noted)⁽¹⁾

PARAMETER

VIN1, VIN2 to AGND, PGND

RBOOT to SW

MIN

-0.3

MAX

42

UNIT

V

5.5

16

V

CBOOT to SW

V

BIAS to AGND, PGND

EN to AGND, PGND

SYNC/MODE to AGND, PGND

FB to AGND, PGND

PGOOD to AGND, PGND

PGND to AGND⁽³⁾

V

Input Voltage

42

V

-0.3 lower of 42 & V_IN+5

V

-0.3

0

16

20

V

-1

2

V

SW to AGND, PGND⁽²⁾

VCC to AGND, PGND

PGOOD sink current⁽⁴⁾

Junction temperature

Storage temperature

-0.3

V_IN+0.3

5.5

V

Output Voltage

V

Current

T_J

10

mA

°C

-40

150

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) A voltage of 2 V below GND and 2 V above V_INcan appear on this pin for ≤200 ns with a duty cycle of ≤0.01%.

(3) This specification applies to voltage durations of 100 ns or less. The maximum D.C. voltage should not exceed ± 0.3 V.

(4) Do not exceed pin’s voltage rating.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Device HBM Classification Level 2

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per AEC Q100-011

Device CDM Classification Level C5

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) ⁽¹⁾

MIN

NOM

MAX

UNIT

V

Input voltage

Output voltage

Frequency

Input voltage range after start-up

Output voltage range for adjustable version ⁽²⁾

Free running frequency

3

36

1

0.95 * V_IN

V

2.1

MHz

kHz

A

Sync frequency

Load current

Temperature

Synchronization frequency range

Output DC current range ⁽³⁾

200

0

2200

3.5

Operating junction temperature T_Jrange

150

°C

–40

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics table.

(2) Under no conditions should the output voltage be allowed to fall below zero volts.

(3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See

Application section for details.

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7.4 Thermal Information

The value of R_θJAgiven in this table is only valid for comparison with other packages and cannot be used for design

purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do

not represent the performance obtained in an actual application. For example, with a 4-layer PCB, a R_ΘJA= 25℃/W can be

achieved. For design information see Maximum Ambient Temperature versus Output Current.

LM62435-Q1

THERMAL METRIC ^{(1) (2)}

RJR (QFN)

UNIT

14 PINS

25

R_θJA

Junction-to-ambient thermal resistance (LM61460-Q1 EVM)

Junction-to-ambient thermal resistance (JESD 51-7)

Junction-to-case (top) thermal resistance

°C/W

R_θJA

58.7

26.1

19.2

1.4

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

19

Ψ_JB

R_θJC(bot)

-

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The value of R_θJAgiven in this table is only valid for comparison with other packages and cannot be used for design purposes. These

values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the

performance obtained in an actual application.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V. VIN1 shorted to VIN2 = V_IN. V_OUTis converter output voltage.

UNI

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

SUPPLY VOLTAGE AND CURRENT

Needed to start up

3.95

3.0

V_{IN_OPERATE}

Input operating voltage⁽²⁾

V

Once operating

V_{IN_OPERATE_H}

I_{Q_VIN}

Hysteresis⁽²⁾

1

9

Operating quiescent current (not

switching)⁽³⁾

V_FB= +5%, V_BIAS= 5 V

18 µA

Shutdown quiescent current;

measured at VIN pin

I_SD

0.6

6

µA

EN = 0 V, T_J= 25℃

ENABLE

V_EN

Enable input threshold voltage -

rising

1.263

V

%

Enable input threshold voltage -

rising deviation from typical

V_EN-ACC

-5

5

Enable threshold hysteresis as

percentage of V_EN(TYP)

V_EN-HYST

24

28

32

V_EN-WAKE

I_EN

Enable wake-up threshold

Enable pin input current

0.4

V

V_IN= EN = 13.5 V

2.3

nA

LDO - VCC

V_BIAS> 3.4 V, CCM Operation⁽²⁾

V_BIAS= 3.1 V, Non-switching

3.3

3.1

V_CC

Internal V_CCvoltage

V

Internal V_CCinput under voltage

lock-out

V_{CC_UVLO}

V_CCrising under voltage threshold

Hysteresis below V_{CC_UVLO}

3.6

1.1

V

Internal V_CCinput under voltage

lock-out

V_{CC_UVLO_HYST}

6

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Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V. VIN1 shorted to VIN2 = V_IN. V_OUTis converter output voltage.

UNI

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

FEEDBACK

V_{FB_acc}

Initial reference voltage accuracy

V_IN= 3.3 V to 36 V, FPWM Mode

V_IN= 13.5 V, FPWM Mode

-1

1

%

V

Reference voltage accuracy for

Fixed 3.3-V V_OUTtrim option

V_{OUT_acc}

3.2587

3.3

5

3.3413

Reference voltage accuracy for

Fixed 5-V V_OUTtrim option

V_IN= 13.5 V, FPWM Mode

4.9375

5.0625

V

5-V Option

1.85

2.1

10

R_FB

Resistance from FB to AGND

Input current from FB to AGND

MΩ

3.3-V Option

I_FB

Adjustable versions only, FB = 1 V

nA

OSCILLATOR

Minimum adjustable frequency by

SYNC

0.18

0.36

1.98

0.2

0.4

2.2

0.22 MHz

0.44 MHz

2.42 MHz

f_ADJ

Adjustable frequency by SYNC

Maximum adjustable frequency

by SYNC

V_IN= 13.5 V, Center frequency with

or without spread spectrum, PWM

operation

f_SW

Switching frequency

1.9

2.1

2

2.3 MHz

Frequency span of spread spectrum

operation - largest deviation from

center frequency

f_{S SS}

Spread spectrum active

%

Spread spectrum pattern

frequency⁽²⁾

Spread spectrum active, f_SW= 2.1

MHz

f_PSS

1.5 Hz

MODE/SYNC PIN

V_IN= 13.5 V, V_SYNC/MODE= 3.3 V

V_IN= 13.5 V, V_SYNC/MODE= 5.5 V

1

MODE/SYNC pin leakage current

after startup

I_MODE/SYNC

nA

V_{MODE_L}

V_{MODE_H}

MODE/SYNC input voltage low

MODE/SYNC input voltage high

0.4

1

V

1.6

MODE/SYNC input voltage

hysteresis

V_{SYNCD_HYST}

0.155

V

Spread spectrum on if MODE/SYNC

voltage is below this voltage and

above V_{MODE_H}

V_{MODE_H2}

Level dependent operation

2.5

30

Spread spectrum off if MODE/SYNC

is above this voltage

V_{MODE_H3}

R_{MODE_H}

R_{MODE_L}

Level dependent operation

4.9

6

V

MODE/SYNC attached resistance

indicating Spread Spectrum off

kΩ

MODE/SYNC attached resistance

indicating Spread Spectrum on

MOSFETS

R_{DS(ON)_HS}

R_{DS(ON)_LS}

Power switch on-resistance

High side MOSFET R_DS(ON)

Low side MOSFET R_DS(ON)

41

21

82

45

mΩ

Voltage on CBOOT pin compared to

SW which will turn off high-side

switch

V_{BOOT_UVLO}

2.1

V

CURRENT LIMITS

I_L-HS

I_L-LS

High side switch current limit⁽¹⁾

Low side switch current limit

Duty cycle approaches 0%

6

7

8.1

5.4

A

3.7

4.8

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Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V. VIN1 shorted to VIN2 = V_IN. V_OUTis converter output voltage.

UNI

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Zero-cross current limit. Positive

current direction is out of SW pin

I_L-ZC

Auto Mode, static measurement

0.25

A

Negative current limit FPWM and

SYNC Modes. Positive current

direction is out of SW pin.

I_L-NEG

FPWM operation

-2

Minimum peak command in Auto

Mode / device current rating

I_{PK_MIN_0}

I_{PK_MIN_100}

V_HICCUP

Pulse duration < 100 ns

Pulse duration > 1 µs

Not during soft start

25

12.5

40

%

Minimum peak command in Auto

Mode / device current rating

Ratio of FB voltage to in-regulation

FB voltage

POWER GOOD

PGD_OV

PGOOD upper threshold - rising

PGOOD lower threshold - falling

% of V_OUTsetting

105

92

107

94

110

%

PGD_{U V}

96.5

PGOOD upper threshold (rising &

falling)

PGD_HYST

% of V_OUTsetting

1.3

%

V

Input voltage for proper

PGOOD function

V_{IN(PGD_VALID)}

1.0

46 µA pullup to PGOOD pin, V_IN

1.0 V, EN = 0 V

=

0.4

Low level PGOOD function output

voltage

1 mA pullup to PGOOD pin, V_IN

13.5 V, EN = 0 V

=

V_PGD(LOW)

V

2 mA pullup to PGOOD pin, V_IN

13.5 V, EN = 3.3 V

=

1 mA pullup to PGOOD pin, EN = 0

V

17

40

90

Ω

R_PGD

R_DS(ON)of PGOOD output

1 mA pullup to PGOOD, EN = 3.3 V

Pull down current at the SW node

under over voltage condition

I_OV

0.5

mA

THERMAL SHUTDOWN

T_{SD_R}

Thermal shutdown rising threshold⁽²⁾

Thermal shutdown hysteresis⁽²⁾

158

168

10

180

℃

T_{SD_HYST}

(1) High side current limit is function of duty factor. High side current limit is highest at small duty factor and less at higher duty factors.

(2) Parameter specified by design, statistical analysis and production testing of correlated parameters.

(3) I_{Q_VIN}= I_Q+ I_BIAS× (V_OUT/ V_IN)

8

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7.6 计时特性

限制值适用于推荐的-40°C 至+150°C 工作结温范围，除非另有说明。最小和最大限制经过测试、设计和统计相关性分析确

定。典型值表示T_J= 25°C 条件下最有可能达到的参数标准，仅供参考。除非另有说明，以下条件适用：V_IN= 13.5V。

参数

测试条件

最小值

典型值

最大值单位

开关节点

V_IN= 20V，I_OUT= 2A，RBOOT 短接

至CBOOT

t_{ON_MIN}

55

9

70 ns

μs

最小高侧开关导通时间

最大高侧开关导通时间

最小低侧开关导通时间

t_{ON_MAX}

t_{OFF_MIN}

V_IN= 4.0V，I_OUT= 1A，RBOOT 短

接至CBOOT

65

85 ns

从设定点的第一个SW 脉冲到90%

Vref 的时间。

t_SS

2

3

4

ms

V_IN≥4.2V

从第一个SW 脉冲到FPWM 锁定释

放的时间（如果输出未处于稳压状

态）

t_SS2

4.5

6.5

40

8.5 ms

ms

t_W

短路等待时间（“断续”时间）

使能

C_VCC= 1µF 时从EN 高电平到第一个

SW 脉冲的时间（如果输出从0V 开

始）

导通延迟⁽¹⁾

t_EN

0.7

ms

t_B

4

9

µs

上升沿或下降沿后EN 消隐

低电平为0.6V。

SYNC

t_{PULSE_H}

t_{PULSE_L}

100

ns

需要识别为脉冲的高电平持续时间

需要识别为脉冲的低电平持续时间

在一个电平上指示FPWM 或自动模

式所需的时间

t_MODE

t_SYNC

16.5

µs

有效同步信号中的高电平或低电平信

号持续时间

8

周期

[cycl

e]

时钟在同步周期中锁定到有效同步信

号所需的时间⁽¹⁾

C_LOCK

2048

25

进入自动模式时的SYNC/MODE 引

脚电阻测试持续时间

t_MEAS

µs

电平相关的SYNC/MODE 引脚运行

电源正常

t_PGDFLT(rise)

1.5

2

2.5 ms

µs

PGOOD 高电平信号的延迟时间

t_PGDFLT(fall)

24

PGOOD 功能的干扰滤波器时间常数

(1) 使用相关参数的设计、统计分析和生产测试指定参数；未经量产测试。

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7.7 Systems Characteristics

The following values are specified by design provided that the component values in the typical application circuit are used.

Limits apply over the junction temperature range of -40°C to +150°C, unless otherwise noted. Minimum and Maximum limits

are derived using test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C,

and are provided for reference purposes only. Unless otherwise stated the following conditions apply: V_IN= 13.5 V. VIN1

shorted to VIN2 = V_IN. V_OUTis output setting. These parameters are not tested in production.

UNI

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

EFFICIENCY

V_OUT= 5 V, I_OUT= 3.5 A, R_BOOT= 0

Ω

93

73

95

76

Typical 2.1 MHz efficiency

Typical 400 kHz efficiency

%

ƞ_{5V_2p1MHz}

V_OUT= 5 V, I_OUT= 100 µA, R_BOOT= 0

Ω

V_OUT= 5 V, I_OUT= 3.5 A, R_BOOT= 0

Ω

%

ƞ_{5V_400kHz}

V_OUT= 5 V, I_OUT= 100 µA, R_BOOT= 0

Ω

RANGE OF OPERATION

V_INfor full functionality at reduced

V_{VIN_MIN1}

V_OUTset to 3.3 V

3.0

V

load, after start-up.

V_INfor full functionality at 100% of

maximum rated load, after start-up.

V_{VIN_MIN2}

3.95

V_OUT= 3.3 V, I_OUT= 0 A, Auto mode,

R_FBT=1 MΩ

7

I_Q-VIN

Operating quiescent current⁽¹⁾

µA

V_OUT= 5 V, I_OUT= 0 A, Auto mode,

R_FBT=1 MΩ

10

5

V_IN= 5.8 V to 36 V, I_OUT= 3.5A

4.9

5.1

5.125

3.35

V

V_OUT5

Output voltage for 5V factory option

Auto mode, V_IN= 5.5V to 36 V,

I_OUT= 100 µA to 100 mA

5.05

3.3

3.33

87

V_IN= 3.9 V to 36 V, I_OUT= 3.5 A

3.24

Output voltage for 3.3V factory

option

V_OUT3

V_IN= 3.9 V to 36 V, I_OUT= 100 µA to

100 mA

3.38

f_SW=1.85 MHz

%

D_MAX

Maximum switch duty cycle

While in frequency fold back

98

RBOOT

R_BOOT= 0 Ω, I_OUT= 2 A (10% to

2.15

2.7

ns

80%)

t_RISE

SW node rise time

R_BOOT= 100 Ω, I_OUT= 2 A (10% to

80%)

(1) See detailed description for the meaning of this specification and how it can be calculated.

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7.8 Typical Characteristics

Unless otherwise specified, V_IN= 13.5 V and f_SW= kHz.

4000

3500

3000

2500

2000

1500

1000

500

16

14

12

10

8

-40C

25C

150C

6

0

4

0

5

10

15

20

25

Input Voltage (V)

30

35

40

-50

-25

0

25

50

75

Temperature (°C)

100

125

150

SNVS

V_EN= 0 V

V_BIAS= 5 V

图7-2. Shutdown Supply Current

图7-1. Non-Switching Input Supply Current

1.01

9

8

7

6

5

4

1.006

1.002

0.998

0.994

0.99

HS

LS

3

-50

-25

0

25

50

75

Temperature (°C)

100

125

150

-25

0

25

50

75

Temperature (°C)

100

125

150

snvs

SNVS

图7-4. LM62435-Q1 High-side and Low-side

图7-3. Feedback Voltage

Current Limits

3500

3250

3000

2750

2500

2250

2000

1750

1500

1250

1000

750

70

60

50

40

30

FREQ = 200 kHz

FREQ = 400 kHz

FREQ = 2.2 MHz

500

20

HS Switch

LS Switch

250

0

-50

10

-50

-25

0

25

50

75

Temperature (°C)

100

125

150

-25

0

25

50

75

Temperature (°C)

100

125

150

SNVS

图7-5. Switching Frequency Set by SYNC

图7-6. High-side and Low-side Switches R_{DS_ON}

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1.4

1.3

1.2

1.1

1

115

110

105

100

95

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

90

OV Tripping

VEN Rising

VEN Falling

VEN_WAKE Rising

VEN_WAKE Falling

OV Recovery

UV Recovery

UV Tripping

85

80

-50

-25

0

25

50

75

Temperature (°C)

100

125

150

-50

-25

0

25

50

75

Temperature (°C)

100

125

150

SNVS

snvs

图7-8. PGOOD Thresholds

图7-7. Enable Thresholds

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8 Detailed Description

8.1 Overview

The LM62435-Q1 is a wide input, synchronous peak-current mode buck regulator designed for a wide variety of

automotive applications. The regulator can operate over a wide range of switching frequencies including sub-AM

band at 400 kHz and above the AM band at 2.1 MHz. This device operates over a wide range of conversion

ratios. If minimum on-time or minimum off-time does not support the desired conversion ratio, the frequency is

reduced automatically, allowing output voltage regulation to be maintained during input voltage transients with a

high operating-frequency setting.

The LM62435-Q1 has been designed for low EMI and is optimized for both above and below AM band

operation:

• Meets CISPR25 class 5 standard

• Hotrod^™package minimizes switch node ringing

• Parallel input path minimizes parasitic inductance

• Spread spectrum reduces peak emissions

• Adjustable SW node rise time

These features together can eliminate shielding and other expensive EMI mitigation measures.

This device is designed to minimize end-product cost and size while operating in demanding automotive

environments. Operation at 2.1 MHz allows for the use of small passive components. State-of-the-art current

limit function allows the use of the inductors that are optimized for 3.5-A regulators. In addition, this device has

low unloaded current consumption, which is desirable for off-battery, always on applications. The low shutdown

current and high maximum operating voltage also allow for the elimination of an external load switch and input

transient protection. To further reduce system cost, an advanced PGOOD output is provided, which can often

eliminate the use of an external reset or supervisory device.

The LM62435-Q1 devices are AEC-Q100-qualified and have electrical characteristics ensured up to a maximum

junction temperature of 150°C.

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8.2 Functional Block Diagram

VCC

Clock

VCC

MODE/

SYNC

Detect

MODE

/SYNC

Sync

Oscillator

BIAS

VCC UVLO

OTP

Slope

compensation

LDO

VIN

Over

Temperature

detect

FPWM/Auto

Frequency Foldback

RBOOT

CBOOT

VIN1

System enable

Enable

EN

HS Current

sense

Error

amplifier

+

œ

VIN

VIN2

Comp Node

œ

Clock

+

High and

low limiting

circuit

+

Output

low

HS

Current

Limit

œ

SW

System enable

OTP

FB

Drivers and

logic

Soft start

circuit and

bandgap

Hiccup active

VCC UVLO

LS

Current

Limit

œ

AGND

+

Voltage Reference

œ

PGND1

PGND2

+

LS

Current

Min

FPWM/Auto

Vout UV/OV

PGOOD

Logic with

filter and

LS Current

sense

release delay

System enable

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8.3 Feature Description

8.3.1 EN Uses for Enable and V_INUVLO

Start-up and shutdown are controlled by the EN input and V_INUVLO. For the device to remain in shutdown

mode, apply a voltage below V_{EN_WAKE}(0.4 V) to the EN pin. In shutdown mode, the quiescent current drops to

0.6 µA (typical). At a voltage above V_{EN_WAKE}and below V_EN, VCC is active and the SW node is inactive. Once

the EN voltage is above V_EN, the chip begins to switch normally, provided the input voltage is above 3 V.

The EN pin cannot be left floating. The simplest way to enable the operation is to connect the EN pin to V_IN,

allowing self-start-up of the LM62435-Q1 when V_INdrives the internal VCC above its UVLO level. However,

many applications benefit from the employment of an enable divider network as shown in 图 8-1, which

establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, preventing re-

triggering of the device when used with long input cables, or reducing the occurrence of deep discharge of a

battery power source. Note that the precision enable threshold, V_EN, has a 5% tolerance. Hysteresis must be

enough to prevent re-triggering. External logic output of another IC can also be used to drive the EN pin,

allowing system power sequencing.

V_IN

R_ENT

EN

R_ENB

AGND

图8-1. VIN UVLO Using the EN pin

Resistor values can be calculated using 方程式1. See 节9.2.2.11 for additional information.

V_EN

R

=

‡

R_ENB

ENT

V_ONÅ V_EN

(1)

where

• V_ONis the desired typical start-up input voltage for the circuit being designed

8.3.2 MODE/SYNC Pin Operation

The LM62435-Q1 features selectable operating modes through the MODE/SYNC input pin. The LM62435-Q1

can operate in one of three selectable modes:

• Auto Mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation

prevents reverse current through the inductor. See 节8.4.3.2 for more details.

• FPWM Mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the

inductor. This allows operation at full frequency even without load current. See 节8.4.3.3 for more details.

• SYNC Mode: The LM62435-Q1 clock locks to an external signal applied to the MODE/SYNC pin. As long as

output voltage can be regulated at full frequency and is not limited by minimum off-time or minimum on-time,

clock frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the

LM62435-Q1 is in SYNC mode, it operates as though in FPWM mode: diode emulation is disabled allowing

the frequency applied to the MODE/SYNC pin to be matched without a load.

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In addition, the MODE/SYNC pin can be used to activate or deactivate the spread spectrum feature of the

LM624-Q1. The MODE/SYNC pin can be configured in two ways: level dependent MODE/SYNC control (see 节

8.3.2.1) or pulse dependent MODE/SYNC pin control (see 节8.3.2.2).

8.3.2.1 Level-Dependent MODE/SYNC Pin Control

If only a single mode is used, the part can be configured using level-dependent control. Note that the LMQ6235-

Q1 cannot be synchronized to an external clock signal in level-dependent mode. 表 8-1 shows a summary of

level-dependent mode selection settings. The level-dependent mode selection setting registers after t_MODE. The

level-dependent mode summary is also depicted in 图8-2.

表8-1. Level-Dependent Mode Selection Settings

MODE/SYNC INPUT

GND

MODE

Auto Mode with Spread Spectrum

FPWM Mode with Spread Spectrum

FPWM Mode without Spread Spectrum

VCC OR > V_{MODE_H}AND < V_{MODE_H2}

VIN OR > V_{MODE_H3}

Above V_{MODE_H3}, operational mode is

FPWM with no spread spectrum

V_{MODE_H3}

Above V_{MODE_H}, FPWM

Mode operation

V_{MODE_H2}

Between V_{MODE_H}and V_{MODE_H2}

,

operational mode is FPWM with

spread spectrum

V_{MODE_H}

V_{MODE_L}/V_{MODE_H}controlled transitions

have V_{SYNCD_HYST}hysteresis

V_{MODE_L}

GND

Below V_{MODE_L}, Auto

Mode operation

图8-2. Level-Dependent Mode Selection Settings

Note that during dropout operation, the input voltage is close to VCC. Since this condition is typically seen while

operating in dropout, frequency is typically folded back and spread spectrum is deactivated. When VIN increases

and the device is no longer in frequency foldback, spread spectrum is reactivated. When the input voltage is

between 3 V to 3.7 V and the LMQ6235-Q1 is not in dropout operation, the spread spectrum operation is not

guaranteed.

One purpose of level-dependent MODE/SYNC pin control is to dynamically change between FPWM and Auto

Mode. To ensure the resistance from MODE/SYNC to ground is < R_{SYNC_L}, it is recommended to use 6 kΩ to

ground. The MODE/SYNC pin can then be toggled between FPWM and Auto Mode as shown in 表8-1.

If Auto Mode without spread spectrum operation is desired, tie the MODE/SYNC pin to ground through a 100-kΩ

resistor. Auto Mode without spread spectrum is a fixed option, and the mode cannot be changed dynamically.

8.3.2.2 Pulse-Dependent MODE/SYNC Pin Control

Most systems that require more than a single mode of operation from the LM62345-Q1 are controlled by digital

circuitry such as a microprocessor. These systems can generate dynamic signals easily but have difficulty

generating multi-level signals. Pulse-Dependent MODE/SYNC pin control is useful with these systems.

To initiate Pulse-Dependent MODE/SYNC pin control, a valid sync signal must be applied. Upon completion of

the fourth pulse in a valid synchronization pulse train, the SYNC mode pin operates in Pulse-Dependent MODE/

SYNC control mode, shown in 图 8-3 and 图 8-4. The only way to return to Level-Dependent MODE/SYNC

control is to restart the LM62345-Q1.

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SYNC/MODE enters Pulse

< t_SYNC

Dependent mode, Spread

spectrum turns on, and part

will synchronize clock if

pulse train continues to

pulse number 2048.

< t_SYNC

FPWM Mode

Pulse 3

Pulse 4

Pulse 1

Pulse 2

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_L}

< t_SYNC

> t_{PULSE_L}

> t_{PULSE_H}

> t_{PULSE_L}

< t_SYNC

> t_{PULSE_H}

> t_{PULSE_L}

< t_SYNC

> t_{PULSE_H}

> t_{PULSE_L}

< t_SYNC

> t_{PULSE_H}

图8-3. Transition from FPWM Mode to Pulse-Dependent Control

SYNC/MODE enters Pulse

Dependent mode, Spread

spectrum turns on, and part

will synchronize clock if

pulse train continues to

pulse number 2048.

< t_SYNC

Pulse 2

Pulse 1

Pulse 4

Pulse 3

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

> t_{PULSE_H}

< t_SYNC

Auto Mode

> t_{PULSE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图8-4. Transition from Auto Mode to Pulse-Dependent Control

Once Pulse Dependent MODE/SYNC control has been initiated, 表 8-2 shows a summary of the pulse

dependent mode selection settings.

表8-2. Pulse-Dependent Mode Selection Settings

MODE/SYNC INPUT

MODE

> V_{MODE_H}

FPWM with Spread Spectrum

Auto Mode with Spread Spectrum

SYNC Mode without Spread Spectrum

FPWM without Spread Spectrum

Auto Mode without Spread Spectrum

< V_{MODE_L}

Synchronization Clock

> V_{MODE_H}AND Double Pulse (图8-6)

< V_{MODE_L}AND Double Pulse (图8-7)

图 8-5 shows the transition between AUTO Mode and FPWM Mode while in Pulse-Dependent MODE/SYNC

control. The LMQ6240-Q1 transitions to a new mode of operation after the time, t_MODE

.

Transition to new mode of operation

starts, spread spectrum turns on

> t_MODE

FPWM Mode

Auto Mode

V_{MODE_H}

V_{MODE_L}

图8-5. Transition from Auto Mode and FPWM Mode

Two positive going pulses can be used to turn off spread spectrum in Auto and FPWM modes. The two positive

pulses must be consistent with the characteristics of a valid sync signal. The following four diagrams, 图 8-6

through 图 8-9, show the only waveforms that result in spread spectrum being turned off. Refer to 节 7.5 for

more information about the timing specifications.

t_MODE

Spread spectrum turns off

< t_SMYO

NDCE

< t_SYNC

FPWM Mode

Pulse 1

Pulse 2

V_{MODE_H}

V_{MODE_L}

Now FPWM Mode, Spread Spectrum off

> t_{PULSE_L}

< t_SYNC

> t_{PULSE_H}

> t_SYNC

> t_{PULSE_L}

>>t_Pt_USLY

SNEC_H

> t_{PULSE_L}

< t_SYNC

< t_MODE

图8-6. Spread Spectrum Disabled in FPWM Mode

< t_SYNC

t_MODE

Pulse 2

Pulse 1

Spread spectrum turns off

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

Now Auto Mode, Spread Spectrum off

Auto Mode

< t

< t_MODE

SYNC

图8-7. Spread Spectrum Disabled in Auto Mode

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< t_SYNC

t_MODE

Spread spectrum turns off,

Mode changes to Auto

Pulse 2

FPWM Mode

Pulse 1

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_MSYONDCE

> t_{PULSE_L}

> t_{PULSE_H}

< t_SYNC

Now Auto Mode, Spread Spectrum off

>>t_Pt_{USLYSNEC_L}

图8-8. Spread Spectrum Disabled in Transition from FPWM Mode to Auto Mode

< t_SYNC

t_MODE

Spread spectrum turns off,

now in FPWM mode

Pulse 2

Pulse 1

V_{MODE_H}

V_{MODE_L}

Now FPWM Mode, Spread Spectrum off

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

> t_{PULSE_H}

< t_SYNC

Auto Mode

> t_{PULSE_L}

图8-9. Spread Spectrum Disabled in Transition from Auto Mode to FPWM Mode

To enter the SYNC Mode, the valid synchronization signal must be present for 2048 cycles.

If MODE/SYNC voltage becomes constant longer than t_MODE, the LM62345-Q1 enters either Auto mode or

FPWM mode. At this time, spread spectrum is turned on and MODE/SYNC operates in Pulse-Dependent mode.

t_MODE

Now Auto Mode, Spread Spectrum on

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图8-10. Transition from SYNC Mode to Auto Mode

t_MODE

< t_SYNC

Now FPWM Mode, Spread Spectrum on

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图8-11. Transition from SYNC Mode to FPWM Mode

8.3.2.3 Clock Locking

Once a valid synchronization signal is detected, a clock locking procedure is initiated. The LM62435-Q1 receives

this signal over the MODE/SYNC pin. After approximately 2048 pulses, the clock frequency completes a smooth

transition to the frequency of the synchronization signal without output variation. Note that while the frequency is

adjusted suddenly, phase is maintained so the clock cycle that lies between operation at the default frequency

and at the synchronization frequency is of intermediate length. This eliminates very long or very short pulses.

Once frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges

correspond to rising SW node pulses.

Pulse

~2048

Pulse

~2049

Pulse

~2050

Pulse

~2051

Pulse 1

Pulse 2

Pulse 3

Pulse 4

V_SYNCDH

V_SYNCDL

Synchronization

signal

Spread Spectrum is on between pulse 1 and

approximately pulse 2048, there is no change to

operating frequency

Also clock frequency matches the

synchronization signal and phase

locking begins

Phase lock achieved, Rising edges

align to within approximately 45 ns,

no spread spectrum

On approximately pulse 2048, spread

spectrum turns off

SW Node

VIN

GND

Pulses four and synchronization signal is detected. After the pulse, approximately 2048 ready to synchronize and frequency is adjusted

using a glitch free technique. Later, phase is locked.

图8-12. Synchronization Process

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Also note that the LM62435-Q1 turns on spread spectrum after the first edge in the synchronization pulse. See

the MODE/SYNC pin description in the 节 6. Upon adjustment of frequency on the approximate 2048th pulse,

spread spectrum is turned off. Finally, if the part runs at reduced frequency due to low or high input voltage or

during current limit, frequency lock does not occur until the condition causing low frequency operation has been

removed.

8.3.3 PGOOD Output Operation

The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The

PGOOD pin voltage goes low when the feedback voltage is outside of the specified PGOOD thresholds (see 图

7-8). This can occur in current limit and thermal shutdown, as well as while disabled and during normal start-up.

A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load

transients. Output voltage excursions that are shorter than t_{PGDFLT_FALL}do not trip the power-good flag. Power-

good operation can be best understood by referring to 图8-13.

The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic

supply or V_OUT. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid

as long as the input voltage is ≥1 V (typical).

Output

Voltage

Input

Voltage

Input Voltage

t_PGDFLT(fall)

t_PGDFLT(rise)

t_PGDFLT(fall)

V_{PGD_HYST}

t_PGDFLT(fall)

V_{PGD_UV}(falling)

V_{IN_OPERATE}(rising)

V_{IN_OPERATE}(falling)

V_{IN(PGD_VALID)}

GND

< 18 V

PGOOD

Small glitches

do not cause

PGOOD to

PGOOD may

not be valid if

input is below

V_{IN(PGD_VALID)}

Small glitches do not

reset t_PGDFLT(rise)timer

PGOOD may not

be valid if input is

below V_{IN(PGD_VALID)}

Startup

delay

signal a fault

图8-13. PGOOD Timing Diagram (Excludes OV Events)

表8-3. Conditions That Cause PGOOD to Signal a Fault (Pull Low)

FAULT CONDITION ENDS (AFTER WHICH t_PGDFLT(rise)MUST PASS

BEFORE PGOOD OUTPUT IS RELEASED)⁽¹⁾

FAULT CONDITION INITIATED

Output voltage in regulation:

V_OUT-target× (PGD_UV+ PGD_HYST) < V_OUT< V_OUT-target× (PGD_OV

-

V_OUT< V_OUT-target× PGD_UVAND t > t_PGDFLT(fall)

PGD_HYST) (See 图7-8)

V_OUT> V_OUT-target× PGD_OVAND t > t_PGDFLT(fall)

T_J> T_{SD_R}

Output voltage in regulation

T_J< T_{SD_F}AND output voltage in regulation

EN > V_ENRising AND output voltage in regulation

V_CC> V_{CC_UVLO}AND output voltage in regulation

EN < V_ENFalling

V_CC< V_{CC_UVLO}- V_{CC_UVLO_HYST}

(1) As an additional operational check, PGOOD remains low during soft start, defined as until the lesser of either full output voltage

reached or t_SS2has passed since initiation.

8.3.4 Internal LDO, VCC UVLO, and BIAS Input

The VCC pin is the output of the internal LDO used to supply the control circuits of the LM62435-Q1. The

nominal output is 3 V to 3.3 V. The BIAS pin is the input to the internal LDO. This input can be connected to

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V_OUTto provide the lowest possible input supply current. If the BIAS voltage is less than 3.1 V, VIN1 and VIN2

directly powers the internal LDO.

To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too low. See

V_{CC_UVLO}and V_{CC_UVLO_HYST}in 节 7.5. Note that these UVLO values and the dropout of the LDO are used to

derive minimum V_{IN_OPERATE}and V_{IN_OPERATE_H}values.

8.3.5 Bootstrap Voltage and V_CBOOT-UVLO(CBOOT Pin)

The driver of the High-Side (HS) switch requires bias higher than V_IN. The capacitor, CBOOT, connected

between CBOOT and SW, works as a charge pump to boost voltage on the CBOOT pin to SW + VCC. A boot

diode is integrated on the LM62435-Q1 die to minimize external component count. It is recommended that a

100-nF capacitor rated for 10 V or higher is used. The V_{BOOT_UVLO}threshold (2.1 V typ.) is designed to maintain

proper HS switch operation. If the CBOOT capacitor voltage drops below V_{BOOT_UVLO}, then the device initiates a

charging sequence, turning on the low-side switch before attempting to turn on the HS switch.

8.3.6 Adjustable SW Node Slew Rate

To allow optimization of EMI with respect to efficiency, the LM62435-Q1 is designed to allow a resistor to select

the strength of the driver of the high-side FET during turn on. See 图 8-14. The current drawn through the

RBOOT pin (the dotted loop) is magnified and drawn through from CBOOT (the dashed line). This current is

used to turn on the high-side power MOSEFT.

VIN

VCC

CBOOT

HS FET RBOOT

HS

Driver

SW

LS FET

图8-14. Simplified Circuit Showing How RBOOT Functions

With RBOOT short circuited to CBOOT, rise time is very fast. As a result, SW node harmonics do not "roll off"

until above 150 MHz. A boot resistor of 100 Ω corresponds to approximately 2.7-ns SW node rise, and this 100-

Ω boot resistor virtually eliminates SW node overshoot. The slower rise time allows energy in SW node

harmonics to roll off near 100 MHz under most conditions. Rolling off harmonics eliminates the need for shielding

and common mode chokes in many applications. Note that rise time increases with increasing input voltage.

Noise due to stored charge is also greatly reduced with higher RBOOT resistance. Switching with slower slew

rate also decreases the efficiency.

8.3.7 Spread Spectrum

Spread spectrum is pin-controlled. The purpose of spread spectrum is to eliminate peak emissions at specific

frequencies by spreading these emissions across a wider range of frequencies rather than apart with fixed

frequency operation. In most systems containing the LM62435-Q1, low frequency-conducted emissions from the

first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction

of emissions at higher harmonics that fall in the FM band. These harmonics often couple to the environment

through electric fields around the switch node and inductor. The LM62435-Q1 uses a ±2% spread of frequencies

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which can spread energy smoothly across the FM and TV bands but is small enough to limit subharmonic

emissions below the device switching frequency. Peak emissions at the switching frequency of the part are only

reduced slightly, by less than 1 dB, while peaks in the FM band are typically reduced by more than 6 dB.

The LM62435-Q1 uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register

(LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple.

The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band.

The spread spectrum is only available while the clock of the LM62435-Q1 devices are free running at their

natural frequency. Any of the following conditions overrides spread spectrum, turning it off:

• The clock is slowed during dropout.

• The clock is slowed at light load in auto mode. In FPWM mode, spread spectrum is active even if there is no

load.

• At a high input voltage/low output voltage ratio when the device operates at minimum on-time, the internal

clock is slowed, disabling spread spectrum. See 节7.6.

• The clock is synchronized with an external clock.

8.3.8 Soft Start and Recovery From Dropout

The LM62435-Q1 uses a reference-based soft start that prevents output voltage overshoots and large inrush

currents during start-up. Soft start is triggered by any of the following conditions:

• Power is applied to the VIN pin of the IC, releasing UVLO.

• EN is used to turn on the device.

• Recovery from a hiccup waiting period

• Recovery from shutdown due to overtemperature protection

Once soft start is triggered, the IC takes the following actions:

• The reference used by the IC to regulate output voltage is slowly ramped. The net result is that output voltage

takes t_SSto reach 90% of its desired value.

• Operating mode is set to auto, activating diode emulation. This allows start-up without pulling output low if

there is a voltage already present on output.

These actions together provide start-up with limited inrush currents and also allow the use of larger output

capacitors and higher loading conditions that cause current to border on current limit during start-up without

triggering hiccup. See 图8-15.

If selected, FPWM

is enabled after

regulation but no

later than t_SS2

If selected, FPWM

is enabled after

regulation but no

later than t_SS2

Triggering event

t_EN

t_SS

t_EN

t_SS

V

V_EN

V_OUTSet

Point

V_OUTSet

Point

V_OUT

90% of

V_OUTSet

Point

90% of

V_OUTSet

Point

t

0 V

Time

t_SS2

Soft start works with both output voltages starting from 0 V on the left curves, or if there is already voltage on the output, as shown on

right. In either case, output voltage must reach within 10% of the desired value t_SSafter soft start is initiated. During soft start, FPWM

and hiccup are disabled. Both hiccup and FPWM are enabled once output reaches regulation or t_SS2, whichever happens first.

图8-15. Soft-Start Operation

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Any time the output voltage falls more than a few percent, the output voltage ramps up slowly. This condition is

called recovery from dropout and differs from soft start in three important ways:

• The reference voltage is set to approximately 1% above what is needed to achieve the existing output

voltage.

• Hiccup is allowed if output voltage is less than 0.4 times its set point. Note that during dropout regulation

itself, hiccup is inhibited.

• FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by

an external supply, the LM62435-Q1 can pull down on the output.

Despite being called recovery from dropout, this feature is active whenever output voltage drops to a few percent

lower than the set point. This primarily occurs under the following conditions:

• Dropout: When there is insufficient input voltage for the desired output voltage to be generated

• Overcurrent: When there is an overcurrent event that is not severe enough to trigger hiccup

V

V_IN

Slope

V_OUT

V_OUTSet

Point

the same

as during

soft start

t

Time

Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall below its set point is

removed, the output climbs at the same speed as during start-up. Even though hiccup does not trigger due to dropout, it can, in

principle, be triggered during recovery if output voltage is below 0.4 times the output set point for more than 128 clock cycles.

图8-16. Recovery From Dropout

8.3.9 Output Voltage Setting

A feedback resistor divider network between the output voltage and the FB pin is used to set output voltage

level. See 图8-17.

V_OUT

R_FBT

FB

R_FBB

AGND

图8-17. Setting Output Voltage of Adjustable Versions

Adjustable versions of the LM62435-Q1 use a 1-V reference voltage for the feedback (FB) pin. The FB pin

voltage is regulated by the internal controller to be the same as the reference voltage. The output voltage level is

then set by the ratio of the resistor divider. Equation 3 can be used to determine R_FBBfor a desired output

voltage and a given R_FBT. Usually R_FBTis between 10 kΩ and 1 MΩ. 100 kΩ is recommended for R_FBTfor

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improved noise immunity compared to 1 MΩ and reduced current consumption compared to lower resistance

values.

R_FBT

R_FBB

=

V_OUTÅ 1

(2)

In addition, a feedforward capacitor, C_FF, connected in parallel with R_FBTcan be required to optimize the

transient response.

8.3.10 Overcurrent and Short Circuit Protection

The LM62435-Q1 is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-

side and the low-side MOSFETs.

High-side MOSFET overcurrent protection is implemented by the nature of the peak-current mode control. The

HS switch current is sensed when the HS is turned on after a short blanking time. Every switching cycle, the HS

switch current is compared to either the minimum of a fixed current set point or the output of the voltage

regulation loop minus slope compensation. Because the voltage loop has a maximum value and slope

compensation increases with duty cycle, HS current limit decreases with increased duty cycle when duty cycle is

above 35%.

When the LS switch is turned on, the switch current is also sensed and monitored. Like the high-side device, the

low-side device turns off as commanded by the voltage control loop and low-side current limit. If the LS switch

current is higher than I_{LS_Limit}at the end of a switching cycle, the switching cycle is extended until the LS current

reduces below the limit. The LS switch is turned off once the LS current falls below its limit, and the HS switch is

turned on again as long as at least one clock period has passed since the last time the HS device has turned on.

V_SW

V_IN

t_ON< t_{ON_MAX}

0

t

Typically, t_SW> Clock setting

i_L

I_L-HS

I_L-LS

I_OUT

t

0

图8-18. Current Limit Waveforms

Since the current waveform assumes values between I_L-HSand I_L-LS, the maximum output current is very close

to the average of these two values. Hysteretic control is used and current does not increase as output voltage

approaches zero.

The LM62435-Q1 employs hiccup overcurrent protection if there is an extreme overload, and the following

conditions are met for 128 consecutive switching cycles:

• Output voltage is below approximately 0.4 times the output voltage set point.

• Greater than t_SS2has passed since soft start has started; see 节8.3.8.

• The part is not operating in dropout, which is defined as having minimum off-time controlled duty cycle.

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In hiccup mode, the device shuts itself down and attempts to soft start after t_W. Hiccup mode helps reduce the

device power dissipation under severe overcurrent conditions and short circuits. See 图8-19.

Once the overload is removed, the device recovers as though in soft start; see 图8-20.

V_OUT

(5 V/DIV)

V_SW

(5 V/DIV)

I_L

(2 A/DIV)

Time (10 ms/DIV)

Time (1.6 ms/DIV)

图8-19. Inductor Current Bursts During Hiccup

图8-20. Short Circuit Recovery

8.3.11 Thermal Shutdown

Thermal shutdown prevents the device from extreme junction temperatures by turning off the internal switches

when the IC junction temperature exceeds 165°C (typical). Thermal shutdown does not trigger below 158°C.

After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature

drops to approximately 155°C. When the junction temperature falls below 155°C (typical), the LM62435-Q1

attempts to soft start.

While the LM62435-Q1 is shut down due to high junction temperature, power continues to be provided to VCC.

To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced

current limit while the part is disabled due to high junction temperature. The VCC current limit is reduced to a few

milliamperes during thermal shutdown.

8.3.12 Input Supply Current

The LM62435-Q1 is designed to have very low input supply current when regulating light loads. This is achieved

by powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that powers the

majority of the control circuits. By connecting the BIAS input pin to the output of the regulator, a small amount of

current is drawn from the output. This current is reduced at the input by the ratio of V_OUT/ V_IN.

≈

∆

«

’

÷

≈

∆

«

’

÷

1

Output Voltage

I_{Q _ VIN}

= I_EN+I_{Q _ VIN}

ì

+I

ì

div

SW

(

)

h_{eff ◊}

Input Voltageì h_{eff ◊}

(3)

where

• I_{Q_VIN}is the current consumed by the operating (switching) buck converter while unloaded.

• I_Qis the current drawn from the V_INterminal. See I_Qin 节7.5.

• I_ENis current drawn by the EN terminal. Include this current if EN is connected to VIN. See I_ENin 节7.5. Note

that this current drops to a very low value if connected to a voltage less than 5 V.

• I_divis the current drawn by the feedback voltage divider used to set output voltage.

• η_effis the light-load efficiency of the buck converter with I_{Q_VIN}removed from the input current of the buck

converter. η_eff= 0.8 is a conservative value that can be used under normal operating conditions.

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, both

the converter and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode,

the quiescent current drops to typically 0.6 µA.

8.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above

1.1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the

VCC voltage at 3.3 V typical. The precision enable circuitry is ON once VCC is above its UVLO. The internal

power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable

threshold. The LM62435-Q1 also employs UVLO protection. If the VCC voltage is below its UVLO level, the

output of the converter is turned off.

8.4.3 Active Mode

The LM61435-Q1 is in active mode whenever the EN pin is above V_EN, V_INis high enough to satisfy

V_{IN_OPERATE}, and no other fault conditions are present. The simplest way to enable the operation is to connect

the EN pin to V_IN, which allows self start-up when the applied input voltage exceeds the minimum V_{IN_OPERATE}

.

In active mode, depending on the load current, input voltage, and output voltage, the LM62435-Q1 is in one of

five modes:

• Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

inductor current ripple.

• Auto Mode - Light Load Operation: PFM when switching frequency is decreased at very light load.

• FPWM Mode - Light Load Operation: Discontinuous conduction mode (DCM) when the load current is lower

than half of the inductor current ripple.

• Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to

maintain regulation.

• Dropout mode: When switching frequency is reduced to minimize voltage dropout.

8.4.3.1 CCM Mode

The following operating description of the LM62435-Q1 refers to 节 8.2 and to the waveforms in 图 8-21. In

CCM, the LM62435-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and low-

side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, V_SW

,

swings up to approximately V_IN, and the inductor current, i_L, increases with a linear slope. The HS switch is

turned off by the control logic. During the HS switch off-time, t_OFF, the LS switch is turned on. Inductor current

discharges through the LS switch, which forces the V_SWto swing below ground by the voltage drop across the

LS switch. The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the

on-time of the HS switch over the switching period:

D = T_ON/ T_SW

(4)

In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage:

D = V_OUT/ V_IN

(5)

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

V_IN

t_OFF

t_ON

0

t

- I_OUT‡R_DSLS

t_SW

i_L

I_LPK

I_OUT

I_ripple

t

0

图8-21. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

8.4.3.2 Auto Mode - Light Load Operation

The LM62435-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows

for seamless transition between normal current mode operation while heavily loaded and highly efficient light

load operation. The other behavior, called FPWM Mode, maintains full frequency even when unloaded. Which

mode the LM62435-Q1 operates in depends on the configuration of the MODE/SYNC pin. See 表 8-1. When

using the LM62435-Q1, light load behavior is selected using the MODE/SYNC pin. Note that all parts operate in

FPWM mode when synchronizing frequency to an external signal.

In auto mode, light load operation is employed in the LM62435-Q1. Light load operation employs two techniques

to improve efficiency:

• Diode emulation, which allows DCM operation

• Frequency reduction

Note that while these two features operate together to create excellent light load behavior, they operate

independently of each other.

8.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to

regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.

With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to

maintain regulation.

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t_ON

V_OUT

V_IN

D =

V_SW

<

t_SW

V_IN

t_OFF

t_ON

t_HIGHZ

0

t

t_SW

i_L

I_LPK

I_OUT

0

t

In auto mode, the low-side device is turned off once SW node current is near zero. As a result, once output current is less than half of

what inductor ripple would be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.

图8-22. PFM Operation

The device has a minimum peak inductor current setting while in auto mode.Once current is reduced to a low

value with fixed input voltage, on-time is constant. Regulation is then achieved by adjusting frequency. This

mode of operation is called PFM mode regulation.

8.4.3.2.2 Frequency Reduction

The LM62435-Q1 reduces frequency whenever output voltage is high. This function is enabled whenever Comp,

an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied to

FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal

operation. Output voltage must be approximately 1% high when the part is completely unloaded.

V_OUT

Current

Limit

1% Above

Set point

V_OUTSet

Point

I_OUT

Output Current

0

In auto mode, once output current drops below approximately 1/10th the rated current of the part, output resistance increases so that

output voltage is 1% high while the buck is completely unloaded.

图8-23. Steady State Output Voltage versus Output Current in Auto Mode

In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The

lower the frequency in PFM, the more DC offset is needed on V_OUT. If the DC offset on V_OUTis not acceptable, a

dummy load at V_OUTor FPWM Mode can be used to reduce or eliminate this offset.

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8.4.3.3 FPWM Mode - Light Load Operation

In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is

allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see 节 7.5 for

reverse current limit values.

V_SW

t_ON

V_OUT

V_IN

D =

≈

t_SW

V_IN

t_OFF

t_ON

0

t

t_SW

i_L

I_LPK

I_OUT

0

I_ripple

t

In FPWM mode, Continuous Conduction (CCM) is possible even if I_OUTis less than half of I_ripple

.

图8-24. FPWM Mode Operation

Transitions between auto mode and FPWM mode can be commanded during operation if you are using the

LM62435-Q1. These transitions are gradual, taking tens of clock cycles, allowing minimal disruption of output

voltage during transitions. If the load is heavy enough to operate in CCM, since operation is identical in FPWM

and Auto mode, no change in behavior is visible until the next time the circuit is lightly loaded.

For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to

command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output

being pulled up.

8.4.3.4 Minimum On-time (High Input Voltage) Operation

The LM62435-Q1 continues to regulate output voltage even if the input-to-output voltage ratio requires an on-

time less than the minimum on-time of the chip with a given clock setting. This is accomplished using valley

current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a

maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until

valley current falls below that determined by the compensation circuit. If the converter is not operating in current

limit, the maximum valley current is set above the peak inductor current, preventing valley control from being

used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high,

even though current exceeds the peak value dictated by compensation, the high-side device cannot be turned

off quickly enough to regulate output voltage. As a result, the compensation circuit reduces both peak and valley

current. Once a low enough current is selected by the compensation circuit, valley current matches that being

commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next

clock cycle is prevented from starting until inductor current drops below the desired valley current. Since on-time

is fixed at its minimum value, this type of operation resembles that of a device using a Constant On-Time (COT)

control scheme; see 图8-25.

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

V_IN

t_ON= t_{ON_MIN}

t_OFF

0

t

- I_OUT‡R_DSLS

t_SW> Clock setting

i_L

I_OUT

I_ripple

I_LVLY

t

0

In valley control mode, minimum inductor current is regulated, not peak inductor current.

图8-25. Valley Current Mode Operation

8.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the

required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. Once this limit is

reached, if clock frequency were maintained, output voltage would fall. Instead of allowing the output voltage to

drop, the LM62435-Q1 extends on-time past the end of the clock cycle until needed peak inductor current is

achieved. The clock is allowed to start a new cycle once peak inductor current is achieved or once a pre-

determined maximum on-time, t_{ON_MAX}, of approximately 9 µs passes. As a result, once the needed duty cycle

cannot be achieved at the selected clock frequency due to the existence of a minimum off-time, frequency drops

to maintain regulation. If input voltage is low enough so that output voltage cannot be regulated even with an on-

time of t_{ON_MAX}, output voltage drops to slightly below the input voltage, V_DROP1. For additional information on

recovery from dropout, reference 图8-16.

V_DROP2if

frequency =

1.85 MHz

Input

Voltage

i_L

V_DROP1

Output

Voltage

Output

Setting

V_IN

0

Input Voltage

i_L

Frequency

Setting

I_OUT

~100kHz

0

V_IN

Input Voltage

Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC

reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,

input voltage tracks output voltage.

图8-26. Frequency and Output Voltage in Dropout

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

t_OFF= t_{OFF_MIN}

V_IN

t_ON< t_{ON_MAX}

0

t

- I_OUT‡R_DSLS

t_SW> Clock setting

i_L

I_LPK

I_OUT

I_ripple

t

0

Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,

frequency drops. This frequency drop is limited by t_{ON_MAX}

.

图8-27. Dropout Waveforms

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The LM62435-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC

voltage with a maximum output current of 3.5 A. The following design procedure can be used to select

components for the LM62435-Q1.

9.2 Typical Application

图 9-1 shows a typical application circuit for the LM62435-Q1. This device is designed to function with a wide

range of external components and system parameters. However, the internal compensation is optimized for a

certain range of external inductance and output capacitance. As a quick start guide, provides typical component

values for some of the common configurations.

5 V to 36 V input

VIN1

VIN2

C_{IN_HF1}

C_{IN_HF2}

C_IN-BLK

PGND1

PGND2

PGOOD

BIAS

EN

R_PG

L1

Output

SW

MODE/SYNC

VCC

C_BT

C_OUT

R_FF

CBOOT

R_FBT

C_FF

RBOOT

FB

C_VCC

R_FBB

AGND

图9-1. Example Application Circuit

9.2.1 Design Requirements

表9-1 provides the parameters for the detailed design procedure example:

表9-1. Detailed Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

13.5 V (5 V to 36 V)

Input voltage for constant f_SW

Output voltage

8 V to 18 V

5 V

Maximum output current

Switching frequency

0 A to 3.5 A

2.1 MHz

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表9-2. Typical External Component Values

R_FBT

(kΩ)

R_FBB

(kΩ)

R_BOOT

(Ω)

f_SW

C_BOOT

(µF)

C_VCC

(µF)

V_OUT(V) L1 (µH)

C_OUT(RATED)

C_FF(pF)

R_FF(kΩ)

(kHz)

2100

400

3.3

5

1.5

8.2

1.5

8.2

3 × 22 µF ceramic

4 × 22 µF ceramic

2 × 22 µF ceramic

3 × 22 µF ceramic

100

43.2

0.1

0

1

10

4.7

22

1

100

43.2

24.9

2100

400

5

9.2.2 Detailed Design Procedure

The following design procedure applies to 图9-1 and 表9-1.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows for the use of smaller inductors and output capacitors, hence, a

more compact design.

When choosing operating frequency, the most important consideration is thermal limitations. This constraint

typically dominates frequency selection. See 图9-2 for circuits running at 400 kHz and 图9-3 for circuits running

at 2.1 MHz. These curves show how much output current can be supported at a given ambient temperature

given these switching frequencies. Note that power dissipation is layout-dependent so while these curves are a

good starting point, thermal resistance in any design will be different from the estimates used to generate 图 9-2

and 图 9-3. The maximum temperature ratings are based on a 100-mm x 80-mm, 4-layer EVM PCB design,

LM61460EVM.

130

125

120

115

110

105

100

95

135

125

115

105

95

85

V_IN= 13.5 V

V_IN= 16 V

V_IN= 24 V

V_IN= 13.5 V

V_IN= 16 V

V_IN= 24 V

75

90

85

65

3

3.1

3.2 3.3

Output Current (A)

3.4

3.5

2

2.25

2.5 2.75

Output Current (A)

3

3.25

3.5

snvs

f_SW= 400 kHz

PCB R_θJA

25°C/W

=

V_OUT= 5 V

f_SW= 2100 kHz PCB R_θJA= 25°C/W

V_OUT= 5 V

图9-3. Maximum Ambient Temperature versus

图9-2. Maximum Ambient Temperature versus

Output Current

Two other considerations are what maximum and minimum input voltage the part must maintain its frequency

setting. Since the LM62435-Q1 adjusts its frequency under conditions in which regulation would normally be

prevented by minimum on-time or minimum off time, these constraints are only important for input voltages

requiring constant frequency operation.

If foldback is undesirable at high input voltage, then use 方程式6:

V_OUT

f_SW

G

V_IN(MAX2) ‡ t_{ON_MIN}(MAX)

(6)

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If foldback at low input voltage is a concern, use 方程式7:

V_INeff(MIN2) œ V_OUT

V_INeff(MIN2) ‡ t_{OFF_MIN}(MAX)

f_SW

≤

(7)

where:

V_INeff(MIN2) = V_IN(MIN2) œ I_OUT(MAX) ‡ (R_{DS(ON)_HS}(MAX) + DCR(MAX))

•

• DCR(MAX) = maximum DCR of the inductor

• t_{OFF_MIN}(MAX) = see 节7.5

• R_{DS(ON)_HS}(MAX) = see 节7.5

The fourth constraint is the rated frequency range of the IC. See f_ADJin 节 7.5. All previously stated constraints

(thermal, V_IN(MAX2), V_IN(MIN2), and device-specified frequency range) must be considered when selecting

frequency.

Many applications require that the AM band can be avoided. These applications tend to operate at either 400

kHz below the AM band or 2.1 MHz above the AM band. In this example, 400 kHz is chosen.

9.2.2.2 Setting the Output Voltage

The adjustable output voltage device variant of LM62435-Q1 is externally adjustable using a resistor divider

network. The range of recommended output voltage is found in 节 7.3. The divider network is comprised of R_FBT

and R_FBB, and closes the loop between the output voltage and the converter. The converter regulates the output

voltage by holding the voltage on the FB pin equal to the internal reference voltage, V_REF. The resistance of the

divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller values of

resistance reduce noise sensitivity but also reduce the light load efficiency. The recommended value for R_FBTis

100 kΩ with a maximum value of 1 MΩ. If 1 MΩ is selected for R_FBT, then a feedforward capacitor must be

used across this resistor to provide adequate loop phase margin (see 节 9.2.2.10). Once R_FBTis selected, 方程

式2 is used to select R_FBB. V_REFis nominally 1 V. For this 5-V example, R_FBT= 100 kΩand R_FBB= 24.9 kΩare

chosen.

For the fixed output voltage versions, FB is connected directly to the output voltage node, preferably, near the

top of the output capacitor. If the feedback point is located further away from the output capacitors (that is,

remote sensing), then a small 100-nF capacitor can be needed at the sensing point.

9.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on

the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the

maximum output current. Experience shows that the best value for inductor ripple current is 30% of the

maximum load current for systems with a fixed input voltage and 25% for systems with a variable input voltage

such as the 12 volt battery in a car. Note that when selecting the ripple current for applications with much smaller

maximum load than the maximum available from the device, the maximum device current must still be used. 方

程式 8 can be used to determine the value of inductance. The constant K is the percentage of inductor current

ripple. For this example, K = 0.25 was chosen and an inductance of approximately 2.3 µH was found. The next

standard value of 1.5 μH was selected.

V_INÅ V_OUT

f_SW‡ K ‡ I_OUT(MAX)

V_OUT

V_IN

L=

‡

(8)

The saturation current rating of the inductor must be at least as large as the high-side switch current limit, I_L-HS

(see 节7.5). This ensures that the inductor does not saturate even during a short circuit on the output. When the

inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very

rapidly. Although the valley current limit, I_L-LS, is designed to reduce the risk of current run-away, a saturated

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inductor can cause the current to rise to high values very rapidly. This can lead to component damage; do not

allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but

usually have lower core losses than powdered iron cores. Powdered iron cores exhibit a soft saturation, allowing

some relaxation in the current rating of the inductor. However, they have more core losses at frequencies

typically above 1 MHz. In any case, the inductor saturation current must not be less than the device high-side

current limit, I_L-HS(see 节7.5). To avoid subharmonic oscillation, the inductance value must not be less than that

given in 方程式 9. The maximum inductance is limited by the minimum current ripple required for the current

mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than

about 10% of the device maximum rated current under nominal conditions.

V_OUT

L ≥ 0.5 ‡

f_SW

(9)

方程式 9 assumes that this design must operate with input voltage near or in dropout. If minimum operating

voltage for this design is high enough to limit duty factor to below 40%, 方程式 8 can be used in place of 方程式

9.

Note that choosing an inductor that is larger than the minimum inductance calculated using 方程式 8 and 方程式

9 results in less output capacitance being needed to limit output ripple but more output capacitance being

needed to manage large load transients. See 节9.2.2.4.

9.2.2.4 Output Capacitor Selection

The value of the output capacitor and its ESR determine the output voltage ripple and load transient

performance. The output capacitor is usually determined by the load transient requirements rather than the

output voltage ripple. 表 9-3 can be used to find the output capacitor and C_FFselection for a few common

applications. Note that a 1-kΩ R_FFcan be used in series with C_FFto further improve noise performance. In this

example, improved transient performance is desired giving 2 x 47-µF ceramic as the output capacitor and 22 pF

as C_FF.

表9-3. Recommended Output Ceramic Capacitors and C_FFValues

3.3-V OUTPUT

5-V OUTPUT

CERAMIC OUTPUT CAPACITANCE

2 x 22 µF

TRANSIENT

PERFORMANCE

FREQUENCY

CERAMIC OUTPUT CAPACITANCE

C_FF

2.1 MHz

400 kHz

Minimum

Better Transient

Minimum

3 x 22 µF

2 x 47 µF

4 x 22 µF

5 x 22 µF

10 pF

33 pF

4.7 pF

33 pF

22 pF

33 pF

10 pF

33 pF

3 x 22 µF

Better Transient

To minimize ceramic capacitance, a low-ESR electrolytic capacitor can be used in parallel with minimal ceramic

capacitance. As a starting point for designing with an output electrolytic capacitor, 表 9-4 shows the

recommended output ceramic capacitance C_FFvalues when using an electrolytic capacitor.

表9-4. Recommended Electrolytic and Ceramic Capacitor and C_FFValues

3.3-V OUTPUT

5-V OUTPUT

TRANSIENT

PERFORMANCE

FREQUENCY

C_OUT

C_FF

C_OUT

C_FF

2 x 22 µF ceramic + 1 x 470 µF, 100-mΩ

400 kHz

Minimum

10 pF

2 x 22 µF ceramic + 1 x 470 µF, 100-mΩelectrolytic

4 x 22 µF ceramic + 2 x 280 µF,100-mΩelectrolytic

electrolytic

3 x 22 µF ceramic + 1 x 560 µF, 100-mΩ

Better Transient

33 pF

22 pF

electrolytic

Most ceramic capacitors deliver far less capacitance than the rating of the capacitor indicates. Be sure to check

any capacitor selected for initial accuracy, temperature derating, and voltage derating. 表 9-3 and 表 9-4 have

been generated assuming typical derating for 16-V, X7R, automotive grade capacitors. If lower voltage, non-

automotive grade, or lower temperature rated capacitors are used, more capacitors than listed are likely to be

needed.

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9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the converter in addition to supplying the ripple

current and isolating switching noise from other circuits. A minimum of 10 μF of ceramic capacitance is required

on the input of the device. This must be rated for at least the maximum input voltage that the application

requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input

voltage ripple and maintain the input voltage during load transients. In addition, a small case size 100-nF

ceramic capacitor must be used at each input/ground pin pair, VIN1/PGND1 and VIN2/PGND2, immediately

adjacent to the converter. This provides a high-frequency bypass for the control circuits internal to the device.

These capacitors also suppress SW node ringing, which reduces the maximum voltage present on the SW node

and EMI. The two 100 nF must also be rated at 50 V with an X7R or better dielectric. The VQFN-HR (RJR)

package provides two input voltage pins and two power ground pins on opposite sides of the package. This

allows the input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus

improving the effectiveness of the input bypassing. In this example, two 4.7-μF and two 100-nF ceramic

capacitors are used, one at each VIN/PGND location. A single 10-μF can also be used on one side of the

package.

Many times, it is desirable and necessary to use an electrolytic capacitor on the input in parallel with the

ceramics. This is especially true if long leads or traces are used to connect the input supply to the converter. The

moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads.

The use of this additional capacitor also helps with momentary voltage dips caused by input supplies with

unusually high impedance.

Most of the input switching current passes through the ceramic input capacitors. The approximate worst case

RMS value of this current can be calculated from 方程式 10 and must be checked against the manufacturers'

maximum ratings.

I_OUT

I_RMS

≈

2

(10)

9.2.2.6 BOOT Capacitor

The LM62435-Q1 requires a bootstrap capacitor connected between the CBOOT pin and the SW pin. This

capacitor stores energy that is used to supply the gate drivers for the high-side power MOSFET. A high-quality

(X7R) ceramic capacitor of 100 nF and at least 10 V is required.

9.2.2.7 BOOT Resistor

A BOOT resistor can be connected between the CBOOT and RBOOT pins. Unless EMI for the application being

designed is critical, these two pins can be shorted. A 100-Ω resistor between these pins eliminates overshoot.

Even with 0 Ω, overshoot and ringing are minimal, less than 2 V if input capacitors are placed correctly. A boot

resistor of 100 Ω, which corresponds to approximately 2.7-ns SW node rise time and decreases efficiency by

approximately 0.5% at 2 MHz. To maximize efficiency, 0 Ω is chosen for this example. Under most

circumstances, selecting an RBOOT resistor value above 100 Ω is undesirable since the resulting small

improvement in EMI is not enough to justify further decreased efficiency.

9.2.2.8 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the converter. This output

requires a 1-μF, 16-V ceramic capacitor connected from VCC to AGND for proper operation. In general, avoid

loading this output with any external circuitry. However, this output can be used to supply the pullup for the

power-good function (see 节 8.3.3). A pullup resistor with a value of 100 kΩ is a good choice in this case. Note,

VCC remains high when V_{EN_WAKE}< EN < V_EN. The nominal output voltage on VCC is 3.3 V. Do not short this

output to ground or any other external voltage.

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9.2.2.9 BIAS

Because V_OUT= 5 V in this design, the BIAS pin is tied to V_OUTto reduce LDO power loss. The output voltage is

supplying the LDO current instead of the input voltage. The power saving is I_LDO× (V_IN– V_OUT). The power

saving is more significant when V_IN>> V_OUTand with higher frequency operation. To prevent V_OUTnoise and

transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, can be added between V_OUTand BIAS. A

bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise. Note the

maximum allowed voltage on the BIAS pin is 16 V.

9.2.2.10 C_FFand R_FFSelection

A feedforward capacitor, C_ff, is used to improve phase margin and transient response of circuits which have

output capacitors with low ESR. Since this capacitor can conduct noise from the output of the circuit directly to

the FB node of the IC, a 1-kΩ resistor, R_ff, can be placed in series with Cff. If the ESR zero of the output

capacitor is below 200 kHz, no C_ffmust be used.

If output voltage is less than 2.5 V, C_ffhas little effect, so it can be omitted. If output voltage is greater than 14 V,

C_ffmust not be used since it introduces too much gain at higher frequencies.

9.2.2.11 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be

accomplished by using the circuit shown in 图 9-4. The input voltage at which the device turns on is designated

V

_ONwhile the turnoff voltage is V_OFF. First, a value for R_ENBis chosen in the range of 10 kΩ to 100 kΩ, then 方

程式 12 is used to calculate R_ENTand V_OFF. R_ENBis typically set based on how much current this voltage divider

must consume. R_ENBcan be calculated using 方程式11.

V_EN‡ V_IN

I_DIVIDER‡ V_ON

R_ENB

=

(11)

V_IN

R_ENT

EN

R_ENB

AGND

图9-4. UVLO Using EN

V

V_EN

^ONÅ 1

‡ R_ENB

R_ENT

=

(1 Å V

‡

)

V_OFF=V_ON

EN-HYST

(12)

where

• V_ON= V_INturnon voltage

• V_OFF= V_INturnoff voltage

• I_DIVIDER= voltage divider current

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9.2.3 Application Curves

100

95

90

85

80

75

70

65

60

100

90

80

70

60

50

40

30

20

10

0

V_IN= 8 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

0.001

0.005

0.02 0.05 0.1 0.2

Output Current (A)

0.5

1

2

3 4

0

1

2

Output Current (A)

3

4

LM61

V_OUT= 3.3 V

F_SW= 2100 kHz

AUTO Mode

V_OUT= 3.3 V

F_SW= 2100 kHz

FPWM Mode

图9-5. LM62435-Q1 Efficiency

图9-6. LM62435-Q1 Efficiency

100

90

80

70

60

50

40

30

20

10

0

95

90

85

80

75

70

65

60

V_IN= 8 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

0.001

0.005

0.02 0.05 0.1 0.2

Output Current (A)

0.5

1

2

3 4

0

1

2

Output Current (A)

3

4

LM61

V_OUT= 5 V

F_SW= 2100 kHz

AUTO Mode

V_OUT= 5 V

F_SW= 2100 kHz

FPWM Mode

图9-7. LM62435-Q1 Efficiency

图9-8. LM62435-Q1 Efficiency

3.37

3.35

3.33

3.31

3.29

3.37

3.35

3.33

3.31

3.29

V_IN= 8 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

0

1

2

Output Current (A)

3

4

0

1

2

Output Current (A)

3

4

LM61

V_OUT= 3.3 V

F_SW= 2100 kHz

Auto Mode

V_OUT= 3.3 V

F_SW= 2100 kHz

FPWM Mode

图9-9. LM62435-Q1 Load and Line Regulation

图9-10. LM62435-Q1 Load and Line Regulation

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9.2.3 Application Curves (continued)

5.11

5.09

5.07

5.05

5.03

5.01

4.99

4.97

4.95

5.11

5.09

5.07

5.05

5.03

5.01

4.99

4.97

4.95

V_IN= 8 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

V_IN= 12 V

V_IN= 13.5 V

V_IN= 24 V

0

1

2

Output Current (A)

3

4

0

1

2

Output Current (A)

3

4

LM61

V_OUT= 5V

F_SW= 2100 kHz

Auto Mode

V_OUT= 5V

F_SW= 2100 kHz

FPWM Mode

图9-11. LM62435-Q1 Load and Line Regulation

图9-12. LM62435-Q1 Load and Line Regulation

3.5

6

5.5

5

3.25

3

4.5

4

2.75

2.5

3.5

3

I_OUT= 0.01 A

I_OUT= 3 A

I_OUT= 0.01 A

I_OUT= 3 A

3

3.25

3.5

3.75

4

Input Voltage (V)

4.25

4.5

4.75

5

4

4.2 4.4 4.6 4.8 5

Input Voltage (V)

5.2 5.4 5.6 5.8

6

SNVS

V_OUT= 3.3 V

F_SW= 2100 kHz

AUTO Mode

V_OUT= 5 V

F_SW= 2100 kHz

AUTO Mode

图9-13. LM62435-Q1 Dropout Curve

图9-14. LM62435-Q1 Dropout Curve

2.5E+6

2.25E+6

2E+6

2.5E+6

2.25E+6

2E+6

1.75E+6

1.5E+6

1.25E+6

1E+6

1.75E+6

1.5E+6

1.25E+6

1E+6

7.5E+5

5E+5

7.5E+5

5E+5

2.5E+5

0

2.5E+5

0

I_OUT= 3 A

3

3.5

4

Input Voltage (V)

4.5

5

5.5

6

Input Voltage (V)

6.5

7

SNVS

V_OUT= 3.3 V

F_SW= 2100 kHz

AUTO Mode

V_OUT= 5 V

F_SW= 2100 kHz

AUTO Mode

图9-15. LM62435-Q1 Frequency Dropout Curve

图9-16. LM62435-Q1 Frequency Dropout Curve

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9.2.3 Application Curves (continued)

Time (400ns/DIV)

V_OUT= 5 V

F_SW= 2100 kHz

V_IN= 13.5 V

AUTO Mode

V_OUT= 5 V

I_OUT= 3.5 A

F_SW= 2100 kHz

V_IN= 13.5 V

AUTO Mode

I_OUT= 100 mA

图9-17. LM62435-Q1 Switching Waveform and V_OUTRipple

图9-18. LM62435-Q1 Switching Waveform and V_OUTRipple

V_OUT

(2 V/DIV)

I_INDUCTOR

(1 A/DIV)

V_PG

(5 V/DIV)

V_EN

(5 V/DIV)

Time (1 ms/DIV)

V_OUT= 5 V

I_OUT= 2.5 A to Short

Circuit

F_SW= 2100 kHz

V_IN= 13.5 V

FPWM Mode

V_OUT= 3.3 V

I_OUT= 3.25 A

F_SW= 2100 kHz

V_IN= 13.5 V

FPWM Mode

图9-19. LM62435-Q1 Start-up with 3.25 A

图9-20. LM62435-Q1 Short Circuit Protection

V_OUT

(5 V/DIV)

V_SW

(5 V/DIV)

I_L

(2 A/DIV)

Time (1.6 ms/DIV)

Time (20 ms/DIV)

V_OUT= 5 V

F_SW= 2100 kHz

FPWM Mode

V_IN= 13.5 V

V_OUT= 5 V

I_OUT= Short Circuit

F_SW= 2100 kHz

V_IN= 13.5 V

FPWM Mode

I_OUT= Short Circuit to 2.5 A

图9-21. LM62435-Q1 Short Circuit Recovery

图9-22. LM62435-Q1 Short Circuit Performance

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9.2.3 Application Curves (continued)

V_OUT= 3.3 V

F_SW= 2100 kHz

V_IN= 13.5 V

AUTO Mode

V_OUT= 5 V

F_SW= 2100 kHz

V_IN= 13.5 V

AUTO Mode

I_OUT= 1.5 A to 3.5 A to 1.5

A

T_R= T_F= 2µs

I_OUT= 1.5 A to 3.5 A to 1.5

A

T_R= T_F= 2µs

图9-23. LM62435-Q1 Load Transient

图9-24. LM62435-Q1 Load Transient

V_OUT= 5 V

F_SW= 400 kHz

I_OUT= 5 A

V_OUT= 5 V

F_SW= 400 kHz

Frequency Tested: 150 kHz to 30 MHz

*Tested on 6 A Variant

I_OUT= 5 A*

Frequency Tested: 30 MHz to 108 MHz

图9-26. Conducted EMI versus CISPR25 Limits (Yellow: Peak

Signal, Blue: Average Signal)

图9-25. Conducted EMI versus CISPR25 Limits (Yellow: Peak

Signal, Blue: Average Signal)

V_OUT= 5 V

F_SW= 400 kHz

I_OUT= 5 A

Frequency Tested: 150 kHz to 30 MHz

图9-27. Radiated EMI Rod versus CISPR25 Limits

V_OUT= 5 V

F_SW= 400 kHz

I_OUT= 5 A

Frequency Tested: 30 MHz to 300 MHz

图9-28. Radiated EMI Bicon Vertical versus CISPR25 Limits

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9.2.3 Application Curves (continued)

V_OUT= 5 V

F_SW= 400 kHz

I_OUT= 5 A

V_OUT= 5 V

F_SW= 400 kHz

I_OUT= 5 A

Frequency Tested: 30 MHz to 300 MHz

Frequency Tested: 300 MHz to 1 GHz

图9-29. Radiated EMI Bicon Horizontal versus CISPR25 Limits

图9-30. Radiated EMI Log Vertical versus CISPR25 Limits

744316220

L=2.2µH

VIN

IN+

IN-

GND

C_F5=2.2uF

C_F6=2.2uF

C_F3=2.2uF

CF4= 2.2uF

C_F1=470nF

CF2=470nF

F_SW= 400 kHz

Note: Measurements taken with

LM61460EVM with 6 A variant

V_OUT= 5 V

F_SW= 400 kHz

I_OUT= 5 A

Frequency Tested: 300 MHz to 1 GHz

图9-32. Recommended Input EMI Filter

图9-31. Radiated EMI Log Horizontal versus CISPR25 Limits

F_SW= 2100 kHz

V_OUT= 5 V

I_OUT= 5 A*

Frequency Tested: 150 kHz to 30 MHz

*Tested on 6 A Variant

F_SW= 2100 kHz

V_OUT= 5 V

I_OUT= 5 A

Frequency Tested: 30 MHz to 108 MHz

图9-33. Conducted EMI versus CISPR25 Limits (Yellow: Peak

Signal, Blue: Average Signal)

图9-34. Conducted EMI versus CISPR25 Limits (Yellow: Peak

Signal, Blue: Average Signal)

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9.2.3 Application Curves (continued)

74438356010

L=1µH

VIN

IN+

IN-

GND

C_F5=2.2uF

C_F6=2.2uF

C_F3=2.2uF

CF4= 2.2uF

C_F1=470nF

CF2=470nF

Note: All EMI measurements taken with 6 A Variant

F_SW= 2100 kHz

图9-35. Recommended Input EMI Filter

表9-5. BOM for Typical Application Curves

V_OUT

3.3 V

5 V

FREQUENCY

2100 kHz

R_FBB

R_T

C_OUT

C_IN+ C_HF

L

C_FF

3 x 22 µF

2 x 22 µF

2 x 4.7 µF + 2 x 100 nF

1.5 µH (MAPI 4020HT)

22 pF

43.2 kΩ

24.9 kΩ

6.04 kΩ

2100 kHz

42

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10 Power Supply Recommendations

The characteristics of the input supply must be compatible with Absolute Maximum Ratings and Recommended

Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required

input current to the loaded converter. The average input current can be estimated with 方程式13.

V_OUT‡ I_OUT

V_IN‡ ꢀ

I_IN=

(13)

where

• ηis the efficiency

If the converter is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic

input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to

the converter or tripping UVLO. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a

load transient is applied to the output. If the application is operating close to the minimum input voltage, this dip

can cause the converter to momentarily shutdown and reset. The best way to solve these kind of issues is to

reduce the distance from the input supply to the converter and use an aluminum input capacitor in parallel with

the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any

overshoot or undershoot at the input. A value in the range of 20 µF to 100 µF is usually sufficient to provide input

damping and help hold the input voltage steady during large load transients.

In some cases, a transient voltage suppressor (TVS) is used on the input of converters. One class of this device

has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not

recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the

output voltage of the converter, the output capacitors discharge through the device back to the input. This

uncontrolled current flow can damage the TVS and cause large input transients.

The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input

test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of

the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If

this scenario is considered likely, then a Schottky diode between the input supply and the output must be used.

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11 Layout

11.1 Layout Guidelines

The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

the EMI performance of the converter is dependent on the PCB layout, to a great extent. In a buck converter, the

most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in

图 11-1. This loop carries large transient currents that can cause large transient voltages when reacting with the

trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of

this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic

inductance. 图11-2 shows a recommended layout for the critical components for the circuit of the device.

• Place the input capacitor or capacitors as close as possible input pin pairs: VIN1 to PGND1 and VIN2 to

PGND2. Each pair of pins are adjacent, simplifying the input capacitor placement. With the VQFN-HR

package, there are two VIN/PGND pairs on either side of the package. This provides for a symmetrical layout

and helps minimize switching noise and EMI generation. Use a wide VIN plane on a lower layer to connect

both of the VIN pairs together to the input supply.

• Place bypass capacitor for VCC close to the VCC pin and AGND pins: This capacitor must routed with short,

wide traces to the VCC and AGND pins.

• Use wide traces for the CBOOT capacitor: Place the CBOOT capacitor as close to the device with short, wide

traces to the CBOOT and SW pins. It is important to route the SW connection under the device through the

gap between VIN2 and RBOOT pins, reducing exposed SW node area. If an RBOOT resistor is used, place

as close as possible to CBOOT and RBOOT pins. If high efficiency is desired, RBOOT and CBOOT pins can

be shorted. This short must be placed as close as possible to RBOOT and CBOOT pins as possible.

• Place the feedback divider as close as possible to the FB pin of the device: Place R_FBB, R_FBT, and C_FF, if

used, physically close to the device. The connections to FB and AGND through R_FBBmust be short and close

to those pins on the device. The connection to V_OUTcan be somewhat longer. However, this latter trace must

not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback

path of the converter. For fixed output variants, the FB pin must be directly routed to the output of the device.

• Layer of the PCB beneath the top layer with the IC must be a ground plane: This plane acts as a noise shield

and a heat dissipation path. Using the layer directly next to the IC reduces the inclosed area in the input

circulating current in the input loop, reducing inductance.

• Provide wide paths for V_IN, V_OUT, and GND: These paths must be wide and direct as possible to reduce any

voltage drops on the input or output paths of the converter and maximizes efficiency.

• Provide enough PCB area for proper heat sinking: Enough copper area must be used to ensure a low R_θJA

commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB

layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers

(recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note

,

that the package of this device dissipates heat through all pins. Wide traces must be used for all pins except

where noise considerations dictate minimization of area.

• Keep switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as

possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

44

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VIN1

VIN2

HS

FET

C_{IN_HF1}

C_{IN_HF2}

SW

LS

FET

PGND1

PGND2

图11-1. Input Current Loop

11.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane

provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control

circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass

capacitors. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected

directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching

frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be

constrained to one side of the ground planes. The other side of the ground plane contains much less noise and

must be used for sensitive routes.

TI recommends providing adequate device heat sinking by using vias near ground and V_INto connect to the

system ground plane or V_INstrap, both of which dissipate heat. Use as much copper as possible, for system

ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper

thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough

copper thickness and proper layout, provides low current conduction impedance, proper shielding, and lower

thermal resistance.

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11.2 Layout Example

GND POUR

VIAS to BIAS

VIA to Feedback

divider

V_OUT

C_OUT2

C_OUT1

GND POUR

INDUCTOR

Inductor

C_{IN_HF2}

C_{IN_HF1}

C_IN2

11

12

9

8

C_IN1

10

V_IN

7

V_IN

13

14

6

C_BOOT

1

2

3

4

5

R_BOOT

R_EN

IC

C_VCC

VCC

V_OUT

R_MODE

R_FBB

C_FF

GND POUR

R_FBT

GND POUR

R_FF

V_OUT

INNER GND PLANE œ LAYER 2

Top Trace/Pour

Inner GDN Plane

VIA to Signal Layer

VIA to GND

图11-2. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, LM61460-Q1 EVM User's Guide

• Texas Instruments, 30 W Power for Automotive Dual USB Type-C Charge Port Reference Design

• Texas Instruments, EMI Filter Components and Their Nonidealities for Automotive DC/DC Regulators

Technical Brief

• Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight Application Report

• Texas InstrumentsOptimizing the Layout for the TPS54424/TPS54824 HotRod QFN Package for Thermal

Performance Application Report

• Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC-DC Converters Application

Report

• Texas Instruments, Practical Thermal Design With DC/DC Power Modules Application Report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

HotRod^™, Hotrod^™, and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RJR0014A

VQFN-HR - 1 mm max height

SCALE 3.200

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

3.6

3.4

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 0.625

2X 0.5

2X 0.55

2X 1.6

2X 0.45

0.4

0.3

C A B

0.7

0.5

(0.2) TYP

2X

6

0.1

0.05

C

9

0.35

0.25

5

0.45

0.35

A

2X 0.525

2X 1.15

A

SYMM

10

2.2 0.05

0.9

0.7

PIN 1

ID

2X

11

1

0.45

4X

0.35

14

0.45

0.35

0.6

0.4

0.1

C A B

C

2X

0.05

PKG

0.1

C A B

C

0.3

0.2

6X

0.05

0.45

0.35

0.6

0.4

2X

0.1

C A B

C

7X

0.05

0.1

C A B

C

0.05

4223976/E 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

RJR0014A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (0.7)

PKG

2X (0.8)

(0.5)

14

2X

(0.35)

2X

(0.4)

2X

(0.4)

(0.625)

4X (1)

2X (1)

1

11

4X (0.4)

SEE SOLDER MASK

DETAIL

(2.4)

(0.3)

SYMM

(0.4)

10

(0.525)

(3.2)

(1)

(2.9)

(R0.05)

TYP

7X (0.7)

9

5

4X (R0.12)

6

6X (0.25)

(0.45)

(1.85)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK DEFINED

DEFINED

(PREFERRED)

SOLDER MASK DETAIL

4223976/E 03/2021

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RJR0014A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

PKG

(0.5)

14

2X (0.8)

2X (0.7)

2X

(0.35)

2X

(0.3)

(0.625)

2X

(0.4)

4X (1)

4X (0.35)

SYMM

EXPOSED METAL

TYP

2X (1)

1

11

2X (1.1)

(2.9)

(0.3)

2X (0.4)

10

(0.525)

(3.2)

EXPOSED

METAL

(0.35)

(1.65)

(R0.05)

TYP

7X (0.7)

9

5

4X (R0.17)

6

6X (0.25)

(0.45)

(1.85)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PADS 1, 5, 9 & 11:

90% PRINTED SOLDER COVERAGE BY AREA

SCALE: 25X

4223976/E 03/2021

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM62435APPQRJRRQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 3V 至 36V、3.5A、低 EMI 同步降压转换器 \| RJR \| 14 \| -40 to 150 开关转换器
文件：	总55页 (文件大小：2776K)
中文：	中文翻译
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LM62435APPQRJRRQ1 [TI]

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