LM63610DQDRRRQ1_技术文档

LM63610-Q1

SNVSBO7A – JULY 2020 – REVISED JULY 2021

LM63610-Q1 3.5-V to 36-V, 1-A, Automotive Step-down Voltage Converter

•

Automotive body electronics and lighting

Automotive ADAS

1 Features

•

AEC-Q100-qualified for automotive applications

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature

Functional Safety-Capable

– Documentation available to aid functional safety

system design

Supports automotive system requirements

– Input voltage range: 3.5 V to 36 V

– Short minimum on-time of 50 ns

– Good performance

Pseudo-random spread spectrum

Compatible with CISPR 25

– Low operating quiescent current of 23 µA

– Junction temperature range –40°C to +150°C

High design flexibility

– Pin selectable V_OUT: 3.3 V, 5 V, adjustable

1 V to 20 V

– Pin compatible with LM63615/LM63625/

LM63635 (1.5 A, or 2.5 A, and 3.25 A)

– Pin selectable frequency: 400 kHz, 2.1 MHz,

adjustable 250 kHz to 2200 kHz

– Pin selectable FPWM, AUTO, sync modes

– TSSOP: Thermally-enhanced package

– WSON: For space-constrained applications

Small solution size

3 Description

The LM63610-Q1 regulators are a family of easy-

to-use, synchronous, step-down DC/DC converters

designed for rugged automotive applications. The

LM63610-Q1 can drive up to 1 A of load current

from an input of up to 36 V. The converter has high

light load efficiency and output accuracy in a small

solution size. Features such as a RESET flag and

precision enable provide both flexible and easy-to-use

solutions for a wide range of applications. Automatic

frequency foldback at light load improves efficiency

while maintaining tight load regulation. Integration

eliminates many external components and provides

a pinout designed for simple PCB layout. Protection

features include thermal shutdown, input undervoltage

lockout, cycle-by-cycle current limit, and hiccup short-

circuit protection. The LM63610-Q1 is available in

both the HTSSOP 16-pin power package, with

PowerPAD^™, and the WSON 12-pin power package.

Please contact Texas Instruments for availability of

the WSON package.

•

Device Information

PART NUMBER

LM63610-Q1

PACKAGE⁽¹⁾

BODY SIZE (NOM)

5.00 mm × 4.00 mm

3.00 mm × 3.00 mm

•

HTSSOP (16)

WSON (12)

– Highly integrated solution

LM63610-Q1

– Low component count

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

•

Automotive infotainment and cluster

95

90

85

80

75

70

65

8V

13.5V

60

55

18V

24V

0.001

0.01

0.1

Output Current (A)

1

2

eff_

Typical Efficiency At 5-V Vout, 2.1 MHz

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM63610-Q1

SNVSBO7A – JULY 2020 – REVISED JULY 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................8

7.6 Timing Characteristics...............................................10

7.7 Switching Characteristics..........................................11

7.8 System Characteristics............................................. 12

7.9 Typical Characteristics..............................................13

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................14

8.4 Device Functional Modes..........................................19

9 Application and Implementation..................................23

9.1 Application Information............................................. 23

9.2 Typical Application.................................................... 23

9.3 What to Do and What Not to Do............................... 34

10 Power Supply Recommendations..............................35

11 Layout...........................................................................36

11.1 Layout Guidelines................................................... 36

11.2 Layout Example...................................................... 38

12 Device and Documentation Support..........................39

12.1 Documentation Support.......................................... 39

12.2 Receiving Notification of Documentation Updates..39

12.3 Support Resources................................................. 39

12.4 Trademarks.............................................................39

12.5 Electrostatic Discharge Caution..............................39

12.6 Glossary..................................................................39

13 Mechanical, Packaging, and Orderable

Information.................................................................... 39

4 Revision History

Changes from Revision * (July 2020) to Revision A (July 2021)

Page

•

Added functional safety bullet to the Features section....................................................................................... 1

Updated the values in Figure 9-1 .....................................................................................................................23

Updated the calculated values for the output capacitance............................................................................... 26

Updated Table 9-3 to reflect the maximum current (1 A)..................................................................................30

2

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5 Device Comparison Table

DEVICE

SAMPLE ORDER NUMBER

OPTION

PACKAGE

RATED CURRENT

BODY SIZE (NOM)

5.00 mm × 4.00 mm

3.00 mm × 3.00 mm

PWP0016D

(HTSSOP)

LM63610DQ

See the orderable addendum at

1 A

the end of the data sheet.

DRR0012

(WSON)

LM63610DQ

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6 Pin Configuration and Functions

SW

1

16

PGND

N/C

SW

2

3

15

14

CBOOT

4

5

VCC

RT

13

12

VIN

DAP

(17)

VIN

VSEL

SYNC/MODE

RESET

EN

6

7

11

10

AGND

8

9

FB

Figure 6-1. PWP Package 16-Pin HTSSOP With PowerPAD Top View

SW

1

12

VIN

2

3

4

11 N/C

10 EN

BOOT

VCC

RT

PGND/DAP

13

AGND

9

8

FB

VSEL

5

6

SYNC/

MODE

RESET

7

Figure 6-2. WSON Package 12-Pin DRR0012 With PowerPad Top View

4

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Table 6-1. Pin Functions

TSSOP WSON

DESCRIPTION

NAME

TYPE

1, 2

3

1

2

SW

P

Regulator switch node. Connect to power inductor.

Boot-strap supply voltage for internal high-side driver. Connect a high-quality, 220-nF

capacitor from this pin to the SW pin.

CBOOT

VCC

P

A

Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect

to external loads. Can be used as logic supply for regulator functions. Connect a high-

quality, 1-µF capacitor from this pin to PGND.

4

5

3

4

Frequency programming input. Tie to VCC for 400 kHz; or to AGND for 2.1 MHz or

connect to an R_Ttiming resistor. See the Switching Frequency Selection section for

details. Do not float.

RT

A

Output voltage select input. Tie to VCC for 5-V output or to AGND for 3.3-V output;

connect to a 10-kΩ for an adjustable output. See the Output Voltage Selection section for

details. Do not float.

6

7

5

6

VSEL

SYNC/MODE

RESET

FB

A

G

A

Mode selection and synchronization input. Tie to VCC for FPWM mode; or to AGND for

AUTO mode; or supply an external synchronizing clock to this input.

Open drain power-good flag output. Connect to suitable voltage supply through a current

limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can

be open when not used.

8

7

Feedback input to regulator. Connect to output capacitor for 5-V or 3.3-V fixed option; or

tap point of feedback voltage divider for ADJ option. Do not float; do not ground.

9

8

Analog ground for regulator and system. Ground reference for internal references and

logic. All electrical parameters are measured with respect to this pin. Connect to system

ground on PCB.

10

11

9

AGND

Enable input to regulator. High = ON, Low = OFF. Can be connected directly to VIN. Do

not float.

10

EN

Input supply to regulator. Connect a high-quality bypass capacitors directly to this pin and

PGND.

12, 13

14

12

11

13

VIN

NC

P

-

No internal connection to device

Power ground terminal. Connect to system ground and AGND. Connect to bypass

capacitor with short wide traces.

15, 16

17

PGND

DAP

G

Electrical ground and heat sink connection. Solder directly to system ground plane.

A = Analog, P = Power, G = Ground

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended junction temperature range⁽¹⁾

PARAMETER

MIN

–0.3

-6

MAX

40

UNIT

V

VIN to PGND (HTSSOP package)

VIN to PGND (WSON package)

EN to AGND (HTSSOP package)

EN to AGND (WSON package)

SYNC/MODE to AGND

42

V

40

V

42

V

6

V

VOUT_SEL and RT to AGND

RESET to AGND

5.5

16

V

FB to AGND (Fixed VOUT mode)

FB to AGND (Adjustable VOUT mode)

AGND to PGND

16

V

5.5

0.3

40

V

SW to PGND for transients of less than 10ns (HTSSOP package)

V

SW to PGND for transients of less than 10ns (WSON package)

-6

42

V

BOOT to SW

–0.3

–40

–65

5.5

150

V

VCC to AGND

V

T_J

Junction temperature

Storage temperature

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾HBM ESD

Clasification Level 2

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC Q100-011 CDM ESD

clasiffication Level C5

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended junction temperature range of –40 °C to 150 °C (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

SYNC/MODE, VOUT_SEL and RT to AGND

RESET

0

5

V

0

(2)

V_OUT

1

20

V_CC

2.7

5.25

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see the Electrical Characteristics Table.

(2) Under no conditions should the output voltage be allowed to fall below zero volts.

6

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7.4 Thermal Information

LM636x5

THERMAL METRIC⁽¹⁾

DRR0012 (WSON)

HTSSOP (PWP)

UNIT

12 PINS

47.4

44.6

20.7

0.7

16 PINS

43.1

35.4

18.5

0.9

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

20.7

6.3

18.5

4.5

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The value of R_ΘJAgiven in this table is only valid for comparison with other packages and can not be used for design purposes.

These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the

performance obtained in an actual application. For design information please see the Maximum Ambient Temperature section.

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7.5 Electrical Characteristics

Limits apply over the junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated. Minimum and maximum

limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at

T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN= 13.5

V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

V_IN

I_Q

Minimum operating input voltage

3.5

40

V

Non-switching input current; measured at

VIN pin⁽²⁾

V_EN= 3.3 V_FB= 1.2x regulation point

V_EN= 0

23

µA

Shutdown quiescent current; measured at

VIN pin

I_SD

5.3

10

µA

V_{UVLO_R}Minimum operating voltage threshold

V_{UVLO_F}Minimum operating voltage threshold

Rising V_IN, I_VCC= 0

Falling V_IN, I_VCC= 0

3.5

3

V

2.6

0.5

Pull down current on SW when OVP is

I_POR

V_EN= 0 V_SW= 5 V

1.5

2.5

mA

triggered

ENABLE (EN PIN)

V_EN-VCCVCC enable voltage

V_ENrising

V_ENfalling

V_EN= 13.5 V

0.85

1.5

V

V_EN-H

V_EN-L

Precision enable high level for VOUT

Precision enable low level for VOUT

Enable input leakage current

1.425

0.9

1.575

150

0.94

0.2

V

I_LKG-EN

–100

nA

OUTPUT VOLTAGE SELECTION (VSEL PIN)

Resistor range for valid adjustable output

R_SEL-ADJ

8

50

kΩ

voltage selection at startup

INTERNAL LDO

V_CC

Internal VCC voltage

VCC Clamp Voltage

6 V ≤ V_IN≤ Max Operating V_IN

1mA sourced into VCC

4.75

5.25

5

5.25

5.8

V

V_CCM

5.55

VOLTAGE REFERENCE (FB PIN)

V_{FB_ADJ}Feedback voltage

V_IN= 3.5-Max Operating V_IN

V_IN= 5.5-Max Operating V_IN

V_IN= 3.8-Max Operating V_IN

FB = 1.0 V

0.985

4.925

3.25

1

5

1.015

5.075

3.35

100

3.4

V

V_{FB_5V}

V_{FB_3p3V}Feedback voltage

I_{FB_ADJ}Input leakage current at FB PIN

I_{FB_5V}Input leakage current at FB PIN

Feedback voltage

3.3

0.2

2.89

1.67

V

nA

µA

FB = 5.0 V

I_{FB_3p3V}Input leakage current at FB PIN

FB = 3.3V

2

CURRENT LIMITS

I_SC

Short circuit high side current Limit

1.9

1.5

2.25

1.8

2.7

2.12

0.7

A

I_LS-LIMITLow side current limit

1-A Version

I_PEAK-MINMinimum Peak Inductor Current

0.375

–1.2

42%

I_L-NEG

Negative current limit

–1.49

37%

–0.75

47%

V_HICCUPHiccup threshold on FB pin

POWER GOOD ( RESET PIN)

V_RESET-

RESET upper threshold - Rising

% of FB voltage

% of FB voltage,

110%

91%

1.1%

0.7

112%

93%

115%

95%

HIGH

V_RESET-

RESET lower threshold - Falling

LOW

V_RESET-

RESET hysteresis

1.8%

2.5%

HYS

V_{RESET_V}Minimum input voltage for proper PG

Measured when V_RESET< 0.4 V with

10kOhm pullup to external 5-V

1.04

60

1.25

150

V

function

ALID

R_RESET

RESET ON resistance,

V_EN= 5.0 V, 1mA pull-up current

Ω

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7.5 Electrical Characteristics (continued)

Limits apply over the junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated. Minimum and maximum

limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at

T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN= 13.5

V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_RESET

RESET ON resistance,

V_EN= 0 V, 1mA pull-up current

40

125

Ω

OSCILLATOR (SYNC/MODE PIN)

V_SYNC-

Sync input and mode high level threshold

1.5

1.8

V

HIGH

V_SYNC-

Sync input hysteresis

0.355

HYS

V_SYNC-

Sync input and mode low level threshold

Pulldown on MODE pin

0.8

1.15

100

V

LOW

R_SYNC

kΩ

MOSFETS(2)

R_DS-ON-

High-side MOSFET on-resistance

Load = 1 A

93

61

mΩ

V

HS

R_DS-ON-

Low-side MOSFET on-resistance

Cboot - SW UVLO threshold⁽³⁾

LS

V_CBOOT-

2.13

UVLO

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range verified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) When the voltage across the C_BOOTcapacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor

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7.6 Timing Characteristics

Limits apply over the junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated. Minimum and maximum

limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at

T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN= 13.5

V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT LIMITS AND HICCUP

Number of switching current limit

N_OC

continuous events before hiccup is

tripped

128

Cycles

t_OC

Overcurrent hiccup retry delay time

70

11

104

16

140

22

ms

Time after soft start done timer before

hiccup current protection is enabled

t_{OC_active}

SOFT START

t_SS

Internal soft-start time

1

5

1.6

8

2.2

11

ms

t_{SS_DONE}Soft-start done timer

POWER GOOD (/RESET PIN) and OVERVOLTAGE PROTECTION

t_dg

RESET edge deglitch delay

RESET active time

10

2

17

3

30

5

µs

t_RISE-

Time FB must be valid before RESET is

released.

ms

DELAY

OSCILLATOR (SYNC/MODE PIN)

t_{ON_OFF-}

Sync input ON and OFF-time

100

ns

SYNC

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

10

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7.7 Switching Characteristics

Limits apply over the junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated. Minimum and maximum

limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at

T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN= 13.5

V.⁽¹⁾

PARAMETER

PWM LIMITS (SW PINS)

t_ON-MINMinimum switch on-time

t_OFF-MINMinimum switch off-time

t_ON-MAXMaximum switch on-time

OSCILLATOR (RT and SYNC PINS)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN=12 V, I_SW= 1 A

50

7

75

100

10

ns

µs

V_IN= 5 V

HS timeout in dropout

5.4

f_OSC

f_ADJ1

f_ADJ2

f_SYNC

Internal oscillator frequency

RT = GND

1.85

360

2.1

400

2.35

440

MHz

kHz

RT = VCC

RT = 66.5 kΩ, 1%

RT = 7.15 kΩ, 1%

240

2200

Synchronization Frequency Range

250

2200

SPREAD SPECTRUM

Spread spectrum pseudo random pattern

frequency

f_{PSS (2)}

FOSC= 2.1 MHz

0.98

Hz

Spread of internal oscillator with Spread

Spectrum Enabled

f_SPREAD

LM636x5DQ Option (HTSSOP package)

LM636x5DQ Option (WSON package)

–3.6%

–5%

3.6%

5%

Spread of internal oscillator with Spread

Spectrum Enabled

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

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7.8 System Characteristics

The following specifications apply only to the typical applications circuit with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to

the case of typical components over the temperature range of T_J= –40°C to 150°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 0 A, R_FBT

= 1 MΩ

I_SUPPLY

V_DROP

D_MAX

Input supply current when in regulation

23

0.95

150

µA

V

Dropout voltage; (V_IN– V_OUT

)

V_OUT= 5 V, I_OUT= 1 A, f_SW= 1850 kHz

V_OUT= 5 V, I_OUT= 1 A, V_OUT-1% of

regulation, f_SW= 140 kHz

mV

Maximum switch duty cycle⁽²⁾

V_IN= V_OUT= 12 V_OUT= 1 A

98%

VOLTAGE REFERENCE (FB PIN)

V_IN= 7 V to 30 V , I_OUT= 1 A to full load,

CCM

(1)

V_OUT

V_OUT= 5 V

V_OUT= 3.3 V

–1.5%

1.5%

2.5%

1.5%

2.5%

V_IN= 7 V to 30 V, I_OUT= 0 A to full load,

AUTO mode

V_IN= 3.8 V to 30 V , I_OUT= 1 A to full

load, CCM

(1)

V_OUT

V_IN= 3.8 V to 30 V , I_OUT= 0 A to full

load, AUTO mode

Delay from sync clock staying low to PFM

entry

t_SYNC-L

t_SYNC-H

100

ns

Delay from sync clock staying high to

default frequency

THERMAL SHUTDOWN

T_SD

Thermal shutdown temperature

Shutdown temperature

Recovery temperature

155

163

150

175

°C

T_SDR

(1) Deviation is with respect to V_IN=13.5 V, I_OUT= 1 A.

(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: f_MIN

1 / (t_ON-MAX+ T_OFF-MIN). D_MAX= t_ON-MAX/(t_ON-MAX+ t_OFF-MIN).

=

12

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7.9 Typical Characteristics

Unless otherwise specified the following conditions apply: T_A= 25°C, V_IN= 13.5 V

12

10

8

6

4

-40C

25C

125C

DN

UP

2

0

5

10

15

20 25

Input Voltage (V)

30

35

40

INPUT VOLTAGE (1V/DIV)

OFF_

EN = 0 V

I_OUT= 1 mA

See Figure 9-23

Figure 7-1. Input Supply Current in Shutdown

Mode

Figure 7-2. UVLO Thresholds

600

575

550

525

500

475

450

425

400

-40C

25C

125C

5

10

15

20 25

Input Voltage (V)

30

35

40

Ipea

I_OUT= 0 A

V_OUT= 5 V

See Figure 9-23

ƒ_SW= 2100 kHz

Figure 7-3. I_PEAK-MINfor LM63610

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8 Detailed Description

8.1 Overview

The LM63610-Q1 devices are synchronous peak-current-mode buck regulators designed for a wide variety of

automotive applications. The regulators automatically switch modes between PFM and PWM, depending on

load. At heavy loads, the devices operate in PWM at a constant switching frequency. At light loads, the mode

changes to PFM with diode emulation, allowing DCM. This reduces the input supply current and keeps efficiency

high. The device features the following:

•

Adjustable switching frequency

Forced PWM mode (FPWM)

Frequency synchronization

Selectable output voltage

The RESET output allows easy system sequencing. In addition, internal compensation reduces design time and

requires fewer external components than externally compensated regulators.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Sync/Mode Selection

The device features selectable operating modes through the SYNC/MODE input. Table 8-1 shows the selection

programming. Mode changes can be made on the fly anytime after the device is powered up. It is not

recommended that this input be allowed to float, however, an internal 100 kΩ pulls the input to ground if left

floating. The value of this internal resistor and the logic thresholds for this input can be found in the Table 8-1.

See Device Functional Modes for details of the operating modes.

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Table 8-1. Mode Selection Settings

SYNC/MODE INPUT

VCC

MODE

FPWM

AUTO

AGND

Synchronizing clock

FPWM; synchronized to external clock

AUTO

Float (not recommended)

8.3.2 Output Voltage Selection

The output voltage of the device is set by the condition of the VSEL input. The condition of this input is tested

when the device is first enabled. Once the converter is running, the voltage selection is fixed and cannot be

changed until the next power-on cycle. Table 8-2 shows the selection programming. The device contains an

integrated voltage divider connected to the FB input. The converter regulates the voltage on the FB input to 5

V, 3.3 V, or 1 V, as selected. In the ADJ mode, the voltage on the FB input is regulated to 1 V and the internal

divider is disabled. In this case, an external voltage divider is used to set the desired output voltage anywhere

within the recommended operating range. The ADJ mode is programmed by connecting a 10 kΩ from the VSEL

input to ground. Although not recommenced, if this input is left floating, the device enters the ADJ mode. See

Setting the Output Voltage for details of selecting the FB divider resistors.

See the Specifications for ensured specifications regarding the accuracy of the FB voltage and input current to

the FB pin.

Providing internal voltage dividers for the 5-V and 3.3-V modes saves external components, reducing both board

space and component cost. The relatively large values of the internal dividers reduce the load on the output,

helping to improve the light load efficiency of the converter. In addition, since the divider is inside the device, it is

less likely to pick up externally generated noise.

Table 8-2. Output Voltage Settings

VSEL INPUT

VCC

OUTPUT VOLTAGE

5 V

3.3 V

ADJ

AGND

10 kΩ to AGND

Float (not recommended)

8.3.3 Switching Frequency Selection

The switching frequency is set by the condition of the RT input. The condition of this input is tested when the

device is first enabled. Once the converter is running, the switching frequency selection is fixed and cannot be

changed until the next power-on cycle. Table 8-3 shows the selection programming. In the adjustable frequency

mode, the switching frequency can be set between 250 kHz and 2200 kHz by proper selection of the value of

R_T. The curve in Figure 8-1 indicates the required resistor value for R_Tto set a desired switching frequency. It

is not recommended that this input be allowed to float; the switching action ceases with no generated output

voltage under this condition.

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15770

RT =

f_SW

(1)

where

•

RT = value of RT timing resistor in kΩ

ƒ_SW= switching frequency in kHz

Table 8-3. Switching Frequency Settings

RT INPUT

VCC

SWITCHING FREQUENCY

400 kHz

AGND

2100 kHz

R_Tto AGND

Float (not recommended)

Adjustable according to R_Tvalue

No switching

80

70

60

50

40

30

20

10

0

200

600

1000

1400

1800

2200

Switching Frequency (kHz)

C002

Figure 8-1. Switching Frequency versus R_T

8.3.3.1 Spread Spectrum Option

The LM63610-Q1 is available with a spread spectrum clock dithering feature. This feature uses a pseudo-

random pattern to dither the internal clock frequency. The pattern repeats at a 0.98-Hz rate while the depth of

modulation is ±3%.

The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading

emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems

containing the LM63610-Q1 devices, low frequency conducted emissions from the first few harmonics of the

switching frequency can be easily filtered. A more difficult design criterion is reduction of emissions at higher

harmonics which fall in the FM band. These harmonics often couple to the environment through electric fields

around the switch node. The LM63610-Q1 devices use a ±3% spread of frequencies which spreads energy

smoothly across the FM band but is small enough to limit subharmonic emissions below its switching frequency.

8.3.4 Enable and Start-up

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use

of an external voltage divider to provide an adjustable input UVLO (see External UVLO). Applying a voltage

greater than V_EN-VCCcauses the device to enter standby mode, powering the internal VCC, but not producing an

output voltage. Increasing the EN voltage to V_EN-Hfully enables the device, allowing it to enter start-up mode and

begin the soft-start period. When the EN input is brought below V_EN-L, the regulator stops running and enters

standby mode. Further decrease in the EN voltage to below V_EN-VCCcompletely shuts down the device. Figure

8-2 shows this behavior. The EN input can be connected directly to VIN if this feature is not needed. This input

must not be allowed to float. The values for the various EN thresholds can be found in Specifications .

The LM63610-Q1 uses a reference-based soft start that prevents output voltage overshoots and large inrush

currents as the regulator is starting up. Once EN goes high, there is a delay of about 1 ms before the soft-start

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period begins. The output voltage begins to rise and reaches the final value in about 1.5 ms (t_ss). After a delay

of about 3 ms (t_rise-delay), the RESET flag goes high. During start-up, the device is not allowed to enter FPWM

mode until the t_ss-donetime has elapsed. This time is measured from the rising edge of EN.

EN

V_EN-H

V_EN-L

V_EN-VCC

VCC

5V

0

VOUT

V_OUT

0

Figure 8-2. Precision Enable Behavior

8.3.5 RESET Flag Output

The RESET flag function (RESET output pin) of the LM63610-Q1 devices can be used to reset a system

microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault

conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents

false flag operation for short excursions of the output voltage, such as during line and load transients. Output

voltage excursions lasting less than t_dgdo not trip the RESET flag. Once the FB voltage has returned to

the regulation value and after a delay of t_rise-delay, the RESET flag goes high. RESET operation can best be

understood by reference to Figure 8-3 and Figure 8-4.

The RESET output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic

supply. It can also be pulled up to either VCC or V_OUTthrough an appropriate resistor, as desired. Values of

pullup resistor in the range of 10 kΩ to 100 kΩ are reasonable. If this function is not needed, the RESET pin can

be left floating. When EN is pulled low, the flag output is also forced low. With EN low, RESET remains valid as

long as the input voltage is ≥ 1.2 V (typical). Limit the current into the RESET flag pin to about 5 mA D.C. The

maximum current is internally limited to about 50 mA when the device is enabled and about 65 mA when the

device is disabled. The internal current limit protects the device from any transient currents that can occur when

discharging a filter capacitor connected to this output.

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V_OUT

V_RESET-HIGH

V_RESET-HYS

V_RESET-LOW

RESET

High = Power Good

Low = Fault

Figure 8-3. Static RESET Operation

Glitches do not cause false operation nor reset timer

V_OUT

V_RESET-LOW

< t_dg

t

RESET

t

T_rise-delay

t_dg

T_rise-delay

Figure 8-4. RESET Timing Behavior

8.3.6 Undervoltage Lockout and Thermal Shutdown and Output Discharge

The LM63610-Q1 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC

pin). When V_INreaches about (V_POR-R), the device is ready to receive an EN signal and start up. When V_IN

falls below (V_POR-F), the device shuts down, regardless of EN status. Since the LDO is in dropout during these

transitions, the above values roughly represent the VCC voltage levels during the transitions.

Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction

temperature reaches about 163°C, the device shuts down; re-start occurs when the temperature falls to about

150°C. An extended input voltage UVLO can also be accomplished as shown in External UVLO.

The LM63610-Q1 features an output voltage discharge FET connected from the SW pin to ground. This FET

is activated when the EN input is below V_EN-L, or when the output voltage exceeds V_RESET-HIGH. This way, the

output capacitors are discharged through the power inductor. At output voltages above about 5 V, the discharge

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current is approximately constant at I_PORor about 1.4 mA. Below this voltage, the FET characteristic looks

approximately resistive at a value of 2.5 kΩ.

8.4 Device Functional Modes

8.4.1 Overview

In typical usage, the device is put in AUTO mode (SYNC/MODE pin = ground). In AUTO mode, the device

moves between PWM and PFM as the load changes. At light loads, the regulator operates in PFM where the

switching frequency is varied to regulate the output voltage. At higher loads, the mode changes to PWM with the

switching frequency set by the condition of the RT pin (see Switching Frequency Selection).

In PWM mode, the regulator operates as a current mode, the constant frequency converter using PWM to

regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a

constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line

and load regulation and low output voltage ripple.

In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.

The duration of the burst depends on how long it takes the inductor current to reach I_PEAK-MIN. The periodicity

of these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency

(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current

required to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger

output voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light

loads. See Application Curves for output voltage variation with load in PFM mode. Figure 8-5 and Figure 8-6

show the typical switching waveforms in PFM and PWM.

There are four cases where the switching frequency does not conform to the condition set by the RT pin:

•

Light load operation (AUTO mode)

Dropout

Minimum on-time operation

Current limit

Under all of these cases, the switching frequency folds back, meaning it is less than that programmed by the

RT control pin. During these conditions, by definition, the output voltage remains in regulation, except for current

limit operation.

When the device is placed in the forced PWM mode (FPWM), the switching frequency remains constant as

programmed by the RT pin for all load conditions. This mode essentially turns off the light-load PFM frequency

foldback mode detailed in Light Load Operation. See Sync/Mode Selection and Sync/FPWM Operation for

details.

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Switch Voltage

5 V/DIV

Switch Voltage

5 V/DIV

0

Inductor Current

200 mA/DIV

Inductor Current

200 mA/DIV

5 µs/DIV

0

100 ns/DIV

Figure 8-6. Typical PWM Switching Waveforms

Figure 8-5. Typical PFM Switching Waveforms V_IN

12 V, V_OUT= 5 V, I_OUT= 10 mA

=

FPWM V_IN= 12 V, V_OUT= 5 V, I_OUT= 0 A, ƒ_SW

2100 kHz

=

8.4.2 Light Load Operation

During light load operation, the device is in PFM mode with DEM. This provides high efficiency at the lower

load currents. The actual switching frequency and output voltage ripple depend on the input voltage, output

voltage, and load. The output current at which the device moves in and out of PFM can be found in Application

Curves. The output current for mode change depends on the input voltage, inductor value, and the programmed

switching frequency. The curves apply for the BOM shown in Table 9-3. At higher programmed switching

frequencies, the load at which the mode change occurs is greater. For applications where the switching

frequency must be known for a given condition, the transition between PFM and PWM must be carefully tested

before the design is finalized. Alternatively, the mode can be set to FPWM.

8.4.2.1 Sync/FPWM Operation

The forced PWM mode (FPWM) can be used to turn off AUTO mode and force the device to switch at the

frequency programmed by the RT pin, even for small loads. This has the disadvantage of lower efficiency at light

loads.

When a valid clock signal is present on the SYNC/MODE input, the switching frequency is locked to the external

clock. The device mode is also FPWM. The mode can be changed dynamically by the system. See Figure 8-7

and Figure 8-8 for typical examples of SYNC/MODE function changes.

Sync Burst

SYNC/MODE

Input

0

Output Voltage

50 mV/DIV

Output Voltage

50 mV/DIV

5 V

0

5 V

0

Inductor Current

500 mA/DIV

Inductor Current

500 mA/DIV

200 µs/DIV

2 ms/DIV

Figure 8-7. Typical Transition from FPWM to AUTO

Mode V_IN= 12 V, V_OUT= 5 V, I_OUT= 1 mA

Figure 8-8. Typical Transition from Sync Mode to

FPWM Mode V_IN= 12 V, V_OUT= 5 V, I_OUT= 1 mA

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8.4.3 Dropout Operation

The dropout performance of any buck regulator is affected by the R_DSONof the power MOSFETs, the DC

resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage

level approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value

(see Specifications). Beyond this point, the switching can become erratic and the output voltage can fall out of

regulation. To avoid this problem, the LM63610-Q1 automatically reduces the switching frequency to increase

the effective duty cycle and maintain regulation. There are two definitions of dropout voltage used in this data

sheet. For both definitions, the dropout voltage is the difference between the input and output voltage under

a specific condition. For the first definition, the difference is taken when the switching frequency has dropped

to 1850 kHz (obviously this applies to cases where the nominal switching frequency is >1850 kHz). For this

condition, the output voltage is within regulation. For the second definition, the difference is taken when the

output voltage has fallen by 1% of the nominal regulation value. In this condition, the switching frequency has

reached the lower limit of about 130 kHz. See Application Curves for details on these characteristics. Typical

overall dropout characteristics can be found in Figure 8-9.

5

1.5 A

2.5 A

4.8

4.6

4.4

4.2

4

3.8

3.6

3.4

3.5

4

4.5

5

5.5 6

Input Voltage (V)

6.5

7

7.5

8

drop

Figure 8-9. Overall Dropout Characteristic V_OUT= 5 V, Refer to LM63615/25 Data Sheet

8.4.4 Minimum On-time Operation

Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking

times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum

conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend

the minimum controllable duty cycle, the LM63610-Q1 automatically reduces the switching frequency when the

minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage

at the maximum input voltage. Use Equation 2 to find an estimate for the approximate input voltage for a given

output voltage before frequency foldback occurs. The values of t_ONand ƒ_SWcan be found in Specifications. As

the input voltage is increased, the switch on-time (duty-cycle) reduces to regulate the output voltage. When the

on-time reaches the limit, the switching frequency drops while the on-time remains fixed. This relationship is

highlighted in ƒ_SWvs V_INcurves in Application Curves.

V_OUT

V

Ç

IN

t_ON∂ f_SW

(2)

8.4.5 Current Limit and Short-Circuit Operation

The LM63610-Q1 incorporates both peak and valley inductor current limits to provide protection to the device

from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor

current run-away during short circuits on the output, while both peak and valley limits work together to limit the

maximum output current of the converter. A "hiccup" type mode is also incorporated for sustained short circuits.

Finally, a zero current detector is used on the low-side power MOSFET to implement DEM at light loads (see the

Glossary). The nominal value of this limit is about 0 A.

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As the device is overloaded, a point is reached where the valley of the inductor current cannot reach below

I_LS-LIMITbefore the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing

the switching frequency to drop. Further overload causes the switching frequency to continue to drop, but the

output voltage remains in regulation. As the overload is increased, both the inductor current ripple and peak

current increases until the high-side current limit, I_SC, is reached. When this limit is activated, the switch duty

cycle is reduced and the output voltage falls out of regulation. This represents the maximum output current from

the converter and is given approximately by Equation 3. The output voltage and switching frequency continue to

drop as the device moves deeper into overload while the output current remains at approximately I_OMAX

.

I_SC+ I_LS-LIMIT

I_OMAX

ö

2

(3)

If a severe overload or short circuit causes the FB voltage to fall below V_HICCUP, the convert enters "hiccup"

mode. V_HICCUPrepresents about 40% of the nominal programmed output voltage. In this mode, the device stops

switching for t_OC, or about 100 ms and then goes through a normal restart with soft start. If the short-circuit

condition remains, the device runs in current limit for a little longer than t_{OC_active}, or about 23 ms, and then

shuts down again. This cycle repeats, as shown in Figure 8-10 as long as the short-circuit condition persists.

This mode of operation reduces the temperature rise of the device during a sustained short on the output. The

output current in this mode is approximately 20% of I_OMAX. Once the output short is removed and the t_OCdelay is

passed, the output voltage recovers normally as shown in Figure 8-11.

See Figure 8-12 for the overall output voltage versus output current characteristic.

Short Removed

Short Applied

Output Voltage

2 V/DIV

0

Inductor Current

2 A/DIV

Inductor Current

500 mA/DIV

50 ms/DIV

20 ms/DIV

0

Figure 8-11. Short-Circuit Transient and Recovery;

Refer to LM63615/25 Data Sheet

Figure 8-10. Inductor Current Burst in Short-Circuit

Mode; Refer to LM63615/25 Data Sheet

Output

Voltage

V_OUT

0.4· V_OUT

Output

Current

I_OMAX

0.2· I_OMAX

Figure 8-12. Output Voltage versus Output Current in Current Limit

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LM63610-Q1 step-down DC-to-DC converters are typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 1 A. The following design procedure can be used to select

components for the device.

Note

In this data sheet, the effective value of capacitance is defined as the actual capacitance under

D.C. bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic

capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a

large voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias,

the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this

regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum

effective capacitance up to the required value. This can also ease the RMS current requirements on

a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be

made to ensure that the minimum value of effective capacitance is provided.

9.2 Typical Application

Figure 9-1 shows a typical application circuit for the device. This device is designed to function over a wide

range of external components and system parameters. However, the internal compensation is optimized for a

certain range of external inductance and output capacitance. As a quick start guide, see for typical component

values.

L

V_OUT

5 V

1 A

V_IN

SW

VIN

6 V to 36 V

4.7 µH

C_IN

4.7 µF

C_BOOT

C_OUT

1x 10 µF

EN

C_HF

220 nF

BOOT

0.22 µF

VSEL

RT

SYNC/

MODE

FB

VCC

PGND AGND

RESET

100 kΩ

C_VCC

1 µF

RESET

Figure 9-1. Example Application Circuit V_IN= 12 V, V_OUT= 5 V, I_OUT= 1 A, ƒ_SW= 2.1 MHz

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Table 9-1. Typical External Component Values for 1 A Output Current

ƒ_SW

TYPICAL⁽²⁾

C_OUT

MINIMUM⁽²⁾

C_OUT

V_OUTL (µH)⁽¹⁾

VSEL

RT

C_IN

C_BOOT

(kHz)

400

2100

400

3.3

5

10

4.7

10

4 × 10 µF

2 × 10 µF

4 × 10 µF

2 × 10 µF

1 × 10 µF

2 × 10 µF

1 × 10 µF

AGND

VCC

AGND

VCC

4.7 µF + 220 nF

220 nF

1 µF

2100

5

4.7

VCC

AGND

(1) See the Inductor Selection section.

(2) See the Output Capacitor Selection section.

9.2.1 Design Requirements

Table 9-2 provides the parameters for the detailed design procedure:

Table 9-2. Detailed Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

12 V (6 V to 36 V)

Output voltage

5 V

Maximum output current

Switching frequency

0 A to 1 A

2.1 MHz

9.2.2 Detailed Design Procedure

The following design procedure applies to Figure 9-1 and Table 9-2.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence, a

more compact design. 2100 kHz was chosen for this example.

9.2.2.2 Setting the Output Voltage

The output voltage of the LM63610-Q1 is set by the condition of the VSEL input. This example requires a 5-V

output, so the VSEL input is connected to VCC and the FB input is connected directly to the output capacitor.

For cases where the desired output voltage is other than 5 V or 3.3 V, an external feedback divider is required.

As shown in Figure 9-2, the divider network is comprised of R_FBTand R_FBB, and closes the loop between the

output voltage and the converter. In this case, a 10-kΩ resistor is connected from the VSEL input go ground.

The converter regulates the output voltage by holding the voltage on the FB pin equal to the internal reference

voltage, 1 V. The resistance of the divider is a compromise between excessive noise pickup and excessive

loading of the output. Smaller values of resistance reduce noise sensitivity, but also reduce the light-load

efficiency. The recommended value for R_FBTis 100 kΩ with a maximum value of 1 MΩ. If 1 MΩ is selected for

R_FBT, then a feedforward capacitor must be used across this resistor to provide adequate loop phase margin

(see C_FFSelection). Once R_FBTis selected, Equation 4 is used to select R_FBB. V_REFis nominally 1 V.

R_FBT

R_FBB

=

»

…

ÿ

V_OUT

V_REF

-1

Ÿ

⁄

(4)

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VOUT

R_FBT

FB

VSEL

R_FBB

10 kΩ

Figure 9-2. Feedback Divider for Adjustable Output Voltage Setting

9.2.2.2.1 C_FFSelection

In some cases, a feed-forward capacitor can be used across R_FBTto improve the load transient response or

improve the loop-phase margin. This is especially true when values of R_FBT> 100 kΩ are used. Large values

of R_FBTin combination with the parasitic capacitance at the FB pin can create a small signal pole that interferes

with the loop stability. A C_FFhelps mitigate this effect. Equation 5 can be used to estimate the value of C_FF. The

value found with Equation 5 is a starting point; use lower values to determine if any advantage is gained by the

use of a C_FFcapacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with

Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.

V_OUT∂C_OUT

C_FF

<

V_REF

V_OUT

120 ∂R_FBT

∂

(5)

9.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based

on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of

the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the

maximum load current. Use the maximum device current when you select the ripple current for applications with

much smaller maximum load than the maximum available from the device. Equation 6 can be used to determine

the value of inductance. The constant K is the percentage of inductor current ripple. K = 0.3 was chosen for this

example and L = 4.7 µH inductance was found.

(

V

_IN- V_OUT

)

V_OUT

L =

∂

f_SW∂K ∂I_OUTmax

V

IN

(6)

Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, I_SC

(see Specifications). This ensures that the inductor does not saturate even during a short circuit on the output.

When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current

to rise very rapidly. Although the valley current limit, I_LIMIT, is designed to reduce the risk of current run-away,

a saturated inductor can cause the current to rise to high values very rapidly. This can lead to component

damage. Do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation

characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft

saturation, allowing some relaxation in the current rating of the inductor. However, they have more core losses at

frequencies above about 1 MHz. In any case, the inductor saturation current must not be less than the maximum

peak inductor current at full load.

To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 7. The

maximum inductance is limited by the minimum current ripple required for the current mode control to perform

correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device

maximum rated current under nominal conditions.

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V_OUT

L_MINí M∂

f_SW

(7)

where

•

M = 0.69 for 1 A device

9.2.2.4 Output Capacitor Selection

The value of the output capacitor and its ESR determine the output voltage ripple and load transient

performance. The output capacitor bank is usually limited by the load transient requirements rather than the

output voltage ripple. Use Equation 8 to estimate a lower bound on the total output capacitance, and an upper

bound on the ESR, which are required to meet a specified load transient.

K²

12

»

…

ÿ

DI_OUT

f_SW∂ DV_OUT∂K

C_OUT

í

∂

(

1- D

)

∂

(

1+ K

)

+

∂

(

2 - D

)

Ÿ

⁄

(

2 + K

)

∂ DV_OUT

ESR Ç

K²

1

»

ÿ

≈

’

2∂ DI_OUT1+ K +

∂∆1+

÷

…

Ÿ

∆

12

(1- D)

…

«

◊Ÿ

⁄

V_OUT

D =

V

IN

(8)

where

•

ΔV_OUT= output voltage transient

ΔI_OUT= output current transient

K = ripple factor from Inductor Selection

Once the output capacitor and ESR have been calculated, use Equation 9 to check the peak-to-peak output

voltage ripple, V_r.

1

V_r@ DI_L∂ ESR²+

2

(

8∂ f_SW∂C_OUT

)

(9)

The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple

requirements.

This example requires a ΔV_OUTof ≤ 150 mV for an output current step of ΔI_OUT= 1 A. Equation 8 gives a

minimum value of 8.1 µF and a maximum ESR of 0.13 Ω. Assuming a 20% tolerance and a 10% bias de-rating,

the user arrives at a minimum capacitance of 10 µF. This can be achieved with a 10-µF, 16-V, ceramic capacitors

in the 1210 case size. More output capacitance can be used to improve the load transient response. Ceramic

capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor

can be placed in parallel with the ceramics to build up the required value of capacitance. When using a mixture

of aluminum and ceramic capacitors, use the minimum recommended value of ceramics and add aluminum

electrolytic capacitors as needed.

In general, use a capacitor rating of at least 10 V for output voltages of 3.3 V or less, and use a capacitor of 16 V

or more for output voltages of 5 V and above.

The recommendations given in Table 9-1 provide typical and minimum values of output capacitance for the

given conditions. These values are the rated or nameplate figures. If the minimum values are to be used, the

design must be tested over all of the expected application conditions, including input voltage, output current, and

ambient temperature. This testing must include both bode plot and load transient assessments. The maximum

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value of total output capacitance must be limited to about 10 times the design value, or 1000 µF, whichever is

smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as

the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and

loop stability must be performed.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and bode plots are the best way to validate any given design and must always be completed

before the application goes into production. In addition to the required output capacitance, a small ceramic

placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF

to 100 nF can help reduce spikes on the output caused by inductor and board parasitics.

9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the

ripple current and isolating switching noise from other circuits. A minimum of 4.7 µF of ceramic capacitance is

required on the input of the LM63610-Q1, connected directly between VIN and PGND. This must be rated for

at least the maximum input voltage that the application requires; preferably twice the maximum input voltage.

This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load

transients. More input capacitance is required for larger output currents. In addition, a small case size 220-nF

ceramic capacitor must be used at the input as close a possible to the regulator, typically within 1 mm of the

VIN and PGND pins. This provides a high frequency bypass for the control circuits internal to the device. For this

example, a 4.7-µF, 50-V, X7R (or better) ceramic capacitor is chosen. The 220 nF must also be rated at 50 V

with an X7R dielectric and preferably a small case size, such as an 0603.

Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is

especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR

of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this

additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitor or capacitors. Use Equation 10

to calculate the approximate RMS current. This value must be checked against the manufacturers' maximum

ratings.

I_OUT

I_RMS

@

2

(10)

9.2.2.6 C_BOOT

The LM63610-Q1 requires a bootstrap capacitor to be connected between the BOOT pin and the SW pin. This

capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic

capacitor of 220 nF and at least 16 V is required.

9.2.2.7 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output

requires a 1-µF, 16-V ceramic capacitor connected from VCC to PGND for proper operation. In general, this

output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for

the RESET function and as a logic supply for the various control inputs of the device. A value of 100 kΩ is a

good choice for the RESET flag pullup resistor. The nominal output voltage on VCC is 5 V.

9.2.2.8 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can

be accomplished by using the circuit shown in Figure 9-3. The input voltage at which the device turns on is

designated as V_ONwhile the turnoff voltage is V_OFF. First, a value for R_ENBis chosen in the range of 10 kΩ to

100 kΩ. Then, Equation 11 is used to calculate R_ENTand V_OFF

.

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VIN

R_ENT

EN

R_ENB

Figure 9-3. Setup for External UVLO Application

≈

’

V_ON

∆

÷

R_ENT

=

- 1 ∂R_ENB

÷

◊

V_{EN -H}

«

≈

’

V_{EN -HYS}

V_{EN -H}

∆

÷

V_OFF= V_ON∂ 1-

∆

«

◊

(11)

where

•

V_ON= V_INturnon voltage

V_OFF= V_INturnoff voltage

9.2.2.9 Maximum Ambient Temperature

As with any power conversion device, the LM63610-Q1 dissipates internal power while operating. The effect

of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal resistance,

R_θJAof the device, and PCB combination. The maximum internal die temperature for the LM63610-Q1 must

be limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the

load current. Equation 12 shows the relationships between the important parameters. It is easy to see that

larger ambient temperatures (T_A) and larger values of R_θJAreduce the maximum available output current. The

converter efficiency can be estimated by using the curves provided in this data sheet. Note that these curves

include the power loss in the inductor. If the desired operating conditions cannot be found in one of the curves,

then interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the

desired application requirements and the efficiency can be measured directly. The correct value of R_θJAis more

difficult to estimate. As stated in the Semiconductor and IC Package Thermal Metrics Application Report, the

value of R_θJAgiven in the Thermal Information table is not valid for design purposes and must not be used to

estimate the thermal performance of the application. The values reported in that table were measured under

a specific set of conditions that are rarely obtained in an actual application. The data given for R_θJC(bott)and

Ψ_JTcan be useful when determining thermal performance. See Semiconductor and IC Package Thermal Metrics

Application Report for more information and the resources given at the end of this section.

(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

MAX

(

)

V_OUT

(12)

where

η = efficiency

The effective R_θJAis a critical parameter and depends on many factors such as the following:

•

Power dissipation

Air temperature/flow

PCB area

Copper heat-sink area

Number of thermal vias under the package

Adjacent component placement

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The HTSSOP uses a die attach paddle, or "thermal pad" (DAP) to provide a place to solder down to the PCB

heat-sinking copper. This provides a good heat conduction path from the regulator junction to the heat sink and

must be properly soldered to the PCB heat sink copper. A typical example of R_θJAversus copper board area can

be found in Figure 9-4. The copper area given in the graph is for each layer. The top and bottom layers are 2 oz.

copper each, while the inner layers are 1 oz. Figure 9-4 shows a typical curve of maximum output current versus

ambient temperature. This data was taken with a device and PCB combination, giving an R_θJAof about 30°C/W.

Remember that the data given in these graphs are for illustration purposes only, and the actual performance in

any given application depends on all of the previously mentioned factors.

40

4L, 0.9W

4L, 2W

2L, 0.9W

2L, 2W

37.5

35

32.5

30

27.5

25

22.5

20

17.5

15

0

20

40

60

80

100

120

140

160

180

Copper Area (cm²)

thet

Figure 9-4. Typical R_θJAversus Copper Area for the HTSSOP Package

The following resources can be used as a guide to optimal thermal PCB design and estimating R_θJAfor a given

application environment:

•

AN-2020 Thermal Design By Insight, Not Hindsight Application Report

A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report

Semiconductor and IC Package Thermal Metrics Application Report

Thermal Design Made Simple with LM43603 and LM43602 Application Report

Using New Thermal Metrics Application Report

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9.2.3 Application Curves

Unless otherwise specified, the following conditions apply: V_IN= 13.5 V, T_A= 25°C. shows the circuit with the appropriate

BOM from .

100

95

90

85

80

75

70

65

95

90

85

80

75

70

65

60

55

8V

13.5V

18V

24V

13.5V

18V

24V

0.001

0.01

0.1

Output Current (A)

1

2

0.001

0.01

0.1

Output Current (A)

1

2

eff_

LM63610

V_OUT= 5 V

ƒ_SW= 400 kHz

(AUTO)

LM63610

V_OUT= 5 V

ƒ_SW= 2100 kHz

(AUTO)

Figure 9-5. Efficiency

Figure 9-6. Efficiency

95

90

85

80

75

70

65

95

90

85

80

75

70

65

60

8V

13.5V

18V

24V

13.5V

18V

24V

60

55

0.001

0.01

0.1

Output Current (A)

1

2

0.001

0.01

0.1

Output Current (A)

1

2

eff_

LM63610

V_OUT= 3.3 V

ƒ_SW= 400 kHz

(AUTO)

LM63610

V_OUT= 3.3 V

ƒ_SW= 2100 kHz

(AUTO)

Figure 9-7. Efficiency

Figure 9-8. Efficiency

5.06

5.05

5.04

5.03

5.02

5.01

5

3.34

3.33

3.32

3.31

3.3

8V

13.5V

18V

24V

13.5V

18V

24V

4.99

4.98

0

3.29

0

0.25

0.5 0.75

Output Current (A)

1

1.25

1.5

0.25

0.5 0.75

Output Current (A)

1

1.25

1.5

LL_5

LL_3

LM63610

V_OUT= 5 V

ƒ_SW= 2100 kHz

(AUTO)

A.

LM63610

V_OUT= 3.3 V

ƒ_SW= 2100 kHz

(AUTO)

Figure 9-9. Line and Load Regulation

Figure 9-10. Line and Load Regulation

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10000

2250

2000

1750

1500

1250

1000

750

1000

100

10

1

500

0.1

5V

3.3V

0A

1.5A

250

0.01

0

1E-6

1E-5

0.0001

0.001

Output Current (A)

0.01

0.1

1

0

4

8

12

16

Input Voltage (V)

20

24

28

32

36

40

Fsw_

LM63610

V_IN= 13.5 V

ƒ_SW= 2100 kHz

(AUTO)

LM63610

V_OUT= 3.3 V

ƒ_SW= 2100 kHz

(FPWM)

Figure 9-11. Switching Frequency versus Output

Current

Figure 9-12. Switching Frequency versus Input

Voltage

2250

2000

1750

1500

1250

1000

750

VOUT, 200mV/DIV

3.3V

Output Current, 1A/DIV

500

0A

1.5A

250

0

50µs/DIV

0

4

8

12

16

20

24

Input Voltage (V)

28

32

36

40

Fsw_

LM63610

V_OUT= 5 V

ƒ_SW= 2100 kHz

(FPWM)

LM63610

V_OUT= 3.3 V

FPWM

ƒ_SW= 2100 kHz

0 A to 1.5 A, 2µs

Figure 9-13. Switching Frequency versus Input

Voltage

Figure 9-14. Load Transient

VOUT, 200mV/DIV

5V

VOUT, 100mV/DIV

3.3V

Output Current, 1A/DIV

50µs/DIV

0

LM63610

V_OUT= 5 V

FPWM

ƒ_SW= 2100 kHz

LM63610

0.5 A to 1.5 A, 2µs

V_OUT= 3.3 V

AUTO

ƒ_SW= 2100 kHz

0 A to 1.5 A, 2µs

Figure 9-15. Load Transient

Figure 9-16. Load Transient

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0.3

0.25

0.2

VOUT, 100mV/DIV

5V

0.15

0.1

Output Current, 1A/DIV

50µs/DIV

0.05

0

0.5 0.6 0.7 0.8 0.9

1

Output Current (A)

1.1 1.2 1.3 1.4 1.5

DO_f

LM63610

ƒ_SW= 140 kHz

(AUTO)

LM63610

V_OUT= 5 V

AUTO

ƒ_SW= 2100 kHz

0.5 A to 1.5 A, 2µs

Figure 9-18. Dropout Voltage versus Output

Current for -1% Drop

Figure 9-17. Load Transient

1.5

1.4

1.3

1.2

1.1

1

29

28

27

26

25

0.9

0.8

0.7

0.6

0.5

24

5V

3.3V

23

0.5 0.6 0.7 0.8 0.9

1

Output Current (A)

1.1 1.2 1.3 1.4 1.5

5

10

15

20 25

Input Voltage (V)

30

35

40

DO_f

Inpu

LM63610

ƒ_SW= 1850 kHz

(AUTO)

LM63610

I_OUT= 0 A

ƒ_SW= 2100 kHz

(AUTO)

Figure 9-19. Dropout Voltage versus Output

Current to 1.85 MHz

Figure 9-20. Input Supply Current versus Input

Voltage

1

0.1

13.5V

18V

13.5V

18V

0.01

0.1

Output Current (mA)

1

0.01

0.1

Output Current (mA)

1

Inpu

LM63610

V_OUT= 5 V

ƒ_SW= 2100 kHz

(AUTO)

LM63610

V_OUT= 3.3 V

ƒ_SW= 2100 kHz

(AUTO)

Figure 9-21. Input Supply Current versus Output

Current

Figure 9-22. Input Supply Current versus Output

Current

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V_OUT

V_IN

U1

SW

VIN

EN

L

C_IN

C_HF

220 nF

C_BOOT

10 µF

BOOT

C_OUT

0.22 µF

SYNC/

MODE

Mode

V_OUT

Frequency

VSEL

RT

FB

VCC

PGND AGND

RESET

100 kΩ

RESET

C_VCC

1 µF

Figure 9-23. Circuit for Typical Application Curves

Table 9-3. BOM for Typical Application Curves

(1)

OUTPUT

CURRENT

V_OUT

FREQUENCY

C_OUT

L

U1

3.3 V

5 V

400 kHz

2100 kHz

400 kHz

2100 kHz

1 A

2 × 22 µF

1 × 10 µF

2 × 22 µF

1 × 10 µF

10 µH, 40 mΩ

4.7 µH, 30 mΩ

10 µH, 40 mΩ

4.7 µH, 30 mΩ

LM63610

1 A

5 V

1 A

(1) The values in this table were selected to enhance certain performance criteria and may not represent typical values.

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9.2.4 EMI Performance Curves

EMI results critically depend on PCB layout and test setup. The results given here are typical and given for

information purposes only. Figure 9-26 shows the used EMI filter. The limit lines shown refer to CISPR25 class 5.

PK

AV

PK

AV

0.15 MHz

1 MHz

10 MHz

30 MHz

100 MHz

30 MHz

80 MHz

LM63625DQ

I_OUT= 2.5 A

V_OUT= 5 V

Dither

ƒ_SW= 2100 kHz

LM63625DQ

I_OUT= 2.5 A

V_OUT= 5 V

Dither

ƒ_SW= 2100 kHz

Figure 9-24. Typical Conducted EMI with LM63625

0.15 MHz to 30 MHz

Figure 9-25. Typical Conducted EMI with LM63625

30 MHz to 108 MHz

Input to

Regulator

1.5 µF

Input Supply

Ferrite Bead

A. Input filter used only for EMI measurements shown in the EMI Performance Curves section.

Figure 9-26. Typical Input EMI Filter with LM63625

9.3 What to Do and What Not to Do

•

Do not exceed the Absolute Maximum Ratings.

Do not exceed the Recommended Operating Conditions.

Do not exceed the ESD Ratings.

Do not allow the EN input to float.

Do not allow the output voltage to exceed the input voltage, nor go below ground.

Do not use the value of R_θJAgiven in the Thermal Information table to design your application. See the

Maximum Ambient Temperature section.

•

Follow all the guidelines and suggestions found in this data sheet before committing the design to production.

TI application engineers are ready to help critique your design and PCB layout to help make your project a

success.

Use a 220 nF capacitor connected directly to the VIN and PGND pins of the device. See the Section 9.2.2.5

section for details.

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10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the limits found in the Section 7 table of this

data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded

regulator. The average input current can be estimated with Equation 13.

V_OUT∂I_OUT

I_IN

=

V_IN∂ h

(13)

where

•

η is the efficiency

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic

input capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to

the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient

is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause

the regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the

distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with

the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and reduce

any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help

hold the input voltage steady during large load transients.

It is recommended that the input supply must not be allowed to fall below the output voltage by more than

0.3 V. Under such conditions, the output capacitors discharges through the body diode of the high-side power

MOSFET. The resulting current can cause unpredictable behavior, and in extreme cases, possible device

damage. If the application allows for this possibility, then use a Schottky diode from VIN to VOUT to provide a

path around the regulator for this current.

In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this

device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not

recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the

output voltage of the regulator, the output capacitors discharges through the device, as mentioned above.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple

Success with Conducted EMI from DCDC Converters User's Guide provides helpful suggestions when designing

an input filter for any switching regulator.

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11 Layout

11.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck converter, the

most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 11-1.

This loop carries large transient currents that can cause large transient voltages when reacting with the trace

inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this,

the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic

inductance. Figure 11-2 shows a recommended layout for the critical components of the .

1. Place the input capacitors as close as possible to the VIN and PGND terminals. VIN and PGND pins

are adjacent, simplifying the input capacitor placement. Thermal reliefs in this area are not recommended.

2. Place a bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the

device and routed with short, wide traces to the VCC and PGND pins. Thermal reliefs in this area are not

recommended.

3. Use wide traces for the C_BOOTcapacitor. Place C_BOOTclose to the device with short and wide traces to

the BOOT and SW pins. Thermal reliefs in this area are not recommended.

4. Place the feedback divider as close as possible to the FB pin of the device. If an external feedback

divider is used with the ADJ option, place R_FBB, R_FBT, and C_FF, close to the device. The connections to FB

and AGND must be short and close to those pins on the device. The connection to V_OUTcan be somewhat

longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can

capacitively couple into the feedback path of the regulator.

5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act

as a heat dissipation path.

6. Connect the thermal pad to the ground plane. The thermal pad (DAP) connection must be soldered down

to the PCB ground plane. This pad acts as a heat-sink connection and an electrical ground connection for

the regulator. The integrity of this solder connection has a direct bearing on the total effective R_θJAof the

application. Thermal reliefs in this area are not recommended.

7. Provide wide paths for VIN, VOUT, SW, and PGND. Making these paths as wide and direct as possible

reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. Thermal

reliefs in this area are not recommended.

8. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature

section, enough copper area must be used to ensure a low R_θJA, commensurate with the maximum load

current and ambient temperature. The top and bottom PCB layers must be made with two ounce copper

and no less than one ounce. Use an array of heat-sinking vias to connect the thermal pad (DAP) to the

ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), these

thermal vias can also be connected to the inner layer heat-spreading ground planes.

9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as

possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

See the following PCB layout resources for additional important guidelines:

•

Layout Guidelines for Switching Power Supplies Application Report

Simple Switcher PCB Layout Guidelines Application Report

Construction Your Power Supply- Layout Considerations Seminar

Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

36

Submit Document Feedback

Product Folder Links: LM63610-Q1

LM63610-Q1

SNVSBO7A – JULY 2020 – REVISED JULY 2021

www.ti.com

VIN

KEEP

CURRENT

LOOP

C_IN

SW

SMALL

GND

Figure 11-1. Current Loops With Fast Edges

11.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane

provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control

circuitry. Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors.

PGND pins are connected directly to the source of the low-side MOSFET switch and also connected directly to

the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can

bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one

side of the ground planes. The other side of the ground plane contains much less noise and must be used for

sensitive routes.

TI recommends providing adequate device heat sinking by using the thermal pad (DAP) of the device as the

primary thermal path. Use a minimum 4 × 3 array of 10 mil thermal vias to connect the DAP to the system

ground plane heat sink. The vias must be evenly distributed under the DAP. Use as much copper as possible

for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with

the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with

enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and

lower thermal resistance.

Submit Document Feedback

37

Product Folder Links: LM63610-Q1

LM63610-Q1

SNVSBO7A – JULY 2020 – REVISED JULY 2021

www.ti.com

11.2 Layout Example

Top Trace

Bottom Trace

VIA to Ground Plane

INDUCTOR

C_OUT

C_IN

CBOOT

VCC

C_IN

RT

EN

VSEL

SYNC/MODE

AGND

FB

RESET

GND

HEATSINK

Figure 11-2. Example Layout

38

Submit Document Feedback

Product Folder Links: LM63610-Q1

LM63610-Q1

SNVSBO7A – JULY 2020 – REVISED JULY 2021

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight Application Report

Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

Application Report

•

Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report

Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report

Texas Instruments, Using New Thermal Metrics Application Report

Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report

Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report

Texas Instruments, Constructing Your Power Supply-layout Considerations Seminar

Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

PowerPAD^™is a trademark of TI.

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

39

Product Folder Links: LM63610-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Nov-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM63610DQDRRRQ1

WSON

DRR

12

16

3000

2000

330.0

12.4

3.3

6.9

3.3

5.6

1.1

1.6

8.0

12.0

Q2

Q1

LM63610DQPWPRQ1 HTSSOP PWP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Nov-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM63610DQDRRRQ1

LM63610DQPWPRQ1

WSON

DRR

PWP

12

16

3000

2000

367.0

853.0

367.0

449.0

35.0

HTSSOP

Pack Materials-Page 2

PACKAGE OUTLINE

PWP0016K

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

6.6

6.2

C

TYP

A

PIN 1 INDEX

AREA

0.1 C

SEATING

PLANE

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

4.5

4.3

B

0.19

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 0.95 MAX

NOTE 5

4X (0.3)

8

9

2X 0.23 MAX

NOTE 5

2.30

1.54

17

0.25

GAGE PLANE

1.2 MAX

0.15

0.05

0.75

0.50

0 -8

16

1

A

20

DETAIL A

TYPICAL

THERMAL

PAD

2.46

1.86

4224484/A 08/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0016K

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(2.46)

16X (1.5)

METAL COVERED

BY SOLDER MASK

SYMM

1

16X (0.45)

16

(1.2) TYP

(2.3)

(R0.05) TYP

SYMM

17

(5)

NOTE 9

(0.6)

14X (0.65)

(

0.2) TYP

VIA

9

8

SOLDER MASK

DEFINED PAD

(1.1) TYP

SEE DETAILS

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4224484/A 08/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0016K

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(2.46)

BASED ON

0.125 THICK

STENCIL

16X (1.5)

METAL COVERED

BY SOLDER MASK

1

16

16X (0.45)

(R0.05) TYP

SYMM

(2.3)

17

BASED ON

0.125 THICK

STENCIL

14X (0.65)

9

8

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.75 X 2.57

2.46 X 2.30 (SHOWN)

2.25 X 2.10

0.125

0.15

0.175

2.08 X 1.94

4224484/A 08/2018

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

WSON - 0.8 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

DRR0012E

3.1

2.9

A

B

3.1

2.9

PIN 1 INDEX AREA

0.100 MIN

(0.130)

SECTION A-A

TYPICAL

0.8

0.7

C

SEATING PLANE

0.08 C

0.05

0.00

1.4

1.2

SYMM

(0.2) TYP

(0.43) TYP

6

10X 0.5

7

A

SYMM

2X

2.6

2.4

2.5

13

1

12

0.3

0.2

12X

PIN 1 ID

(OPTIONAL)

0.52

0.32

12X

0.1

C A B

C

0.05

4224874/B 03/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WSON - 0.8 mm max height

DRR0012E

PLASTIC QUAD FLAT PACK- NO LEAD

2X (2.78)

(1.3)

12X (0.62)

12X (0.25)

1

12

10X (0.5)

SYMM

(2.5)

13

2X

(2.5)

2X

(1)

(R0.05)

TYP

7

6

SYMM

(Ø0.2) VIA

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

0.07 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224874/B 03/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WSON - 0.8 mm max height

DRR0012E

PLASTIC QUAD FLAT PACK- NO LEAD

2X (2.78)

12X (0.62)

12X (0.25)

2X (1.21)

13

1

12

2X

(1.1)

10X (0.5)

SYMM

2X

(2.5)

(R0.05)

TYP

2X

(0.65)

7

6

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

82% PRINTED COVERAGE BY AREA

SCALE: 20X

4224874/B 03/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM63610DQDRRRQ1
厂家：	TEXAS INSTRUMENTS
描述：	LM63610-Q1 3.5-V to 36-V, 1-A, Automotive Step-down Voltage Converter
文件：	总51页 (文件大小：4013K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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