LM66200 [TI]
1.6V 至 5.5V、40mΩ、2.5A、低 IQ、双输入理想二极管;
| 型号： | LM66200 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.6V 至 5.5V、40mΩ、2.5A、低 IQ、双输入理想二极管 二极管 |
| 文件： | 总19页 (文件大小：1656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM66200
ZHCSMV5 –NOVEMBER 2021
LM66200 1.6V 至5V、2.5A 双理想二极管，具有自动切换功能
1 特性
3 说明
• 输入电压范围：1.6V 至5.5V
• 最大持续电流：2.5A
• 导通电阻：40mΩ（典型值）
• 待机电流：50nA（典型值）
• 静态电流：1.32μA（典型值）
• 自动二极管切换
LM66200 是一款双输入理想二极管器件，具有 1.6V
至 5.5V 的额定电压和每通道 2.5A 的最大额定电流。
该器件使用N 沟道MOSFET 在电源之间切换，同时在
第一次施加电压时提供受控的压摆率。
凭借 1.32μA（典型值）的低静态电流和 50nA（典型
值）的低待机电流，LM66200 适用于其中一个输入由
电池供电的系统。这些低电流延长了电池的使用寿命和
续航时间。
• 受控输出压摆率：
– 电压为3.3V 时为1.3ms（典型值）
• VOUT 大于VINx 时实现反向电流阻断
• 热关断
LM66200 采用自动二极管模式，可为电压最高的电源
分配优先级，并将其输送至输出端。低电平有效使能引
脚 (ON) 可禁用两个通道，允许用户在无需任一电源的
情况下将器件设为关断模式。
2 应用
• 电表
器件信息(1)
• 电机驱动器
• 楼宇自动化
• 电子销售终端
• 资产跟踪器
封装尺寸（标称值）
器件型号
LM66200
封装
SOT (8)
2.1mm × 1.6mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSG04
LM66200
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Table of Contents
7.5 Output Voltage Drop................................................. 10
7.6 Device Functional Modes..........................................10
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
9 Power Supply Recommendations................................13
10 Layout...........................................................................13
10.1 Layout Guidelines................................................... 13
10.2 Layout Example...................................................... 13
11 Device and Documentation Support..........................14
11.1 Documentation Support.......................................... 14
11.2 接收文档更新通知................................................... 14
11.3 Trademarks............................................................. 14
11.4 Electrostatic Discharge Caution..............................14
11.5 术语表..................................................................... 14
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
7.4 VINx Collapse Rate...................................................10
Information.................................................................... 14
4 Revision History
DATE
REVISION
NOTES
November 2021
*
Initial release.
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5 Pin Configuration and Functions
图5-1. DRL Package 8-Pin SOT Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
NO.
1, 5
2, 7
3
Device ground
—
O
I
VOUT
VIN1
Output power
Channel 1 input power
Active low enable pin. Device is enabled when ON is pulled low
and the device turns off both channels when ON is pulled high.
ON
4
6
I
I
VIN2
Channel 2 input power
Status pin. Pulled high when VIN1 is being used and pulled low
when VIN2 is being used. Can be pulled up to VIN1 to reduce
quiescent current when VIN2 is powering the output.
ST
8
O
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
6
UNIT
VIN1, VIN2
VOUT
Input Voltage
V
V
V
A
Output Voltage
Control Pin Voltage
Maximum Current
6
VST, VON
IMAX
6
2.5
Maximum Pulsed Current
Max duration 1ms, Duty cycle of 2%
IMAX,PLS
4
A
Internally
Limited
TJ
Junction temperature
Storage temperature
°C
°C
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), ANSI/ESDA/
JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
0
NOM
MAX
5.5
UNIT
V
VIN1, VIN2
VOUT
Input Voltage
Output Voltage
5.5
V
VST, VON
TA
Control Pin Voltage
Ambient Temperature
0
5.5
V
125
°C
–40
6.4 Thermal Information
LM66200
THERMAL METRIC(1)
DRL (SOT)
8-PINS
111.5
19.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
35.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ΨJT
19.1
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
Power Consumption
25°C
0.22
uA
ISTBY,
VIN2 powers VOUT
VIN2 > VIN1 + 0.2 V
0.31
0.32
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
VIN1 Standby Current
VIN2 Standby Current
–40°C to 85°C
–40°C to 105°C
25°C
VIN1
0.05
1.32
1.35
0.1
ISTBY,
VIN1 powers VOUT
VIN1 > VIN2 + 0.1 V
0.07
0.09
–40°C to 85°C
–40°C to 105°C
25°C
VIN2
VIN1 powers VOUT
VIN1 > VIN2 + 0.1 V
3.6
4.4
IQ, VIN1 VIN1 Quiescent Current
IQ, VIN2 VIN2 Quiescent Current
–40°C to 85°C
–40°C to 105°C
25°C
VIN2 powers VOUT
VIN2 > VIN1 + 0.2 V
3.7
4.5
–40°C to 85°C
–40°C to 105°C
25°C
ON = 5 V
VIN1 > VIN2
VOUT = 0 V
1.3
2.9
–40°C to 85°C
–40°C to 105°C
25°C
ISD,VIN1 VIN1 Shutdown Current
0.05
0.05
0.05
ON = 5 V
VIN1 < VIN2
VOUT = 0 V
1
–40°C to 85°C
–40°C to 105°C
25°C
2.4
ON = 5 V
VIN2 > VIN1
VOUT = 0 V
1.3
2.9
–40°C to 85°C
–40°C to 105°C
25°C
ISD,VIN2 VIN2 Shutdown Current
ON = 5 V
VIN2 < VIN1
VOUT = 0 V
0.7
2.1
–40°C to 85°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
ION
IST
ON pin leakage
ST pin leakage
VIN1 = VIN2 = PR1 = 5.5 V
VIN1 = VIN2 = ST = 5.5 V
0.1
0.03
Performance
25°C
37
40
41
42
46
55
60
48
55
59
51
61
66
52
68
74
0.1
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
V
VINx = 5 V
IOUT = 200 mA
–40°C to 85°C
–40°C to 105°C
25°C
VINx = 3.3 V
IOUT = 200 mA
–40°C to 85°C
–40°C to 105°C
25°C
RON
On-Resistance
VINx = 1.8 V
IOUT = 200 mA
–40°C to 85°C
–40°C to 105°C
25°C
VINx = 1.6 V
IOUT = 200 mA
–40°C to 85°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
VOL,ST Status pin VOL
IST = 1 mA
tST
Status pin response time
5
us
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MAX UNIT
6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
VON
ON reference voltage
0.8
1
1.2
V
1.6 V ≤VINx ≤5.5 V
–40°C to 105°C
Protection
Reverse current blocking response
time
tRCB
VOUT > VINx + 1 V
2
42
us
mV
mV
A
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
Reverse current blocking rising
threshold
VRCB,R
VRCB,F
70
40
4
1.6 V ≤VINx ≤5.5 V
1.6 V ≤VINx ≤5.5 V
1.6 V ≤VINx ≤5.5 V
Reverse current blocking falling
threshold
17
Reverse current blocking activation
current
IRCB
TSD
1.4
Thermal shutdown
-
-
170
20
°C
°C
TSDHYS Thermal shutdown hysteresis
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switchover
tSW
tSW
tSW
tD
Switchover time, VINx = 5 V
Switchover time, VINx = 3.3 V
Switchover time, VINx = 1.8 V
Delay time, VINx = 5 V
8
6.2
17.7
1
us
us
RL = 10Ω, CL = 10uF
RL = 10Ω, CL = 10uF
RL = 10Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
RL = 100Ω, CL = 10uF
us
ms
ms
ms
ms
ms
ms
tD
Delay time, VINx = 3.3 V
Delay time, VINx = 1.8 V
Soft-start time, VINx = 5 V
Soft-start time, VINx = 3.3 V
Soft-start time, VINx = 1.8 V
1.2
1.4
1.7
1.3
0.9
tD
tSS
tSS
tSS
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6.7 Typical Characteristics
1.5
1.55
1.5
-40°C
-40°C
25°C
85°C
105°C
25°C
85°C
105°C
1.45
1.4
1.45
1.4
1.35
1.3
1.35
1.3
1.25
1.2
1.25
1.2
1.15
1.1
1.15
1.1
1.05
1.5
2
2.5
3
VIN1 Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
VIN2 Voltage (V)
3.5
4
4.5
5
5.5
D001
D002
VIN2 = 1.6 V
VOUT = Open
VIN1 = 1.6 V
VOUT = Open
图6-1. VIN1 Quiescent Current vs Input Voltage
图6-2. VIN2 Quiescent Current vs Input Voltage
0.36
0.4
-40°C
25°C
85°C
-40°C
25°C
85°C
105°C
0.3
0.33
0.35
0.3
105°C
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
0.25
0.2
0.15
0.1
0.05
1.5
2
2.5
3
VIN1 Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
VIN2 Voltage (V)
3.5
4
4.5
5
5.5
D005
D006
VIN2 = 1.6 V
VOUT = 0 V
VIN1 = 1.6 V
VOUT = 0 V
图6-3. VIN1 Shutdown Current vs Input Voltage
图6-4. VIN2 Shutdown Current vs Input Voltage
60
60
-40°C
25°C
-40°C
25°C
56
56
85°C
105°C
85°C
105°C
52
48
52
48
44
40
36
32
28
24
20
44
40
36
32
28
24
20
1.5
2
2.5
3
VIN1 Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
VIN2 Voltage (V)
3.5
4
4.5
5
5.5
D007
D008
IOUT = 200 mA
IOUT = 200 mA
图6-5. Channel 1 On-Resistance vs Input Voltage
图6-6. Channel 2 On-Resistance vs Input Voltage
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6.7 Typical Characteristics (continued)
240
160
140
120
100
80
-40°C
-40°C
25°C
85°C
105°C
25°C
85°C
105°C
210
180
150
120
90
60
60
40
30
20
0
0
1.5
2
2.5
3
VOUT Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
VOUT Voltage (V)
3.5
4
4.5
5
5.5
D009
D010
VINx = 0 V
VINy = Open
VINx = 0 V
VINy = Open
图6-7. Reverse Leakage Current into VOUT
图6-8. Reverse Leakage Current out of VINx
图6-9. Diode Mode Switchover Behavior (RL = 10 Ω, CL = 10 uF)
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7 Detailed Description
7.1 Overview
The LM66200 is a dual ideal diode device with a voltage rating of 1.6 V to 5.5 V and a maximum current rating of
2.5 A per channel. The device uses N-channel MOSFETs to switch between supplies, while providing a
controlled slew rate when voltage is first applied.
When in operation, the device has a quiescent of 1.32 μA (typical), which is drawn from the highest VINx
supply. The lower voltage VINx supply only sees a standby current of 50 nA (typical).
The LM66200 uses automatic diode mode to prioritize the highest voltage supply and pass it through to the
output. The active low enable pin (ON) allows the user to disable both channels, putting the device into
shutdown mode when neither supply is needed.
7.2 Functional Block Diagram
7.3 Feature Description
The below sections detail the features of the LM66200.
7.3.1 Truth Table
The below table shows the expected behavior of the LM66200.
VIN1
VIN2
ON
Low
Low
ST
VOUT
VIN1
VIN2
Hi-Z
VIN1 > VIN2
VIN1 < VIN2
High
Low
Low
X
X
High
X = do not care
7.3.2 Soft Start
When an input voltage is applied to the LM66200 and the output voltage is lower than 1 V, the output is brought
up with soft start to minimize the inrush current due to output capacitance. During switchover, soft start is not
used to minimize output voltage drop. For linear soft start behavior, iTI recommends to have an output
capacitance of at least 0.1 uF.
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7.3.3 Status Indication
The ST pin is an open drain output that must be pulled up to an external voltage for proper operation. When the
LM66200 is powering the output using VIN1, the ST pin is pulled high. When the LM66200 is powering the
output using VIN2, the ST pin is pulled low. During a fault condition the ST pin is pulled low, regardless of the
channel being used.
7.4 VINx Collapse Rate
The LM66200 uses the highest voltage supply to power the device. When one supply drops below the other, the
device changes the supply used to power the device. If the supply powering the device drops at a rate faster
than 1 V/10 μs, the other supply must be at 2.5 V or higher to prevent the device from resetting. If the other
supply is lower than 2.5 V, then the device is not be able to switch to the supply quickly enough, and the device
resets and turns on with soft start timing. To slow down the decay of the input, capacitance can be added to the
input or output.
7.5 Output Voltage Drop
The output voltage drop is based on the load capacitance and load resistance. The stronger the resistive load,
the faster the output discharges during switchover. The higher the capacitance on the output, the less the
voltage drops during switchover.
7.6 Device Functional Modes
The below sections detail the operation of the LM66200 device.
7.6.1 Automatic Switchover
When both inputs are applied to the device, the highest voltage is used to power the output. IThe ON pin is used
as an active low device enable, turning off the device when it is pulled high. When the device is turned back on,
soft start is used to power the output. The expected behavior for the device is shown in the waveform below.
图7-1. Automatic Switchover Waveform
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
8.2 Typical Application
This typical application demonstrates how the LM66200 device can be used to control inrush current for high
output capacitances.
图8-1. LM66200 Typical Application Diagram
8.2.1 Design Requirements
For this example, the values below are used as the design parameters.
表8-1. Design Parameters
PARAMETER
VALUE
VIN1 input voltage
5 V
Output capacitance
100 μF
Maximum inrush current
500 mA
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8.2.2 Detailed Design Procedure
Use 方程式1 to determine how much inrush current is caused by the output capacitor.
IINRUSH = COUT × VOUT / tSS
(1)
where
• IINRUSH = amount of inrush current caused by COUT
• COUT = capacitance on VOUT
• tSS = output voltage soft start time
• VOUT = final value of the output voltage
With a final output voltage of 5 V, the expected rise time is 1.7 ms. Using the inrush current equation, the inrush
current caused by a 100-µF capacitance is 294 mA, well below the 500-mA target.
8.2.3 Application Performance Plots
The below oscilloscope capture shows 5 V being applied to VIN1. The output comes up with slew rate control
and limits the inrush current to below 500 mA.
图8-2. LM66200 Inrush Current Control
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9 Power Supply Recommendations
The device is designed to operate with a VIN range of 1.6 V to 5.5 V. The VIN power supplies must be well
regulated and placed as close to the device terminals as possible. The power supplies must be able to withstand
all transient load current steps. In most situations, using an input capacitance (CIN) of 1 μF is sufficient to
prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is slow to
respond to a large transient current or large load current step, additional bulk capacitance can be required on the
input.
10 Layout
10.1 Layout Guidelines
For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances can have
on normal operation. Using wide traces for VIN1, VIN2, VOUT, and GND helps minimize the parasitic electrical
effects.
10.2 Layout Example
图10-1. LM66200 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Basics of Power MUX application note
• Texas Instruments, 11 Ways to Protect Your Power Path e-book
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 Trademarks
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
14
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Product Folder Links: LM66200
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM66200DRLR
ACTIVE
SOT-5X3
DRL
8
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
LM66
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
LM6687IM
IC DUAL COMPARATOR, 1900 uV OFFSET-MAX, PDSO16, 0.150 INCH, PLASTIC, SOP-16, Comparator
NSC
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