LM7171QML-SP [TI]
超高速、高输出电流、电压反馈放大器;
| 型号： | LM7171QML-SP |
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TEXAS INSTRUMENTS |
| 描述： | 超高速、高输出电流、电压反馈放大器 放大器 |
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LM7171QML, LM7171QML-SP
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SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
LM7171QML Very High Speed, High Output Current, Voltage Feedback Amplifier
Check for Samples: LM7171QML, LM7171QML-SP
1
FEATURES
DESCRIPTION
The LM7171 is a high speed voltage feedback
amplifier that has the slewing characteristic of a
current feedback amplifier; yet it can be used in all
traditional voltage feedback amplifier configurations.
The LM7171 is stable for gains as low as +2 or −1. It
provides a very high slew rate at 4100V/μs and a
wide unity-gain bandwidth of 200 MHz while
consuming only 6.5 mA of supply current. It is ideal
for video and high speed signal processing
applications such as HDSL and pulse amplifiers. With
100 mA output current, the LM7171 can be used for
video distribution, as a transformer driver or as a
laser diode driver.
23
•
(Typical Unless Otherwise Noted)
Easy-To-Use Voltage Feedback Topology
Very High Slew Rate: 2400V/μs
Wide Unity-Gain Bandwidth: 200 MHz
−3 dB Frequency @ AV = +2: 220 MHz
Low Supply Current: 6.5 mA
•
•
•
•
•
•
•
•
•
High Open Loop Gain: 85 dB
High Output Current: 100 mA
Specified for ±15V and ±5V Operation
Available with Radiation Guarantee
–
–
Total Ionizing Dose 300 Krad(Si)
ELDRS Free 300 Krad(Si)
Operation on ±15V power supplies allows for large
signal swings and provides greater dynamic range
and signal-to-noise ratio. The LM7171 offers low
SFDR and THD, ideal for ADC/DAC systems. In
addition, the LM7171 is specified for ±5V operation
for portable applications.
APPLICATIONS
•
•
•
•
•
•
•
•
HDSL and ADSL Drivers
Multimedia Broadcast Systems
Professional Video Cameras
Video Amplifiers
The LM7171 is built on Texas Instruments's
advanced VIP™ III (Vertically integrated PNP)
complementary bipolar process.
Copiers/Scanners/Fax
HDTV Amplifiers
Pulse Amplifiers and Peak Detectors
CATV/Fiber Optics Signal Processing
Connection Diagram
NC
IN-
NC
IN+
V-
1
2
3
4
5
10
9
NC
V+
8
NC
7
VOUTPUT
NC
6
Figure 1. 8-Pin CDIP Top View
Figure 2. 10-Pin CFP Top View
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VIP is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LM7171QML, LM7171QML-SP
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
www.ti.com
Simplified Schematic Diagram
Note: M1 and M2 are current mirrors.
Typical Performance
Large Signal Pulse Response
AV = +2, VS = ±15V
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
Absolute Maximum Ratings(1)
Supply Voltage (V+–V−)
Differential Input Voltage(2)
36V
±10V
Maximum Power Dissipation(3)
Output Short Circuit to Ground(4)
Storage Temperature Range
730mW
Continuous
−65°C ≤ TA ≤ +150°C
106°C/W
Thermal Resistance(5)
θJA
8LD CDIP (Still Air)
8LD CDIP (500LF/Min Air flow)
10LD CFP (Still Air)
53°C/W
182°C/W
10LD CFP (500LF/Min Air flow)
105°C/W
10LD CFP "WG" (device 01, 02) (Still Air)
10LD CFP "WG" (device 01, 02) (500LF/Min Air flow)
8LD CDIP
182°C/W
105°C/W
3°C/W
5°C/W
5°C/W
965mg
235mg
230mg
150°C
θJC
10LD CFP
10LD CFP "WG" (device 01, 02)(6)
Package Weight (Typical)
8LD CDIP
10LD CFP
10LD CFP "WG" (device 01, 02)
Maximum Junction Temperature(3)
ESD Tolerance(7)
3000V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the
Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Differential input voltage is applied at VS = ±15V.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) All numbers apply for packages soldered directly into a PC board.
(6) The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full
advantage of this improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either
metal traces on, or thermal vias through, the printed circuit board. Without this additional heat sinking, device power dissipation must be
calculated using θJA, rather than θJC, thermal resistance. It must not be assumed that the device leads will provide substantial heat
transfer out the package, since the thermal resistance of the leadframe material is very poor, relative to the material of the package
base. The stated θJC thermal resistance is for the package material only, and does not account for the additional thermal resistance
between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and
must combine this with the stated value for the package, to calculate the total allowed power dissipation for the device.
(7) Human body model, 1.5 kΩ in series with 100 pF.
Recommended Operating Conditions(1)
Supply Voltage
5.5V ≤ VS ≤ 36V
Operating Temperature Range
−55°C ≤ TA ≤ +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the
Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Copyright © 2009–2013, Texas Instruments Incorporated
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Table 1. Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp °C
25
1
2
Static tests at
125
-55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
5
125
-55
25
6
7
8A
8B
9
125
-55
25
10
11
12
13
14
125
-55
25
125
-55
4
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SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
LM7171 (±15) Electrical Characteristics DC Parameters(1)(2)
The following conditions apply, unless otherwise specified.
DC:
TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL > 1MΩ
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Units
VIO
Input Offset Voltage
−1.0
−7.0
1.0
7.0
10
mV
mV
µA
µA
µA
µA
µA
µA
dB
dB
dB
dB
dB
dB
dB
dB
V
1
2, 3
1
+IIB
Input Bias Current
12
2, 3
1
-IIB
Input Bias Current
10
12
2, 3
1
IIO
Input Offset Current
−4.0
−6.0
85
4.0
6.0
2, 3
1
CMRR
PSRR
AV
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
VCM = ±10V
70
2, 3
1
VS = ±15V to ±5V
RL = 1KΩ, VO = ±5V
RL = 100Ω, VO = ±5V
RL = 1KΩ
85
80
2, 3
1
See(3)
See(3)
See(3)
See(3)
80
75
2, 3
1
75
70
2, 3
1
VO
Output Swing
13
-13
12.7 -12.7
10.5 -9.5
V
2, 3
1
RL = 100Ω
V
9.5
105
95
-9.0
V
2, 3
1
Output Current (Open Loop)
Supply Current
Sourcing
RL = 100Ω
See(4)
See(4)
See(4)
See(4)
mA
mA
mA
mA
mA
mA
2, 3
1
Sinking
RL = 100Ω
-95
-90
8.5
9.5
2, 3
1
IS
2, 3
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are specified only for the conditions as specified in MIL-STD-883, per Test Method
1019, Condition A.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. Low dose rate testing has been peformed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-
STD-883, with no enhanced low dose rate sensitivity (ELDRS).
(3) Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT
±5V. For VS = ±5V, VOUT = ±1V.
=
(4) The open loop output current is specified, by the measurement of the open loop output voltage swing, using 100Ω output load.
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LM7171 (±15) Electrical Characteristics AC Parameters(1)(2)
The following conditions apply, unless otherwise specified.
AC:
TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL > 1MΩ
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Units
SR
Slew Rate
Unity-Gain Bandwidth
AV = 2, VI = ±2.5V
3nS Rise & Fall time
See(3)(4) 2000
V/µS
4
GBW
See(5)
170
MHz
4
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are specified only for the conditions as specified in MIL-STD-883, per Test Method
1019, Condition A.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. Low dose rate testing has been peformed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-
STD-883, with no enhanced low dose rate sensitivity (ELDRS).
(3) See AN00001 for SR test circuit.
(4) Slew Rate measured between ±4V.
(5) See AN00002 for GBW test circuit.
LM7171 (±15) Electrical Characteristics DC Drift Parameters(1)(2)
The following conditions apply, unless otherwise specified.
DC:
Delta calculations performed on QMLV devices at group B , subgroup 5.
TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL > 1MΩ
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Units
VIO
Input Offset Voltage
Input Bias Current
Input Bias Current
-250 250
-500 500
-500 500
µV
nA
nA
1
1
1
+IBias
-IBias
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are specified only for the conditions as specified in MIL-STD-883, per Test Method
1019, Condition A.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. Low dose rate testing has been peformed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-
STD-883, with no enhanced low dose rate sensitivity (ELDRS).
6
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SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
LM7171 (±5) Electrical Characteristics DC Parameters(1)(2)
The following conditions apply, unless otherwise specified.
DC:
TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL > 1MΩ
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Units
VIO
+IIB
-IIB
Input Offset Voltage
−1.5
−7.0
1.5
7.0
10
mV
mV
µA
µA
µA
µA
µA
µA
dB
dB
dB
dB
dB
dB
V
1
2, 3
1
Input Bias Current
12
2, 3
1
Input Bias Current
10
12
2, 3
1
IIO
Input Offset Current
−4.0
−6.0
80
4.0
6.0
2, 3
1
CMRR
AV
Common Mode Rejection Ratio
Large Signal Voltage Gain
VCM = ±2.5V
70
2, 3
1
RL = 1KΩ, VO = ±1V
RL = 100Ω, VO = ±1V
RL = 1KΩ
See(3)
See(3)
See(3)
See(3)
75
70
2, 3
1
72
67
2, 3
1
VO
Output Swing
3.2
3.0
2.9
-3.2
-3.0
-2.9
V
2, 3
1
RL = 100Ω
V
2.8 -2.75
V
2, 3
1
Output Current (Open Loop)
Supply Current
Sourcing
RL = 100Ω
See(4)
See(4)
See(4)
See(4)
29
mA
mA
mA
mA
mA
mA
28
2, 3
1
Sinking
RL = 100Ω
-29
-27.5
8.0
9.0
2, 3
1
IS
2, 3
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are specified only for the conditions as specified in MIL-STD-883, per Test Method
1019, Condition A.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. Low dose rate testing has been peformed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-
STD-883, with no enhanced low dose rate sensitivity (ELDRS).
(3) Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT
±5V. For VS = ±5V, VOUT = ±1V.
=
(4) The open loop output current is specified, by the measurement of the open loop output voltage swing, using 100Ω output load.
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LM7171 (±5) Electrical Characteristics DC Drift Parameters(1)(2)
The following conditions apply, unless otherwise specified.
DC:
Delta calculations performed on QMLV devices at group B , subgroup 5.
TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL > 1MΩ
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Units
VIO
Input Offset Voltage
Input Bias Current
Input Bias Current
-250 250
-500 500
-500 500
µV
nA
nA
1
1
1
+IBias
-IBias
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are specified only for the conditions as specified in MIL-STD-883, per Test Method
1019, Condition A.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. Low dose rate testing has been peformed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-
STD-883, with no enhanced low dose rate sensitivity (ELDRS).
8
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SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
Typical Performance Characteristics
unless otherwise noted, TA= 25°C
Supply Current
vs Supply Voltage
Supply Current
vs Temperature
Figure 3.
Figure 4.
Input Offset Voltage
vs Temperature
Input Bias Current
vs Temperature
Figure 5.
Figure 6.
Short Circuit Current
vs Temperature (Sourcing)
Short Circuit Current
vs Temperature (Sinking)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Output Voltage
vs Output Current
Output Voltage
vs Output Current
Figure 9.
Figure 10.
CMRR
vs
Frequency
PSRR
vs
Frequency
Figure 11.
Figure 12.
PSRR
vs
Frequency
Open Loop Frequency
Response
Figure 13.
Figure 14.
10
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SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Open Loop Frequency
Gain-Bandwidth Product
vs Supply Voltage
Response
Figure 15.
Figure 16.
Gain-Bandwidth Product
vs Load Capacitance
Large Signal Voltage Gain
vs Load
Figure 17.
Figure 18.
Large Signal Voltage Gain
vs Load
Input Voltage Noise
vs Frequency
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Input Voltage Noise
Input Current Noise
vs Frequency
vs Frequency
Figure 21.
Figure 22.
Input Current Noise
vs Frequency
Slew Rate
vs Supply Voltage
Figure 23.
Figure 24.
Slew Rate
vs Input Voltage
Slew Rate
vs Load Capacitance
Figure 25.
Figure 26.
12
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Open Loop Output
Open Loop Output
Impedance
vs
Impedance
vs
Frequency
Frequency
Figure 27.
Figure 28.
Large Signal Pulse
Response AV = −1,
VS = ±15V
Large Signal Pulse
Response AV = −1,
VS = ±5V
Figure 29.
Figure 30.
Large Signal Pulse
Response AV = +2,
VS = ±15V
Large Signal Pulse
Response AV = +2,
VS = ±5V
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Small Signal Pulse
Small Signal Pulse
Response AV = −1,
VS = ±5V
Response AV = −1,
VS = ±15V
Figure 33.
Figure 34.
Small Signal Pulse
Response AV = +2,
VS = ±15V
Small Signal Pulse
Response AV = +2,
VS = ±5V
Figure 35.
Figure 36.
Closed Loop Frequency
Response
Closed Loop Frequency
Response
vs
vs
Supply
Voltage (AV = +2)
Capacitive
Load (AV = +2)
Figure 37.
Figure 38.
14
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Closed Loop Frequency
Closed Loop Frequency
Response
Response
vs
vs
Capacitive
Load (AV = +2)
Input Signal
Level (AV = +2)
Figure 39.
Figure 40.
Closed Loop Frequency
Response
Closed Loop Frequency
Response
vs
vs
Input Signal
Level (AV = +2)
Input Signal
Level (AV = +2)
Figure 41.
Figure 42.
Closed Loop Frequency
Response
Closed Loop Frequency
Response
vs
vs
Input Signal
Level (AV = +2)
Input Signal
Level (AV = +4)
Figure 43.
Figure 44.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Closed Loop Frequency
Closed Loop Frequency
Response
Response
vs
vs
Input Signal
Level (AV = +4)
Input Signal
Level (AV = +4)
Figure 45.
Figure 46.
Closed Loop Frequency
Response
vs
Input Signal
Level (AV = +4)
Total Harmonic Distortion
vs Frequency
Figure 47.
Figure 48.
Total Harmonic Distortion
vs Frequency
Undistorted Output Swing
vs Frequency
Figure 49.
Figure 50.
16
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Typical Performance Characteristics (continued)
unless otherwise noted, TA= 25°C
Undistorted Output Swing
Undistorted Output Swing
vs Frequency
vs Frequency
Figure 51.
Figure 52.
Harmonic Distortion
vs Frequency
Harmonic Distortion
vs Frequency
Figure 53.
Figure 54.
Maximum Power Dissipation
vs Ambient Temperature
The THD measurement at low frequency is limited by the test instrument.
Figure 55.
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APPLICATION NOTES
LM7171 Performance Discussion
The LM7171 is a very high speed, voltage feedback amplifier. It consumes only 6.5 mA supply current while
providing a unity-gain bandwidth of 200 MHz and a slew rate of 4100V/μs. It also has other great features such
as low differential gain and phase and high output current.
The LM7171 is a true voltage feedback amplifier. Unlike current feedback amplifiers (CFAs) with a low inverting
input impedance and a high non-inverting input impedance, both inputs of voltage feedback amplifiers (VFAs)
have high impedance nodes. The low impedance inverting input in CFAs and a feedback capacitor create an
additional pole that will lead to instability. As a result, CFAs cannot be used in traditional op amp circuits such as
photodiode amplifiers, I-to-V converters and integrators where a feedback capacitor is required.
LM7171 Circuit Operation
The class AB input stage in the LM7171 is fully symmetrical and has a similar slewing characteristic to the
current feedback amplifiers. In the LM7171 Simplified Schematic, Q1 through Q4 form the equivalent of the
current feedback input buffer, RE the equivalent of the feedback resistor, and stage A buffers the inverting input.
The triple-buffered output stage isolates the gain stage from the load to provide low output impedance.
LM7171 Slew Rate Characteristic
The slew rate of the LM7171 is determined by the current available to charge and discharge an internal high
impedance node capacitor. This current is the differential input voltage divided by the total degeneration resistor
RE. Therefore, the slew rate is proportional to the input voltage level, and the higher slew rates are achievable in
the lower gain configurations. A curve of slew rate versus input voltage level is provided in the “Typical
Performance Characteristics”.
When a very fast large signal pulse is applied to the input of an amplifier, some overshoot or undershoot occurs.
By placing an external resistor such as 1 kΩ in series with the input of the LM7171, the bandwidth is reduced to
help lower the overshoot.
Slew Rate Limitation
If the amplifier's input signal has too large of an amplitude at too high of a frequency, the amplifier is said to be
slew rate limited; this can cause ringing in time domain and peaking in frequency domain at the output of the
amplifier.
In the Typical Performance Characteristics section, there are several curves of AV = +2 and AV = +4 versus input
signal levels. For the AV = +4 curves, no peaking is present and the LM7171 responds identically to the different
input signal levels of 30 mV, 100 mV and 300 mV.
For the AV = +2 curves, slight peaking occurs. This peaking at high frequency (>100 MHz) is caused by a large
input signal at high enough frequency that exceeds the amplifier's slew rate. The peaking in frequency response
does not limit the pulse response in time domain, and the LM7171 is stable with noise gain of ≥+2.
Layout Consideration
PRINTED CIRCUIT BOARDS AND HIGH SPEED OP AMPS
There are many things to consider when designing PC boards for high speed op amps. Without proper caution, it
is very easy to have excessive ringing, oscillation and other degraded AC performance in high speed circuits. As
a rule, the signal traces should be short and wide to provide low inductance and low impedance paths. Any
unused board space needs to be grounded to reduce stray signal pickup. Critical components should also be
grounded at a common point to eliminate voltage drop. Sockets add capacitance to the board and can affect high
frequency performance. It is better to solder the amplifier directly into the PC board without using any socket.
USING PROBES
Active (FET) probes are ideal for taking high frequency measurements because they have wide bandwidth, high
input impedance and low input capacitance. However, the probe ground leads provide a long ground loop that
will produce errors in measurement. Instead, the probes can be grounded directly by removing the ground leads
and probe jackets and using scope probe jacks.
18
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM7171QML LM7171QML-SP
LM7171QML, LM7171QML-SP
www.ti.com
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
COMPONENT SELECTION AND FEEDBACK RESISTOR
It is important in high speed applications to keep all component leads short. For discrete components, choose
carbon composition-type resistors and mica-type capacitors. Surface mount components are preferred over
discrete components for minimum inductive effect.
Large values of feedback resistors can couple with parasitic capacitance and cause undesirable effects such as
ringing or oscillation in high speed amplifiers. For the LM7171, a feedback resistor of 510Ω gives optimal
performance.
Compensation for Input
Capacitance
The combination of an amplifier's input capacitance with the gain setting resistors, adds a pole that can cause
peaking or oscillation. To solve this problem, a feedback capacitor with a value
CF > (RG × CIN)/RF
(1)
can be used to cancel that pole. For the LM7171, a feedback capacitor of 2 pF is recommended. Figure 56
illustrates the compensation circuit.
Figure 56. Compensating for Input Capacitance
Power Supply Bypassing
Bypassing the power supply is necessary to maintain low power supply impedance across frequency. Both
positive and negative power supplies should be bypassed individually by placing 0.01 μF ceramic capacitors
directly to power supply pins and 2.2 μF tantalum capacitors close to the power supply pins.
Figure 57. Power Supply Bypassing
Termination
In high frequency applications, reflections occur if signals are not properly terminated. Figure 58 shows a
properly terminated signal while Figure 59 shows an improperly terminated signal.
Copyright © 2009–2013, Texas Instruments Incorporated
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19
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LM7171QML, LM7171QML-SP
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
www.ti.com
Figure 58. Properly Terminated Signal
Figure 59. Improperly Terminated Signal
To minimize reflection, coaxial cable with matching characteristic impedance to the signal source should be
used. The other end of the cable should be terminated with the same value terminator or resistor. For the
commonly used cables, RG59 has 75Ω characteristic impedance, and RG58 has 50Ω characteristic impedance.
Driving Capacitive Loads
Amplifiers driving capacitive loads can oscillate or have ringing at the output. To eliminate oscillation or reduce
ringing, an isolation resistor can be placed as shown below in Figure 60. The combination of the isolation resistor
and the load capacitor forms a pole to increase stability by adding more phase margin to the overall system. The
desired performance depends on the value of the isolation resistor; the bigger the isolation resistor, the more
damped the pulse response becomes. For LM7171, a 50Ω isolation resistor is recommended for initial
evaluation. Figure 61 shows the LM7171 driving a 150 pF load with the 50Ω isolation resistor.
Figure 60. Isolation Resistor Used
to Drive Capacitive Load
20
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Product Folder Links: LM7171QML LM7171QML-SP
LM7171QML, LM7171QML-SP
www.ti.com
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
Figure 61. The LM7171 Driving a 150 pF Load
with a 50Ω Isolation Resistor
Power Dissipation
The maximum power allowed to dissipate in a device is defined as:
PD = (TJ(max) − TA)/θJA
(2)
Where
PD is the power dissipation in a device
TJ(max) is the maximum junction temperature
TA is the ambient temperature
θJA is the thermal resistance of a particular package
For example, for the LM7171 in a CFP package, the maximum power dissipation at 25°C ambient temperature is
680 mW.
Thermal resistance, θJA, depends on parameters such as die size, package size and package material. The
smaller the die size and package, the higher θJA becomes. The 8-pin CDIP package has a lower thermal
resistance (106°C/W) than that of the CFP (182°C/W). Therefore, for higher dissipation capability, use an 8-pin
CDIP package.
The total power dissipated in a device can be calculated as:
PD = PQ + PL
(3)
PQ is the quiescent power dissipated in a device with no load connected at the output. PL is the power dissipated
in the device with a load connected at the output; it is not the power dissipated by the load.
Furthermore,
PQ: = supply current × total supply voltage with no load
PL: = output current × (voltage difference between supply voltage and output voltage of the same side of
supply voltage)
For example, the total power dissipated by the LM7171 with VS = ±15V and output voltage of 10V into 1 kΩ is
PD = PQ + PL
= (6.5 mA) × (30V) + (10 mA) × (15V − 10V)
= 195 mW + 50 mW
= 245 mW
Copyright © 2009–2013, Texas Instruments Incorporated
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LM7171QML, LM7171QML-SP
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
www.ti.com
Application Circuit
Figure 62. Fast Instrumentation Amplifier
Figure 63. Multivibrator
Figure 64. Pulse Width Modulator
22
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Product Folder Links: LM7171QML LM7171QML-SP
LM7171QML, LM7171QML-SP
www.ti.com
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
Figure 65. Video Line Driver
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LM7171QML LM7171QML-SP
LM7171QML, LM7171QML-SP
SNOSAR5C –FEBRUARY 2009–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Released
Revision
Section
Changes
02/04/09
A
New Release, Corporate format
1 MDS data sheet converted into one Corp. data
sheet format. Added ELDRS NSID's to Ordering
Information Table. MNLM7171AM-X-RH Rev 0C0 will
be archived.
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM7171QML LM7171QML-SP
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-9553601QPA
ACTIVE
CDIP
CFP
NAB
8
40
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
LM7171AMJQML
5962-95536
01QPA Q ACO
01QPA Q >T
Samples
5962-9553601QXA
5962F9553601VHA
ACTIVE
ACTIVE
NAC
NAD
10
54
19
Non-RoHS
& Green
Call TI
Call TI
-55 to 125
-55 to 125
LM7171AM
WG Q
5962-95536
01QXA ACO
01QXA >T
Samples
Samples
CFP
10
Non-RoHS
& Green
Level-1-NA-UNLIM
LM7171AM
WFQMLV Q
5962F95536
01VHA ACO
01VHA >T
5962F9553601VPA
5962F9553601VXA
ACTIVE
ACTIVE
CDIP
CFP
NAB
NAC
8
40
54
Non-RoHS
& Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
LM7171AMJFQV
5962F95536
01VPA Q ACO
01VPA Q >T
Samples
Samples
10
Non-RoHS
& Green
LM7171AM
WGFQMLV Q
5962F95536
01VXA ACO
01VXA >T
5962F9553602VHA
ACTIVE
CFP
NAD
10
19
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
LM7171AM
WFLQMLV Q
5962F95536
02VHA ACO
02VHA >T
Samples
LM7171AMJ-QML
ACTIVE
ACTIVE
CDIP
CDIP
NAB
NAB
8
8
40
40
Non-RoHS
& Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
LM7171AMJQML
5962-95536
01QPA Q ACO
01QPA Q >T
Samples
Samples
LM7171AMJFQMLV
Non-RoHS
& Green
LM7171AMJFQV
5962F95536
01VPA Q ACO
01VPA Q >T
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM7171AMWFLQMLV
LM7171AMWFQMLV
LM7171AMWG-QML
LM7171AMWGFQMLV
LM7171NAB/EM
ACTIVE
CFP
CFP
CFP
CFP
CDIP
NAD
10
10
10
10
8
19
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
LM7171AM
Samples
WFLQMLV Q
5962F95536
02VHA ACO
02VHA >T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NAD
NAC
NAC
NAB
19
54
54
40
Non-RoHS
& Green
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
-55 to 125
-55 to 125
LM7171AM
WFQMLV Q
5962F95536
01VHA ACO
01VHA >T
Samples
Samples
Samples
Samples
Non-RoHS
& Green
LM7171AM
WG Q
5962-95536
01QXA ACO
01QXA >T
Non-RoHS
& Green
LM7171AM
WGFQMLV Q
5962F95536
01VXA ACO
01VXA >T
Non-RoHS
& Green
LM7171NABEM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2023
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM7171QML, LM7171QML-SP :
Military : LM7171QML
•
Space : LM7171QML-SP
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-9553601QPA
5962F9553601VHA
5962F9553601VPA
LM7171AMJ-QML
LM7171AMJFQMLV
LM7171AMWFQMLV
LM7171NAB/EM
NAB
NAD
NAB
NAB
NAB
NAD
NAB
CDIP
CFP
8
10
8
40
19
40
40
40
19
40
506.98
502
15.24
23
13440
9398
NA
9.78
NA
CDIP
CDIP
CDIP
CFP
506.98
506.98
506.98
502
15.24
15.24
15.24
23
13440
13440
13440
9398
8
NA
8
NA
10
8
9.78
NA
CDIP
506.98
15.24
13440
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
5962-9553601QXA
5962F9553601VXA
LM7171AMWG-QML
LM7171AMWGFQMLV
NAC
NAC
NAC
NAC
CFP
CFP
CFP
CFP
10
10
10
10
54
54
54
54
6 X 9
6 X 9
6 X 9
6 X 9
100
100
100
100
101.6 101.6 8001 2.78 16.08 16.08
101.6 101.6 8001 2.78 16.08 16.08
101.6 101.6 8001 2.78 16.08 16.08
101.6 101.6 8001 2.78 16.08 16.08
Pack Materials-Page 2
MECHANICAL DATA
NAB0008A
J08A (Rev M)
www.ti.com
PACKAGE OUTLINE
NAC0010A
CFP - 2.33mm max height
S
C
A
L
E
1
.
8
0
0
CERAMIC FLATPACK
LEAD 1 ID
NOTE 3
SUPPLIER OPTION
NOTE 3
.010 .002
[0.25 0.05]
.005 MIN
[0.12]
TYP
10
1
.2410 .0030
[6.121 0.076]
8X .050 .002
[1.27 0.05]
5
6
10X .017 .002
[0.43 0.05]
+.020
-.005
.241
+0.50
-0.12
6.12
[
]
.410 .010
[10.41 0.25]
+.010
.070
-.020
+0.25
SEE DETAIL A
.045 MAX TYP
[1.14]
1.78
[
-0.50
]
.004 [0.1]
.008 .004 TYP
[0.2 0.1]
.006 .002 TYP
[0.15 0.05]
SEATING PLANE
R.015 .002
[0.38 0.05]
.040 .003
[1.02 0.07]
0 -4
DETAIL A
TYPICAL
4215196/D 08/2022
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. For solder thickness and composition, see the "Lead Finish Composition/Thickness" link in the packaging section of the
Texas Instruments website
3. Lead 1 identification shall be:
a) A notch or other mark within this area
b) A tab on lead 1, either side
4. No JEDEC registration as of December 2021
www.ti.com
EXAMPLE BOARD LAYOUT
NAC0010A
CFP - 2.33mm max height
CERAMIC FLATPACK
(10X .090 )
SYMM
[2.29]
(8X .050 )
[1.27]
(10X .027 )
[0.69]
SYMM
(R.002 ) TYP
[0.05]
(.37 )
[9.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 7X
.003 MAX
[0.07]
ALL AROUND
.003 MIN
[0.07]
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
METAL
SOLDERMASK
OPENING
METAL UNDER
SOLDER MASK
SOLDERMASK
OPENING
SOLDERMASK
DEFINED
NON SOLDERMASK
DEFINED
4215196/D 08/2022
www.ti.com
REVISIONS
REV
A
DESCRIPTION
E.C.N.
DATE
BY/APP'D
RELEASE TO DOCUMENT CONTROL
2197877
2198820
2198845
2200915
12/30/2021
02/14/2022
02/18/2022
08/08/2022
DAVID CHIN / ANIS FAUZI
K. SINCERBOX
B
NO CHANGE TO DRAWING; REVISION FOR YODA RELEASE;
CHANGE PIN 1 ID LOCATION ON PIN
C
D. CHIN / K. SINCERBOX
D. CHIN / K. SINCERBOX
D
.2410 .0030 WAS .2700 +.0012/-.0002;
REV
SCALE
SIZE
PAGE
OF
4215196
D
4
4
A
PACKAGE OUTLINE
NAD0010A
CFP - 2.03 mm max height
S
C
A
L
E
1
.
4
0
0
CERAMIC FLATPACK
.045 MAX
TYP
.010 .002
.27 MAX
GLASS
.005 MIN
TYP
PIN 1 ID
10
1
5
8X .050 .005
.27 MAX
6
10X .017 .002
+.019
.241
5X .32 .01
5X .32 .01
-.003
.005 .001
+.013
.067
-.012
.045
.026
4215191/A 06/2021
NOTES:
1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Copyright © 2023, Texas Instruments Incorporated
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