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LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

LM73605/LM73606 3.5V 至 36V、5A 或 6A 同步

降压转换器

1 特性

2 应用

1

•

同步整流

•

工业分布式电源应用

电信系统

可湿侧面 QFN 封装 (WQFN)

低静态电流

通用宽输入电压应用

–

关断模式下 0.8µA（典型值）

3 说明

无负载有源模式下 15µA（典型值）

LM73605/LM73606 系列同步降压直流/直流转换器器

件简单易用，可在 3.5V 至 36V 的电源电压范围内驱

动高达 5A (LM73605) 或 6A (LM73606) 的负载电流。

LM73605/LM73606可以极小的解决方案尺寸提供优异

的效率和输出精度。采用峰值电流模式控制。可调开

关频率、与外部时钟同步、FPWM 选项、电源正常状

态标志、精密使能、可调式软启动和跟踪等其他特性可

为各种应用提供灵活且简单易用的解决方案。轻负载

时的自动频率折返和可选的外部偏置电源可在整个负载

范围内提高效率。该产品系列需要极少外部组件，引脚

排列设计可简化 PCB 布局，提供最佳的 EMI 和热性

能。保护特性包括热关断、输入欠压锁定、逐周期电

流限制和断续短路保护。LM73605 和 LM73606 器件

实现了引脚对引脚的兼容，便于进行简单的电流调节。

•

宽电压转换范围：

–

t_ON-MIN= 60ns（典型值）

t_OFF-MIN= 70ns（典型值）

低 MOSFET 导通电阻：

–

R_{DS_ON_HS}= 53mΩ（典型值）

R_{DS_ON_LS}= 31mΩ（典型值）

•

具有用于提高效率的外部偏置输入

引脚可选自动模式或强制 PWM 工作模式

可调频率范围：350kHz 至 2.2MHz

可与外部时钟同步

内部补偿

电源正常状态标志

具有用于对系统 UVLO 进行编程的精密使能功能

灵活的软启动特性：

器件信息⁽¹⁾

–

启动至预偏置负载

固定或可调的软启动时间

输出电压跟踪

器件型号

LM73605

LM73606

封装

封装尺寸（标称值）

WQFN (30)

可湿侧面

6.00mm × 4.00mm

•

逐周期电流限制

具有断续模式的短路保护

热关断保护

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

借助 WEBENCH^®电源设计器并使用 LM73605 或

LM73606 创建定制设计

效率与负载电流

V_OUT= 5V，f_SW= 500kHz，自动模式

100

95

90

85

80

75

70

65

简化原理图

L

V_IN

V_OUT

SW

PVIN

EN

C_BOOT

C_OUT

C_IN

CBOOT

BIAS

RT

PGND

PGOOD

60

VIN = 12 V

VIN = 24 V

SS/TRK

R_FBT

55

50

SYNC/

MODE

FB

0.001

0.01 0.02 0.05 0.1 0.2 0.5

Load Current (A)

1

2

3 456

Eff_

R_FBB

VCC

C_VCC

AGND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAH5

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

7.4 Device Functional Modes........................................ 24

Application and Implementation ........................ 26

8.1 Application Information............................................ 26

8.2 Typical Application ................................................. 26

Power Supply Recommendations...................... 40

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Timing Characteristics............................................... 7

6.7 Switching Characteristics.......................................... 8

6.8 System Characteristics ............................................. 8

6.9 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

10 Layout................................................................... 40

10.1 Layout Guidelines ................................................. 40

10.2 Layout Example .................................................... 43

11 器件和文档支持 ..................................................... 44

11.1 器件支持................................................................ 44

11.2 相关文档 ............................................................... 44

11.3 相关链接................................................................ 44

11.4 接收文档更新通知 ................................................. 44

11.5 社区资源................................................................ 45

11.6 商标....................................................................... 45

11.7 静电放电警告......................................................... 45

11.8 Glossary................................................................ 45

12 机械、封装和可订购信息....................................... 45

7

4 修订历史记录

日期

修订版本

说明

2017 年 9 月

*

初始发行版

2

LM73605, LM73606

www.ti.com.cn

ZHCSH36 –SEPTEMBER 2017

5 Pin Configuration and Functions

RNP Package

30-Pin Wettable Flanks QFN (WQFN) 6 mm × 4 mm × 0.8 mm

Top View

NC

30

NC

29

NC

28

NC

27

26

25

24

23

22

PGND

PVIN

SW

1

2

3

4

5

SW

CBOOT

VCC

21

20

19

18

17

6

7

DAP

PVIN

BIAS

AGND

8

RT

9

EN

SYNC/

MODE

SS/TRK

FB

10

11

16

PGOOD

13

14

NC

15

NC

12

NC

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS

FET. Connect to power inductor and bootstrap capacitor.

1, 2, 3, 4, 5

SW

P

Bootstrap capacitor connection for HS FET driver. Connect a high-quality 470-nF capacitor from

this pin to the SW pin.

6

7

CBOOT

VCC

Output of internal bias supply. Used as supply to internal control circuits and drivers. Connect a

high-quality 2.2-µF capacitor from this pin to GND. TI does not recommend loading this pin by

external circuitry.

P

Optional BIAS LDO supply input. TI recommends tying to V_OUTwhen 3.3 V ≤ V_OUT≤ 18 V, or tie to

an external 3.3-V or 5-V rail if available, to improve efficiency. BIAS pin voltage must not be

greater than V_IN. Tie to ground when not in use.

8

9

BIAS

RT

P

A

Switching frequency setting pin. Place a resistor from this pin to ground to set the switching

frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground.

Soft-start control pin. Leave this pin floating for a 5-ms internal soft-start ramp. An external

capacitor can be connected from this pin to ground to extend the soft start time. A 2-µA current

sourced from this pin charges the capacitor to provide the ramp. Connect to external ramp for

tracking. Do not short to ground.

10

SS/TRK

A

Feedback input for output voltage regulation. Connect a resistor divider to set the output voltage.

Never short this pin to ground during operation.

11

FB

I

12–15,

27–30

No internal connection. Connect to ground net and copper to improve heat sinking and board-level

reliability.

NC

—

Open drain power-good flag output. Connect to suitable voltage supply through a current limiting

resistor. High = V_OUTregulation OK, Low = V_OUTregulation fault. PGOOD = LOW when EN = low

and V_IN> 2 V.

16

PGOOD

O

(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

3

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

Synchronization input and mode setting pin. Do not float. Tie to ground if not used.

Tie to ground: auto mode, higher efficiency at light loads;

Tie to logic high: forced PWM, constant switching frequency over load;

17

SYNC/MODE

I

Tie to external clock source: forced PWM, synchronize to the rising edge of the external clock.

Enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to PVIN. Precision

enable input allows adjustable input voltage UVLO using external resistor divider.

18

19

EN

I

Analog ground. Ground reference for internal circuitry. All electrical parameters are measured with

respect to this pin. Connect to system ground on PCB.

AGND

G

Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass

capacitors C_IN. C_INmust be placed right next to this pin and PGND pins on PCB, and connected

with short and wide traces.

20–22

23–26

EP

PVIN

PGND

DAP

P

G

Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP,

AGND, ground side of C_INand C_OUTon PCB. Path to C_INmust be as short as possible

Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation

path for the device. Must be used for heat sinking by soldering to ground copper on PCB. Thermal

vias are preferred to improve heat dissipation to other layers.

4

LM73605, LM73606

www.ti.com.cn

ZHCSH36 –SEPTEMBER 2017

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range of –40°C to +125°C (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

–0.1

–0.3

–3.5

–0.3

–40

MAX

UNIT

PVIN to PGND

EN to AGND

42

V_IN+ 0.3

5

FB, RT, SS/TRK to AGND

PGOOD to AGND

SYNC to AGND

Input voltages

20

V

5.5

BIAS to AGND

Lower of (V_IN+ 0.3) or 20

AGND to PGND

0.3

SW to PGND

V_IN+ 0.3

SW to PGND less than 10-ns transients

CBOOT to SW

42

5

Output voltages

V

VCC to AGND

5

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range of –40°C to +125°C (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

PVIN to PGND

3.5

0

36

EN

FB

V_IN

0

4.5

Input voltages PGOOD

0

18

V

BIAS input not used

BIAS input used

AGND to PGND

0

0.3

0

Lower of (V_IN+ 0.3) or 18

–0.1

1

0.1

Output voltage V_OUT

95% of V_IN

V

A

I_OUT, LM73605

0

5

6

Output current

Temperature

I_OUT, LM73606

0

A

Operating junction temperature, T_J

–40

125

°C

(1) Recommended operating rating indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics

5

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

6.4 Thermal Information

LM73605/LM73606

THERMAL METRIC⁽¹⁾

RNP (WQFN)

UNIT

30 PINS

34.3

14.6

7.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

7.1

R_θJC(bot)

1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, V_IN= 12 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (PVIN PINS)

Operating input voltage

range

V_IN

3.5

36

10

12

V

V_EN= 0 V

T_J= 25℃

Shutdown quiescent current;

I_SD

0.8

0.6

µA

measured at VIN pin⁽¹⁾

Operating quiescent current V_EN= 2 V, V_FB= 1.5 V, V_BIAS= 3.3 V

from V_IN(non-switching)

I_{Q_NONSW}

external

ENABLE (EN PIN)

Enable input high level for

V_CCoutput

V_{EN_VCC_H}

V_{EN_VCC_L}

V_{EN_VOUT_H}

V_ENrising

1.15

V

Enable input low level for

V_CCoutput

V_ENfalling

0.3

Enable input high level for

V_OUT

V_ENrising

1.14

1.196

1.25

200

Enable input hysteresis for

V_OUT

V_{EN_VOUT_HYS}

V_ENfalling hysteresis

–100

1.4

mV

nA

I_{LKG_EN}

Enable input leakage current V_EN= 2 V

INTERNAL LDO (VCC PIN, BIAS PIN)

PWM operation

PFM operation

V_CCrising

3.27

3.1

V

V_CC

Internal V_CCvoltage

2.96

3.14

–605

3.09

–63

3.27

3.25

V

Internal V_CCundervoltage

lockout

V_{CC_UVLO}

V_CCfalling hysteresis

V_BIASrising

mV

V

V_{BIAS_ON}

Input changeover

V_BIASfalling hysteresis

mV

Operating quiescent current

from external V_BIAS(non-

switching)

V_EN= 2 V, V_FB= 1.5 V, V_BIAS= 3.3 V

external

I_{BIAS_NONSW}

21

50

µA

VOLTAGE REFERENCE (FB PIN)

V_FB

Feedback voltage

PWM mode

V_FB= 1 V

0.987

1.006

0.2

1.017

60

V

Input leakage current at FB

I_{LKG_FB}

nA

(1) Shutdown current includes leakage current of the switching transistors.

6

LM73605, LM73606

www.ti.com.cn

ZHCSH36 –SEPTEMBER 2017

Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, V_IN= 12 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HIGH SIDE DRIVER (CBOOT PIN)

CBOOT - SW undervoltage

lockout

V_{CBOOT_UVLO}

1.6

2.2

2.7

V

CURRENT LIMITS AND HICCUP

LM73605

LM73606

LM73605

LM73606

LM73605

LM73606

6

7.4

7.3

8.7

5.5

6.6

–5

8.35

9.85

6.1

Short-circuit, high-side

I_{HS_LIMIT}

A

current limit⁽²⁾

4.79

5.8

I_{LS_LIMIT}

Low-side current limit⁽²⁾

Negative current limit

7.25

I_{NEG_LIMIT}

–6

V_HICCUP

I_{L_ZC}

Hiccup threshold on FB pin

Zero cross-current limit

0.36

1.8

0.4

0.06

0.44

2.2

V

A

SOFT START (SS/TRK PIN)

I_SSC

Soft-start charge current

2

1

µA

Soft-start discharge

resistance

R_SSD

UVLO, TSD, OCP, or EN = 0

kΩ

POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION

Power-good overvoltage

threshold

V_{PGOOD_OV}

% of FB voltage

106%

86%

110%

113%

93%

Power-good undervoltage

threshold

V_{PGOOD_UV}

% of FB voltage

90%

1.2%

1.3

V_{PGOOD_HYS}

V_{PGOOD_VALID}

Power-good hysteresis

Minimum input voltage for

proper PGOOD function

50-µA pullup to PGOOD pin, V_EN= 0 V,

T_J= 25°C

2

V

V_EN= 2.5V

V_EN= 0 V

40

30

100

90

R_PGOOD

Power-good ON-resistance

Ω

MOSFETS

High-side MOSFET ON-

resistance

(3)

R_{DS_ON_HS}

I_OUT= 1 A, V_BIAS= V_OUT= 3.3 V

53

31

90

55

mΩ

Low-side MOSFET ON-

resistance

(3)

R_{DS_ON_LS}

THERMAL SHUTDOWN

Thermal shutdown threshold Shutdown threshold

Recovery threshold

160

135

°C

(4)

T_SD

(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers,

the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.

(3) Measured at pins

(4) Ensured by design

6.6 Timing Characteristics

MIN

NOM

MAX

UNIT

CURRENT LIMITS AND HICCUP

Number of switching cycles

(1)

N_OC

128

46

Cycles

ms

before hiccup is tripped

Overcurrent hiccup retry delay

time

t_OC

(1) Ensured by design

7

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

Timing Characteristics (continued)

MIN

NOM

MAX

UNIT

SOFT START (SS/TRK PIN)

C_SS= OPEN, from EN rising

edge to PGOOD rising edge

t_SS

Internal soft-start time

3.5

6.3

ms

POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION

PGOOD rising edge deglitch

delay

t_{PGOOD_RISE}

t_{PGOOD_FALL}

80

140

200

µs

PGOOD falling edge deglitch

delay

6.7 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM LIMITS (SW PINS)

t_ON-MIN

t_OFF-MIN

t_ON-MAX

Minimum switch on-time

Minimum switch off-time

Maximum switch on-time

60

70

6

82

120

9

ns

µs

HS timeout in dropout

3

OSCILLATOR (RT and SYNC PINS)

f_OSC

Internal oscillator frequency

R_T= Open

440

315

500

350

560

385

kHz

Minimum adjustable frequency by

R_Tor SYNC

R_T=115 kΩ, 0.1%

f_ADJ

Maximum adjustable frequency by

R_Tor SYNC

R_T= 17.4 kΩ, 0.1%

1980

0.4

2200

2420

2

kHz

V_{SYNC_HIGH}

V_{SYNC_LOW}

Sync input high level threshold

Sync input low level threshold

V

Mode input high level threshold for

FPWM

V_{MODE_HIGH}

V_{MODE_LOW}

t_{SYNC_MIN}

0.42

0.4

80

V

Mode input low level threshold for

AUTO mode

Sync input minimum ON and OFF-

time

ns

6.8 System Characteristics

The following specifications apply to the circuit found in typical schematic with appropriate modifications from typical bill of

materials. These parameters are not tested in production and represent typical performance only. Unless otherwise stated the

following conditions apply: T_A= 25°C, V_IN= 12 V, V_OUT= 3.3 V, f_SW= 500 kHz.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output voltage offset at no load V_IN= 3.8 V to 36 V, V_SYNC= 0 V, auto mode

V_{FB_PFM}

V_DROP

I_{Q_SW}

2%

in auto mode

I_OUT= 0 A

Minimum input to output

voltage differential to maintain V_OUT= 5 V, I_OUT= 3 A, f_SW= 2.2 MHz

specified accuracy

0.4

V

Operating quiescent current

(switching)

V_EN= 3.3 V, I_OUT= 0 A, R_T= open, V_BIAS

V_OUT= 3.3 V , R_FBT= 1 Meg

=

15

1

µA

LM73605 :

V_SYNC= 0, I_OUT= 10 mA

I_{PEAK_MIN}

Minimum inductor peak current

A

LM73606 :

1.3

V_SYNC= 0 V, I_OUT= 10 mA

f_SW= 500 kHz, I_OUT= 1 A

f_SW= 2.2 MHz, I_OUT= 1 A

While in frequency foldback

7

mA

Operating quiescent current

from external V_BIAS(switching)

I_{BIAS_SW}

D_MAX

t_DEAD

25

Maximum switch duty cycle

97.5%

Dead time between high-side

and low-side MOSFETs

4

ns

8

LM73605, LM73606

www.ti.com.cn

ZHCSH36 –SEPTEMBER 2017

6.9 Typical Characteristics

Unless otherwise specified, V_IN= 12 V. Curves represent most likely parametric norm at specified condition.

75

70

65

60

55

50

45

40

35

30

25

20

1600

1500

1400

1300

1200

1100

1000

900

VIN = 3.5 V

VIN = 12 V

VIN = 36 V

HS Switch

LS Switch

800

700

600

500

400

300

200

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

CHAR

CHPAloRt

图 1. High-Side and Low-Side Switches R_DS-ON

图 2. Shutdown Quiescent Current

1.01

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

7.5

7

Temp = -40°C

Temp = 25°C

Temp = 125°C

6.5

6

HS

LS

5.5

5

3

6

9

12 15 18 21 24 27 30 33 36

VIN (V)

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

CHAR

图 3. Feedback Voltage

图 4. LM73605 High-Side and Low-Side Current Limits

2500

9

8.4

7.8

7.2

6.6

6

2250

2000

1750

1500

1250

1000

750

FREQ = 350 kHz

FREQ = 1 MHz

FREQ = 2.2 MHz

HS

LS

500

250

0

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

CHAR

图 5. LM73606 High-Side and Low-Side Current Limit

图 6. Switching Frequency Set by R_TResistor

9

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

Unless otherwise specified, V_IN= 12 V. Curves represent most likely parametric norm at specified condition.

550

540

530

520

510

500

490

480

470

460

450

1.28

1.2

1.12

1.04

0.96

0.88

0.8

VEN_VOUT Rising

VEN_VOUT Falling

VEN_VCC Rising

VEN_VCC Falling

VIN = 3.5 V

VIN = 12 V

VIN = 36 V

0.72

0.64

0.56

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

CHAR

图 7. Switching Frequency with RT Pin Open Circuit

图 8. Enable Thresholds

115

110

105

100

95

OV Tripping

OV Recovery

UV Recovery

UV Tripping

90

85

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

CHAR

图 9. PGOOD Thresholds

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7 Detailed Description

7.1 Overview

The LM73605/6 is an easy-to-use synchronous step-down DC-DC converter that operates from a 3.5-V to 36-V

supply voltage. It is capable of delivering up to 5-A (LM73605) or 6-A (LM73606) DC load current with

exceptional efficiency and thermal performance in a very small solution size.

The LM73605/6 employs fixed-frequency peak current-mode control with configurable auto or FPWM operation

mode. Auto mode provides very high efficiency at light loads, and FPWM mode maintains constant switching

frequency over entire load range.

The device is internally compensated, which reduces design time and the number of external components. The

switching frequency is programmable from 350 kHz to 2.2 MHz by an external resistor. The LM73605/6 can also

synchronize to an external clock within the same frequency range. The wide switching frequency range allows

the device to be optimized for a wide range of system requirements. It can be optimized for small solution size

with higher frequency; or for high efficiency with lower switching frequency. The LM73605/6 has very low

quiescent current, which is critical for battery operated systems. It allows for a wide range of voltage conversion

ratios due to very small minimum ON-time (t_ON-MIN) and minimum OFF-time (t_OFF-MIN). Automated frequency

foldback is employed at very high or low duty cycles to further extend the operating range.

The LM73605/6 also features a power-good (PGOOD) flag, precision enable, internal or adjustable soft start,

pre-biased start-up, and output voltage tracking. Protection features include thermal shutdown, undervoltage

lockout (UVLO), cycle-by-cycle current limiting, and short-circuit hiccup protection. It provides flexible and easy-

to-use solutions for a wide range of applications.

The family requires very few external components and has a pin out designed for simple, optimum PCB layout

for enhanced EMI and thermal performance. The LM73605/6 device is available in a 30-pin WQFN leadless

package.

7.2 Functional Block Diagram

ENABLE

VCC

BIAS

LDO

PVIN

I_SSC

Internal

SS

V_BOOT

Precision

Enable

CBOOT

V_CC

SS/TRK

HS I Sense

I_CMD

+

V_BOOTV_SW

EA

+

REF

œ

R_C

C_C

œ

+

UVLO

FB

UVLO

FB

V_SW

OV/UV

Detector

SW

PFM

Detector

CONTROL LOGIC

PGood

PGOOD

AGND

TSD

Hiccup

Detector

+

œ

Slope Comp

Oscillator

CLK

I_LIMIT

LS I Sense

FPWM

SYNC/

MODE

RT

PGND

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7.3 Feature Description

7.3.1 Synchronous Step-Down Regulator

The LM73605/6 is a synchronous buck converter with both power MOSFETs integrated in the device. 图 10

shows a simplified schematic for synchronous and non-synchronous buck converters. The synchronous buck

integrates both high-side (HS) and low-side (LS) power MOSFETs. The non-synchronous buck integrates HS

MOSFET and works with a discrete power diode as LS rectifier.

Synchronous

Buck

Non Synchronous

Buck

L

VIN

SW

V_OUT

C_OUT

V_OUT

V_IN

C_IN

V_IN

C_IN

C_OUT

PGND

图 10. Simplified Synchronous vs Non-synchronous Buck Converters

A synchronous converter with integrated HS and LS MOSFETs offers benefits such as less design effort, lower

external components count, reduced total solution size, higher efficiency at heavier load, easier PCB design, and

more control flexibility.

The main advantage of a synchronous converter is that the voltage drop across the LS MOSFET is lower than

the voltage drop across the power diode of a non-synchronous converter. Lower voltage drop translates into less

power dissipation and higher efficiency. The LM73605/6 integrates HS and LS MOSFETs with very low on-time

resistance to improve efficiency. It is especially beneficial when the output voltage is low. Because the LS

MOSFET is integrated into the device, at light loads a synchronous converter has the flexibility to operate in

either discontinuous or continuous conduction mode.

An integrated LS MOSFET also allows the controller to obtain inductor current information when the LS switch is

on. It allows the control loop to make more complex decisions based on HS and LS currents. It allows the

LM73605/6 to have peak and valley cycle-by-cycle current limiting for more robust protection.

7.3.2 Auto Mode and FPWM Mode

The LM73605/6 has configurable auto mode or FPWM options.

In auto mode, the device operates in diode emulation mode (DEM) at light loads. In DEM, inductor current stops

flowing when it reaches 0 A. This is also referred to as discontinuous conduction mode (DCM). This is the same

behavior as the non-synchronous regulator, with higher efficiency. At heavier load, when the inductor current

valley is above 0 A, the device operates in continuous conduction mode (CCM), where the switching frequency is

fixed and set by RT pin.

In auto mode, the peak inductor current has a minimum limit, I_{PEAK_MIN}, in the LM73605/6. When peak current

reaches I_{PEAK_MIN}, the switching frequency reduces to regulate the required load current. Switching frequency

lowers when load reduces. This is when the device operates in pulse frequency modulation (PFM). PFM further

improves efficiency by reducing switching losses. Light load efficiency is especially important for battery operated

systems.

In forced PWM (FPWM) mode, the device operates in CCM regardless of load with the frequency set by RT pin

or synchronization input. Inductor current can go negative at light loads. At light loads, the efficiency is lower than

auto mode, due to higher conduction losses and switching losses. In FPWM, the device has fixed switching

frequency over the entire load range, which is beneficial to noise sensitive applications.

图 11 shows the inductor current waveforms in each mode with heavy load, light load, and very light load. The

difference between the two modes is at lighter loads where inductor current valley reaches zero.

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Feature Description (接下页)

Auto Mode

FPWM Mode

I_L

CCM

Heavy

Loads

t

I_L

Light

Loads

CCM

DCM

PFM

t

I_L

Very Light

Loads

t

图 11. Inductor Current Waveforms at Auto Mode and FPWM Mode with Different Loads

In CCM, the inductor current peak-to-peak ripple can be estimated by 公式 1:

(V_IN- V_OUT

f_SWì L

)

V_OUT

I_Lripple

=

ì

V

IN

(1)

The average or DC value of the inductor current equals the load current, or output current I_OUT, in steady state.

Peak inductor current can be calculated by 公式 2

I_PEAK= I_OUT+ I_Lripple/ 2

(2)

Valley inductor current can be calculated by 公式 3

I_VALLEY= I_OUT– I_Lripple/ 2

(3)

In auto mode, the CCM to DCM boundary condition is when I_VALLEY= 0 A. When I_Lripple≥ I_{PEAK_MIN}, the load

current at the DCM boundary condition can be found by 公式 4. When the peak-to-peak ripple current is smaller

than I_Lripple≥ I_PEAK-MIN, the PFM boundary will be reached first.

I_OUT-DCM= I_Lripple/ 2

when

•

I_Lripple≥ I_{PEAK_MIN}

(4)

In auto mode, the PFM operation boundary condition is when I_PEAK= I_{PEAK_MIN}. Frequency foldback occurs when

peak current drops to I_{PEAK_MIN}, no matter whether in CCM or DCM operation. When current ripple is small, I_Lripple

< I_{PEAK_MIN}, the peak current reaches I_{PEAK_MIN}when still in CCM. The output current at CCM PFM boundary can

be found by 公式 5

I_OUT-CCM-PFM= I_PEAK-MIN– I_Lripple/ 2

when

•

I_Lripple< I_PEAK-MIN

(5)

The current ripple increases with reduced frequency if load reduces. When valley current reaches zero, the

frequency continues to fold back with constant peak current and discontinuous current.

In FPWM mode, there is no I_PEAK-MINlimit. The peak current is defined by 公式 2 at light loads and heavy loads.

See Frequency Synchronization and Mode Setting for mode setting options in LM73605/6. Mode setting only

affects operation at light loads. There is no difference if load current is above the DCM and PFM boundary

conditions discussed above.

7.3.3 Fixed-Frequency Peak Current-Mode Control

The LM73605/6 synchronous switched mode voltage regulator employs fixed frequency peak current mode

control with advanced features. The fixed switching frequency is controlled by an internal clock. To get accurate

DC load regulation, a voltage feedback loop is implemented to generate peak current command. The HS switch

is turned on at the rising edge of the clock. As shown in 图 12, during the HS switch on-time t_ON, the SW pin

voltage V_SWswings up to approximately V_IN, and the inductor current I_Lincreases with a linear slope. The HS

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Feature Description (接下页)

switch is turned off when the inductor current reaches the peak current command. During the HS switch off-time

t_OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the V_SWto

swing below ground by the voltage drop across the LS switch. The LS switch is turned off at the next clock cycle,

before the HS switch is turned on. The regulation loop adjusts the peak current command to maintain a constant

output voltage.

V

SW

D = t

/ T

SW

ON

V

IN

t

OFF

ON

0

t

-V

D

T

SW

I_L

I

L-PEAK

I

OUT

I

Lripple

I

L-VALLEY

0

t

图 12. SW Voltage and Inductor Current Waveforms in CCM

Duty cycle D is defined by the on-time of the HS switch over the switching period:

D = t_ON/ T_SW

where

•

T_SW= 1 / f_SWis the switching period

(6)

In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inverse

proportional to the input voltage: D = V_OUT⁄ V_IN.

When the LM73605/6 is set to operate in auto mode, the LS switch is turned off when its current reaches zero

ampere before the next clock cycle comes. Both HS switch and LS switch are off before the HS switch is turned

on at the next clock cycle.

7.3.4 Adjustable Output Voltage

The voltage regulation loop in the LM73605/6 regulates the FB pin voltage to be the same as the internal

reference voltage. The output voltage of the LM73605/6 is set by a resistor divider to program the ratio from V_OUT

to V_FB. The resistor divider is connected from the output to ground with the mid-point connecting to the FB pin.

VOUT

R_FBT

FB

R_FBB

图 13. Output Voltage Setting by Resistor Divider

The internal voltage reference and feedback loop produce precise voltage regulation over temperature. TI

recommends using divider resistors with 1% tolerance or better, and with temperature coefficient of 100 ppm or

lower. Typically, R_FBT= 10 kΩ to 100 kΩ is recommended. Larger R_FBTand R_FBBvalues reduce the quiescent

current going through the divider, which help maintain high efficiency at very light load. But larger divider values

also make the feedback path more susceptible to noise. If efficiency at very light load is critical in a certain

application, R_FBTup to 1 MΩ can be used.

R_FBBcan be calculated by 公式 7:

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Feature Description (接下页)

V_FB

R_FBB

=

R_FBT

V_OUT- V_FB

(7)

The minimum programmable V_OUTequals V_FB, with R_FBBopen. The maximum V_OUTis limited by the maximum

duty cycle at a given frequency:

D_MAX= 1 – (t_OFF-MIN/ T_SW

)

where

•

t_OFF-MINis the minimum off time of the HS switch

T_SW= 1 / f_SWis the switching period

(8)

Ideally, without frequency foldback, V_{OUT_MAX}= V_{IN_MIN}× D_MAX

.

Power losses in the circuit reduces the maximum output voltage. The LM73605/6 folds back switching frequency

under t_{OFF_MIN}condition to further extend V_{OUT_MAX}. The device maintains output regulation with lower input

voltage. The minimum fold-back frequency is limited by the maximum HS on-time, t_{ON_MAX}. Maximum output

voltage with frequency foldback can be estimated by:

t_{ON_MAX}

V_{OUT _MAX}= V

ì

- I_OUTì (R_{DS_ON_HS}+ DCR)

IN_MIN

t_{ON_MAX}+ t_{OFF_MIN}

(9)

The voltage drops on the HS MOSFET and inductor DCR have been taken into account in 公式 9. The switching

losses were not included.

If the resistor divider is not connected properly, the output voltage cannot be regulated because the feedback

loop cannot obtain correct output voltage information. If the FB pin is shorted to ground or disconnected, the

output voltage is driven close to V_IN. The load connected to the output could be damaged under this condition.

Do not short FB to ground or leave it open circuit during operation.

The FB pin is a noise sensitive node. It is important to place the resistor divider as close as possible to the FB

pin, and route the feedback node with a short and thin trace. The trace connecting V_OUTto R_FBTcan be long, but

it must be routed away from the noisy area of the PCB. For more layout recommendations, see Layout.

7.3.5 Enable and UVLO

The LM73605/6 regulates output voltage when the VCC voltage is higher than the undervoltage lock out (UVLO)

level, V_{CC_UVLO}, and the EN voltage is higher than V_{EN_VOUT_H}

.

The internal LDO output voltage VCC is turned on when the EN voltage is higher than V_{EN_VCC_H}. The precision

enable circuitry is also turned on when VCC is above UVLO. Normal operation of the LM73605/6 with regulated

output voltage is enabled when the EN voltage is greater than V_{EN_VOUT_H}. When the EN voltage is less than

V_{EN_VCC_L}, the device is in shutdown mode. The internal dividers make sure V_{EN_VOUT_H}is always higher than

V_{EN_VCC_H}

.

The EN pin cannot be left floating. The simplest way to enable the operation of the LM73605/6 is to connect the

EN pin to PVIN, which allows self-start-up of the LM73605/6 when V_INrises. Use of a pullup resistor between

PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.

Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be

used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a

battery power source. 图 14 shows how to use a resistor divider to set a system UVLO level. An external logic

output can also be used to drive the EN pin for system sequencing.

VIN

R_ENT

ENABLE

R_ENB

图 14. System UVLO

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Feature Description (接下页)

With a selected R_ENT, the R_ENBcan be calculated by:

V_{EN_ VOUT _H}

R_ENB

=

R_ENT

V

- V_{EN_VOUT_H}

IN_ON_H

where

•

V_{IN_ON_H}is the desired supply voltage threshold to turn on this device

(10)

Note that the divider adds to supply quiescent current by V_IN/ (R_ENT+ R_ENB). Small R_ENTand R_ENBvalues add

more quiescent current loss. However, large divider values make the node more sensitive to noise. R_ENTin the

hundreds of kΩ range is a good starting point.

7.3.6 Internal LDO, V_{CC_UVLO}, and BIAS Input

The LM73605/6 integrates an internal LDO, generating VCC voltage for control circuitry and MOSFET drivers.

The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and properly

grounded. Do not load the VCC pin or short it to ground during operation. Shorting VCC pin to ground during

operation may damage the device.

The UVLO on VCC voltage, V_{CC_UVLO}, turns off the regulation when VCC voltage is too low. It prevents the

LM73605/6 from operating until the VCC voltage is enough for the internal circuitry. Hysteresis on V_{CC_UVLO}

prevents the part from turning off during power up if V_INdroops due to input current demands. The LDO

generates VCC voltage from one of the two inputs: the supply voltage V_IN, or the BIAS input. When BIAS is tied

to ground, the LDO input is V_IN. When BIAS is tied to a voltage higher than 3.3 V, the LDO input is V_BIAS. BIAS

voltage must be lower than both V_INand 18 V.

The BIAS input is designed to reduce the LDO power loss. The LDO power loss is:

P_{LOSS_LDO}= I_LDO× (V_{IN_LDO}– V_{OUT_LDO}

)

(11)

The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the

same LDO output current. The BIAS input provides an option to supply the LDO with a lower voltage than V_IN, to

reduce the difference of the input and output voltages of the LDO and reduce power loss. For example, if the

LDO current is 10 mA at a certain frequency with V_IN= 24 V and V_OUT= 5 V. The LDO loss with BIAS tied to

ground is equal to 10 mA × (24 V – 3.27 V) = 207.3 mW, while the loss with BIAS tied to V_OUTis equal to 10 mA

× (5 – 3.27) = 17.3 mW.

The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher

percentage in the total loss. The improvements is more significant with higher switching frequency because the

LDO current is higher at higher switching frequency. The improvement is more significant when V_IN» V_OUT

because the voltage difference is higher.

图 15 and 图 16 show efficiency improvement with bias tied to V_OUTin a V_OUT= 5 V and f_SW= 2200 kHz

application, in auto mode and FPWM mode, respectively.

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Feature Description (接下页)

100

95

90

85

80

75

70

65

60

55

100

80

60

40

20

0

VIN = 12 V BIAS = VOUT

VIN = 12 V BIAS = GND

VIN = 24 V BIAS = VOUT

VIN = 24 V BIAS = GND

VIN = 12 V BIAS = VOUT

50

45

40

35

30

VIN = 12 V BIAS = GND

VIN = 24 V BIAS = VOUT

VIN = 24 V BIAS = GND

0.001

0.01 0.02 0.05 0.1 0.2 0.5

Load Current (A)

1

2

3 456

0.001

0.010.02 0.05 0.1 0.2 0.5

1

2 3 45 7 10

Load Current (A)

EFF_

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

图 15. LM73606 Efficiency Comparison With Bias = V_OUTto

图 16. LM73606 Efficiency Comparison With Bias = V_OUTto

Bias = GND in Auto Mode

Bias = GND in FPWM Mode

TI recommends tying the BIAS pin to V_OUTwhen V_OUTis equal to or greater than 3.3 V and no greater than 18 V.

Tie the BIAS pin to ground when not in use. A ceramic capacitor, C_BIAS, can be used from the BIAS pin to ground

for bypassing. If V_OUThas high frequency noise or spikes during transients or fault conditions, a resistor (1 to 10

Ω) connected between V_OUTto BIAS can be used together with C_BIASfor filtering.

The VCC voltage is typically 3.27 V. When the LM73605/6 is operating in PFM mode with frequency foldback,

VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very

light loads. 图 17 shows an example of VCC voltage change with mode change.

3.5

3.4

3.3

3.2

3.1

3

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2

Auto Mode

FPWM Mode

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2 3 45

VCC_

V_OUT= 5 V

f_SW= 500 kHz

V_IN= 12 V

图 17. VCC Voltage vs Load Current

VCC voltage has an internal undervoltage lockout threshold, V_{CC_UVLO}. When VCC voltage is higher than

V_{CC_UVLO}rising threshold, the device is active and in normal operation if V_EN> V_{EN_VOUT_H}. If VCC voltage droops

below V_{CC_UVLO}falling threshold, the V_OUTis shut down.

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Feature Description (接下页)

7.3.7 Soft Start and Voltage Tracking

The LM73605/6 features controlled output voltage ramp during start-up. The soft-start feature reduces inrush

current during start-up and improves system performance and reliability.

If the SS/TRK pin is floating, the LM73605/6 starts up following the fixed internal soft-start ramp.

If longer soft-start time is desired, an external capacitor can be added from SS/TRK pin to ground. There is a 2-

µA (typical) internal current source, I_SSC, to charge the external capacitor. For a desired soft-start time t_SS

,

capacitance of C_SScan be found by 公式 12.

C_SS= I_SSC× t_SS

where

•

C_SS= soft-start capacitor value (F)

I_SSC= soft-start charging current (A)

t_SS= desired soft-start time (s)

(12)

The FB voltage always follows the lower potential of the internal voltage ramp or the voltage on the SS/TRK pin.

Thus, the soft-start time can only be extended longer than the internal soft-start time by connecting C_SS. Use C_SS

to extend soft-start time when there are a large amount of output capacitors, or the output voltage is high, or the

output is heavily loaded during start-up.

LM73605/6 is operating in diode emulation mode during start-up regardless of mode setting. The device is

capable of starting up into pre-biased output conditions. During start-up, the device sets the minimum inductor

current to zero to avoid back charging the input capacitors.

LM73605/6 can track an external voltage ramp applied to the SS/TRK pin, if the ramp is slower than the internal

soft-start ramp. The external ramp final voltage after start-up must be greater than 1.5 V to avoid noise interfering

with the reference voltage. 图 18 shows how to use resistor divider to set V_OUTto follow an external ramp.

EXT RAMP

R_TRT

SS/TRK

R_TRB

图 18. Soft Start Tracking External Ramp

V_OUTtracking also provides the option of ramping up faster than the internal start-up ramp. The FB voltage

always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. 图 19 shows

the case when V_OUTramps slower than the internal ramp, while 图 20 shows when V_OUTramps faster than the

internal ramp. If the tracking ramp is delayed after the internal ramp is completed, V_FBfollows the tracking ramp

even if it is faster than the internal ramp. Faster start-up time may result in large inductor current during start-up.

Use with special care.

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

V_OUT

图 19. Tracking With Longer Start-up Time than the Internal Ramp

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Feature Description (接下页)

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

V_OUT

图 20. Tracking With Shorter Start-up Time than the Internal Ramp

The SS/TRK pin is discharged to ground by an internal pulldown resistor R_SSDwhen the output voltage is

shutting down, such as in the event of UVLO, thermal shutdown, hiccup, or V_EN= 0. If a large C_SSis used, and

the time when V_EN= 0 V is very short, the C_SSmay not be fully discharged before the next soft start. Under this

condition, the FB voltage follows the internal ramp slew rate until the voltage on C_SSis reached, then follow the

slew rate defined by C_SS

.

7.3.8 Adjustable Switching Frequency

The internal oscillator frequency is controlled by the impedance on the RT pin. If the RT pin is open circuit, the

LM73605/6 operates at its default switching frequency, 500 kHz. The RT pin is not designed to be connected

directly to ground. To program the switching frequency by R_Tresistor, 公式 13, or 图 21, or 表 1 can be used to

find the resistance value.

1

R_T(kW) =

f_SW(kHz) ì 2.675 ì 10^-5- 0.0007

(13)

120

110

100

90

80

70

60

50

40

30

20

10

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Frequency (kHz)

RT_F

图 21. R_TResistance vs Switching Frequency

表 1. Typical Frequency Setting Resistance

SWITCHING FREQUENCY f_SW(kHz)

R_TRESISTANCE (kΩ)

350

400

115

100

500

78.7 (or open)

52.3

750

1000

1500

2000

2200

39.2

26.1

19.1

17.4

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The choice of switching frequency is usually a compromise between conversion efficiency and the size of the

solution. Lower switching frequency has lower switching losses (including gate charge losses, switch transition

losses, etc.). It usually results in higher overall efficiency. However, higher switching frequency allows the use of

smaller power inductor and output capacitors, hence a more compact design. Lower inductance also helps

transient response (higher large signal slew rate of inductor current), and has lower DCR. The optimal switching

frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.

Factors that need to be taken into account include input voltage range, output voltage, most frequent load current

level(s), external component choices, solution size/cost requirements, efficiency and thermal management

requirements.

The choice of switching frequency may also be limited whether an operating condition triggers t_{ON_MIN}or t_OFF-MIN

.

Minimum on-time, t_ON-MIN, is the smallest time that the HS switch can be on. Minimum OFF-time, t_OFF-MIN, is the

smallest duration that the HS switch can be off.

In CCM operation, t_ON-MINand t_{OFF_MIN}limits the voltage conversion range given a selected switching frequency,

F_SW. The minimum duty cycle allowed is:

D_MIN= t_ON-MIN× f_SW

(14)

The maximum duty cycle allowed is:

D_MAX= 1 – t_OFF-MIN× f_SW

(15)

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size and efficiency. The maximum operational supply voltage can be found by:

V_IN-MAX= V_OUT/ (f_SW× t_ON-MIN

)

(16)

At lower supply voltage, the switching frequency decreases once t_OFF-MINis tripped. The minimum V_INwithout

frequency foldback can be approximated by:

V_IN-MIN= V_OUT/ (1 – f_SW× t_OFF-MIN

)

(17)

With a desired V_OUT, the range of allowed V_INis narrower with higher switching frequency.

LM73605/6 has an advanced frequency fold-back algorithm under both t_{ON_MIN}and t_{OFF_MIN}conditions. With

frequency foldback, stable output voltage regulation is extended to wider range of supply voltages.

At very high V_INconditions, where t_{ON_MIN}limitation is met, the switching frequency reduces to allow higher V_IN

while maintaining V_OUTregulation. Note that the peak to peak inductor current ripple will increase with higher V_IN

and lower frequency. TI does not recommend designing the circuit to operate with t_{ON_MIN}under typical

conditions.

At very low V_INconditions, where t_{OFF_MIN}limitation is met, the switching frequency decreases until t_{ON_MAX}

condition is met. Such frequency fold-back mechanism allows the LM73605/6 to have very low dropout voltage

regardless of frequency setting.

7.3.9 Frequency Synchronization and Mode Setting

The LM73605/6 switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends

connecting the external clock to the SYNC/MODE pin with an appropriate termination resistor. Ground the

SYNC/MODE pin if not used.

SYNC/

MODE

EXT CLOCK

R

SYNC

图 22. Frequency Synchronization

Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V,

duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the

external clock fails at logic high or low, the LM73605/6 switches at the frequency programmed by the R_Tresistor

after a time-out period. TI recommends connecting a resistor to the RT pin such that the internal oscillator

frequency is the same as the external clock frequency. This allows the regulator to continue operating at

approximately the same switching frequency if the external clock fails with the same control loop behavior.

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The SYNC/MODE pin is also used as an operation mode control input.

•

To set the operation in auto mode, connect SYNC/MODE pin to ground, or a logic signal lower than 0.3 V.

To set the operation in FPWM mode, connect SYNC/MODE pin to a bias voltage or logic signal greater than

0.6 V.

•

When the LM73605/6 is synchronized to an external clock, the operation mode is FPWM.

表 2 summarizes the operation mode and features according to the SYNC/MODE input signal. For more details,

see Active Mode and Auto Mode and FPWM Mode.

表 2. SYNC/MODE Pin Settings and Operation Modes

SYNC/MODE

INPUT

SWITCHING

FREQUENCY

OPERATING

MODE

LIGHT LOAD BEHAVIOR

•

No negative inductor current, device operates in discontinuous conduction mode

(DCM) when current valley reaches 0 A.

Logic low

Set by R_Tresistor

Auto mode

Minimum peak inductor current is limited at I_{PEAK_MIN}; device operates in pulse

frequency modulation (PFM) mode when peak current reaches I_{PEAK_MIN}

.

Switching frequency reduces in PFM mode.

Logic high

•

Fixed frequency continuous conduction mode (CCM) regardless of load

Inductor current have negative portion at light loads

No I_{PEAK_MIN}

FPWM mode

Set by external

clock

External clock

7.3.10 Internal Compensation and C_FF

The LM73605/6 is internally compensated. The internal compensation is designed such that the loop response is

stable over a wide operating frequency and output voltage range. The internal R-C values are 500 kΩ and 30 pF

respectively.

When large resistance value (MΩ) is used for R_FBT, the pole formed by an internal parasitic capacitor and R_FBT

can be low enough to reduce the phase margin. If only low ESR output capacitors (ceramic types) are used for

C_OUT, the control loop could have low phase margin. To provide a phase boost an external feed-forward

capacitor (C_FF) can be added in parallel with R_FBT. Choose the C_FFcapacitor to provide most phase boost at the

estimated crossover frequency f_X:

K

f_X

=

V_OUTì C_OUT

where

•

K = 20.27 with LM73605

K = 24.16 with LM73606

(18)

Select C_OUTso that the f_Xis no higher than 1/6 of the switching frequency. Typically, f_X/ f_SW= 1/10 to 1/8

provides a good combination of stability and performance.

Place the external feed-forward capacitor in parallel with the top resistor divider R_FBTwhen additional phase

boost is needed.

VOUT

R_FBT

C_FF

FB

R_FBB

图 23. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FFin parallel with R_FBTplaces an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by 公式 19:

f_Z-CFF= 1 / (2π × R_FBT× C_FF

)

(19)

An additional pole is also introduced with C_FFat the frequency of:

f_P-CFF= 1 / (2π × C_FF× (R_FBT// R_FBB))

(20)

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Select the C_FFso that the bandwidth of the control loop without the C_FFis centered between f_Z-CFFand f_P-CFF. The

zero at f_Z-CFFadds phase boost at the crossover frequency and improves transient response. The pole at f_P-CFF

helps maintaining proper gain margin at frequency beyond the crossover.

The need of C_FFdepends on R_FBTand C_OUT. Typically, choose R_FBT≤ 100 kΩ. C_FFmay not be required, because

the internal parasitic pole is at higher frequency. If C_OUThas larger ESR, and ESR zero f_Z-ESR= 1 / (2π × ESR ×

C_OUT) is low enough to provide phase boost around the crossover frequency, do not use C_FF. 公式 21 was tested

for ceramic output capacitors:

1

C_FF

=

ì

2 ì p ì f_x

R_FBTì (R_FBT// R_FBB

)

(21)

The C_FFcreates a time constant with R_FBTthat couples in the attenuated output voltage ripple to the FB node. If

the C_FFvalue is too large, it can couple too much ripple to the FB and affect V_OUTregulation. It could also couple

too much transient voltage deviation and falsely trigger PGOOD flag.

7.3.11 Bootstrap Capacitor and V_BOOT-UVLO

The driver of the HS switch requires a bias voltage higher than the V_INvoltage. The capacitor, C_BOOTin 简化原理

图, connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to

(V_SW+ V_CC). A boot diode is integrated on the die to minimize external component count. TI recommends a high-

quality 0.47-µF, 6.3-V or higher voltage ceramic capacitor for C_BOOT. The V_{BOOT_UVLO}threshold is designed to

maintain proper HS switch operation. If the C_BOOTis not charged above this voltage with respect to SW, the

device initiates a charging sequence using the LS switch before turning on the HS switch.

7.3.12 Power-Good and Overvoltage Protection

The LM73605/6 has a built-in power-good (PGOOD) flag to indicate whether the output voltage is at an

appropriate level or not. The PGOOD flag can be used for start-up sequencing of multiple rails. The PGOOD pin

is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 15 V).

The pin can sink 5 mA of current and maintain its specified logic low level. A typical pullup resistor value is 10 kΩ

to 100 kΩ. When the FB voltage is higher than V_PGOOD-OVor lower than V_PGOOD-UVthreshold, the PGOOD internal

switch is turned on, and the PGOOD pin voltage is pulled low. When the FB is within the range, the PGOOD

switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. The PGOOD function

also have a deglitch timer for about 140 µs for each transition. If it is desired to pull up PGOOD pin to a voltage

higher than 15 V, a resistor divider can be used to divide the voltage down.

V_PU

R_PGT

PGOOD

R_PGB

图 24. Divider for PGOOD Pullup Voltage

With a given pullup voltage V_PU, select a desired voltage on the PGOOD pin, V_PG. With a selected R_PGT, the

R_PGBcan be found by:

V_PG

R_PGB

=

R_PGT

V_PU- V_PG

(22)

When the device is disabled, the output voltage is low, and the PGOOD flag indicates logic low as long as V_IN

2 V.

>

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7.3.13 Overcurrent and Short-Circuit Protection

The LM73605/6 is protected from overcurrent conditions with cycle-by-cycle current limiting on both HS and LS

MOSFETs.

The HS switch is turned off when HS current goes beyond the peak current limit, I_HS-LIMIT. The LS switch can only

be turned off when LS current is below LS current limit, I_LS-LIMIT. If the LS switch current is higher than I_LS-LIMITat

the end of a switching cycle, the switching cycle is extended until the LS current reduces below the limit.

Current limiting on both HS and LS switches provides tighter control of the maximum DC inductor current, or

output current. They also help prevent runaway current at extreme conditions. With LM73605/6, the maximum

output current is always limited at

I_{DC_LIMIT}= (I_{HS_LIMIT}+ I_{LS_LIMIT}) / 2

(23)

The LM73605/6 employs hiccup current protection at extreme overload conditions, including short-circuit

condition. Hiccup is only activated when V_OUTdroops below 40% (typical) of the regulation voltage and stays

below for 128 consecutive switching cycles. Under overcurrent conditions when V_OUThas not fallen below 40% of

regulation, the LM73605/6 continues operation with cycle-by-cycle HS and LS current limiting.

Hiccup is disabled during soft-start. When hiccup is triggered, the device turns off V_OUTregulation and re-tries

soft start after a re-try delay time, T_OC= 46 ms (typical). The long wait time allows the device, and the load, to

cool down under such fault conditions. If the fault condition still exists when re-try, hiccup shuts down the device

and repeats the wait and re-try cycle. If the fault condition has been removed, the device starts up normally.

If tracking was used for initial sequencing, the device restarts using the internal soft-start ramp. Hiccup mode

helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short

circuits. It improves system reliability and prolongs the life span of the device.

In FPWM mode, negative current protection is implemented to protect the switches from extreme negative

currents. When LS switch current reaches I_NEG-LIMIT, LS switch turns off, and HS switch turns on to conduct the

negative current. HS switch is turned off once its current reaches 0 A.

7.3.14 Thermal Shutdown

Thermal shutdown protection prevents the device from extreme junction temperature. The device is turned off

when the junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the

device from switching until the junction temperature drops to approximately 135°C. When the junction

temperature falls below 135°C, the LM73605/6 restarts.

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7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical on/off control of the device. When the EN pin voltage is below V_{EN_VCC_L}, the

device is in shutdown mode. The LDO output voltage V_CC= 0 V and the output voltage V_OUT= 0 V. In shutdown

mode the quiescent current drops to a very low value.

7.4.2 Standby Mode

The internal LDO has a lower EN threshold than that required to start the regulator. When the EN pin voltage is

above V_{EN_VCC_H}, the internal LDO regulates the VCC voltage. The precision enable circuitry is turned on once

V_CCis above V_{CC_UVLO}. The device is in standby mode if EN voltage is below V_{EN_VOUT_H}. The internal MOSFETs

remains in tri-state unless the voltage on EN pin goes beyond V_{EN_VOUT_H}threshold. The LM73605/6 also

employs UVLO protection. If the VCC voltage is below the V_{CC_UVLO}level, the output of the regulator is turned

off.

7.4.3 Active Mode

The LM73605/6 is in active mode when the EN voltage is above V_{EN_VOUT_H}, and V_CCis above V_{CC_UVLO}. The

simplest way to enable the operation of the LM73605/6 is to pull up the EN pin to PVIN, which allows self-start-

up when the input voltage ramps up.

In active mode, depending on the load current and mode setting, the LM73605/6 is in one of four modes:

1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current

ripple;

2. DCM with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current

ripple in CCM operation;

3. PFM when switching frequency is decreased at very light load;

4. Under overcurrent or overtemperature conditions, the device operates in one of the fault protection modes.

See 表 2 for mode-setting details.

7.4.3.1 CCM Mode

In CCM operation, inductor current has a continuous triangular waveform. The HS switch is on at the beginning

of a switching cycle and the LS switch is turned off the end of each switching cycle. In auto mode, the

LM73605/6 operates in CCM when the load current is higher than ½ of the peak-to-peak inductor current (I_Lripple).

In FPWM mode, the LM73605/6 operates in CCM regardless of load.

In CCM operation, the switching frequency is typically constant, unless t_ON-MIN, t_OFF-MIN, or I_PEAK-MINconditions are

met. The constant switching frequency is determined by RT pin setting, or the external synchronization clock

frequency. The duty cycle is also constant in CCM: D = V_OUT/ V_INif loss is ignored, regardless of load. The

peak-to-peak inductor ripple is constant with the same V_INand V_OUT, regardless of load.

With very high or very low supply voltages, when the t_ON-MINor t_OFF-MINcondition is met, the frequency reduces to

maintain V_OUTregulation with even higher or lower V_IN, respectively. When the I_{PEAK_MIN}condition is met in auto

mode, switching frequency will fold back to provide higher efficiency. I_{PEAK_MIN}is disabled in FPWM mode.

7.4.3.2 DCM Mode

DCM operation only happens in auto mode, when the load current is lower than half of the CCM inductor current

ripple, and peak current is higher than I_PEAK-MIN. There is no DCM in FPWM mode. DCM is also known as diode

emulation mode. The LS FET is turned off when the inductor current ramps to 0 A. DCM has the same switching

frequency as CCM, which is set by the RT pin. Duty cycle and peak current reduces with lighter load in DCM.

DCM is more efficient than FPWM under the same condition, because of lower switching losses and lower

conduction losses. When the peak current reduces to I_{PEAK_MIN}at lighter load, the LM73605/6 operates in PFM

mode.

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Device Functional Modes (接下页)

7.4.3.3 PFM Mode

Pulse-frequency-modulation (PFM) mode is activated when peak current is lower than I_PEAK-MIN, only in auto

mode. Peak current is kept constant and V_OUTis regulated by frequency. Efficiency is greatly improved by

lowered switching losses, especially at very light loads.

In PFM operation, a small DC positive offset appears on V_OUT. The lower the frequency is folded back in PFM,

the more the DC offset is on V_OUT. See V_OUTregulation curves in Application Curves. If the DC offset on V_OUTis

not acceptable, a dummy load at V_OUT, or lower R_FBTand R_FBBresistance values can be used to reduce the

offset. Alternatively the device can be run in FPWM mode where the switching frequency is constant, and no

offset is added to affect the V_OUTaccuracy unless t_{ON_MIN}is reached.

7.4.3.4 Fault Protection Mode

The LM73605/6 has hiccup current protection at extreme overload and short circuit conditions. Hiccup is

activated when V_OUTdroops below 40% (typical) of the regulation voltage and stays for 128 consecutive

switching cycles. Hiccup is disabled during soft start. In hiccup, the device turns off V_OUTand re-tries soft start

after 46-ms wait time. Cycle repeats until overcurrent fault condition has been removed. Hiccup mode helps to

reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits.

It improves system reliability and prolongs the life span of the device.

Under overcurrent conditions when V_OUTdroops below regulation but above 40% of regulated voltage, the

LM73605/6 stays in cycle-by-cycle HS and LS current limiting protection mode.

Thermal shutdown prevents the device from extreme junction temperature by turning off the device when the

junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device

from switching until the junction temperature drops to approximately 135°C. When the junction temperature falls

below 135°C, the LM73605/6 restarts.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM73605/6 device is a step-down DC-DC voltage regulator. It is designed to operate with a wide supply

voltage range (3.5 V to 36 V), wide switching frequency range (350 kHz to 2.2 MHz), and wide output voltage

range: up to 95% V_IN. is a synchronous converter with both HS and LS MOSFETs integrated, and it is capable of

delivering a maximum output current of 5 A (LM73605) or 6 A (LM73606). The following design procedure can be

used to select component values for the LM73605/6. Alternately, the WEBENCH® software may be used to

generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a

comprehensive database of components when generating a design (see Custom Design With WEBENCH®

Tools). This section presents a simplified discussion of the design process.

8.2 Typical Application

The LM73605/6 only requires a few external components to perform high-efficiency power conversion, as shown

in Simplified Schematic.

L

V_IN

V_OUT

SW

PVIN

EN

C_BOOT

C_OUT

C_IN

CBOOT

BIAS

RT

PGND

PGOOD

SS/TRK

R_FBT

SYNC/

MODE

FB

R_FBB

VCC

C_VCC

AGND

图 25. LM73605/6 Basic Schematic

The LM73605/6 also integrates many practical features to meet a wide range of system design requirements and

optimization, such as UVLO, programmable soft-start time, start-up tracking, programmable switching frequency,

clock synchronization and a power-good flag. Note that for ease of use, the feature pins do not require an

additional component when not in use. They can be either left floating or shorted to ground. Please refer to Pin

Configuration and Functions for details.

A comprehensive schematic with all features utilized is shown in 图 26.

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Typical Application (接下页)

V_IN

L

C_IN

V_OUT

PVIN

PGND

EN

SW

R_ENT

C_OUT

C_BOOT

CBOOT

BIAS

R_ENB

SS/TRK

RT

PGOOD

FB

C_SS

R_FBT

R_FBB

R_T

AGND

VCC

SYNC/

MODE

C_VCC

R_SYNC

图 26. LM73605/6 Comprehensive Schematic with All Features Utilized

The external components must fulfill not only the needs of the power conversion, but also the stability criteria of

the control loop. The LM73605/6 is optimized to work with a range of external components. For quick component

selection, 表 3 can be used.

表 3. Typical Component Selection

f_SW(kHz)

350

V_OUT(V)

L (µH)

2.2

1.5

0.68

0.47

4.7

3.3

1.8

1.2

6.8

4.7

3.3

2.2

15

C_OUT(µF)⁽¹⁾

500

400

200

100

200

150

88

R_FBT(kΩ)

100

R_FBB(kΩ)

OPEN

43.5

25

R_T(kΩ)

115

1

500

78.7 or open

39.2

1000

2200

350

1

17.4

3.3

5

115

500

78.7 or open

39.2

1000

2200

350

44

17.4

120

88

115

500

5

25

78.7 or open

39.2

1000

2200

350

5

66

25

5

44

25

17.4

12

24

66

9.1

115

500

10

44

9.1

78.7 or open

39.2

1000

350

6.8

22

9.1

40

4.3

115

500

15

30

4.3

78.7 or open

(1) All the C_OUTvalues are after derating. Add more when using ceramics.

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8.2.1 Design Requirements

Detailed design procedure is described based on a design example. For this design example, use the

parameters listed in 表 4.

表 4. Design Example Parameters

DESIGN PARAMETER

Typical input voltage

Output voltage

VALUE

12 V

5 V

Output current

5 A

Operating frequency

Soft-start time

500 kHz

11 ms

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

To create a custom design with the WEBENCH® Power Designer, click the LM73605 or LM73606 device.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the LM73605/6 device is externally adjustable using a resistor divider network. The divider

network is comprised of top feedback resistor R_FBTand bottom feedback resistor R_FBB. Use 公式 24 to determine

the output voltage of the converter.

≈

∆

«

’

÷

◊

R_FBT

R_FBB

V_OUT= V_FB

ì

1+

(24)

Typically, R_FBT= 10 kΩ to 100 kΩ is recommended. Larger R_FBTand R_FBBvalues reduce the quiescent current

going through the divider, which help maintain high efficiency at very light loads. But larger divider values also

make the feedback path more susceptible to noise. If efficiency at very light loads is critical in a certain

application, R_FBTup to 1 MΩ can be used.

V_FB

R_FBB

=

R_FBT

V_OUT- V_FB

(25)

R_FBT= 100 kΩ is selected here. R_FBB= 24.99 kΩ can be calculated to get 5-V output voltage.

8.2.2.3 Switching Frequency

The default switching frequency of the LM73605/6 device is set at 500 kHz. For this design, the RT pin can be

floating, and the LM73605/6 switches at 500 kHz in CCM mode. An R_Tresistor of 78.7 kΩ, calculated using 公式

13, 图 21, or 表 1, can be connected from RT pin to ground to obtain 500-kHz operation frequency as well.

The LM73605/6 switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends

connecting an external clock to the SYNC/MODE pin with a 50-Ω to 100-Ω termination resistor. The

SYNC/MODE pin must be grounded if not used.

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RT pin is floating and SYNC/MODE pin is tied to ground in this design.

8.2.2.4 Input Capacitors

The LM73605/6 device requires high-frequency ceramic input decoupling capacitors. Depending on the

application, a bulk input capacitor can also be added. The typical recommended ceramic decoupling capacitors

include one small, 0.1 µF to 1 µF, and one large, 10 µF to 22 µF, capacitors. TI recommends high-quality

ceramic type X5R or X7R capacitors. The voltage rating must be greater than the maximum input voltage. As a

general rule, to compensate the derating TI recommends a voltage rating of twice the maximum input voltage.

It is very important in buck regulator to place the small decoupling capacitor right next to the PVIN and PGND

pins. This capacitor is used to bypass the high frequency switching noise by providing a return path of the noise.

It prevents the noise from spreading to wider area of the board. The large bypass ceramic capacitor must also be

as close as possible to the PVIN and PGND pins.

Additionally, some bulk capacitance may be required, especially if the LM73605/6 circuit is not located within

approximately 2 inches from the input voltage source. This capacitor is used to provide damping to the voltage

spike due to the lead inductance of the cable. The optimum value for this capacitor is four times the ceramic

input capacitance with ESR close to the characteristic impedance of the LC filter formed by your input inductance

and your ceramic input capacitors. It is not critical that the electrolytic filter be at the optimum value for damping,

but it must be rated to handle the maximum input voltage including ripple voltage.

For this design, two 10-µF, X7R dielectric capacitors rated for 50 V are used for the input decoupling

capacitance, and a capacitor with a value of 0.47 µF for high-frequency filtering.

注

DC bias effect: High capacitance ceramic capacitors have a DC bias derating effect, which

will have a strong influence on the final effective capacitance. Therefore, the right

capacitor value has to be chosen carefully. Package size and voltage rating in

combination with dielectric material are responsible for differences between the rated

capacitor value and the effective capacitance.

8.2.2.5 Inductor Selection

The first criterion for selecting an output inductor is the inductance. In most buck converters, this value is based

on the desired peak-to-peak ripple current in the inductor, I_Lripple. An inductance that gives a ripple current of 10%

to 30% of the maximum output current (5 A or 6 A) is a good starting point. The inductance can be calculated

from 公式 26:

V

_IN- V_OUTìD

(

)

L =

ƒ_SWìI_Lripple

where

•

I_Lripple= (0.1 to 0.3) × I_{L_MAX}

I_{L_MAX}= 5 A for LM73605 and 6 A for LM73606

D = V_OUT/ V_IN

(26)

Selected I_Lrippleis between 10% to 30% of the rated current of the device.

As with switching frequency, the selection of the inductor is a tradeoff between size, cost, and performance.

Higher inductance gives lower ripple current and hence lower output voltage ripple. With peak current mode

control, the current ripple is the input signal to the control loop. A certain amount of ripple current is needed to

maintain the signal-to-noise ratio of the control loop. Within the same series (same size/height), a larger

inductance will have a higher series resistance (ESR). With similar ESR, size and/or height will be greater.

Larger inductance also has slower current slew rate during large load transients.

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Lower inductance usually results in a smaller, less expensive component; however, the current ripple will be

higher, thus more output capacitor is needed to maintain the same amount of output voltage ripple. The RMS

current is higher with the same load current due to larger ripple. The switching loss is higher because the switch

current, which is the peak current, is higher when the HS switch turns off and LS switch turns on. Core loss of

the inductor is also larger with higher ripple. Core loss needs to be considered, especially with higher switching

frequencies. Check the ripple current over V_{IN_MIN}to V_{IN_MAX}range to make sure current ripple is reasonable over

entire supply voltage range.

For applications with large V_OUTand typical V_OUT/ V_IN> 50%, sub-harmonic oscillation can be a concern in peak

current-mode-controlled buck converters. Select inductance so that

L ≥ V_OUT/ (N × f_SW

)

where

•

N = 3 with LM73605

N = 3.6 with LM73606

(27)

The second criterion is inductor saturation current rating. Because the maximum inductor current is limited by the

high-side switch current limit, it is advised to select an inductor with a saturation current higher than the I_LIMIT-HS

.

TI recommends selection of soft saturation inductors. A power inductor could be the major source of radiated

noise. When EMI is a concern in the application, select a shielded inductor, if possible.

For this design, 20% ripple of 5 A yields 5.8-µH inductance. A 4.7-µH inductor is selected, which gives 25%

ripple current.

8.2.2.6 Output Capacitor Selection

The output capacitor is responsible for filtering the inductor current, and supplying load current during transients.

Capacitor selection depends on application conditions as well as ripple and transient requirements. Best

performance is achieved by using ceramic capacitors or combinations of ceramic and other types of capacitors.

For high output voltage conditions, such as 12 V and above, finding ceramic capacitors that are rated for an

appropriate voltage becomes challenging. In such cases choose a low-ESR SP-CAP™ or POSCAP™-type

capacitor. It is a good idea to use a low-value ceramic capacitor in parallel with other capacitors, to bypass high

frequency noise between ground and V_OUT

.

For a given input and output requirement, 公式 28 gives an approximation for a minimum output capacitor

required.

2

»

…

ÿ

Ÿ

≈

’

1

r

Å

C_OUT

>

ì

ì(1+ D ) + D ì(1+ r)

∆

÷

(

)

÷

(f_SWìr ì DV_OUT/ I_OUT

)

12

Ÿ

⁄

«

◊

where

•

r = Ripple ratio of the inductor ripple current (I_Lripple/ 5 A or 6 A)

ΔV_OUT= Target output voltage undershoot, for example, 5% to 10% of V_OUT

D’ = 1 – duty cycle

f_SW= switching frequency

I_OUT= load current

(28)

(29)

Along with 公式 28, for the same requirement calculate the maximum ESR with 公式 29.

Å

D

1

ESR <

ì( + 0.5)

f_SWìC_OUT

r

The output capacitor is also the dominating factor in the loop response of a peak-current mode controlled buck

converter. A simplified estimation of the control loop crossover frequency can be found by 公式 18.

Select C_OUTso that the f_Xis no higher than 1/6 of the switching frequency. Typically, f_X/ f_SW= 1/10 to 1/8

provides a good combination of stability and performance.

For this design, one 0.47-µF, 50-V X7R and four 22-µF, 16-V, X7R ceramic capacitors are used in parallel.

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LM73605, LM73606

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ZHCSH36 –SEPTEMBER 2017

8.2.2.7 Feed-Forward Capacitor

The LM73605/6 is internally compensated. Typically, select R_FBT≤ 100 kΩ, then C_FFis not needed. When very

low quiescent current is needed, R_FBT= 1 MΩ may be used. If C_OUTis mainly ceramic type low ESR capacitors,

an external feed-forward capacitor C_FFmay be needed to improve the phase margin. Add C_FFin parallel with

R_FBT. C_FFis chosen such that the phase boost is maximized at the estimated crossover frequency f_X. 公式 21

was tested.

With this design, because R_FBT= 100 kΩ is selected, no C_FFis needed.

8.2.2.8 Bootstrap Capacitors

Every LM73605/6 design requires a bootstrap capacitor, C_BOOT. The recommended bootstrap capacitor is 0.47

µF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the CBOOT pin.

The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature

stability.

8.2.2.9 VCC Capacitor

The VCC pin is the output of an internal LDO for LM73605/6. The input for this LDO comes from either V_INor

BIAS pin voltage. The recommended C_VCCcapacitor is 2.2 µF and rated at 6.3 V or greater. It must be a high-

quality ceramic type with X7R or X5R grade to insure stability. Never short VCC pin to ground during operation.

8.2.2.10 BIAS

Because V_OUT= 5 V in this design, the BIAS pin is tied to V_OUTto reduce LDO power loss. The output voltage is

supplying the LDO current instead of the input voltage. The power saving is I_LDO× (V_IN– V_OUT). The power

saving is more significant when V_IN>> V_OUTand with higher frequency operation. To prevent V_OUTnoise and

transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, may be added between V_OUTand BIAS. A

bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise.

8.2.2.11 Soft Start

The SS/TRK pin can be floating to start up following the internal soft-start ramp. In order to extend the soft-start

time, an external soft-start capacitor can be used. Use 公式 12 in order to calculate the soft-start capacitor value.

With a desired soft-start time t_SS= 11 ms, a soft-start charging current of I_SSC= 2 µA (typical), and V_FB= 1.006 V

(typical), 公式 12 yields a soft-start capacitor value of 22 nF.

8.2.2.12 Undervoltage Lockout Setpoint

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. With one selected R_ENTvalue, R_ENBcan be found by 公式 10.

Note that the divider adds to supply quiescent current by V_IN/ (R_ENT+ R_ENB). Small R_ENTand R_ENBvalues add

more quiescent current loss. However, large divider values make the node more sensitive to noise.

In this design, EN pin is tied to PVIN pin with a 100-kΩ resistor.

8.2.2.13 PGOOD

For this design, a 100-kΩ resistor is used to pull up PGOOD to V_OUT

.

31

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

8.2.3 Application Curves

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 5 V

VIN = 8V

VIN = 12 V

VIN = 5 V

VIN = 8V

VIN = 12 V

0.001

0.01 0.02 0.05 0.1 0.2

0.5

1

2

3 45

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Load Current (A)

EFF_

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 500 kHz

FPWM Mode

图 27. LM73605 Efficiency

图 28. LM73605 Efficiency

100

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

VIN = 5 V

VIN = 8V

VIN = 12 V

VIN = 5 V

VIN = 8V

VIN = 12 V

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2

3 45

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Load Current (A)

EFF_

V_OUT= 3.3 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 2200 kHz

FPWM Mode

图 29. LM73605 Efficiency

图 30. LM73605 Efficiency

100

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

VIN = 5 V

VIN = 8V

VIN = 12 V

VIN = 5 V

VIN = 8V

VIN = 12 V

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2

3 45

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2 3 45

EFF_

V_OUT= 3.3 V

f_SW= 350 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 1000 kHz

Auto Mode

图 31. LM73605 Efficiency

图 32. LM73605 Efficiency

32

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ZHCSH36 –SEPTEMBER 2017

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

VIN = 7 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 7 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

50

0.001

0.01 0.02 0.05 0.1 0.2 0.5

Load Current (A)

1

2

3 456

0

0.6 1.2 1.8 2.4

3

3.6 4.2 4.8 5.4

6

EFF_

Load Current (A)

EFF_

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

图 33. LM73606 Efficiency

图 34. LM73606 Efficiency

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 7 V

VIN = 12 V

VIN = 24 V

VIN = 7 V

VIN = 12 V

VIN = 24 V

0.001

0.01 0.02 0.05 0.1 0.2 0.5

Load Current (A)

1

2

3 456

0

0.6 1.2 1.8 2.4

3

3.6 4.2 4.8 5.4

6

EFF_

Load Current (A)

EFF_

V_OUT= 5 V

f_SW= 1000 kHz

Auto Mode

V_OUT= 5 V

f_SW= 1000 kHz

FPWM Mode

图 35. LM73606 Efficiency

图 36. LM73606 Efficiency

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 7 V

VIN = 12 V

VIN = 24 V

VIN = 7 V

VIN = 12 V

VIN = 24 V

0.001

0.01 0.02 0.05 0.1 0.2 0.5

Load Current (A)

1

2

3 456

0

0.6 1.2 1.8 2.4

3

3.6 4.2 4.8 5.4

6

EFF_

Load Current (A)

EFF_

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

图 37. LM73606 Efficiency

图 38. LM73606 Efficiency

33

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100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 14 V

VIN = 24V

VIN = 36 V

VIN = 14 V

VIN = 24V

VIN = 36 V

0.001

0.01 0.02 0.05 0.1 0.2

0.5

1

2

3 45

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Load Current (A)

EFF_

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

V_OUT= 12 V

f_SW= 500 kHz

FPWM Mode

图 39. LM73605 Efficiency

图 40. LM73605 Efficiency

5.2

5.1

5.16

5.12

5.08

5.04

5

5.08

5.06

5.04

5.02

5

4.96

4.92

4.88

4.84

4.8

4.98

4.96

4.94

4.92

4.9

VIN = 7 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 12 V

VIN = 24 V

VIN = 36 V

0.001

0.010.02 0.05 0.1 0.2 0.5

Load Current (A)

1

2

3 45 7 10

REG_

0

0.6 1.2 1.8 2.4

3

3.6 4.2 4.8 5.4

6

REG_

Load Current (A)

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

图 41. LM73606 Load and Line Regulation

图 42. LM73606 Load and Line Regulation

5.2

5.16

5.12

5.08

5.04

5

5.05

5.04

5.03

5.02

5.01

5

4.96

4.92

4.88

4.84

4.8

4.99

4.98

4.97

4.96

4.95

VIN = 7 V

VIN = 12 V

VIN = 24 V

VIN = 7 V

VIN = 12 V

VIN = 24 V

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2

3 45

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Load Current (A)

REG_

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

图 43. LM73605 Load and Line Regulation

图 44. LM73605 Load and Line Regulation

34

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ZHCSH36 –SEPTEMBER 2017

3.4

3.38

3.36

3.34

3.32

3.3

3.32

3.315

3.31

3.305

3.3

3.295

3.29

3.28

3.26

3.24

3.22

3.285

3.28

VIN = 5 V

VIN = 8V

VIN = 12 V

VIN = 5 V

VIN = 8V

VIN = 12 V

3.275

3.27

3.2

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2

3 45

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2 3 45

REG_

V_OUT= 3.3 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 2200 kHz

FPWM Mode

图 45. LM73605 Load and Line Regulation

图 46. LM73605 Load and Line Regulation

3.4

3.38

3.36

3.34

3.32

3.3

3.4

3.38

3.36

3.34

3.32

3.3

3.28

3.26

3.24

3.22

3.28

3.26

3.24

3.22

3.2

VIN = 5 V

VIN = 8V

VIN = 12 V

VIN = 5 V

VIN = 8V

VIN = 12 V

3.2

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2

3 45

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2 3 45

REG_

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 1000 kHz

Auto Mode

图 47. LM73605 Load and Line Regulation

图 48. LM73605 Load and Line Regulation

12.4

12.36

12.32

12.28

12.24

12.2

12.16

12.12

12.08

12.04

12

11.96

11.92

11.88

11.84

11.8

12.1

12.08

12.06

12.04

12.02

12

11.98

11.96

11.94

11.92

11.9

VIN = 14 V

VIN = 24V

VIN = 36 V

VIN = 14 V

VIN = 24V

VIN = 36 V

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2

3 45

0.001

0.01 0.02 0.05 0.1 0.2

Load Current (A)

0.5

1

2 3 45

REG_

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

V_OUT= 12 V

f_SW= 500 kHz

FPWM Mode

图 49. LM73605 Load and Line Regulation

图 50. LM73605 Load and Line Regulation

35

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ZHCSH36 –SEPTEMBER 2017

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6

5.8

5.6

5.4

5.2

5

6

5.8

5.6

5.4

5.2

5

4.8

4.6

4.4

4.2

4

4.8

4.6

4.4

4.2

4

Load = 1.5mA

Load = 1A

Load = 3A

Load = 5A

Load = 1.5mA

Load = 1A

Load = 3A

Load = 5A

3.8

3.6

3.4

3.2

3.8

3.6

3.4

3.2

4

4.4

4.8

5.2

5.6

6

6.4

6.8

4

4.4

4.8

5.2

5.6

6

6.4

6.8

VIN (V)

DO_5

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

图 51. LM73605 Dropout Curve

图 52. LM73605 Dropout Curve

6

5.8

5.6

5.4

5.2

5

6

5.8

5.6

5.4

5.2

5

4.8

4.6

4.4

4.2

4

4.8

4.6

4.4

4.2

4

Load = 1.5mA

Load = 1A

Load = 3A

Load = 5A

Load = 1A

Load = 3A

Load = 5A

3.8

3.6

3.4

3.2

3.8

3.6

3.4

3.2

4

4.4

4.8

5.2

5.6

6

6.4

6.8

4

4.4

4.8

5.2

5.6

6

6.4

6.8

VIN (V)

DO_5

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 1000 kHz

Auto Mode

图 53. LM73605 Dropout Curve

图 54. LM73605 Dropout Curve

13

12.8

12.6

12.4

12.2

12

11.8

11.6

11.4

11.2

11

10.8

10.6

10.4

10.2

10

3.5

3.4

3.3

3.2

3.1

3

2.9

2.8

2.7

2.6

2.5

Load = 1.5mA

Load = 1A

Load = 3A

Load = 5A

Load = 1A

Load = 3A

Load = 5A

3.3

3.5

3.7

3.9

4.1

4.3

4.5

4.7

4.9

11

11.4

11.8

12.2

12.6

13

13.4

13.8

VIN (V)

DO_3

DO_1

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

图 55. LM73605 Dropout Curve

图 56. LM73605 Dropout Curve

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I_INDUCTOR

(1 A/DIV)

V_OUTRipple

(20 mV/DIV)

V_OUTRipple

(20 mV/DIV)

V_SW

(5 V/DIV)

Time (500 µs/DIV)

Time (2 µs/DIV)

V_IN= 12 V

I_OUT= 1 mA

V_OUT= 3.3 V

Auto Mode

f_SW= 500 kHz

V_IN= 12 V

I_OUT= 1 mA

V_OUT= 3.3 V

FPWM Mode

f_SW= 500 kHz

图 57. LM73606 Switching Waveform and V_OUTRipple

图 58. LM73606 Switching Waveform and V_OUTRipple

I_INDUCTOR

(1 A/DIV)

V_OUTRipple

(20 mV/DIV)

V_OUTRipple

(20 mV/DIV)

V_SW

(5 V/DIV)

V_SW

(5 V/DIV)

Time (5 µs/DIV)

V_IN= 12 V

I_OUT= 100 mA

V_OUT= 3.3 V

Auto Mode

f_SW= 500 kHz

V_IN= 12 V

I_OUT= 100 mA

V_OUT= 3.3 V

FPWM Mode

f_SW= 500 kHz

图 59. LM73606 Switching Waveform and V_OUTRipple

图 60. LM73606 Switching Waveform and V_OUTRipple

I_INDUCTOR

(2 A/DIV)

(1 A/DIV)

V_OUTRipple

(20 mV/DIV)

V_OUTRipple

(20 mV/DIV)

V_SW

(5 V/DIV)

Time (2 µs/DIV)

Time (5 µs/DIV)

V_IN= 12 V

I_OUT= 6 A

V_OUT= 3.3 V

Auto Mode

f_SW= 500 kHz

V_IN= 3.66 V

I_OUT= 3 A

V_OUT= 3.3 V

Auto Mode

f_SWset at 500 kHz

图 61. LM73606 Switching Waveform and V_OUTRipple

图 62. LM73606 Switching Waveform at Dropout

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I_INDUCTOR

(2 A/DIV)

V_OUT

(1 V/DIV)

V_OUT

(1 V/DIV)

I_INDUCTOR

(2 A/DIV)

V_SW

(5 V/DIV)

V_SW

(5 V/DIV)

Time (5 µs/DIV)

Time (50 ms/DIV)

V_IN= 12 V

V_OUTset at 3.3 V

f_SWset at 500 kHz

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 500 kHz

I_OUT= 7.5 A

V_OUTdroops to 2 V

图 64. LM73606 Short-Circuit Hiccup Protection and

Recovery

图 63. LM73606 Overcurrent Behavior

Enable

(5 V/DIV)

V_OUT

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

PGOOD

(10 V/DIV)

Time (2 ms/DIV)

V_IN= 12 V

I_OUT= 200 mA

V_OUT= 3.3 V

FPWM Mode

f_SW= 500 kHz

V_IN= 12 V

I_OUT= 200 mA

V_OUT= 3.3 V

Auto Mode

f_SW= 500 kHz

图 65. LM73606 Soft Start With 200-mA Load in FPWM

图 66. LM73606 Soft Start With 200-mA Load in Auto Mode

Mode

Enable

(5 V/DIV)

V_OUT

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

PGOOD

(5 V/DIV)

Time (2 ms/DIV)

V_IN= 12 V

I_OUT= 5 A

V_OUT= 3.3 V

Auto Mode

f_SW= 500 kHz

V_IN= 12 V

V_PRE-BIAS= 1.5 V

V_OUT= 3.3 V

Auto Mode

f_SW= 500 kHz

图 67. LM73606 Soft Start With 5-A Load

图 68. LM73606 Soft Start With Pre-Biased Output Voltage

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I_OUT

(5 A/DIV)

I_INDUCTOR

(5 A/DIV)

V_OUT

(200 mV/

DIV AC)

V_OUT

(200 mV/

DIV AC)

Time (200 µs/DIV)

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 500 kHz

FPWM Mode

I_OUT= 10 mA to 6 A to 10 mA

图 69. LM73606 Load Transients

图 70. LM73606 Load Transients

I_OUT

(5 A/DIV)

I_INDUCTOR

(5 A/DIV)

V_OUT

(500 mV/

DIV AC)

(500 mV/

DIV AC)

Time (200 µs/DIV)

V_IN= 12 V

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_IN= 12 V

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

I_OUT= 10 mA to 5 A to 10 mA

图 71. LM73605 Load Transients

图 72. LM73605 Load Transients

V_IN

(20 V/DIV)

V_OUT

(200 mV/

DIV)

(200 mV/

DIV)

I_INDUCTOR

(2 A/DIV)

Time (200 µs/DIV)

I_OUT= 100 mA

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

I_OUT= 2 A

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_IN= 10 V to 35 V to 10 V

图 73. LM73606 Line Transients

图 74. LM73606 Line Transients

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9 Power Supply Recommendations

The LM73605/6 is designed to operate from an input voltage supply range from 3.5 V to 36 V. This input supply

must be able to withstand the maximum input current and maintain a voltage above 3.5 V at the PVIN pin. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the LM73605/6 supply voltage that can cause a false UVLO fault triggering and system reset. If

the input supply is located more than a few inches from the LM73605/6, additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. A 47-μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

The performance of any switching converter depends heavily upon the layout of the PCB. Use the following

guidelines to design a PCB layout with optimum power conversion performance, EMI performance, and thermal

performance.

1. Place ceramic high frequency bypass capacitors as close as possible to the PVIN and PGND pins, which are

right next to each other on the package. Place the small value ceramic capacitor closest to the pins. This is

very important for EMI performance.

2. Use short and wide traces, or localized IC layer planes, for high current paths, such as V_IN, V_OUT, SW and

GND connections. Short and wide copper traces reduce power loss and noise due to low parasitic resistance

and inductance. Wide copper traces also help reduce die temperature, because they also provide wide heat

dissipation paths. Use thick copper (2 oz) on high current layer(s) if possible.

3. Confine pulsing current paths (V_IN, SW, and ground return for V_IN) on the device layer as much as possible

to prevent switching noises from contaminating other layers.

4. C_BOOTcapacitor also contains pulsing current. Place C_BOOTclose to the pin and route to SW with short trace.

The pinout of the device makes it easy to optimize the C_BOOTplacement and routing.

5. Use a solid ground plane at the layer right underneath the device as a noise shielding and heat dissipation

path.

6. Place the VCC bypass capacitor close to the VCC pin. Tie the ground pad of the capacitor to the ground

plane using a via right next to it.

7. Use via next to AGND pin to the ground plane.

8. Minimize trace length to the FB pin. Both feedback resistors must be located right next to the FB pin. Tie the

ground side of R_FBBto the ground plane with a via right next to it. Place C_FFdirectly in parallel with R_FBTif

used.

9. If V_OUTaccuracy at the load is important, make sure the V_OUTsense point is made close to the load. Route

V_OUTsense to R_FBTthrough a path away from noisy nodes and preferably on a layer on the other side of the

ground plane. If BIAS is connected to V_OUT, do not use the same trace to route V_OUTto BIAS and to R_FBT

.

BIAS current contains pulsing driver current and it changes with operating mode. Use separated traces for

BIAS and V_OUTsense to optimize V_OUTregulation accuracy.

10. Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane and the bottom PCB layer. Connect the DAP and NC pins on the short sides of the device to

the GND net, so that IC layer ground copper can provide an optimal dog-bone shape heat sink. Heat

generated on the die can flow directly from device junction to the DAP then to the copper and spread to the

wider copper outside of the device. Try to keep copper area solid on the top and bottom layer around thermal

vias on the DAP to optimize heat dissipation.

40

LM73605, LM73606

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ZHCSH36 –SEPTEMBER 2017

Layout Guidelines (接下页)

10.1.1 Layout For EMI Reduction

To optimize EMI performance, place the components in the high di/dt current path, as shown in 图 75, as close

as possible to each other. When the components are close to each other, the area of the loop enclosed by these

components, and the parasitic inductance of this loop, are minimized. The noises generated by the pulsing

current and parasitic inductances are then minimized.

BUCK

CONVERTER

L

VIN

V_IN

C_IN

SW

V_OUT

C_OUT

PGND

High di/dt current

图 75. Pulsing Current Path of Buck Converter

In a buck converter, the high di/dt current path is composed of the HS and LS MOSFETs and the input

capacitors. Because the two MOSFETs are integrated inside the device, they are closer to each other than in

discrete solutions. PVIN and PGND pins are the connections from the MOSFETs to the input capacitors. The first

step of the layout must be placing the input capacitors, especially the small value ceramic bypass one, as close

as possible to PVIN and PGND pins.

The LM73605/6 pinout is optimized for low EMI layout. Multiple pins are used for PVIN and PGND to minimized

bond wire resistances and inductances. The PVIN and PGND pins are right next to each other to simplify optimal

layout. The CBOOT pin is placed next to SW pin for easy and compact C_BOOTcapacitor layout.

10.1.2 Ground Plane

The ground plane of a PCB provides the best return path for the pulsing current on the device layer. Make sure

the ground plane is solid, especially the part right underneath the pulsing current paths. Solid copper under a

pulsing current path provide a mirrored return path for the high frequency components and minimize voltage

spikes generated by the pulsing current. It shields the layers on the other side of the plane from switching noises.

Route signal traces on the other side of the ground plane as much as possible. Use multiple vias in parallel to

connect the grounds on the device layer to the ground plane.

10.1.3 Optimize Thermal Performance

The key to thermal optimization on PCB design is to provide heat transferring paths from the device to the outer

large copper area. Use thick copper (2 oz) on high current layer(s) if possible. Use thermal vias under the DAP to

transfer heat to other layers. Connect NC pins to the GND net, so that GND copper can run underneath the

device to create dog-bone shape heat sink. Try to leave copper solid on IC side as much as possible above and

below the device. Place components and route traces away from major heat transferring paths if possible, to

avoid blocking heat dissipation path. Try to leave copper solid, free of components and traces, around the

thermal vias on the other side of the board as well. Solid copper behaves as heat sink to spread the heat to a

larger area and provide more contact area to the air.

When calculating power dissipation, use the maximum input voltage and the average output current for the

application. Many common operating conditions are provided in Application Curves. Less common applications

can be derived through interpolation. In all designs, the junction temperature must be kept below the rated

maximum of 125°C.

41

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

Layout Guidelines (接下页)

The thermal characteristics of the LM73605/6 are specified using the parameter R_θJA, which characterize thermal

resistance from the junction of the silicon to the ambient in a specific system. Although the value of R_θJAis

dependant on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use 公式 30:

T_J= P_{IC_LOSS}× R_θJA+ T_A

where

•

T_J= junction temperature in °C

P_{IC_LOSS}= V_IN× I_IN× (1 − Efficiency) − 1.1 × I_OUT× DCR

DCR = inductor DC parasitic resistance in Ω

R_θJA= junction-to-ambient thermal resistance of the device in °C/W

T_A= ambient temperature in °C.

(30)

The maximum operating junction temperature of the LM73605/6 is 125°C. R_θJAis highly related to PCB size and

layout, as well as environmental factors such as heat sinking and air flow. 图 76 shows measured results of R_θJA

with different copper area on 2-layer boards and 4-layer boards, with 1-W and 2-W power dissipation on the

LM73605/6.

30

1í @0 fpm - 2layer

28

1í @0 fpm - 4layer

26

2í @0 fpm - 2layer

2í @0 fpm - 4layer

24

22

20

18

16

14

12

10

20

30

30mm × 30mm

40

40mm × 40mm

50

50mm × 50mm

60

70

80

70mm ×70mm

Copper Area

图 76. Measured R_θJAvs PCB Copper Area on 2-Layer Boards and 4-Layer Boards

42

LM73605, LM73606

www.ti.com.cn

ZHCSH36 –SEPTEMBER 2017

10.2 Layout Example

A layout example is shown in 图 77. A four-layer board is used with 2-oz copper on the top and bottom layers

and 1-oz copper on the inner two layers. 图 77 shows the relative scale of the LM73605/6 device with 0805 and

1210 input and output capacitors, 7-mm × 7-mm inductor and 0603 case size for all other passive components.

The trace width of the signal connections are not to scale.

The components are placed on the top layer and the high current paths are routed on the top layer as well. The

remaining space on the top layer can be filled with GND polygon. Thermal vias are used under the DAP and

around the device. The GND copper was extended to the outside of the device, which serves as copper heat

sink.

The mid-layer 1 is right underneath the top layer. It is a solid ground plane, which serves as noise shielding and

heat dissipation path.

The V_OUTsense trace is routed on the 3rd layer, which is mid-layer 2. Ground plane provided noise shielding for

the sense trace. The V_OUTto BIAS connection is routed by a separate trace.

The bottom layer is also a solid ground copper in this example. Solid copper provides best heat sinking for the

device. If components and traces need to be on the bottom layer, leave the area around thermal vias as solid as

possible. Try not to cut heat dissipation path by a trace. The board can be used for various frequencies and

output voltages, with component variation. For more details, see the LM73605/LM73606 EVM User's Guide.

图 77. LM73605/6 Layout Example

43

LM73605, LM73606

ZHCSH36 –SEPTEMBER 2017

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 使用 WEBENCH® 工具创建定制设计

单击此处，以使用 LM73605 或 LM73606 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 首先键入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

11.2 相关文档

请参阅如下相关文档：

《AN-2020 热设计：学会洞察先机，不做事后诸葛》

11.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。

表 5. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

LM73605

LM73606

11.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

44

LM73605, LM73606

www.ti.com.cn

ZHCSH36 –SEPTEMBER 2017

11.5 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.6 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

SP-CAP is a trademark of Panasonic.

POSCAP is a trademark of Sanyo Electric Co., Ltd..

11.7 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.8 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

45

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM73605RNPR

LM73605RNPT

LM73606RNPR

LM73606RNPT

WQFN

RNP

30

3000

250

330.0

180.0

330.0

180.0

16.4

4.25

6.25

0.95

8.0

16.0

Q1

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM73605RNPR

LM73605RNPT

LM73606RNPR

LM73606RNPT

WQFN

RNP

30

3000

250

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

38.0

35.0

38.0

35.0

3000

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RNP 30

4 x 6, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225831/A

www.ti.com

PACKAGE OUTLINE

RNP0030A

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

6.1

5.9

0.1 MIN

(0.05)

E

SCAL

C

T

SECTION A-A

TYPICAL

0.8

0.7

C

SEATING PLANE

0.08

0.05

0.00

2.2 0.1

2X 1.5

(0.2) TYP

EXPOSED

THERMAL PAD

12

15

26X 0.5

11

16

SYMM

A

4.6 0.1

2X

5

1

26

0.3

PIN 1 ID

(OPTIONAL)

30

27

30X

0.2

0.1

0.05

SYMM

0.5

0.3

8X

C A B

0.65

0.45

22X

4222145/C 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RNP0030A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.2)

SYMM

8X (0.6)

30

27

22X (0.75)

1

26

30X (0.25)

2X

(2.05)

(0.5) TYP

SYMM

(5.8)

(4.6)

6X

(1.16)

(R0.05) TYP

16

11

(

0.2) TYP

VIA

12

15

6X (0.85)

(3.65)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222145/C 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RNP0030A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.59) TYP

30

8X (0.6)

27

22X (0.75)

1

26

30X (0.25)

26X (0.5)

(1.16)

TYP

(0.58)

TYP

SYMM

(5.8)

METAL

TYP

8X (0.96)

16

11

(R0.05) TYP

12

15

8X (0.98)

(3.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

74.4% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4222145/C 02/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

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型号：	LM73605
厂家：	TEXAS INSTRUMENTS
描述：	3.5V 至 36V、5A 同步降压转换器转换器
文件：	总54页 (文件大小：2628K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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