LM74700-EP [TI]
增强型低 IQ 理想二极管控制器;
| 型号： | LM74700-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型低 IQ 理想二极管控制器 控制器 二极管 |
| 文件： | 总31页 (文件大小：2517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74700-EP
ZHCSMT1 –SEPTEMBER 2021
LM74700-EP 低Iq 理想二极管控制器
1 特性
3 说明
• 3.2V 至65V 输入范围（3.9V 启动）
• -65V 反向电压额定值
• 适用于外部N 沟道MOSFET 的电荷泵
• 20mV 阳极至阴极正向压降调节
• 使能引脚特性
• 1µA 关断电流（EN = 低电平）
• 80µA 工作静态电流（EN = 高电平）
• 2.3A 峰值栅极关断电流
• 快速响应反向电流阻断：
小于0.75µs
LM74700-EP 是一款理想二极管控制器，与外部 N 沟
道 MOSFET 配合工作，可作为理想二极管整流器利用
20mV 正向压降实现低损耗反向保护。3.2V 至 65V 的
宽电源输入范围可实现对众多常用直流总线电压（例
如：12V、24V 和 48V 系统）的控制。该器件可耐受
低至–65V 的负电源电压，并提供负载保护。
该器件通过控制 MOSFET 的栅极将正向压降调节至
20mV。该电流调节方案可在反向电流事件中支持平稳
关机，并确保零直流反向电流。该器件能够快速 (<
0.75µs) 响应反向电流阻断，因此适用于在电源故障和
输入微短路条件下要求保持输出电压的系统。
• 采用合适的TVS 二极管，符合汽车ISO7637 瞬态
要求
• 采用8 引脚SOT-23 封装2.90mm × 1.60mm
• 军用级温度范围（–55°C 至+125°C）
• 制造、组装和测试一体化基地
• 延长了产品生命周期
• 延长了产品变更通知
• 产品可追溯性
LM74700-EP 控制器可提供适用于外部 N 沟道
MOSFET 的电荷泵栅极驱动器。LM74700-EP 的高电
压额定值有助于简化用于汽车 ISO7637 保护的系统设
计。当使能引脚处于低电平时，控制器关闭，消耗大约
1µA 的电流。LM74700-EP 的完全额定工作温度范围
为TA = –55°C 至+125°C。
器件信息(1)
2 应用
封装尺寸（标称值）
器件型号
封装
• 航空航天与国防
• 医疗成像
LM74700-EP
SOT-23 (8)
2.90mm × 1.60mm
• 用于冗余电源的有源ORing
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VOUT
VBATT
TVS
VOUT
VGATE
VBATT
Voltage
Regulator
GATE CATHODE
LM74700
ANODE
VCAP
EN
GND
ON OFF
IBATT
典型应用原理图
输入短路期间的反向电流阻断
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDD6
LM74700-EP
ZHCSMT1 –SEPTEMBER 2021
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Table of Contents
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
9.3 OR-ing Application Configuration..............................21
10 Power Supply Recommendations..............................22
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................24
12.1 接收文档更新通知................................................... 24
12.2 支持资源..................................................................24
12.3 Trademarks.............................................................24
12.4 Electrostatic Discharge Caution..............................24
12.5 术语表..................................................................... 24
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
Information.................................................................... 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
September 2021
*
Initial Release
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5 Pin Configuration and Functions
EN
CATHODE
N.C
1
2
3
4
8
7
GND
N.C
GATE
6
5
ANODE
VCAP
图5-1. DDF Package 8-Pin SOT-23 Top View
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
1
NAME
EN
I
Enable pin. Can be connected to ANODE for always ON operation.
Ground pin
2
GND
N.C
G
3
No connection. Keep this pin floating.
4
VCAP
O
I
Charge pump output. Connect to external charge pump capacitor.
Anode of the diode and input power. Connect to the source of the external N-channel
MOSFET.
5
ANODE
6
7
8
GATE
N.C
O
Gate drive output. Connect to gate of the external N-channel MOSFET.
No connection. Keep this pin floating.
CATHODE
I
Cathode of the diode. Connect to the drain of the external N-channel MOSFET.
(1) I = Input, O = Output, G = GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
MAX
65
UNIT
ANODE to GND
V
V
V
V
V
Input Pins
EN to GND, V(ANODE) > 0 V
EN to GND, V(ANODE) ≤0 V
GATE to ANODE
65
–0.3
V(ANODE)
–0.3
(65 + V(ANODE))
15
15
Output Pins
VCAP to ANODE
–0.3
Output to Input
Pins
CATHODE to ANODE
75
V
–5
Operating junction temperature(2)
150
150
°C
°C
–55
–55
Storage temperature, Tstg
(1) Operation outside the Absolute Maximum Ratings can cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device can not be fully functional,
and this can affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per JEDEC JS-001(1)
±2000
Corner pins (VCAP, EN,
ANODE, CATHODE)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged device model (CDM),
per JEDEC JS-002 (2)
Other pins
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP155 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
60
UNIT
ANODE to GND
CATHODE to GND
EN to GND
–60
Input Pins
60
V
60
–60
–70
Input to Output
pins
ANODE to CATHODE
V
ANODE
22
nF
µF
External
capacitance
CATHODE, VCAP to ANODE
0.1
External
MOSFET max GATE to ANODE
VGS rating
15
V
TJ
Operating junction temperature range(2)
125
°C
–55
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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6.4 Thermal Information
LM74700-EP
DDF (SOT)
8 PINS
189.8
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
103.8
45.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
19.4
45.5
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –55°C to +125°C; typical values at TJ = 25°C, V(ANODE) = 12 V, C(VCAP) = 0.1 µF, V(EN) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VANODE SUPPLY VOLTAGE
V(ANODE)
Operating input voltage
4
60
3.9
3.1
0.7
1.5
140
150
V
V
VANODE POR Rising threshold
VANODE POR Falling threshold
V(ANODE POR)
2.2
2.8
V
V(ANODE POR(Hys)) VANODE POR Hysteresis
0.39
V
I(SHDN)
Shutdown Supply Current
V(EN) = 0 V
0.9
80
80
µA
µA
µA
I(Q)
Operating Quiescent Current
VANODE = 28 V
ENABLE INPUT
V(EN_IL)
Enable input low threshold
Enable input high threshold
Enable Hysteresis
0.5
1.06
0.52
0.9
2
1.22
2.6
1.42
5
V
V(EN_IH)
V(EN_Hys)
V
I(EN)
Enable sink current
V(EN) = 12 V
3
µA
VANODE to VCATHODE
13
13
20
20
30
30
mV
mV
V(AK REG)
Regulated Forward V(AK) Threshold
VANODE = 28 V
V(AK) threshold for full conduction
mode
V(AK)
34
55
70
mV
mV
mV
–17
–17
–11
–11
–5
–5
V(AK) threshold for reverse current
blocking
V(AK REV)
VANODE = 28 V
Regulation Error AMP
Transconductance(1)
Gm
440
1800
4900 µA/V
GATE DRIVE
V
V
(ANODE) –V(CATHODE) = 100 mV,
(GATE) –V(ANODE) = 5 V
Peak source current
3
11
2370
26
mA
mA
µA
V
V
(ANODE) –V(CATHODE) = –20 mV,
(GATE) –V(ANODE) = 5 V
I(GATE)
Peak sink current
V
V
(ANODE) –V(CATHODE) = 0 V,
(GATE) –V(ANODE) = 5 V
Regulation max sink current
discharge switch RDSON
2
V
V
(ANODE) –V(CATHODE) = –20 mV,
(GATE) –V(ANODE) = 100 mV
RDSON
0.4
2
Ω
CHARGE PUMP
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6.5 Electrical Characteristics (continued)
TJ = –55°C to +125°C; typical values at TJ = 25°C, V(ANODE) = 12 V, C(VCAP) = 0.1 µF, V(EN) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Charge Pump source current (Charge
pump on)
162
300
600
10
µA
µA
V
V
V
(VCAP) –V(ANODE) = 7 V
I(VCAP)
Charge Pump sink current (Charge
pump off)
5
(VCAP) –V(ANODE) = 14 V
Charge pump voltage at V(ANODE)
3.2 V
=
8
I
(VCAP) ≤30 µA
Charge pump turn on voltage
Charge pump turn off voltage
10.4
11
11.6
12.4
12.9
13.9
V
V
V(VCAP)
V(ANODE)
–
Charge Pump Enable comparator
Hysteresis
0.54
5.6
0.8
6.6
5.4
1.36
8.7
6
V
V
V
V
(VCAP) –V(ANODE) UV release at
V
V
(ANODE) –V(CATHODE) = 100 mV
(ANODE) –V(CATHODE) = 100 mV
rising edge
V(VCAP UVLO)
V
(VCAP) –V(ANODE) UV threshold at
5.05
falling edge
CATHODE
V(ANODE) = 12 V, V(ANODE)
V(CATHODE) = –100 mV
–
1.2
2
µA
I(CATHODE)
CATHODE sink current
1.6
2.2
µA
µA
V
(ANODE) –V(CATHODE) = –100 mV
1.25
2.06
V(ANODE) = –12 V, V(CATHODE) = 12 V
(1) Parameter guaranteed by design and characterization
6.6 Switching Characteristics
TJ = –55°C to +125°C; typical values at TJ = 25°C, V(ANODE) = 12 V, C(VCAP) = 0.1 µF, V(EN) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(VCAP) > V(VCAP UVLOR)
(ANODE) –V(CATHODE) = 100 mV to –
MIN
TYP
MAX UNIT
Enable (low to high) to Gate Turn On
delay
ENTDLY
75
110
0.75
0.75
3.1
µs
µs
µs
µs
µs
V
0.45
0.45
1.4
100 mV
Reverse voltage detection to Gate Turn
Off delay
tReverse delay
V(ANODE) = 28V, V(ANODE) –V(CATHODE)
= 100 mV to –100 mV
V
(ANODE) –V(CATHODE) = –100 mV to
700 mV
Forward voltage detection to Gate Turn
On delay
tForward recovery
V(ANODE) = 28V, V(ANODE) –V(CATHODE)
= –100 mV to 700 mV
1.4
2.6
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6.7 Typical Characteristics
6
-55C
5.5
25C
5
125C
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VANODE (V)
图6-2. Operating Quiescent Current vs Supply Voltage
图6-1. Shutdown Supply Current vs Supply Voltage
21
18
15
12
9
-55C
25C
125C
6
3
0
0
10
20
30
40
50
60
70
VANODE = VEN (V)
图6-4. Cathode Sink Current vs Supply Voltage
图6-3. Enable Sink Current vs Supply Voltage
图6-5. Charge Pump Current vs Supply Voltage at VCAP = 6 V
图6-6. Charge Pump V-I Characteristics at VANODE > = 12 V
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6.7 Typical Characteristics (continued)
图6-8. Enable Falling Threshold vs Temperature
图6-7. Charge Pump V-I Characteristics at VANODE = 3.2 V
2.2
2.1
2
VA = 12V
VA = 28V
1.9
1.8
1.7
1.6
-60
-30
0
30
60
90
120
150
Free-Air Temperature (C)
图6-9. Reverse Current Blocking Delay vs Temperature
图6-10. Forward Recovery Delay vs Temperature
13.5
VCAP ON
VCAP OFF
13.2
12.9
12.6
12.3
12
11.7
11.4
-60
-30
0
30
60
90
120
150
Free-Air Temperature (C)
图6-12. Charge Pump ON/OFF Threshold vs Temperature
图6-11. Enable to Gate Delay vs Temperature
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6.7 Typical Characteristics (continued)
100
80
7.2
6.8
6.4
6
VCAP UVLOR
VCAP UVLOF
60
40
20
0
-20
-40
-60
-80
-100
5.6
5.2
4.8
IGATE
60
-60
-30
0
30
60
90
120
150
-20
0
20
VANODE-VCATHODE (mV)
40
Free-Air Temperature (C)
D022
图6-14. Charge Pump UVLO Threshold vs Temperature
图6-13. Gate Current vs Forward Voltage Drop
图6-15. VANODE POR Threshold vs Temperature
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7 Parameter Measurement Information
3.3 V
0V
VGATE
90%
0 V
tENTDLY
t
100 mV
VANODE > VCATHODE
0 mV
VCATHODE > VANODE
-100 mV
VGATE
10%
0 V
tTREVERSE DELAY
t
700 mV
VANODE > VCATHODE
0 mV
VCATHODE > VANODE
-100 mV
VGATE
90%
0 V
tTFWD_RECOVERY
t
图7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74700-EP ideal diode controller has all the features necessary to implement an efficient and fast reverse
polarity protection circuit or be used in an ORing configuration while minimizing the number of external
components. This easy to use ideal diode controller is paired with an external N-channel MOSFET to replace
other reverse polarity schemes, such as a P-channel MOSFET or a Schottky diode. An internal charge pump is
used to drive the external N-Channel MOSFET to a maximum gate drive voltage of approximately 15 V. The
voltage drop across the MOSFET is continuously monitored between the ANODE and CATHODE pins, and the
GATE to ANODE voltage is adjusted as needed to regulate the forward voltage drop at 20 mV. This closed loop
regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures zero DC
reverse current flow. A fast reverse current condition is detected when the voltage across ANODE and
CATHODE pins reduces below –11 mV, resulting in the GATE pin being internally connected to the ANODE pin
turning off the external N-channel MOSFET, and using the body diode to block any of the reverse current. An
enable pin, EN, is available to place the LM74700-EP in shutdown mode, disabling the N-Channel MOSFET and
minimizing the quiescent current.
8.2 Functional Block Diagram
CATHODE
ANODE
GATE
VANODE
VCAP
COMPARATOR
+
œ
Bias Rails
VANODE
+
50 mV
œ
GM AMP
+
œ
ENGATE
VANODE
VCAP_UV
GATE DRIVER
ENABLE
LOGIC
+
20 mV
œ
VCAP_UV
S
R
Q
Q
COMPARATOR
+
œ
+
-11 mV
œ
VANODE
VANODE
VCAP
Charge Pump
Enable Logic
Charge
Pump
REVERSE
PROTECTION
LOGIC
ENABLE LOGIC
VCAP_UV
VCAP
VCAP
EN
GND
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8.3 Feature Description
8.3.1 Input Voltage
The ANODE pin is used to power the LM74700-EP's internal circuitry, typically drawing 80 µA when enabled and
1 µA when disabled. If the ANODE pin voltage is greater than the POR Rising threshold, then LM74700-EP
operates in either shutdown mode or conduction mode in accordance with the EN pin voltage. The voltage from
ANODE to GND is designed to vary from 65 V to –65 V, allowing the LM74700-EP to withstand negative
voltage transients.
8.3.2 Charge Pump
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between VCAP and ANODE pins to provide energy to turn on the external MOSFET. In
order for the charge pump to supply current to the external capacitor the EN pin voltage must be above the
specified input high threshold, V(EN_IH). When enabled the charge pump sources a charging current of 300-µA
typical. If EN pins is pulled low, then the charge pump remains disabled. To ensure that the external MOSFET
can be driven above its specified threshold voltage, the VCAP to ANODE voltage must be above the
undervoltage lockout threshold, typically 6.5 V, before the internal gate driver is enabled. Use 方程式 1 to
calculate the initial gate driver enable delay.
T
(DRV_EN) = 75 µs + C(VCAP) × V(VCAP_UVLOR)
300 µA
(1)
where
• C(VCAP) is the charge pump capacitance connected across ANODE and VCAP pins
• V(VCAP_UVLOR) = 6.5 V (typical)
To remove any chatter on the gate drive, approximately 800 mV of hysteresis is added to the VCAP
undervoltage lockout. The charge pump remains enabled until the VCAP to ANODE voltage reaches 12.4 V,
typically, at which point the charge pump is disabled decreasing the current draw on the ANODE pin. The charge
pump remains disabled until the VCAP to ANODE voltage is below to 11.6-V typically, at which point the charge
pump is enabled. The voltage between VCAP and ANODE continue to charge and discharge between 11.6 V
and 12.4 V as shown in 图 8-1. By enabling and disabling the charge pump, the operating quiescent current of
the LM74700-EP is reduced. When the charge pump is disabled it sinks to 5-µA typical.
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TDRV_EN
TON
TOFF
VIN
VANODE
0V
VEN
12.4 V
11.6 V
VCAP-VANODE
6.5 V
V(VCAP UVLOR)
GATE DRIVER
ENABLE
图8-1. Charge Pump Operation
8.3.3 Gate Driver
The gate driver is used to control the external N-Channel MOSFET by setting the GATE to ANODE voltage to
the corresponding mode of operation. There are three defined modes of operation that the gate driver operates
under forward regulation, full conduction mode and reverse current protection, according to the ANODE to
CATHODE voltage. Forward regulation mode, full conduction mode and reverse current protection mode are
described in more detail in the Regulated Conduction Mode, Full Conduction Mode and Reverse Current
Production Mode sections. 图 8-2 depicts how the modes of operation vary according to the ANODE to
CATHODE voltage of the LM74700-EP. The threshold between forward regulation mode and conduction mode is
when the ANODE to CATHODE voltage is 50 mV. The threshold between forward regulation mode and reverse
current protection mode is when the ANODE to CATHODE voltage is –11 mV.
Reverse Current
Protection Mode
Full Conduction Mode
Regulated Conduction Mode
GATE connected
to ANODE
GATE connected
to VCAP
GATE to ANODE Voltage Regulated
-11 mV
0 mV
20 mV
50 mV
VANODE œ VCATHODE
图8-2. Gate Driver Mode Transitions
Before the gate driver is enabled. the following three conditions must be achieved:
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• The EN pin voltage must be greater than the specified input high voltage.
• The VCAP to ANODE voltage must be greater than the undervoltage lockout voltage.
• The ANODE voltage must be greater than VANODE POR Rising threshold.
If the above conditions are not achieved, then the GATE pin is internally connected to the ANODE pin, assuring
that the external MOSFET is disabled. Once these conditions are achieved, the gate driver operates in the
correct mode depending on the ANODE to CATHODE voltage.
8.3.4 Enable
The LM74700-EP has an enable pin, EN. The enable pin allows for the gate driver to be either enabled or
disabled by an external signal. If the EN pin voltage is greater than the rising threshold, the gate driver and
charge pump operates as described in Gate Driver and Charge Pump sections. If the enable pin voltage is less
than the input low threshold, the charge pump and gate driver are disabled placing the LM74700-EP in shutdown
mode. The EN pin can withstand a voltage as large as 65 V and as low as –65 V. This ability allows for the EN
pin to connect directly to the ANODE pin if enable functionality is not needed. In conditions where EN is left
floating, the internal sink current of 3 uA pulls EN pin low and disables the device.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The LM74700-EP enters shutdown mode when the EN pin voltage is below the specified input low threshold
V(EN_IL). Both the gate driver and the charge pump are disabled in shutdown mode. During shutdown mode the
LM74700-EP enters low IQ operation with the ANODE pin only sinking 1 µA. When the LM74700-EP is in
shutdown mode, forward current flow through the external MOSFET is not interrupted but is conducted through
the MOSFET's body diode.
8.4.2 Conduction Mode
Conduction mode occurs when the gate driver is enabled. There are three regions of operating during
conduction mode based on the ANODE to CATHODE voltage of the LM74700-EP. Each of the three modes is
described in the Regulated Condution Mode, Full Conduction Mode and Reverse Current Protection Mode
sections.
8.4.2.1 Regulated Conduction Mode
For the LM74700-EP to operate in regulated conduction mode, the gate driver must be enabled as described in
the Gate Driver section, and the current from source to drain of the external MOSFET must be within the range
to result in an ANODE to CATHODE voltage drop of –11 mV to 50 mV. During forward regulation mode, the
ANODE to CATHODE voltage is regulated to 20 mV by adjusting the GATE to ANODE voltage. This closed loop
regulation scheme enables graceful turn off of the MOSFET at very light loads and ensures zero DC reverse
current flow.
8.4.2.2 Full Conduction Mode
For the LM74700-EP to operate in full conduction mode, the gate driver must be enabled as described in the
Gate Driver section. The current from source to drain of the external MOSFET must be large enough to result in
an ANODE to CATHODE voltage drop of greater than 50-mV typical. If these conditions are achieved, the GATE
pin is internally connected to the VCAP pin resulting in the GATE to ANODE voltage being approximately the
same as the VCAP to ANODE voltage. By connecting VCAP to GATE the external MOSFETs, RDS(ON) is
minimized, reducing the power loss of the external MOSFET when forward currents are large.
8.4.2.3 Reverse Current Protection Mode
For the LM74700-EP to operate in reverse current protection mode, the gate driver must be enabled as
described in the Gate Driver section, and the current of the external MOSFET must be flowing from the drain to
the source. When the ANODE to CATHODE voltage is typically less than –11 mV, reverse current protection
mode is entered and the GATE pin is internally connected to the ANODE pin. The connection of the GATE to
ANODE pin disables the external MOSFET. The body diode of the MOSFET blocks any reverse current from
flowing from the drain to source.
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LM74700-EP is used with N-Channel MOSFET controller in a typical reverse polarity protection application.
The schematic for the 12-V battery protection application is shown in 图 9-1, where the LM74700-EP is used in
series with a battery to drive the MOSFET Q1. The TVS is not required for the LM74700-EP to operate, but they
are used to clamp the positive and negative voltage surges. The output capacitor, COUT, is recommended to
protect the immediate output voltage collapse as a result of line disturbance.
9.2 Typical Application
Q1
Voltage
Regulator
COUT
CIN
VBAT
GATE CATHODE
LM74700
EN
TVS
ANODE
VCAP
VCAP
GND
图9-1. Typical Application Circuit
9.2.1 Design Requirements
A design example, with system design parameters, is listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V cold crank and 35-V load
dump
Input voltage range
Output voltage
Output current range
Output capacitance
3.2 V during cold crank to 35-V load dump
3-A nominal, 6-A maximum
1-µF minimum, 220-µF typical hold up capacitance
ISO 7637-2 and ISO 16750-2
Automotive EMC compliance
9.2.2 Detailed Design Procedure
9.2.2.1 Design Considerations
• Input operating voltage range, including cold crank and load dump conditions
• Nominal load current and maximum load current
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9.2.2.2 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous drain current, ID, the maximum
drain-to-source voltage, VDS(MAX), and the maximum source current through body diode and the drain-to-source
On resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The
maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage
seen in the application. This would include any anticipated fault conditions. TI recommends to use MOSFETs
with voltage rating up to 60-V maximum with the LM74700-EP because anode-cathode maximum voltage is 65
V. The maximum VGS LM74700-EP can drive is 13 V, so a MOSFET with 15-V minimum VGS must be selected. If
a MOSFET with < 15-V VGS rating is selected, a zener diode can be used to clamp VGS to safe level. During
startup, inrush current flows through the body diode to charge the bulk hold-up capacitors at the output. The
maximum source current through the body diode must be higher than the inrush current that can be seen in the
application.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred, but selecting a MOSFET based
on low RDS(ON) can not always be beneficial. Higher RDS(ON) will provide increased voltage information to
LM74700-EP's reverse comparator at a lower reverse current. Reverse current detection is better with increased
RDS(ON). TI recommends to operate the MOSFET in regulated conduction mode during nominal load conditions
and select RDS(ON), such that at nominal operating current, forward voltage drop VDS is close to 20-mV regulation
point and not more than 50 mV.
As a guideline, TI suggests to choose (20 mV / ILoad(Nominal)) ≤RDS(ON) ≤( 50 mV / ILoad(Nominal)).
MOSFET manufacturers usually specify RDS(ON) at 4.5-V VGS and 10-V VGS. RDS(ON) increases drastically below
4.5-V VGS and RDS(ON) is highest when VGS is close to MOSFET Vth. For stable regulation at light load
conditions, TI recommends to operate the MOSFET close to 4.5-V VGS, that is, much higher than MOSFET gate
threshold voltage. TI recommends to choose MOSFET gate threshold voltage Vth of 2-V to 2.5-V maximum.
Choosing a lower Vth MOSFET also reduces the turn ON time.
Based on the design requirements, preferred MOSFET ratings are:
• 60-V VDS(MAX) and ±20-V VGS(MAX)
• RDS(ON) at 3-A nominal current: (20 mV / 3A ) ≤RDS(ON) ≤( 50 mV / 3A ) = 6.67 mΩ≤RDS(ON) ≤16.67
mΩ.
• MOSFET gate threshold voltage Vth: 2-V maximum
DMT6007LFG MOSFET from Diodes Inc. is selected to meet this 12-V reverse battery protection design
requirements and it is rated at:
• 60-V VDS(MAX) and ±20-V VGS(MAX)
• RDS(ON) 6.5-mΩtypical and 8.5-mΩmaximum rated at 4.5-V VGS
• MOSFET Vth: 2-V maximum
Thermal resistance of the MOSFET must be considered against the expected maximum power dissipation in the
MOSFET to ensure that the junction temperature (TJ) is well controlled.
9.2.2.3 Charge Pump VCAP, input and output capacitance
Minimum required capacitance for charge pump VCAP and input and output capacitance are:
• VCAP: Minimum 0.1 µF is required; recommended value of VCAP (µF) ≥10 × CISS(MOSFET)(µF)
• CIN: minimum 22 nF of input capacitance
• COUT: minimum 100 nF of output capacitance
9.2.3 Selection of TVS Diodes for 12-V Battery Protection Applications
TVS diodes are used in automotive systems for protection against transients. In the 12-V battery protection
application circuit shown in 图 9-2, a bi-directional TVS diode is used to protect from positive and negative
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transient voltages that occur during normal operation of the car and these transient voltage levels, and pulses
are specified in ISO 7637-2 and ISO 16750-2 standards.
Two important specifications are breakdown voltage and clamping voltage of the TVS. Breakdown voltage is the
voltage at which the TVS diode goes into avalanche similar to a zener diode and is specified at a low current
value typical 1 mA and the breakdown voltage must be higher than worst case steady state voltages seen in the
system. The breakdown voltage of the TVS+ must be higher than 24-V jump start voltage and 35-V suppressed
load dump voltage and less than the maximum ratings of LM74700-EP (65 V). The breakdown voltage of TVS–
must be beyond than maximum reverse battery voltage –16 V, so that the TVS- is not damaged due to long
time exposure to reverse connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. TVS diodes are meant to clamp transient pulses and must not interfere with
steady state operation. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V with a
generator impedance of 10 Ω. This action translates to 15 A flowing through the TVS– and the voltage across
the TVS would be close to its clamping voltage.
Q1
Voltage
Regulator
COUT
47 µF
CIN
22 nF
VBAT
GATE CATHODE
LM74700
EN
TVS
SMBJ33CA
ANODE
VCAP
0.1 µF
VCAP
GND
图9-2. Typical 12-V Battery Protection With Single Bi-directional TVS
The next criterion is that the absolute maximum rating of Anode to Cathode reverse voltage of the LM74700-EP
(–75 V) and the maximum VDS rating MOSFET are not exceeded. In the design example, 60-V rated MOSFET
is chosen and maximum limit on the cathode to anode voltage is 60 V.
In case of ISO 7637-2 pulse 1, the anode of LM74700-EP is pulled down by the ISO pulse and clamped by
TVS–. The MOSFET is turned off quickly to prevent reverse current from discharging the bulk output capacitors.
When the MOSFET turns off, the cathode to anode voltage seen is equal to (TVS Clamping voltage + Output
capacitor voltage). If the maximum voltage on output capacitor is 16-V (maximum battery voltage), then the
clamping voltage of the TVS–must not exceed (60 V –16) V = –44 V.
The SMBJ33CA TVS diode can be used for 12-V battery protection application. The breakdown voltage of 36.7
V meets the jump start, load dump requirements on the positive side and 16-V reverse battery connection on the
negative side. During ISO 7637-2 pulse 1 test, the SMBJ33CA clamps at –44 V with 15 A of peak surge current
as shown in 图9-5 and it meets the clamping voltage ≤44 V.
SMBJ series of TVS are rated up to 600-W peak pulse power levels. This rating is sufficient for ISO 7637-2
pulses and suppressed load dump (ISO-16750-2 pulse B).
9.2.4 Selection of TVS Diodes and MOSFET for 24-V Battery Protection Applications
Typical 24-V battery protection application circuit shown in 图 9-3 uses two uni-directional TVS diodes to protect
from positive and negative transient voltages.
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Q1
TVS+
SMBJ58A
Voltage
Regulator
COUT
47 µF
CIN
22 nF
VBAT
GATE CATHODE
LM74700
EN
ANODE
VCAP
0.1 µF
VCAP
TVS-
SMBJ26A
GND
图9-3. Typical 24-V Battery Protection With Two Uni-directional TVS
The breakdown voltage of the TVS+ must be higher than 48-V jump start voltage, less than the absolute
maximum ratings of anode and enable pin of LM74700-EP (65 V) and must withstand 65-V suppressed load
dump. The breakdown voltage of TVS– must be lower than maximum reverse battery voltage –32 V, so that
the TVS–is not damaged due to long time exposure to reverse connected battery.
During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. This
action translates to 12 A flowing through the TVS–. The clamping voltage of the TVS- cannot be same as that of
12-V battery protection circuit. Because during the ISO 7637-2 pulse, the Anode to Cathode voltage seen is
equal to (– TVS Clamping voltage + Output capacitor voltage). For 24-V battery application, the maximum
battery voltage is 32 V, then the clamping voltage of the TVS–must not exceed 75 V –32 V = 43 V.
Single bi-directional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥65
V, maximum clamping voltage is ≤ 43 V and the clamping voltage cannot be less than the breakdown voltage.
Two un-directional TVS connected back-to-back needs to be used at the input. For positive side TVS+,
SMBJ58A with the breakdown voltage of 64.4 V (minimum), 67.8 (typical) is recommended. For the negative
side TVS–, SMBJ26A with breakdown voltage close to 32-V (to withstand maximum reverse battery voltage –
32 V) and maximum clamping voltage of 42.1 V is recommended.
For 24-V battery protection, a 75-V rated MOSFET is recommended to be used along with SMBJ26A and
SMBJ58A connected back-to-back at the input.
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9.2.5 Application Curves
VOUT
VGATE
VIN
GATE TURNS OFF QUICKLY WITHIN1 ꢀs
TVS CLAMPING AT -42 V
IIN
图9-4. ISO 7637-2 Pulse 1
Time (5 ms/DIV)
图9-5. Response to ISO 7637-2 Pulse 1
Time (4 ms/DIV)
Time (4 ms/DIV)
图9-6. Startup With 3-A Load
图9-7. Startup With 6-A Load
Time (20 ms/DIV)
Time (40 ms/DIV)
图9-8. VCAP During Startup at 3-A Load
图9-9. VCAP During Startup at 6-A Load
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Time (100 µs/DIV)
Time (4 ms/DIV)
图9-11. Enable Turn ON Delay
图9-10. Enable Threshold
Time (4 ms/DIV)
Time (4 ms/DIV)
图9-13. ORing VIN1 to VIN2 Switch Over
图9-12. ORing VIN1 to VIN2 Switch Over
Time (4 ms/DIV)
Time (4 ms/DIV)
图9-14. ORing VIN2 to VIN1 Switch Over
图9-15. ORing VIN2 to VIN1 Switch Over
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Time (4 ms/DIV)
Time (10 ms/DIV)
图9-16. ORing –VIN2 Failure and Switch Over to
图9-17. ORing - VIN2 Failure and Switch Over to
VIN1
VIN1
9.3 OR-ing Application Configuration
Basic redundant power architecture comprises of two or more voltage or power supply sources driving a single
load. In its simplest form, the OR-ing solution for redundant power supplies consists of Schottky OR-ing diodes
that protect the system against an input power supply fault condition. A diode OR-ing device provides effective
and low cost solution with few components. However, the diodes forward voltage drops affects the efficiency of
the system permanently, since each diode in an OR-ing application spends most of its time in forward conduction
mode. These power losses increase the requirements for thermal management and allocated board space.
The LM74700-EP ICs combined with external N-Channel MOSFETs can be used in OR-ing Solution as shown in
图 9-18. The forward diode drop is reduced as the external N-Channel MOSFET is turned ON during normal
operation. LM74700-EP quickly detects the reverse current, pulls down the MOSFET gate fast, leaving the body
diode of the MOSFET to block the reverse current flow. An effective OR-ing solution needs to be extremely fast
to limit the reverse current amount and duration. The LM74700-EP devices in OR-ing configuration constantly
sense the voltage difference between Anode and Cathode pins, which are the voltage levels at the power
sources (VIN1, VIN2) and the common load point respectively. The source to drain voltage VDS for each MOSFET
is monitored by the Anode and Cathode pins of the LM74700-EP. A fast comparator shuts down the Gate Drive
through a fast pull-down within 0.45 μs (typical) as soon as V(IN) – V(OUT) falls below –11 mV. The fast
comparator turns on the Gate with 11-mA gate charge current once the differential forward voltage V(IN) –V(OUT)
exceeds 50 mV.
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VIN1
GATE CATHODE
LM74700
EN
ANODE
VOUT
VCAP
GND
LOAD
COUT
VIN2
GATE CATHODE
LM74700
EN
ANODE
VCAP
GND
图9-18. Typical OR-ing Application
图9-12 to 图9-15 show the smooth switch over between two power supply rails VIN1 at 28 V and VIN2 at 33 V. 图
9-16 and 图 9-17 illustrate the performance when VIN2 fails. LM74700-EP controlling VIN2 power rail turns off
quickly, so that the output remains uninterrupted and VIN1 is protected from VIN2 failure.
10 Power Supply Recommendations
The LM74700-EP ideal diode controller is designed for the supply voltage range of 3.2 V ≤ VANODE ≤ 65 V. If
the input supply is located more than a few inches from the device, an input ceramic bypass capacitor higher
than 22 nF is recommended. To prevent LM74700-EP and surrounding components from damage under the
conditions of a direct output short circuit, it is necessary to use a power supply having over load and short circuit
protection.
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11 Layout
11.1 Layout Guidelines
• Connect ANODE, GATE and CATHODE pins of LM74700-EP close to the MOSFET's SOURCE, GATE and
DRAIN pins.
• The high current path for this solution is through the MOSFET. Therefore, it is important to use thick traces for
source and drain of the MOSFET to minimize resistive losses.
• The charge pump capacitor across VCAP and ANODE pins must be kept away from the MOSFET to lower
the thermal effects on the capacitance value.
• The Gate pin of the LM74700-EP must be connected to the MOSFET gate with short trace. Avoid excessively
thin and long trace to the Gate Drive.
• Keep the GATE pin close to the MOSFET to avoid increase in MOSFET turn-off delay due to trace
resistance.
• Obtaining acceptable performance with alternate layout schemes is possible. However, the layout shown in
图11-1 is intended as a guideline.
11.2 Layout Example
MOSFET DRAIN
Signal Via
Power Via
Top layer
MOSFET SOURCE
VOUT
VIN
COUT
CIN
CVCAP
GND PLANE
图11-1. LM74700-EP DDF Package Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74700MDDFREP
V62/21608
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-50 to 125
-50 to 125
EP747
EP747
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2021
OTHER QUALIFIED VERSIONS OF LM74700-EP :
Automotive : LM74700-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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