LM74720QDRRRQ1 [TI]
具有有源整流和负载突降保护功能的汽车类低 IQ 理想二极管控制器 | DRR | 12 | -40 to 125;
| 型号： | LM74720QDRRRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有有源整流和负载突降保护功能的汽车类低 IQ 理想二极管控制器 | DRR | 12 | -40 to 125 控制器 二极管 |
| 文件： | 总28页 (文件大小：3108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74720-Q1
ZHCSOW4B –SEPTEMBER 2021 –REVISED MARCH 2022
LM74720-Q1 具有有源整流和负载突降保护功能的低IQ 汽车类理想二极管控制
器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性
LM74720-Q1 理想二极管控制器可驱动和控制外部背
对背N 沟道MOSFET，从而模拟具有电源路径开/关控
制和过压保护功能的理想二极管整流器。3V 至 65V 的
宽输入电源电压可保护和控制 12V 和 24V 汽车类电池
供电的 ECU。该器件可承受并保护负载免受低至 –
65V 的负电源电压的影响。集成的理想二极管控制器
(GATE) 可驱动第一个 MOSFET 来代替肖特基二极
管，实现反向输入保护和输出电压保持功能。具有快速
导通和关断比较器的强大升压稳压器可确保在汽车测试
（如 ISO16750 或 LV124）期间实现稳健、高效的
MOSFET 开关性能，期间 ECU 会收到输入短时中断
以及频率高达 100 kHz 的交流叠加输入信号。运行期
间的低静态电流 35 µA（最大值）可实现常开型系统设
计。在电源路径中使用了第二个 MOSFET 的情况下，
该器件允许使用 EN 引脚实现负载断开控制。在EN 处
于低电平时，静态电流降至 3.3 μA（最大值）。该器
件具有可调节过压切断保护功能，可提供负载突降保
护。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 3V 至65V 输入范围
• 反向输入保护低至–65V
• 低静态电流：运行时35 µA（最大值）
• 3.3 µA（最大值）低关断电流（EN = 低电平）
• 17 mV 阳极至阴极正向压降调节下，理想二极管正
常运行
• 驱动外部背对背N 沟道MOSFET
• 集成型29 mA 升压稳压器
• 快速响应反向电流阻断：0.5 µs
• 高达100 kHz 的有源整流
• 可调节过压保护
• 采用合适的TVS 二极管，符合汽车ISO7637 瞬态
要求
• 采用节省空间的12 引脚WSON 封装
• 与LM74721-Q1 引脚对引脚兼容
器件信息
封装(1)
封装尺寸（标称值）
器件型号
LM74720-Q1
WSON (12)
3.0mm × 3.0mm
2 应用
• 汽车电池保护
– ADAS 域控制器
– 出色的音频放大器
– 音响主机
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 网关
Q1
Q1
Q2
VBATT
12 V
VOUT
VBATT
12 V
VOUT
PD
C VS CAP LX
GATE
A
D1
C VS CAP LX
PD
GATE
A
D1
SMBJ36CA
SMBJ36CA
VSNS
SW
VSNS
SW
R1
BATT_MON
LM74720-Q1
GND
R1
BATT_MON
LM74720-Q1
GND
R2
EN
R2
ON OFF
OV
EN
R3
ON OFF
OV
R3
具有开关输出的低IQ 理想二极管
低IQ 理想二极管
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFH8
LM74720-Q1
ZHCSOW4B –SEPTEMBER 2021 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
9.1 Application Information............................................. 14
9.2 Typical 12-V Reverse Battery Protection
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
8.4 Device Functional Mode (Shutdown Mode)..............13
9 Application and Implementation..................................14
Application...................................................................14
9.3 Do's and Don'ts.........................................................22
10 Power Supply Recommendations..............................23
10.1 Transient Protection................................................23
10.2 TVS Selection for 12-V Battery Systems................ 24
10.3 TVS Selection for 24-V Battery Systems................ 24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 第三方产品免责声明................................................26
12.2 接收文档更新通知................................................... 26
12.3 支持资源..................................................................26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
12.6 术语表..................................................................... 26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2022) to Revision B (March 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
Changes from Revision * (September 2021) to Revision A (January 2022)
Page
• Updated the Electrical Characteristics and Switching Characteristics with specification limits.......................... 4
• Added the Typical Characteristics section..........................................................................................................7
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5 Pin Configuration and Functions
12
11
10
1
2
3
4
GATE
A
C
VS
CAP
LX
VSNS
SW
RTN
9
8
7
Exposed
Thermal
Pad
PD
5
6
OV
EN
GND
图5-1. WSON 12-Pin DRR Transparent Top View
表5-1. Pin Functions
PIN
LM74720-Q1
TYPE
DESCRIPTION
NAME
DRR-12 (WSON)
Diode controller gate drive output. Connect to the GATE of the external
MOSFET.
GATE
1
O
A
2
3
I
I
Anode of the ideal diode. Connect to the source of the external MOSFET.
Voltage sensing input
VSNS
Voltage sensing disconnect switch terminal. VSNS and SW are internally
connected through a switch. Use SW as the top connection of the battery
sensing or OV resistor ladder network. When EN is pulled low, the switch is
OFF, disconnecting the resistor ladder from the battery line, thereby cutting off
the leakage current. If the internal disconnect switch between VSNS and SW
is not used, then short them together and connect to C pin.
SW
4
I
Adjustable overvoltage threshold input. Connect a resistor ladder across SW
to OV terminal. When the voltage at OV exceeds the overvoltage cut-off
threshold, then the PD is pulled low turning OFF the HSFET. PD is driven high
when the sense voltage goes below the OV falling threshold.
OV
EN
5
6
I
I
EN Input. Connect to A or C pin for always ON operation. In this mode, the
device consumes an IQ of 35 µA (maximum). Can be driven externally from a
micro controller I/O. Pulling the pin low below 0.5 V enters the device in low Iq
shutdown mode.
GND
PD
7
8
G
O
Connect to the system ground plane.
Pull down connection for the external load disconnect FET. Connect to the
GATE of the external FET to PD pin.
Leave PD pin floating if the load disconnect FET is not used.
Switch node of the internal boost regulator. This node must be kept small on
the PCB for good performance and low EMI. Connect the boost inductor
between this pin and the DRAIN connection of the external FET.
LX
9
I
Boost Regulator Output. This pin is used to provide a drive voltage to the gate
driver of the ideal diode stage as well as drive supply for the HSFET. Connect
a 1-µF capacitor between this pin and the VS pin.
CAP
10
O
VS
C
11
12
I
I
Supply voltage pin
Cathode of the ideal diode. Connect to the DRAIN of the external MOSFET.
The voltage sensed at this pin is used to control the external MOSFET GATE.
RTN
Thermal Pad
Leave exposed pad floating. Do not connect to GND plane.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
MAX
70
UNIT
A to GND
VS, C to GND
70
–0.3
–0.3
V(A)
VSNS, SW, EN, OV to GND, V(A) > 0 V
70
V
(70 + V(A)
)
VSNS, SW, EN, OV to GND, V(A) ≤0 V
Input Pins
RTN to GND
0.3
10
–65
IVSNS, ISW
–1
mA
IEN, IOV, V(A) > 0 V
IEN, IOV, V(A) ≤0 V
CAP to C
–1
Internally limited
–0.3
–0.3
–0.3
–0.3
–5
15.9
85
CAP to A
Output Pins
GATE to A
15
V
LX, CAP, PD to GND
85
Output to Input Pins
C to A
85
(2)
Operating junction temperature, Tj
Storage temperature, Tstg
150
150
–40
°C
–40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
Corner pins (GATE, EN, GND,
C)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged device model (CDM),
per AEC Q100-011
Other pins
(1) AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
65
UNIT
A to GND
C to GND
EN to GND
A
–60
Input Pins
65
V
65
–60
0.1
1
µF
µF
External
capacitance
VS, CAP to C
External
Inductor
LX
100
µH
External
MOSFET max GATE to A
VGS rating
15
V
TJ
Operating junction temperature range(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
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conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM74720-Q1
THERMAL METRIC(1)
DRR (WSON)
UNIT
12 PINS
61.6
50
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
32.7
1.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
32.7
6.9
ΨJB
RθJC
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
VA POR Rising threshold
VA POR Falling threshold
Minimum Voltage at VS
Shutdown Supply Current
3.1
2.2
3.4
2.6
3.85
2.9
3
V
V
V(A POR)
V(VS)
V
I(SHDN)
V(EN) = 0 V
1.5
27
3.3
µA
V(EN) = 2 V, Active Rectifier Controller
In Regulation, –40°C ≤TJ ≤+85°C
32
35
µA
µA
I(Q)
Total System Quiescent Current
V(EN) = 2 V, Active Rectifier Controller
In Regulation, –40°C ≤TJ ≤+125°C
27
ENABLE INPUT
V(EN_IH)
Enable input high threshold
Enable input low threshold
Enable Hysteresis
2
V
V(EN_IL)
0.5
0.85
380
52
1.2
V(EN_Hys)
I(EN)
mV
nA
Enable sink current
V(EN) = 12 V
155
VANODE to VCATHODE (VA –C
)
V(AC REG)
V(AC_FWD)
Regulated Forward V(AC) Threshold
V(AC) threshold from RCB to oFCB
9
16.4
105
22.7
140
mV
mV
75
V(AC) threshold for reverse current
blocking
V(AC_REV)
mV
–12
–5.65
–1.3
GATE DRIVE
3 V < V(VS) < 65 V
V(A) –V(C) = –20 mV
V(A) –V(C) = 0 V,
9.5
13
V
A
V
(GATE) –V(A)
Peak sink current
2.5
26
I(GATE)
Regulation max sink current
14
39
µA
V
(GATE) –V(A) = 5 V
V(A) –V(C) = –20 mV,
(GATE) –V(A) = 100 mV
RGATE
GATE pulldown resistance
1.2
Ω
V
BOOST REGULATOR
Boost output rising threshold
Hysteresis
13
15.5
V
V
V
(CAP) – V(VS)
1.1
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(CAP) –V(VS) = 7.5 V
MIN
110
1.3
TYP
29
MAX UNIT
I(CAP)
I(LX)
Boost load capacity
mA
V
V(VS) = 12 V
V(VS) = 3 V
140
170
210
5.1
mA
mA
Ω
Peak inductor current limit threshold
Low side switch On-Resistance
R(LX)
2.7
BATTERY SENSING (VSNS, SW) AND OVER VOLTAGE DETECTION (OV, PD)
Battery sensing disconnect switch
resistance
R(SW)
104
226
430
Ω
V(OVR)
V(OVF)
V(OV_Hys)
I(OV)
Overvoltage threshold input, rising
Overvoltage threshold input, falling
OV Hysteresis
1.13
1.03
1.231
1.125
110
50
1.33
V
1.215
V
mV
nA
µA
mA
mA
OV Input leakage current
Pullup current
0 V < V(OV) < 5 V
3 V < V(VS) < 65 V
110
60
I(PD_SRC)
43
55
7
50
Peak pulldown current
DC pulldown current
88
117
14
I(PD_SINK)
CATHODE (C)
I(C)
V(OV) > V(OVR)
10
8.5
15
18
µA
µA
V(A) = 12 V, V(A) –V(C) = –100 mV
V(A) = –14 V, V(C) = 14 V
CATHODE sink current
10.6
6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(A) ↑V(A POR) to V(GATE –A) > 5 V,
C(GATE –A) = 10 nF,
ENTDLY
A (low to high) to GATE Turn On delay
200
µs
V(A) –V(C) = +30 mV to –100
mV, V(GATE) –V(A) < 1 V, C(GATE –A)
10 nF
Reverse voltage detection to Gate Turn
Off delay
tGATE_OFF(DLY)
0.47
1.9
0.81
µs
=
=
V(A) –V(C) = –100 mV to +700
mV, V(GATE) –V(A) > 5 V, C(GATE –A)
10 nF
Forward voltage detection to Gate Turn
On delay
tGATE_ON(DLY)
2.9
µs
tEN_OFF(DLY)PD EN to PD Delay
tOV_OFF(DLY)PD OV to PD Delay
6.5
0.9
38
12
1.5
65
µs
µs
µs
EN ↓to PD ↓
OV ↑to PD ↓
tPD_Pk
Peak Pull Down duration
11
I(PD_SINK, Pk) ↑to I(PD_SINK, DC)
↓
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6.7 Typical Characteristics
650
600
550
500
450
400
350
300
250
200
150
100
50
8
7
6
5
4
3
2
1
0
−40C
25C
85C
125C
150C
−40C
25C
85C
125C
150C
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VA (V)
图6-1. Operating Quiescent Current vs Supply Voltage
图6-2. Shutdown Supply Current vs Supply Voltage
3.5
3
2.5
2
1.5
VS PORR
VS PORF
1
-50
0
50
100
150
200
Temperature (C)
图6-3. VA POR Threshold vs Temperature
图6-4. VS POR Threshold vs Temperature
14
40
35
30
25
20
15
10
5
VS = 12 V
VS = 3 V
13
12
11
(VCAP−VS) R
(VCAP−VS) F
10
0
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (C)
Temperature (C)
图6-5. Boost Comparator Threshold vs Temperature
图6-6. Boost Loading Capacity vs Temperature
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6.7 Typical Characteristics (continued)
1.2
1
1.3
1.2
1.1
1
0.8
0.6
0.4
0.2
VOV_R
VOV_F
-50
0
50
100
150
200
Temperature (C)
-50
0
50
100
150
200
Temperature (C)
图6-8. PD Turn-off Delay During OV
图6-7. OV Threshold vs Temperature
8
7
6
5
4
3
2
4
3
2
1
0
C(GATE − A) = 4.7 nF
C(GATE − A) = 10 nF
C(GATE − A) = 22 nF
C(GATE − A) = 33 nF
C(GATE − A) = 47 nF
-50
0
50
100
150
200
-50
0
50
100
150
200
Temperature (C)
Temperature (C)
图6-9. PD Turn-off Delay During EN
图6-10. Forward Turn-on Delay vs Temperature
90
60
5
RPD = 270
RPD = 330
4.5
4
30
0
3.5
3
-30
-60
-90
2.5
2
-10
0
10
20
30
40
50
V(A− C) mV
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
图6-11. Gate Current vs Forward Voltage Drop
图6-12. PD Turn-off Delay vs Supply Voltage
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7 Parameter Measurement Information
30 mV
VA > VC
0 mV
VC > VA
–100 mV
VGATE
1 V
0 V
ttGATE_OFF(DLY)
t
700 mV
VA > VC
0 mV
VC > VA
–100 mV
VGATE
5 V
0 V
ttGATE_ON(DLY)
t
VOVR + 0.1 V
0 V
VPD
0 V
ttOV_OFF(DLY)PD
t
图7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74720-Q1 ideal diode controller drives and controls external back-to-back N-Channel MOSFETs to
emulate an ideal diode rectifier with power path ON and OFF control and overvoltage protection. The wide input
supply of 3 V to 65 V allows protection and control of 12-V and 24-V automotive battery powered ECUs. IQ
during operation (EN = High) is < 35 µA and < 3.3 µA during shutdown mode (EN = Low). The device can
withstand and protect the loads from negative supply voltages down to –65 V. An integrated ideal diode
controller (GATE) drives the first MOSFET to replace a Schottky diode for reverse input protection and output
voltage holdup. A strong 29-mA boost regulator and short turn-ON and turn-OFF delay times of comparators
ensures fast transient response ensuring robust and efficient MOSFET switching performance during automotive
testing such as ISO16750 or LV124 where an ECU is subjected to input short interruptions and AC superimpose
input signals up to 100-kHz frequency. The device features an adjustable over voltage cut-off protection feature
for load dump protection.
The LM74720-Q1 controls the GATE of the MOSFET to regulate the forward voltage drop at 17 mV. The linear
regulation scheme in these devices enables graceful control of the GATE voltage and turns off of the MOSFET
during a reverse current event and ensures zero DC reverse current flow.
Low quiescent current (< 35 µA) in operation enables always ON system designs. With a second MOSFET in the
power path, the device allows load disconnect control using EN pin. Quiescent current reduces to 3.3 μA with
EN low.
8.2 Functional Block Diagram
Q1
Q2
VBATT
VOUT
18V
CAP LX
PD
C
VS
A
GATE
VSNS
SW
50 µA
EN
Boost
Converter and
control
Reverse Current
Protection controller and
Gate Driver
EN
R1
BATT_MON
A+10 V
88 mA
10 mA
R2
OV
+
–
OV
RTN
1.231 V
1.125 V
R3
EN
C
+
2.55 V
2.5 V
–
OV
EN
+
–
VCAP
VA
A+10 V
2 V
Bias Rails
0.5 V
RTN
A
Reverse
Protection Logic
GND
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8.3 Feature Description
8.3.1 Dual Gate Control (GATE, PD)
The LM74720-Q1 features two separate gate control and driver outputs. That is, GATE and PD to drive back-to-
back N-channel MOSFETs.
8.3.1.1 Reverse Battery Protection (A, C, GATE)
A, C, GATE comprises of Ideal Diode stage. Connect the Source of the external MOSFET to A, Drain to C and
Gate to GATE pin. The LM74720-Q1 has integrated reverse input protection down to –65 V.
In LM74720-Q1, the voltage drop across the MOSFET is continuously monitored between the A and C pins, and
the GATE to A voltage is adjusted as needed to regulate the forward voltage drop at 17 mV (typical) for
LM74720-Q1. This closed loop regulation scheme enables graceful turn-off of the MOSFET during a reverse
current event and ensures zero DC reverse current flow. This scheme ensures robust performance during slow
input voltage ramp down tests. Along with the linear regulation amplifier scheme, the LM74720-Q1 also
integrates a fast reverse voltage comparator. When the voltage drop across A and C reaches V(AC_REV)
threshold, then the GATE goes low within 0.5 µs (typical). This fast reverse voltage comparator scheme ensures
robust performance during fast input voltage ramp down tests such as input micro-shorts. The external MOSFET
is turned back ON when the voltage across A and C hits V(AC_FWD) threshold within 1.9 µs (typical). For ideal
diode only designs, connect LM74720-Q1 as shown in 图8-1.
Q1
VBATT
12 V
VOUT
C VS CAP LX
PD
GATE
A
D1
SMBJ36CA
VSNS
SW
R1
BATT_MON
LM74720-Q1
R2
EN
ON OFF
GND
OV
R3
图8-1. Configuring LM74720-Q1 for Ideal Diode Only
8.3.1.2 Load Disconnect Switch Control (PD)
PD pin provides a 50-µA drive and 88-mA peak pulldown strength for the load disconnect switch stage. Connect
the Gate of the FET to PD pin. Place a 18-V Zener (Dz) across the FET gate and source.
For inrush current limiting, connect CdVdT capacitor and R1 as shown in 图8-2.
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Q1
Dz
18 V
R1
COUT
RPD
CdVdT
50 µA
PD
Fault
Off
88 mA
10 mA
GND
图8-2. Inrush Current Limiting
The CdVdT capacitor is required for slowing down the PD voltage ramp during power up for inrush current
limiting. Use 方程式1 to calculate CdVdT capacitance value.
IPD_DRV
CdVdT
=
x COUT
IINRUSH
(1)
where IPD_DRV is 50 μA (typical), IINRUSH is the inrush current, and COUT is the output load capacitance. An extra
resistor, R1, in series with the CdVdT capacitor improves the turn-off time.
PD is pulled low during the following conditions:
• During an OV event with the OV pin voltage rising above the V(OVR) threshold
• When the EN pin is pulled low with V(EN) driven lower than V(EN_IL) level
• When the voltage at VS pin drops below the V(VS POR) falling threshold
During these conditions, the FET Q1 turns OFF with its GATE connected to its SOURCE terminal through the
external Zener (Dz).
The peak power dissipated in the LM74720-Q1 at the instance of PD pulldown can be calculated approximately
using 方程式2.
PPD_peak = VOUT × IPD_SINK
(2)
where
• IPDSINK_peak is the peak sink current of 88 mA (typical)
In the system designs with input voltage above 48 V, TI recommends to place a resistor, RPD, in series with the
PD pin as shown in 图 8-2. The peak power dissipation during the pulldown events gets distributed in RPD and
the internal PD switch. A resistor value in the range of 270 Ω to 330 Ω can be selected to limit the device power
dissipation within the safe limits. 图6-12 shows the turn-OFF delay characteristics with various resistors.
8.3.2 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
Connect a resistor ladder as shown in 图8-3 for overvoltage threshold programming.
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VBATT
A
SNS
SW
EN
R1
R2
R3
BATT_MON
LM74720-Q1
OV
+
–
PD_OFF
1.231 V
1.125 V
图8-3. Programming Overvoltage Threshold and Battery Sensing
A disconnect switch is integrated between VSNS and SW pins. This switch is turned OFF when EN pin is pulled
low. This action helps to reduce the leakage current through the resistor divider network during system shutdown
state (IGN_OFF state).
8.3.3 Boost Regulator
The LM74720-Q1 integrates a boost converter to provide voltage necessary to drive the external N-channel
MOSFETs for the ideal diode and the load disconnect stages. The boost converter uses hysteretic mode control
scheme for the output voltage (VCAP–VVS) regulation along with the constant peak inductor current limit (ILX).
When the CAP–VS voltage is below its nominal value of typically 11.9 V, the low side switch of the boost is
turned on and the inductor current rises with the slope of VS/L approximately. After the current hits the limit of
ILX , that is,140 mA (typical), then the low side switch is turned off and the inductor current discharges to the
output till it reaches zero. The low side switch is turned on again and the switching cycle repeats until the CAP–
VS voltage has risen above the boost rising threshold of 13 V (typical). After this threshold level is reached, the
boost converter switching is turned OFF to reduce the quiescent current.
For the boost converter to be enabled, the EN pin voltage must be above the specified input high threshold,
V(ENR). The boost converter has a maximum output load capacity of 29-mA typical. If EN pin is pulled low, then
the boost converter remains disabled.
8.4 Device Functional Mode (Shutdown Mode)
The LM74720-Q1 enters shutdown mode when the EN pin voltage is below the specified input low threshold,
V(EN_IL). Both the gate drivers (GATE and PD) and the boost regulator are disabled in shutdown mode. During
shutdown mode, the LM74720-Q1 enters low IQ operation with a total input quiescent consumption of 1.5 µA
(typical).
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
LM74720-Q1 controls two N-channel power MOSFETs with GATE used to control diode MOSFET to emulate an
ideal diode and PD controlling second MOSFET for power path cut-off when disabled or during an overvoltage
protection and provide inrush current limiting. IQ during operation (EN = High) is < 35 µA and <3.3 µA during
shutdown mode (EN = Low). LM74720-Q1 can be placed into low quiescent current mode using EN = low, where
both GATE and PD are turned OFF.
9.2 Typical 12-V Reverse Battery Protection Application
A typical application circuit of LM74720-Q1 configured to provide reverse battery protection with overvoltage
protection and inrush current limiting is shown in 图9-1.
C2
1 µF, 50 V
Q1
Q2
VOUT
VBATT
12 V
D2
18 V
CLOAD
470 µF
C1
0.1 µF,
50 V
L1
100 µH
C3
1 µF, 50 V
D1
SMBJ36CA
R4
100
R5
0
C4
10 nF
PD
C VS CAP LX
GATE
A
VSNS
SW
R1
LM74720-Q1
GND
90.9 k
BATT_MON
R2
EN
9.09 k
ON OFF
OV
R3
3.48 k
图9-1. Typical Application Circuit –12-V Reverse Battery Protection and Overvoltage Protection
9.2.1 Design Requirements for 12-V Battery Protection
The system design requirements are listed in 表9-1.
表9-1. Design Parameters –12-V Reverse Battery Protection and Overvoltage Protection
DESIGN PARAMETER
Operating input voltage range
Output power
EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V cold crank and 35-V load dump
50 W
4-A nominal, 5-A maximum
Output current range
Input capacitance
0.1-µF minimum
Output capacitance
0.1-µF minimum, (optional 220 µF for E-10 functional class A performance)
37 V, output cut-off > 37 V
Overvoltage cut-off
AC super imposed test
Automotive transient immunity compliance
Battery monitor ratio
2-V peak-peak 30 kHz, extendable to 6-V peak-peak 30 kHz
ISO 7637-2, ISO 16750-2 and LV124
8:1
9.2.2 Automotive Reverse Battery Protection
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9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
ISO 7637-2 pulse 1 specifies negative transient immunity of electronic modules connected in parallel with an
inductive load when the battery is disconnected. A typical pulse 1 specified in ISO 7637-2 starts with battery
disconnection where supply voltage collapses to 0 V followed by –150 V 2 ms applied with a source impedance
of 10 Ω at a slew rate of 1 µs on the supply input. LM74720-Q1 blocks reverse current and prevents the output
voltage from swinging negative, protecting the rest of the electronic circuits from damage due to negative
transient voltage. MOSFET Q1 is quickly turned off within 0.5 µs by fast reverse comparator of LM74720-Q1. A
single bidirectional TVS is required at the input to clamp the negative transient pulse within the operating
maximum voltage across cathode to anode of 85 V and does not violate the MOSFET Q1 drain-source
breakdown voltage rating.
图9-2 shows ISO 7637-2 pulse 1 performance of LM74720-Q1.
VOUT
VIN
IIN
VGATE
图9-2. Performance During ISO 7637-2 Pulse 1 Test
9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
All electronic modules are tested for proper operation with superimposed AC ripple on the DC battery voltage.
AC super imposed test specified in ISO 16750-2 and LV124 E-06 requires AC ripple of 2-V peak-peak on a 13.5-
V DC battery voltage, swept from 15 Hz to 30 kHz. LM74720-Q1 rectifies the AC superimposed voltage by
turning the MOSFET Q1 OFF quickly to cut off reverse current and turning the MOSFET Q1 ON quickly during
forward conduction. Active rectification of 2-V peak-peak 5-kHz AC input by LM74720-Q1 is shown in 图 9-3.
Fast turn-OFF and quick turn-ON of the MOSFET reduces power dissipation in the MOSFET Q1 and active
rectification reduces power dissipation in the output hold-up capacitor's ESR by half. Active rectification of 2-V
peak-peak 30-kHz AC input is shown in 图9-4.
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VIN
VIN
VOUT
VOUT
VGATE
VGATE
IIN
IIN
图9-3. AC Super Imposed Test –2-V Peak-Peak 5 图9-4. AC Super Imposed Test –2-V Peak-Peak 30
kHz
kHz
9.2.2.3 Input Micro-Short Protection: LV124 E-10
E-10 test specified in LV124 standard checks for immunity of electronic modules to short interruptions in power
supply input due to contact issues or relay bounce. During this test (case 2), micro-short is applied on the input
for a duration as low as 10 µs to several ms. For a functional pass status A, electronic modules are required to
run uninterrupted during the E-10 test (case 2) with 100-µs duration. When input micro-short is applied for 100
µs, LM74720-Q1 quickly turns off MOSFET Q1 by shorting GATE to ANODE (source of MOSFET) within 0.5 µs
to prevent the output from discharging and the PD remains ON keeping MOSFET Q2 ON, enabling fast recovery
after the input short is removed.
图9-5 shows performance of LM74720-Q1 during E10 input power supply interruption test case 2. After the input
short is removed, input voltage recovers and MOSFET Q1 is turned back ON within 200 µs. Note that dual-gate
drive topology allows MOSFET Q2 to remain ON during the test and helps in restoring the input power faster.
Output voltage remains unperturbed during the entire duration, achieving functional status A.
VIN
VIN
VOUT
VOUT
VGATE
VGATE
VPD
IIN
图9-5. Input Micro-Short –LV124 E10 TC 2 100 µs 图9-6. Input Micro-Short –LV124 E10 TC 2 100 µs
With PD
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9.2.3 Detailed Design Procedure
9.2.3.1 Design Considerations
表 9-1 summarizes the design parameters that must be known for designing an automotive reverse battery
protection circuit with overvoltage cut-off. During power up, inrush current through MOSFET Q2 must be limited
so that the MOSFET operates well within its SOA. Maximum load current, maximum ambient temperature, and
thermal properties of the PCB determine the RDSON of the MOSFET Q2 and maximum operating voltage
determines the voltage rating of the MOSFET Q2. Selection of MOSFET Q2 is determined mainly by the
maximum operating load current, maximum ambient temperature, maximum frequency of AC super imposed
voltage ripple, and ISO 7637-2 pulse 1 requirements. Overvoltage threshold is decided based on the rating of
downstream DC/DC converter or other components after the reverse battery protection circuit. A single
bidirectional TVS or two back-back unidirectional TVS are required to clamp input transients to a safe operating
level for the MOSFETs Q1, Q2, and LM74720-Q1.
9.2.3.2 Boost Converter Components (C2, C3, L1)
Place a minimum of a 1-μF capacitor across drain of the FET to GND (C2) and across CAP pin of LM74720- Q1
to drain of the FET (C3). Use a 100-μH inductor (L1) with saturation current rating > 175 mA. Example:
XPL2010-104ML from coil craft.
9.2.3.3 Input and Output Capacitance
TI recommends a minimum input capacitance C1 of 0.1 µF and output capacitance COUT of 0.1 µF.
9.2.3.4 Hold-Up Capacitance
Usually bulk capacitors are placed on the output due to various reasons such as uninterrupted operation during
power interruption or micro-short at the input, hold-up requirements for doing a memory dump before turning of
the module and filtering requirements as well. This design considers minimum bulk capacitors requirements for
meeting functional status "A" during LV124 E10 test case 2 100-µs input interruption. To achieve functional pass
status A, acceptable voltage droop in the output of LM74720-Q1 is based on the UVLO settings of downstream
DC/DC converters. For this design, a 1-V drop in output voltage for 100 µs is considered and the minimum hold-
up capacitance required is calculated by
ILOAD_MAX
CHOLD_UP_MIN
=
x100m s
dVOUT
(3)
Hold-up capacitance required for 1-V drop in 100 µs is 470 µF.
9.2.3.5 Overvoltage Protection and Battery Monitor
Resistors R1, R2 and R3 connected in series are used to program the overvoltage threshold and battery monitor
ratio. The resistor values required for setting the overvoltage threshold VOV to 37 V and battery monitor ratio
VBATT_MON : VBATT to 1:8 are calculated by solving Equation 3 and Equation 4.
R3
VOVR
=
x VOV
R1+ R2 + R3
(4)
R2 + R3
VBAT_MON
=
x VBATT
R1+ R2 + R3
(5)
For minimizing the input current drawn from the battery through resistors R1, R2 and R3, TI recommends to use
higher value of resistance. Using high value resistors adds error in the calculations because the current through
the resistors at higher value become comparable to the leakage current into the OV pin. Maximum leakage
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current into the OV pin is 1 µA and choosing (R1 + R2 + R3) < 120 kΩ ensures current through resistors is 100
times greater than leakage through OV pin.
Based on the device electrical characteristics, VOVR is 1.23 V and battery monitor ratio (VBATT_MON / VBATT) is
designed for a ratio of 1:8. To limit (R1 + R2 + R3) < 120 kΩ, select (R1 + R2) = 100 kΩ. Solving Equation 3 gives
R3 = 3.45 kΩ. Solving Equation 4 for R2 using (R1 + R2) = 100 kΩ and R3 = 3.45 kΩ, gives R2 = 9.48 kΩ and
R1 = 90.52 kΩ.
Standard 1% resistor values closest to the calculated resistor values are R1 = 90.9 kΩ, R2 = 9.09 kΩ, and R3 =
3.48 kΩ.
9.2.3.6 MOSFET Selection: Blocking MOSFET Q1
For selecting the blocking MOSFET Q1, important electrical parameters are the maximum continuous drain
current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), the
maximum source current through body diode and the drain-to-source ON resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. This action includes all the automotive transient events and any anticipated fault
conditions. TI recommends to use MOSFETs with VDS voltage rating of 60 V along with a single bidirectional
TVS or a VDS rating 40-V maximum rating along with two unidirectional TVS connected back-to-back at the
input.
The maximum VGS LM74720-Q1 can drive is 14 V, so a MOSFET with 15-V minimum VGS rating must be
selected. If a MOSFET with < 15-V VGS rating is selected, a zener diode can be used to clamp VGS to safe level,
but this results in increased IQ current.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred, but selecting a MOSFET based
on low RDS(ON) cannot be beneficial always. Higher RDS(ON) provides increased voltage information to LM74720-
Q1's reverse comparator at a lower reverse current. Reverse current detection is better with increased RDS(ON)
.
Choosing a MOSFET with < 50-mV forward voltage drop at maximum current is a good starting point. Based on
the design requirements, BUK7Y4R8-60E MOSFET is selected
9.2.3.7 MOSFET Selection: Load Disconnect MOSFET Q2
The VDS rating of the MOSFET Q2 must be sufficient to handle the maximum system voltage along with the
input transient voltage. For this 12-V design, transient overvoltage events are during suppressed load dump 35
V 400 ms and ISO 7637-2 pulse 2 A 50 V for 50 µs. Furthermore, ISO 7637-2 Pulse 3B is a very fast repetitive
pulse of 100 V 100 ns that is usually absorbed by the input and output ceramic capacitors and the maximum
voltage on the 12-V battery can be limited to < 40 V the minimum recommended input capacitance of 0.1 µF.
The 50-V SO 7637-2 Pulse 2 A can also be absorbed by input and output capacitors and its amplitude can be
reduced to 40-V peak by placing sufficient amount of capacitance at input and output. Choose a MOSFET with
≥40-V VDS rating.
The VGS rating of the MOSFET Q2 must be higher than that maximum boost drive output of 15.5 V. FET with
VGS absolute maximum rating of +/–20 VGS is selected.
Inrush current through the MOSFET during input hot-plug into the 12-V battery is determined by output
capacitance. External capacitor on PD, CDVDT, is used to limit the inrush current during input hot-plug or startup.
The value of inrush current determined by 方程式 1 must be selected to ensure that the MOSFET Q2 is
operating well within its safe operating area (SOA). To limit inrush current to 1.8-A, value of CDVDT is 10.43 nF,
closest standard value of 10.0 nF is chosen.
Duration of inrush current is calculated by:
12
dT
=
x COUT
INRUSH
IINRUSH
(6)
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Calculated inrush current duration is 3.13 ms with 1.8-A inrush current.
MOSFET BUK7Y4R8-60E having 60-V VDS and ±20-V VGS rating is selected for Q2. Power dissipation during
inrush is well within the MOSFET's safe operating area (SOA).
9.2.3.8 TVS Selection
TI recommends a 600-W SMBJ TVS such as SMBJ33CA for input transient clamping and protection. For
detailed explanation on TVS selection for 12-V battery systems, refer to TVS Selection for 12-V Battery Systems.
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9.2.4 Application Curves
VIN
VIN
VOUT
VCAP
VLX
IL
VGATE
VPD
图9-8. Start-up 12 V Showing Boost Output (VCAP
)
图9-7. Start-up 12 V with EN Pulled to VIN
and Switching (VLX)
VIN
VIN
VOUT
VPD
VOUT
VGATE
IIN
IIN
图9-9. Reverse Input Voltage –14 V for 60 s
图9-10. Inrush Current with No Load at Output
VIN
VIN
VOUT
VPD
VOUT
VPD
IIN
IIN
图9-11. Inrush Current with 60-ΩLoad
图9-12. Hot-Plug into 12 V
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VIN
VIN
VOUT
VOUT
VEN
VGATE
VEN
IIN
图9-13. Output Turn-on with Enable
图9-14. GATE Turn-on with Enable
VIN
VIN
VOUT
VPD
VOUT
VPD
IIN
VEN
图9-15. PD Turn-on with Enable
图9-16. Overvoltage Protection
VIN
VIN
VOUT
VPD
VOUT
VEN
VPD
IIN
图9-18. Turn-on Delay –PD
图9-17. Overvoltage Recovery
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VIN
VIN
VOUT
VOUT
VPD
VGATE
VEN
VEN
图9-19. Turn-off Delay –GATE
图9-20. Turn-off Delay –PD
9.3 Do's and Don'ts
• Leave the exposed pad (RTN) of the IC floating. Do not connect the exposed pad to the GND plane.
Connecting RTN to GND disables the reverse polarity protection feature.
• Connect a limiting resistor RPD in series with the PD pin in the system application designs with input voltage
above 48 V. This resistor value can be chosen in the range of 270 Ω to 330 Ω.
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10 Power Supply Recommendations
10.1 Transient Protection
When the external MOSFETs turn OFF during the conditions, such as overvoltage cut-off, reverse current
blocking, EN causing an interruption of the current flow, the input line inductance generates a positive voltage
spike on the input and output inductance generates a negative voltage spike on the output. The peak amplitude
of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device.
These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to address the
issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Using a Schottky diode across the output and GND to absorb negative spikes
• Using a low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with 方程式7.
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(7)
where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications can require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during EMC testing such as
automotive ISO7637 pulses.
The circuit implementation with optional protection components (a ceramic capacitor, TVS, and Schottky diode)
is shown in 图10-1.
Q1
Q2
VOUT
*
VIN
D1
C2
C3
*
CIN
D3
L1
D2
PD
C VS CAP LX
GATE
A
VSNS
SW
R1
BATT_MON
R2
LM74720-Q1
GND
EN
ON OFF
OV
R3
* Optional components needed for suppression of transients
图10-1. Circuit Implementation With Optional Protection Components for LM74720-Q1
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10.2 TVS Selection for 12-V Battery Systems
In selecting the TVS, important specifications are breakdown voltage and clamping voltage. The breakdown
voltage of the TVS+ must be higher than 24-V jump start voltage and 35-V suppressed load dump voltage and
less than the maximum ratings of LM74720-Q1 (65 V). The breakdown voltage of TVS– must be beyond than
maximum reverse battery voltage –16 V, so that the TVS– is not damaged due to long time exposure to
reverse connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V
with a generator impedance of 10 Ω. This action translates to 15 A flowing through the TVS–, and the voltage
across the TVS is close to its clamping voltage.
The next criterion is that the absolute maximum rating of cathode to anode voltage of the LM74720-Q1 (85 V)
and the maximum VDS rating MOSFET are not exceeded. In the design example, 60-V rated MOSFET is chosen
and maximum limit on the cathode to anode voltage is 60 V.
During ISO 7637-2 pulse 1, the anode of LM74720-Q1 is pulled down by the ISO pulse, clamped by TVS– and
the MOSFET Q1 is turned off quickly to prevent reverse current from discharging the bulk output capacitors.
When the MOSFET turns off, the cathode to anode voltage seen is equal to (TVS Clamping voltage + Output
capacitor voltage). If the maximum voltage on output capacitor is 16 V (maximum battery voltage), then the
clamping voltage of the TVS–must not exceed, (60 V –16) V = –44 V.
The SMBJ33CA TVS diode can be used for 12-V battery protection application. The breakdown voltage of 36.7
V meets the jump start, load dump requirements on the positive side and 16-V reverse battery connection on the
negative side. During ISO 7637-2 pulse 1 test, the SMBJ33CA clamps at –44 V with 12 A of peak surge current
as shown in and it meets the clamping voltage ≤44 V.
SMBJ series of TVS' are rated up to 600-W peak pulse power levels and are sufficient for ISO 7637-2 pulses.
10.3 TVS Selection for 24-V Battery Systems
For 24-V battery protection application, the TVS and MOSFET in 图 9-1 must be changed to suit 24-V battery
requirements.
The breakdown voltage of the TVS+ must be higher than 48-V jump start voltage, less than the absolute
maximum ratings of anode and enable pin of LM74720-Q1 (70 V) and must withstand 65-V suppressed load
dump. The breakdown voltage of TVS– must be lower than maximum reverse battery voltage –32 V, so that
the TVS–is not damaged due to long time exposure to reverse connected battery.
During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. This
translates to 12 A flowing through the TVS–. The clamping voltage of the TVS– cannot be same as that of 12-
V battery protection circuit. Because during the ISO 7637-2 pulse, the Anode to Cathode voltage seen is equal
to (– TVS Clamping voltage + Output capacitor voltage). For 24-V battery application, the maximum battery
voltage is 32 V, then the clamping voltage of the TVS- must not exceed, 85 V –32 V = 53 V.
Single bidirectional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥ 65
V, maximum clamping voltage is ≤ 53 V and the clamping voltage cannot be less than the breakdown voltage.
Two un-directional TVS connected back-to-back must be used at the input. For positive side TVS+, TI
recommends SMBJ58A with the breakdown voltage of 64.4 V (minimum), 67.8 (typical). For the negative side
TVS–, TI recommends SMBJ28A with breakdown voltage close to 32 V (to withstand maximum reverse battery
voltage –32 V) and maximum clamping voltage of 42.1 V.
For 24-V battery protection, TI recommends a 75-V rated MOSFET to be used along with SMBJ28A and
SMBJ58A connected back-to-back at the input.
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11 Layout
11.1 Layout Guidelines
• For the ideal diode stage, connect A, GATE and C pins of LM74720-Q1 close to the MOSFET's SOURCE,
GATE and DRAIN pins.
• The high current path of for this solution is through the MOSFET; therefore, it is important to use thick and
short traces for source and drain of the MOSFET to minimize resistive losses.
• The GATE pin of the LM74720-Q1 must be connected to the MOSFET GATE with short trace.
• Boost converter switching currents flow into LX, CAP, GND pins and C3 (across DRAIN of the FET to GND).
The loops formed by capacitor across CAP pin and DRAIN of the FET and C3 to GND must be minimized by
placing these capacitors as close as possible. Keep the GND side of the C3 capacitor close to GND pin of
LM74720-Q1.
• Place transient suppression components like input TVS and output Schottky close to LM74720-Q1.
11.2 Layout Example
G
S
s
S
Q1
Q2
s
s
S
G
D2
GTE
C
C2
VIN PLANE
VS
CAP
VOUT PLANE
A
L1
VSNS
C3
LX
PD
SW
COUT
D1
OV
EN
GND
GND PLANE
图11-1. LM74720-Q1 Layout Example
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12 Device and Documentation Support
12.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
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TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74720QDRRRQ1
ACTIVE
WSON
DRR
12
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
L74720
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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