LM74910-Q1 [TI]
具有断路器、200kHz ACS 以及欠压和过压保护功能的汽车类理想二极管;
| 型号： | LM74910-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断路器、200kHz ACS 以及欠压和过压保护功能的汽车类理想二极管 断路器 二极管 |
| 文件： | 总48页 (文件大小：4659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74900-Q1, LM74910-Q1
ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
LM749x0-Q1 具有断路器、欠压和过压保护以及故障输出功能的汽车类理想二
极管
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
LM749x0-Q1 理想二极管控制器可驱动和控制外部背
对背N 沟道MOSFET，从而模拟具有电源路径开/关控
制及过流和过压保护功能的理想二极管整流器。3V 至
65V 的宽输入电源电压可保护和控制 12V 和 24V 汽车
类电池供电的 ECU。该器件可以承受并保护负载免受
低至 –65V 的负电源电压的影响。集成的理想二极管
控制器 (DGATE) 可驱动第一个 MOSFET 来代替肖特
基二极管，以实现反向输入保护和输出电压保持。在电
源路径中使用了第二个 MOSFET 的情况下，该器件允
许在发生过流和过压事件时使用HGATE 控制将负载断
开（开/关控制）。该器件具有集成电流检测放大器，
可提供具有可调过流和短路阈值的精确电流监控。该器
件具有可调节过压切断保护功能。该器件具有睡眠模
式，可实现超低静态电流消耗 (6µA)，同时在车辆处于
停车状态时为始终开启的负载提供刷新电流。
LM749x0-Q1 的最大额定电压为65V。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
• 功能安全型
– 可提供用于功能安全系统设计的文档
• 3V 至65V 输入范围
• 反向输入保护低至–65V
• 在共漏极配置下，可驱动外部背对背N 沟道
MOSFET
• 10.5mV 阳极至阴极正向压降调节下，理想二极管
正常运行
• 低反向检测阈值(-10.5mV)，具有快速关断响应
(0.5µs)
• 20mA 峰值栅极(DGATE) 导通电流
• 2.6A 峰值DGATE 关断电流
• 可调过流和短路保护
• 精度为10% 的模拟电流监视器输出(IMON)
• 可调节过压和欠压保护
• 2.5µA 低关断电流（EN = 低电平）
• 睡眠模式，电流为6µA（EN=高电平，SLEEP=低
电平）
封装信息
封装(1)
封装尺寸（标称值）
器件型号
LM74900-Q1(2)
LM74910-Q1
VQFN (24)
4.00mm × 4.00mm
• 采用合适的TVS 二极管，符合汽车ISO7637 瞬态
要求
• 采用节省空间的24 引脚VQFN 封装
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 预发布信息（非量产数据）。
2 应用
• 汽车电池保护
– ADAS 域控制器
– 信息娱乐系统与仪表组
– 汽车音频：外部放大器
• 用于冗余电源的有源ORing
Q1
Q2
VBATT
RSENSE
VOUT
RISCP
RSET
RG
COUT
CIN
Cdvdt
C
VS
ISCP CS+
CS-
DGATE CAP
HGATE
A
OUT
SW
R1
R2
FLT
EN
LM749x0-Q1
UVLO
OV
ON OFF
ON
SLEEP
OFF
TMR
CT
IMON
ILIM
RLIM
GND
R3
RMON
典型应用图
具有过流保护功能的器件启动
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDE6
LM74900-Q1, LM74910-Q1
ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
9.3 Feature Description...................................................16
10 Applications and Implementation..............................25
10.1 Application Information........................................... 25
10.2 Typical 12-V Reverse Battery Protection
Application...................................................................25
10.3 Addressing Automotive Input Reverse Battery
Protection Topologies With LM749x0-Q1....................36
10.4 Power Supply Recommendations...........................36
10.5 Layout..................................................................... 38
11 Device and Documentation Support..........................39
11.1 接收文档更新通知................................................... 39
11.2 支持资源..................................................................39
11.3 Trademarks............................................................. 39
11.4 静电放电警告...........................................................39
11.5 术语表..................................................................... 39
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Compariosn Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 开关特性......................................................................9
7.7 Typical Characteristics..............................................10
8 Parameter Measurement Information..........................14
9 Detailed Description......................................................15
9.1 Overview...................................................................15
9.2 Functional Block Diagram.........................................16
Information.................................................................... 39
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2022) to Revision A (June 2023)
Page
• 将状态从预告信息 更改为量产数据 ................................................................................................................... 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNOSDE6
2
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LM74900-Q1, LM74910-Q1
ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
5 Device Compariosn Table
Parameter
LM74900-Q1
LM74910-Q1
Charge pump strength
2.7 mA
3.8 mA
6 Pin Configuration and Functions
24
23
22
21
20
19
ISCP
DGATE
A
1
2
3
4
18
17
16
NC
SLEEP_OV
SW
Exposed
Thermal Pad
UVLO
15
14
13
OUT
HGATE
OV
EN
5
6
GND
7
8
9
10
11
12
图6-1. RGE Package, 24-Pin VQFN (Transparent Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DGATE
A
NO.
1
O
I
Diode controller gate drive output. Connect to the GATE of the external MOSFET.
Anode of the ideal diode. Connect to the source of the external MOSFET.
2
Voltage sensing disconnect switch terminal. VSNS and SW are internally connected
through a switch. Use SW as the top connection of the battery sensing or OV resistor
ladder network. When EN is pulled low, the switch is OFF disconnecting the resistor
ladder from the battery line thereby cutting off the leakage current. If the internal
disconnect switch between VSNS and SW is not used then short them together and
connect to VS pin.
SW
3
I
Adjustable undervoltage threshold input. Connect a resistor ladder across SW to
UVLO terminal to GND. When the voltage at UVLO goes below the undervoltage cut-
off threshold then the HGATE is pulled low turning OFF the HSFET. HGATE turns ON
when the sense voltage goes above the UVLO falling threshold.
UVLO
OV
4
5
I
I
Adjustable overvoltage threshold input. Connect a resistor ladder across SW to OV
terminal. When the voltage at OVP exceeds the overvoltage cut-off threshold then the
HGATE is pulled low turning OFF the HSFET. HGATE turns ON when the sense
voltage goes below the OVP falling threshold.
EN input. Connect to VS pin for always ON operation. Can be driven externally from a
microcontroller I/O. Pulling it low below V(ENF) makes the device enter into low Iq
shutdown mode.
EN
6
7
I
I
Active low SLEEP mode input. Can be driven from the microcontroller. When pulled
low device enters into low power state with charge pump and gate drive turned off.
Internal bypass switch provides output voltage with limited current capacity.
SLEEP
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English Data Sheet: SNOSDE6
LM74900-Q1, LM74910-Q1
ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
NC
8
No connect.
—
Fault timer input. A capacitor across TMR pin to GND sets the times for fault warning,
fault turn off (FLT), and retry periods. Leave it open for fastest setting. Connect TMR to
GND to disable overcurrent protection.
TMR
9
I
Analog current monitor output. This pin sources a scaled down ratio of current through
the external current sense resistor RSNS. A resistor from this pin to GND converts
current to proportional voltage. If unused, leave it floating.
IMON
10
O
Overcurrent detection setting. A resistor across ILIM to GND sets the overcurrent
comparator threshold. Connect ILIM to GND if overcurrent protection feature is not
desired.
ILIM
FLT
11
12
I
Open drain fault output. FLT pin is pulled low in case of UVLO, OV, OCP, or SCP
event.
O
GND
13
14
15
G
O
I
Connect to the system ground plane.
HGATE
OUT
GATE driver output for the HSFET. Connect to the GATE of the external FET.
Connect to the output rail (external MOSFET source).
SLEEP mode overvoltage protection pin. Connect this pin to VS for overvoltage cut-off
functionality. Connect to OUT for overvoltage clamp functionality.
SLEEP_OV
NC
16
17
I
No connect.
—
Short circuit detection threshold setting.
ISCP
18
I
Leave ISCP floating if short circuit protection is not desired. When ISCP is connected
to CS+, device sets an internal fix threshold of 20 mV.
19
20
21
22
I
I
Current sense negative input.
CS–
CS+
NC
Current sense positive input. Connect a TBD resistor across CS+ to the external
current sense resistor.
No connect.
—
Input power supply to the IC. Connect VS to middle point of the common drain back to
back MOSFET configuration. Connect a 100-nF capacitor across VS and GND pins.
VS
P
CAP
C
23
24
O
I
Charge pump output. Connect a 100-nF capacitor across CAP and VS pins.
Cathode of the ideal diode. Connect to the drain of the external MOSFET.
Leave exposed pad floating. Do not connect to GND plane.
RTN
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power, G = ground
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNOSDE6
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ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
MAX
70
UNIT
A to GND
VS, CS+, CS-, ISCP, OUT, SLEEP_OV to GND
SW, C, EN, SLEEP, FLT, UVLO, OV to GND, V(A) > 0 V
SW, C, EN, SLEEP, FLT, UVLO, OV to GND, V(A) ≤0 V
70
–1
70
V
–0.3
V(A)
(70 + V(A)
)
Input Pins
RTN to GND
ISW ,IFLT
0.3
10
–65
mA
V
–1
TMR, ILIM
5.5
–0.3
–1
IEN, IUVLO,IOV V(A) > 0 V
mA
Internally limited
IEN, IUVLO,IOV V(A) ≤0 V
ISCP, CS+ to CS-
OUT to VS
Input Pins
0.3
5
V
V
–0.3
–65
–0.3
–0.3
–0.3
-0.3
CAP to VS
15
CAP to A
85
Output Pins
DGATE to A
FLT to GND
15
V
70
IMON
-1
5.5
15
HGATE to OUT
–0.3
–5
Output to Input Pins
C to A
85
(2)
Operating junction temperature, Tj
Storage temperature, Tstg
150
150
–40
–40
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
±750
±500
V(ESD) Electrostatic discharge
Corner pins
Other pins
V
Charged device model (CDM), per
AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
65
65
65
65
5
UNIT
A to GND
V
V
V
V
V
–60
Input Pins
0
0
0
0
VS, SW, CS+, CS–, ISCP to GND
EN,UVLO, OV, SLEEP to GND
Output pins FLT to GND
Output pins IMON to GND
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Product Folder Links: LM74900-Q1 LM74910-Q1
English Data Sheet: SNOSDE6
LM74900-Q1, LM74910-Q1
ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
External
Capacitanc CAP to A, VS to GND, A to GND
e
0.1
µF
External
MOSFET
max VGS
DGATE to A and HGATE to OUT
15
V
rating
Tj
Operating Junction temperature(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.4 Thermal Information
LM749x0-Q1
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
44
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
38.3
21.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ΨJT
21.3
ΨJB
RθJC(bot)
5.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = 12 V, C(CAP) = 0.1 µF, V(EN) , V(SLEEP)= 2 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
V(VS)
Operating input voltage
VS POR threshold, rising
VS POR threshold, falling
SHDN current, I(GND)
3
2.4
2.2
65
2.9
2.7
5
V
V
V(VS_PORR)
V(VS_PORF)
I(SHDN)
2.6
2.4
V
V(EN) = 0 V
2.5
µA
µA
µA
µA
I(SLEEP)
SLEEP mode current, I(GND)
V(EN) = 2 V, V(SLEEP) = 0 V
V(EN) = 2 V
5.5
10
630
635
750
750
I(Q)
Total System Quiescent current, I(GND)
V(A) = V(VS) = 24 V, V(EN) = 2 V
I(A) leakage current during Reverse
Polarity,
µA
µA
–100
–1
–35
I(REV)
0 V ≤V(A) ≤–65 V
I(OUT) leakage current during Reverse
Polarity
–0.3
ENABLE
V(ENF)
Enable rising threshold voltage
0.6
0.8
0.7
55
1.05
0.98
200
V
V
Enable threshold voltage for low Iq
shutdown, falling
V(ENF)
I(EN)
0.41
nA
0 V ≤V(EN) ≤ 65 V
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNOSDE6
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ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
7.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = 12 V, C(CAP) = 0.1 µF, V(EN) , V(SLEEP)= 2 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
UNDER VOLTAGE LOCKOUT COMPARATOR (SW, UVLO)
V(UVLOR)
V(UVLOF)
I(UVLO)
UVLO threshold voltage, rising
UVLO threshold voltage, falling
0.585
0.533
0.6
0.55
50
0.63
0.573
200
V
V
nA
0 V ≤V(UVLO) ≤ 5 V
OVER VOLTAGE PROTECTION AND BATTERY SENSING (SW, OV) INPUT
Battery sensing disconnect switch
resistance
R(SW)
10
22.5
46
3 V ≤V(A) ≤65 V
Ω
V(OVR)
V(OVF)
I(OV)
Overvoltage threshold input, rising
Overvoltage threshold input, falling
OV Input leakage current
0.585
0.533
0.6
0.55
50
0.63
0.573
200
V
V
nA
0 V ≤V(OV) ≤5 V
CURRENT SENSE AMPLIFIER
RSET = 50Ω, RIMON = 5kΩ,
10kΩ (corresponds to VSNS = 6mV to
30mV) Gain of 45 and 90 respectively.
Input referred offset (VSNS to VIMON
scaling)
V(OFFSET)
-2.1
82
2.1
97
mV
RSET = 50Ω, RIMON = 5kΩ,
(corresponds to VSNS = 6mV to
30mV)
V(GE_SET)
VSNS to VIMON scaling
90
OCP comparator threshold, rising
(ILIM)
V(SNS_TH)
V(SNS_TH)
1.08
1.02
1.22
1.15
1.32
1.25
OCP comparator threshold, falling
(ILIM)
V
ISCP
SCP Input Bias current
SCP threshold
VISCP = 12V
9.5
10.5
20
12
µA
mV
mV
%
V(SNS_SCP)
V(SNS_SCP)
IMON_ACC
FAULT
R(FLT)
17.86
22.77
R(ISCP) = 0Ω (ISCP connected to VS)
R(ISCP) = 1kΩ (external)
VSENSE = 20mV
SCP threshold
31
Current monitor output accuracy
-12.5
12.5
FLT_I Pull-down resistance
FLT Input leakage current
11
25
60
Ω
I_FLT
400
nA
0 V ≤V(FLT) ≤20 V
–100
DELAY TIMER (TMR)
I(TMR_SRC_CB)
I(TMR_SRC_FLT)
I(TMR_SNK)
TMR source current
65
1.94
2
85
2.7
2.7
1.2
1.1
97
3.4
µA
µA
µA
V
TMR source current
TMR sink current
3.15
1.4
V(TMR_OC)
Voltage at TMR pin for IWRN shut off
Voltage at TMR pin for IFLT triggerring
1.1
V(TMR_FLT)
1.04
1.2
V
Voltage at TMR pin for AR counter
falling threshold
V(TMR_LOW)
N(A_R_Count)
0.1
0.2
32
0.3
V
Number of autoretry cycles
CHARGE PUMP (CAP)
Charge Pump source current (Charge
pump on)
V
V
(CAP) –V(A) = 7 V, 6 V ≤V(S) ≤65
I(CAP)
1.3
2.5
2.7
4.2
mA
mA
V(CAP) –V(A) = 7 V, VS= 65 V,
LM74910-Q1 Only
Charge Pump Turn ON voltage
Charge Pump Turnoff voltage
11
12.2
13.2
13.2
14.1
V
V
VCAP –VS
11.9
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Product Folder Links: LM74900-Q1 LM74910-Q1
English Data Sheet: SNOSDE6
LM74900-Q1, LM74910-Q1
ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
7.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = 12 V, C(CAP) = 0.1 µF, V(EN) , V(SLEEP)= 2 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Charge Pump UVLO voltage
threshold, rising
5.4
6.6
7.9
6.6
V
V
V(CAP UVLO)
Charge Pump UVLO voltage
threshold, falling
4.4
5.5
IDEAL DIODE (A, C, DGATE)
V(A_PORR) V(A) POR threshold, rising
V(A_PORF)
2.2
2
2.45
2.25
2.7
V
V
V(A) POR threshold, falling
2.45
Regulated Forward V(A)–V(C)
Threshold
V(AC_REG)
V(AC_REV)
V(AC_FWD)
3.6
–16
150
10.5
–10.5
177
13.4
–5
mV
mV
mV
V(A)–V(C) Threshold for Fast Reverse
Current Blocking
V(A)–V(C) Threshold for Reverse to
Forward transition
200
3 V < V(S) < 5 V
7
V
V
Gate Drive Voltage
V
(DGATE) –V(A)
5 V < V(S) < 65 V
9.2
11.5
18.5
14
V(A) –V(C) = 100 mV, V(DGATE) –V(A)
= 1 V
Peak Gate Source current
Peak Gate Sink current
mA
mA
V(A) –V(C) = –12 mV, V(DGATE)
V(A) = 11 V
–
I(DGATE)
2670
V(A) –V(C) = 0 V, V(DGATE) –V(A) = 11
V
Regulation sink current
Cathode leakage Current
5
4
13.5
9
µA
µA
I(C)
32
V(A) = –14 V, V(C) = 12 V
HIGH SIDE CONTROLLER (HGATE, OUT)
3 V < V(S) < 5 V
5 V < V(S) < 65 V
7
10
V
V
Gate Drive Voltage
(HGATE) –V(OUT)
V
11.1
55
14.5
75
Source Current
Sink Current
39
µA
mA
I(HGATE)
V(OV) > V(OVR)
128
180
SLEEP MODE
V(SLEEPR)
SLEEP high threshold voltage
0.85
0.7
1.05
V
V
SLEEP threshold voltage for low Iq
shutdown, falling
V(SLEEPF)
I(SLEEP)
0.41
SLEEP input leakage current
100
21.3
160
23
nA
V
Overvoltage
threshold
SLEEP mode overvoltage rising
threshold
SLEEP=Low, EN=High
SLEEP=Low, EN=High
19.3
18.4
150
Overvoltage
threshold
SLEEP mode overvoltage threshold
21
22.2
310
V
Overcurrent
threshold
SLEEP mode overcurrent threshold
(device Latch-off)
250
mA
T(TSD)
SLEEP mode TSD Threshold, rising
TSD Hysteresis
SLEEP=Low, EN=High
SLEEP=Low, EN=High
155
10
℃
℃
T(TSDhyst)
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7.6 开关特性
TJ = –40°C 至+125°C；TJ = 25°C、V(A) = V(OUT) = V(VS) = 12V、C(CAP) = 0.1µF、V(EN)、V(SLEEP) = 2V 时的典型值，在自然
通风条件下的工作温度范围内（除非另有说明）
参数
测试条件
最小值 典型值 最大值 单位
V(A) –V(C) = +30mV 至–100mV
tDGATE_OFF(dly)
0.5
2
0.95
3.8
µs
µs
µs
反向电压检测期间的DGATE 关断延迟
至V(DGATE–A) < 1V，C(DGATE–A)
=
10nF
V(A)–V(C) = –20mV 至+700mV 至
V(DGATE-A) > 5V，C(DGATE-A) = 10nF，
仅限LM74900-Q1
tDGATE_ON(dly)
正向电压检测期间的DGATE 导通延迟
V(A)–V(C) = –20mV 至+700mV 至
V(DGATE-A) > 5V，C(DGATE-A) = 10nF，
仅限LM74910-Q1
tDGATE_ON(dly)
0.75
1.6
正向电压检测期间的DGATE 导通延迟
EN 期间的DGATE 导通延迟
EN ↑至V(DGATE-A) > 5V，C(DGATE-A)
= 10nF
tEN(dly)_DGATE
180
5
270
7
µs
µs
µs
tUVLO_OFF(deg)_HGA
UVLO 期间的HGATE 关断抗尖峰脉冲 UVLO ↓至HGATE ↓
UVLO 期间的HGATE 关断抗尖峰脉冲 UVLO ↑至HGATE ↑
TE
tUVLO_ON(deg)_HGAT
8.5
E
tOVP_OFF(deg)_HGAT
4
9
3
7
µs
µs
µs
OV 期间的HGATE 关断抗尖峰脉冲
OV 期间的HGATE 关断抗尖峰脉冲
OV ↑至HGATE ↓
OV ↓至HGATE ↑
E
tOVP_ON(deg)_HGATE
tSCP_DLY
(VISCP - VCS-) = 0mv 至100mV
HGATE↓，CGS = 4.7nF
5.5
短路保护关闭延迟
(VCS+ - VCS-)↑HGATE↓，CTMR
=
=
35
190
1.5
µs
µs
50pF
过流保护关闭延迟
tOCP_TMR_DLY
(VCS+ - VCS-)↑HGATE↓，CTMR
10nF
过流保护关闭延迟
(VCS+ - VCS-) ↓HGATE ↑，CTMR
50pF
=
=
ms
过流/短路保护自动重试延迟
tAUTO_RETRY_DLY
(VCS+ - VCS-) ↓HGATE ↑，CTMR
10nF
230
35
ms
µs
过流/短路保护自动重试延迟
(VCS+ - VCS-)↑FLT↓，CTMR = 50pF
OV ↑至FLT ↓
故障置位延迟
tFLT_ASSERT
3
4
µs
µs
µs
µs
µs
故障置位延迟
tFLT_DE-ASSERT
tSLEEP_OCP_LATCH
tSLEEP_MODE
tOVCLAMP
故障取消置位延迟
睡眠OCP 锁存延迟
3.5
95
3.5
7.5
SLEEP=低电平，EN=高电平
睡眠模式进入延迟
OV 钳位响应延迟
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7.7 Typical Characteristics
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
20
16
12
8
–40C
25C
85C
125C
150C
–40C
25C
85C
125C
150C
4
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS Supply Voltage (V)
图7-1. Operating Quiescent Current vs Supply Voltage
图7-2. Shutdown Current vs Supply Voltage
18
16
14
12
3.3
3
2.7
2.4
2.1
1.8
10
–40C
–40C
1.5
1.2
0.9
0.6
0.3
25C
25C
8
85C
85C
125C
125C
150C
6
150C
4
2
3
4
5
6
7
8
9
10
11
12
5
10 15 20 25 30 35 40 45 50 55 60 65
VS Supply Voltage (V)
VS Supply Voltage (V)
图7-4. Charge Pump Current vs Supply Voltage at CAP –VS ≥
图7-3. SLEEP Mode Current vs Supply Voltage
6 V (LM74900-Q1)
5
6
5
4
–40C
25C
4.5
4
85C
125C
150C
3.5
3
3
–40C
2.5
2
25C
2
1
0
85C
125C
150C
1.5
1
0
2
4
6
8
10
12
3
4
5
6
7
8
9
10
11
12
VCAP –VS Voltage (V)
VS Supply Voltage (V)
图7-6. Charge Pump V-I Characteristics at VS ≥12 V (LM74900-
图7-5. Charge Pump Current vs Supply Voltage at CAP –VS ≥
Q1)
6 V (LM74910-Q1)
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7.7 Typical Characteristics (continued)
7.5
12.6
12
–40C
7
6.5
6
25C
85C
125C
150C
11.4
10.8
10.2
9.6
5.5
5
4.5
4
–40C
25C
85C
125C
150C
3.5
3
2.5
2
9
1.5
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS Supply voltage (V)
0
2
4
6
8
10
12
VCAP –VS (V)
图7-8. DGATE Drive Voltage vs Supply Voltage
图7-7. Charge Pump V-I Characteristics at VS ≥12 V (LM74910-
Q1)
12.6
12
11.4
10.8
–40C
10.2
25C
85C
125C
9.6
150C
9
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS Supply Voltage (V)
图7-9. HGATE Drive Voltage vs Supply Voltage
图7-10. ANODE Leakage Current vs Reverse ANODE Voltage
0.65
0.65
0.61
0.57
0.53
0.61
0.57
0.53
OV Rising
OV Falling
UVLO Rising
UVLO Falling
0.49
0.49
0.45
0.45
-40
0
40
80
120
160
-40
0
40
80
120
160
Temperature (C)
Temperature (C)
图7-11. UVLO Thresholds vs Temperature
图7-12. OVP Thresholds vs Temperature
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7.7 Typical Characteristics (continued)
7.5
20.8
20.6
20.4
20.2
20
CP UVLO Rising
CP UVLO Falling
6.9
6.3
5.7
5.1
4.5
19.8
-40
0
40
80
120
160
-40
0
40
80
120
160
Temperature (C)
Temperature (C)
图7-14. ISCP to CS–Threshold vs Temperature
图7-13. Charge Pump UVLO Threshold vs Temperature
11.2
2.6
VA POR RISING
VA POR FALLING
2.5
11
10.8
10.6
10.4
10.2
2.4
2.3
2.2
2.1
2
-40
0
40
80
120
160
-40
0
40
80
120
160
Temperature (C)
Temperature (C)
图7-15. ISCP Bias Current vs Temperature
图7-16. VA POR Threshold vs Temperature
2.7
0.85
2.65
0.77
0.69
0.61
0.53
0.45
2.6
2.55
2.5
VS_POR_RISING
VS_POR_FALLING
2.45
2.4
-40
0
40
80
120
160
-40
0
40
80
120
160
Temperature (C)
Temperature (C)
图7-17. VS POR Threshold vs Temperature
图7-18. DGATE Turn OFF Delay
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7.7 Typical Characteristics (continued)
3
5
4.6
4.2
3.8
3.4
3
LM74910-Q1
LM74900-Q1
2.4
1.8
1.2
0.6
0
-40
0
40
80
120
160
-40
0
40
80
120
160
Temperature (C)
Temperature (C)
图7-19. DGATE Turn On Delay During Forward Conduction
图7-20. HGATE Turn OFF Delay During OV
3
5
4.5
2.8
2.6
2.4
2.2
2
4
3.5
3
2.5
2
–40C
25C
85C
125C
150C
1.5
1
0.5
0
-40
0
40
80
120
160
0
5
10
15
20
25
30
35
40
45
50
Temperature (C)
VRSENSE (V)
图7-21. HGATE Turn OFF Delay During SCP
图7-22. IMON Voltage vs Sense Voltage
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8 Parameter Measurement Information
700 mV
30 mV
VA > VC
0 mV
VA > VC
0 mV
VC > VA
-100 mV
VC > VA
-20 mV
VDGATE
VDGATE
5V
1V
0 V
0 V
ttDGATE_OFF(DLY)
t
ttDGATE_ON(DLY)t
0.1 V
+
VOVR
VUVLOF
–
0.1 V
0 V
0 V
11 V
11 V
1 V
0 V
1 V
0 V
ttOVP_OFF(deg)HGATE
t
ttUVLO_OFF(deg)HGATE
t
0.1 V
–
VOVF
0.1 V
+
VSNS
0 V
0 V
12.4 V
11 V
5 V
0 V
0 V
ttOVP_ON(deg)GATE
t
ttSCP_DLY
图8-1. Timing Waveforms
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9 Detailed Description
9.1 Overview
The LM749x0-Q1 family of ideal diode controllers drive back-to-back external N-Channel MOSFETs to realize
low-loss power path protection with circuit breaker, undervoltage, and overvoltage protection functionality.
The wide input supply of 3 V to 65 V allows protection and control of 12-V and 24-V automotive battery powered
ECUs. The device can withstand and protect the loads from negative supply voltages down to –65 V. An
integrated ideal diode controller (DGATE) drives the first MOSFET to replace a Schottky diode for reverse input
protection and output voltage holdup. With a second MOSFET in the power path the device allows load
disconnect (ON/OFF control) and overvoltage protection using HGATE control. The device features an
adjustable overvoltage cut-off protection feature. With common drain configuration of the power MOSFETs, the
mid-point can be utilized for OR-ing designs using another ideal diode. The LM749x0-Q1 has a maximum
voltage rating of 65 V.
The device has accurate current sensing output (IMON) with typical accuracy of (±10%) enabling systems for
energy management. It has integrated two level overcurrent protection with circuit breaker functionality (TMR)
and fault (FLT) output with complete adjustability of thresholds and response time. Auto-retry and latch-off fault
behavior can be configured.
The device offers adjustable overvoltage and undervoltage protection, providing robust load disconnect in case
of voltage transient events.
LM749x0-Q1 features two different low power modes based on status of EN and SLEEP pin. In SLEEP mode
(SLEEP = Low, EN = High) the device consumes only 6-μA current by turning off both the external MOSFET
gate drives and internal charge pump but at the same time providing internal bypass path to power up always
ON loads with limited current capacity. With the enable pin low, device enters into ultra-low-power mode by
completely cutting off loads with typical current consumption of 2.87 μA. The high voltage rating of LM749x0-Q1
helps to simplify the system designs for automotive ISO7637 protection. The LM749x0-Q1 is also suitable for
ORing and priority power MUX applications.
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9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Charge Pump
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between CAP and VS pins to provide energy to turn on the external MOSFET. In order
for the charge pump to supply current to the external capacitor, the EN and SLEEP pin voltage must be above
the specified input high threshold. When enabled the charge pump sources a charging current of 2.7-mA typical.
If EN and SLEEP pin is pulled low, then the charge pump remains disabled. To ensure that the external
MOSFET can be driven above its specified threshold voltage, the CAP to VS voltage must be above the
undervoltage lockout threshold, typically 6.6 V, before the internal gate driver is enabled. Use 方程式 1 to
calculate the initial gate driver enable delay.
C
(CAP) × V(CAP_UVLOR)
2.7 mA
T
(DRV_EN) = 175 µs +
(1)
where
• C(CAP) is the charge pump capacitance connected across VS and CAP pins
• V(CAP_UVLOR) = 6.6 V (typical)
To remove any chatter on the gate drive approximately 1 V of hysteresis is added to the VCAP undervoltage
lockout. The charge pump remains enabled until the CAP to VS voltage reaches 13.2 V, typically, at which point
the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until
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the CAP to VS voltage is below to 12.2 V typically at which point the charge pump is enabled. The voltage
between CAP and VS continue to charge and discharge between 12.2 V and 13.2 V as shown in 图 9-1. By
enabling and disabling the charge pump, the operating quiescent current of the LM749x0-Q1 is reduced. When
the charge pump is disabled it sinks 15 µA.
TON
TDRV_EN
TOFF
VIN
VA=Vs
0V
VEN/UVLO
13.2 V
12.2 V
VCAP-VS
6.6 V
V(VCAP UVLOR)
GATE DRIVER
ENABLE
图9-1. Charge Pump Operation
9.3.2 Dual Gate Control (DGATE, HGATE)
The LM749x0-Q1 features two separate gate control and driver outputs i.e DGATE and HGATE to drive back to
back N-channel MOSFETs.
9.3.2.1 Reverse Battery Protection (A, C, DGATE)
A, C, DGATE comprises of Ideal Diode stage. Connect the Source of the external MOSFET to A, Drain to C and
Gate to DGATE. The LM749x0-Q1 has integrated reverse input protection down to –65 V.
Before the DGATE driver is enabled, following conditions must be achieved:
• The EN and SLEEP pin voltage must be greater than the specified input high voltage.
• The CAP to VS voltage must be greater than the undervoltage lockout voltage.
• Voltage at A pin must be greater than VA POR Rising threshold.
• Voltage at VS pin must be greater than Vs POR Rising threshold.
If the above conditions are not achieved, then the DGATE pin is internally connected to the A pin, assuring that
the external MOSFET is disabled.
In LM749x0-Q1 the voltage drop across the MOSFET is continuously monitored between the A and C pins, and
the DGATE to A voltage is adjusted as needed to regulate the forward voltage drop at 10.5 mV (typ). This closed
loop regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures
zero DC reverse current flow. This scheme ensures robust performance during slow input voltage ramp down
tests. Along with the linear regulation amplifier scheme, the LM749x0-Q1 also integrates a fast reverse voltage
comparator. When the voltage drop across A and C reaches V(AC_REV) threshold then the DGATE goes low
within 0.5-µs (typ). This fast reverse voltage comparator scheme ensures robust performance during fast input
voltage ramp down tests such as input micro-shorts. The external MOSFET is turned ON back when the voltage
across A and C hits V(AC_FWD) threshold within 2.8 µs (typ).
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In LM749x0-Q1, reverse current blocking is by fast reverse voltage comparator only. When the voltage drop
across A and C reaches V(AC_REV) threshold then the DGATE goes low within 0.5 µs (typ). This fast reverse
voltage comparator scheme ensures robust performance during fast input voltage ramp down tests such as input
micro-shorts. The external MOSFET is turned ON back when the voltage across A and C hits V(AC_FWD)
threshold within 2.8 µs (typ).
9.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
HGATE and OUT comprises of Load disconnect switch control stage. Connect the Source of the external
MOSFET to OUT and Gate to HGATE.
Before the HGATE driver is enabled, following conditions must be achieved:
• The EN and SLEEP pin voltage must be greater than the specified input high voltage.
• The CAP to VS voltage must be greater than the undervoltage lockout voltage.
• Voltage at VS pin must be greater than Vs POR Rising thershold.
If the above conditions are not achieved, then the HGATE pin is internally connected to the OUT pin, assuring
that the external MOSFET is disabled.
For Inrush Current limiting, connect CdVdT capacitor and R1 as shown in 图9-2.
Q1
RG
Cdvdt
HGATE
OUT
LM749x0-Q1
图9-2. Inrush Current Limiting
The CdVdT capacitor is required for slowing down the HGATE voltage ramp during power up for inrush current
limiting. Use 方程式2 to calculate CdVdT capacitance value .
I(HGATE_DRV)
C
(dVdT) = COUT ×
IINRUSH
(2)
where IHATE_DRV is 55 μA (typ), IINRUSH is the inrush current and COUT is the output load capacitance. An extra
resistor, R1, in series with the CdVdT capacitor improves the turn off time.
9.3.3 Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
LM749x0 has two level overcurrent protection. The device senses the voltage across the external current sense
resistor through CS+ and CS–.
9.3.3.1 Pulse Overload Protection, Circuit Breaker
LM749x0-Q1 provides programmable overcurrent threshold setting by means of resistor (RLIM) connected from
ILIM pin to GND.
12 × RSET
R(ILIM)
=
R
SENSE × ILIM
(3)
where
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• RSET is the resistor connected across CS+ and VS
• RSNS is the current sense resistor
• ILIM is the overcurrent level
The CTMR programs the circuit breaker and auto-retry time. Once the voltage across CS+ and CS–exceeds the
set point, the CTMR starts charging with 85-µA pull up current. Once the CTMR charges to VTMR_FLT, FLT asserts
low providing warning on impending FET turn OFF. Once CTMR charges to VTMR_OC, HGATE is pulled to OUT
turning OFF the HFET. After this event, the auto-retry behavior starts. The CTMR capacitor starts discharging with
2.7-µA pull down current. Once the voltage reaches VTMR_Low level, the capacitor starts charging with 2.7-µA
pull up. After 32 charging/discharging cycles of CTMR, the FET turns ON and FLT de-asserts after de-assertion
delay.
CTMR
T
(OC) = 1.2 ×
82.3 µA
(4)
where
• TOC is the delay to turn OFF the FET
• CTMR is the capacitance across TMR to GND
The auto-retry time can be computed as
T
RETRY = 22.7 × 106 × CTMR
(5)
If the overcurrent pulse duration is below TOC then the FET remains ON and CTMR gets discharged using internal
pull down switch.
When not used, ILIM is connected to ground while TMR can be left floating.
VINT
85 µA / 5.4 µA
TMR
2.7 µA
LM749x0-Q1
图9-3. LM749x0 Auto Retry TIMER Functionality
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ILIM
I_LOAD
TPULSE
0-A
TOC = TCB
VTMR_OC
VTMR_FLT
VTMR_Low
VTMR
FLT
1st
2nd
32nd
Vcc
0 V
TLIM
TFLT = 0.9xTCB
12 V
0 V
HGATE-
OUT
图9-4. Overcurrent Protection With Auto Retry Timing Diagram
If the overcurrent pulse duration is below TOC then the HFET remains ON and CTMR gets discharged using
internal pull down switch.
9.3.3.2 Overcurrent Protection With Latch-Off
With about a 100-kΩ resistor across CTMR as shown in figure, overcurrent latch-off functionality can be achieved.
With this resistor, during the charging cycle the voltage across CTMR gets clamped to a level below VTMR_OC
resulting in a latch-off behavior.
VINT
85 µA / 5.4 µA
TMR
2.7 µA
100 kΩ
LM749x0-Q1
图9-5. LM749x0 Overcurrent Protection With Latch
Toggle EN (below ENF) or power cycle Vs below VSPORF to reset the latch. At low edge, the timer counter is
reset and CTMR is discharged.
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ILIM
I_LOAD
TPULSE
0 A
TOC = TCB
VTMR_OC
The resistor across TMR to GND prevents the VTMR to charge to upper threshold and the
counter does not see next counts, resulting in FET to stay latch OFF
VTMR_FLT
VTMR_Low
VTMR
FLT
1st
Vcc
0 V
TLIM
TFLT = 0.9xTCB
12 V
0 V
HGATE-
OUT
When EN is pulled low, the timer counter is reset
and TMR cap is discharged
EN
Starts a fresh turn ON cycle
图9-6. Overcurrent Protection With Latch Timing Diagram
9.3.3.3 Short Circuit Protection (ISCP)
LM749x0-Q1 offers fast response to any short circuit events with the short circuit protection feature. Once the
voltage across CS+ and CS– exceeds the ISCP set point of 20-mV typical (default threshold), HGATE is pulled
to OUT within 5 µs protecting the HFET. FLT asserts low at the same time. Subsequent to this event, the charge/
discharge cycles of CTMR starts similar to the behavior post FET OFF event in circuit breaker operation.
Short circuit protection threshold can be increased using an external series resistor (RISCP) from ISCP pin to
common drain point. The shift in the short circuit protection threshold can be calculated using 方程式6.
V
SNS_SCP = (10.5 µA × RISCP) + 20 mV
(6)
An additional deglitch filter consisting of RSCP and CSCP can be added from ISCP pin to CS–pin as shown in 图
9-7 to avoid any false short circuit trigger in case of fast automotive transients such as Input Micro cuts (LV124,
E-10), AC superimpose (LV124, E-06), ISO7637-2 Pulse 2A.
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Q2
RSENSE
VOUT
RISCP
RSET
CSET
COUT
CISCP
ISCP
C
CS-
VS
CS+
HGATE
OUT
10.5µA
+
–
+20mV
LM749x0-Q1
图9-7. Short Circuit Protection With Deglitch Filter
Latch off can also achieved in the similar way as explained in the circuit breaker section.
9.3.3.4 Analog Current Monitor Output (IMON)
LM749x0 features analog load current monitor output (IMON) with adjustable gain. The resistor connected from
IMON pin to ground sets the current monitor output voltage given by 方程式7.
0.9 × VSENSE × RIMON
VIMON
=
RSET
(7)
RSNS
VIN
RISCP
ISCP
RSET
50
CS+
CS-
10.5 µA
+
CS-
–
To OCP Logic
VREF
–
+
LM749x0-Q1
ILIM
RLIM
IMON
RIMON
图9-8. Analog Current Monitoring
9.3.4 Undervoltage Protection, Overvoltage Protection, and Battery Voltage Sensing (UVLO, OV, SW)
Connect a resistor ladder as shown in 图9-9 for overvoltage threshold programming.
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VIN
A
EN / SLEEP
SW
R1
R2
R3
UVLO
OV
+
UVLOb
0.6 V
0.55 V
+
OVP
0.6 V
0.55 V
LM749x0-Q1
图9-9. Programming Overvoltage Threshold and Battery Sensing
A disconnect switch is integrated between A and SW pins. This switch is turned OFF when EN or SLEEP pin is
pulled low. This helps to reduce the leakage current through the resistor divider network during system shutdown
state (IGN_OFF state).
When undervoltage functionality is not required then it is recommended to connect UVLO pin to EN or VS. It is
recommended to connect OV pin to ground when overvoltage protection feature is not used.
9.3.5 Low IQ SLEEP Mode (SLEEP)
LM749x0-Q1 supports low IQ SLEEP mode operation. This mode can be enabled by pulling SLEEP pin low (EN
= High). In SLEEP mode, device turns off internal charge pump, SW switch and disables DGATE and HGATE
drive thus achieving low current consumption of 6-μA typical. However at the same time device power up
always on loads connected on OUT pin through an internal low power MOSFET with typical on resistance of 7
Ω. In this mode device can support peak load current of 100 mA. As load is increased, voltage drop across
internal MOSFET increases. Device offers overcurrent protection during sleep mode with typical overcurrent
threshold of 250 mA. In case of overcurrent event during sleep mode, device protects internal FET by
disconnecting the internal MOSFET switch and latching off the device. As an additional layer of protection,
device also features thermal shutdown with latch off feature in SLEEP mode in case of any overheating of the
device in SLEEP mode. To put the device out of the latch mode user has to toggle the SLEEP or EN pin.
In SLEEP mode LM749x0-Q1 offers protection against input overvoltage events. Device can be configured in
either overvoltage cut-off (SLEEP_OV connected to C) or overvoltage clamp mode (SLEEP_OV connected to
VOUT) with default overvoltage threshold of 21-V typical.
If SLEEP mode feature is not required then SLEEP pin should be tied to EN. When not used SLEEP_OV pin can
be left floating.
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Q2
Q1
VOUT
RSENSE
VBATT
COUT
VS
C
HGATE
OUT
DGATE
CAP
A
SLEEP Switch
FLT
EN
SLEEP
mode
control logic
UVLO
EN = High
ON
OFF
ON
SLEEP = Low
SLEEP
OFF
LM749x0-Q1
图9-10. LM749x0-Q1 SLEEP Mode Operation
A higher overvoltage threshold for SLEEP mode can be achieved by adding an external Zener diode between
SLEEP_OV pin to OUT/C as shown in 图 9-11. This feature is useful while configuring overvoltage threshold for
24-V or 48-V powered systems.
Q2
Q1
VOUT
RSENSE
VBATT
COUT
C
VS
HGATE
OUT
DGATE
CAP
A
Vz
“C” (OV cutoff)
SLEEP_OV
VOUT (OV clamp)
SLEEP
mode
control logic
ON
SLEEP
EN
OFF
ON
OFF
LM749x0-Q1
图9-11. Increasing SLEEP_OV Threshold Using an External Zener Diode
9.3.6 Ultra Low IQ Shutdown (EN)
The enable pin allows for the gate driver to be either enabled or disabled by an external signal. If the EN pin
voltage is greater than the rising threshold, the gate driver and charge pump operates as described in Charge
Pump. If EN pin voltage is less than the input low threshold, V(ENF), the charge pump and both the gate drivers
(DGATE and HGATE) are disabled placing the LM749x0-Q1 in shutdown mode with ultra-low-current
consumption of 3 μA. The EN pin can withstand a maximum voltage of 65 V. For always ON operation, connect
EN pin to VS.
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10 Applications and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
LM749x0-Q1 controls two N-channel power MOSFETs with DGATE used to control diode MOSFET to emulate
an ideal diode and HGATE controlling second MOSFET for power path cut-off when disabled or during an
overcurrent, overvoltage, undervoltage events. HGATE controlled MOSFET can be used to clamp the output
during overvoltage or load dump conditions. LM749x0-Q1 can be placed into low quiescent current mode using
EN or SLEEP, where both DGATE and HGATE are turned OFF.
The device has a separate supply input pin (VS). The charge pump is derived from this supply input. With the
separate supply input provision and separate GATE control architecture, the LM749x0-Q1 device drives back to
back connected MOSFET in common drain topology thus enabling various system architectures such as power
supply ORing and Power supply priority MUX applications. With these various topologies, the system designers
can design the front-end power system to meet various system design requirements.
10.2 Typical 12-V Reverse Battery Protection Application
A typical application circuit of LM749x0-Q1 configured in common-drain topology to provide reverse battery
protection with overvoltage protection is shown in 图10-1.
RSENSE
1 m
Q1
Q2
VBATT
VOUT
RG
RSET
RISCP
CVS
0.1µF
COUT
100 µF
CIN
0.1µF
CCS+
10 nF
Cdvdt
CCAP
SMBJ33CA
0.1µF
CISCP
10 nF
ISCP
VS
CAP
C
DGATE
CS+
CS-
HGATE
OUT
A
SW
SLEEP_OV
R1
100 k
RFLT
10 k
VVCC_MCU
UVLO
OV
LM74900-Q1
FLT
EN
R2
11.5 k
CUV
0.1 µF
R3
100 k
ON
OFF
ON
R4
1.65 k
TMR
IMON
SLEEP
ILIM
GND
OFF
CT
10 nF
RMON
30 k
RLIM
60 k
图10-1. Typical Application Circuit - 12-V Reverse Battery Protection and Overcurrent, Overvoltage
Protection
10.2.1 Design Requirements for 12-V Battery Protection
The system design requirements are listed in 表10-1.
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表10-1. Design Parameters - 12-V Reverse Battery Protection and Overvoltage Protection
DESIGN PARAMETER
EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V Cold Crank and 35-V Load
Dump
Operating Input Voltage Range
Output Power
Output Current Range
Input Capacitance
50 W
4-A Nominal, 5-A maximum
0.1-µF minimum
0.1-µF minimum, (optional 100 µF for E-10 functional class A
performance)
Output Capacitance
Short circuit current limit
20-A
Overcurrent limit
Overvoltage Cut-off
10-A
37.0 V, output cut-off > 37.0 V
ISO 7637-2, ISO 16750-2 and LV124
Automotive Transient Immunity Compliance
10.2.2 Automotive Reverse Battery Protection
The LM749x0-Q1 feature two separate gate control and driver outputs i.e DGATE and HGATE to drive back to
back N-channel MOSFETs. This enables LM749x0-Q1 to provide comprehensive immunity with robust system
protection during various automotive transient tests as per ISO 7637-2 and ISO 16750-2 standard as well as
other automotive OEM standards. For more information, see the Automotive EMC-compliant reverse-battery
protection with ideal-diode controllers article.
LM749x0-Q1 gate drive output DGATE controls MOSFET Q1 to provide reverse battery protection and true
reverse current blocking functionality. HGATE controls MOSFET Q2 to turn off the power path during input
overvoltage condition. Resistor network R1, R2 and R3, R4 connected from SW pin to ground can be configured
for undervoltage and overvoltage protection. Bi-directional TVS D1 clamps the automotive transient input
voltages on the 12-V battery, both positive and negative transients, to voltage levels safe for MOSFET Q1 and
LM749x0-Q1.
Fast reverse current blocking response and quick reverse recovery enables LM749x0-Q1 to turn ON/OFF
MOSFET Q1 during AC super imposed input specified by ISO 16750-2 and LV124 E-06 and provide active
rectification of the AC input superimposed on DC battery voltage. Fast reverse current blocking response of
LM749x0-Q1 helps to turn off MOSFET Q1 during negative transients inputs such as –150-V 2-ms Pulse 1
specified in ISO 7637-2 and input micro short conditions such as LV124 E-10 test.
10.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
ISO 7637-2 Pulse 1 specifies negative transient immunity of electronic modules connected in parallel with an
inductive load when the battery is disconnected. A typical pulse 1 specified in ISO 7637-2 starts with battery
disconnection where supply voltage collapses to 0 V followed by –150 V 2 ms applied with a source impedance
of 10 Ω at a slew rate of 1 µs on the supply input. LM749x0-Q1 blocks reverse current and prevents the output
voltage from swinging negative, protecting the rest of the electronic circuits from damage due to negative
transient voltage. MOSFET Q1 is quickly turned off within 0.5 µs by fast reverse comparator of LM749x0-Q1. A
single bi-directional TVS is required at the input to clamp the negative transient pulse within the operating
maximum voltage across cathode to anode of 85 V and does not violate the MOSFET Q1 drain-source
breakdown voltage rating.
ISO 7637-2 Pulse 1 performance of LM749x0-Q1 is shown in 图10-2.
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图10-2. ISO 7637-2 Pulse 1
10.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
Alternators are used to power the automotive electrical system and charge the battery during normal runtime of
the vehicle. Rectified alternator output contains residual AC ripple voltage superimposed on the DC battery
voltage due to various reasons which includes engine speed variation, regulator duty cycle with field switching
ON/OFF and electrical load variations. On a 12-V battery supply, alternator output voltage is regulated by a
voltage regulator between 14.5 V to 12.5 V by controlling the field current of alternator's rotor. All electronic
modules are tested for proper operation with superimposed AC ripple on the DC battery voltage. AC super
imposed test specified in ISO 16750-2 and LV124 E-06 requires AC ripple of 2-V Peak-Peak on a 13.5-V DC
battery voltage, swept from 15 Hz to 30 kHz. LM74900-Q1 rectifies the AC superimposed voltage by turning the
MOSFET Q1 OFF quickly to cut-off reverse current and turning the MOSFET Q1 ON quickly during forward
conduction. Active rectification of 2-V peak-peak 30-kHz AC input by LM749x0-Q1 is shown in Figure 10-3.
LM74910-Q1 has higher DGATE strength and is capable of achieving active rectification at AC superimpose
frequency of 200-kHz as shown in 图 10-4. Fast turn off and quick turn ON of the MOSFET reduces power
dissipation in the MOSFET Q1 and active rectification reduces power dissipation in the output hold-up
capacitor's ESR by half.
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图10-3. AC Super Imposed Test - 2-V Peak-Peak 30 kHz
图10-4. AC Super Imposed Test - 2-V Peak-Peak 200 kHz (LM74910-Q1)
10.2.2.3 Input Micro-Short Protection: LV124 E-10
E-10 test specified in LV124 standard checks for immunity of electronic modules to short interruptions in power
supply input due to contact issues or relay bounce. During this test (case 2), micro-short is applied on the input
for a duration as low as 10 µs to several ms. For a functional pass status A, electronic modules are required to
run uninterrupted during the E-10 test (case 2) with 100-µs duration. Dual-Gate drive architecture of LM749x0-
Q1 - DGATE and HGATE - enables to achieve a functional pass status A with optimum hold up capacitance on
the output when compared to a single gate drive controller. When input micro-short is applied for 100 µs,
LM749x0-Q1 quickly turns off MOSFET Q1 by shorting DGATE to ANODE (source of MOSFET) within 0.5µs to
prevent the output from discharging and the HGATE remains ON keeping MOSFET Q2 ON, enabling fast
recovery after the input short is removed.
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Performance of LM749x0-Q1 during E10 input power supply interruption test case 2 is shown in Figure 10-4.
After the input short is removed, input voltage recovers and VAC voltage crosses forward turn on threshold
(VAC_FWD), MOSFET Q1 is turned back ON quickly. Note that dual-gate drive topology allows MOSFET Q2 to
remain ON during the test and helps in restoring the input power faster. Output voltage remains unperturbed
during the entire duration, achieving functional status A.
图10-5. Input Micro-Short - LV124 E10 TC 2 100 µs
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10.2.3 Detailed Design Procedure
10.2.3.1 Design Considerations
表 10-1 summarizes the design parameters that must be known for designing an automotive reverse battery
protection circuit with overvoltage cut-off. During power up, inrush current through MOSFET Q2 needs to be
limited so that the MOSFET operates well within its SOA. Maximum load current, maximum ambient temperature
and thermal properties of the PCB determine the RDSON of the MOSFET Q2 and maximum operating voltage
determines the voltage rating of the MOSFET Q2. Selection of MOSFET Q1 is determined mainly by the
maximum operating load current, maximum ambient temperature, maximum frequency of AC super imposed
voltage ripple and ISO 7637-2 pulse 1 requirements. overvoltage threshold is decided based on the rating of
downstream DC/DC converter or other components after the reverse battery protection circuit. A single bi-
directional TVS or two back-back uni-directional TVS are required to clamp input transients to a safe operating
level for the MOSFETs Q1, Q2 and LM749x0-Q1.
10.2.3.2 Charge Pump Capacitance VCAP
Minimum required capacitance for charge pump VCAP is based on input capacitance of the MOSFET Q1,
CISS(MOSFET_Q1)and input capacitance of Q2 CISS(MOSFET)
.
Charge Pump VCAP: Minimum 0.1 µF is required; recommended value of VCAP (µF) ≥ 10 x ( CISS(MOSFET_Q1)
+ CISS(MOSFET_Q2) ) (µF)
10.2.3.3 Input and Output Capacitance
A minimum input capacitance CIN of 0.1 µF and output capacitance COUT of 0.1 µF is recommended.
10.2.3.4 Hold-Up Capacitance
Usually bulk capacitors are placed on the output due to various reasons such as uninterrupted operation during
power interruption or micro-short at the input, hold-up requirements for doing a memory dump before turning of
the module and filtering requirements as well. This design considers minimum bulk capacitors requirements for
meeting functional status "A" during LV124 E10 test case 2 100-µs input interruption. To achieve functional pass
status A, acceptable voltage droop in the output of LM74900-Q1 is based on the UVLO settings of downstream
DC-DC converters. For this design, drop from 12-V to 6.5V in output voltage for 100 µs is considered (assuming
downstram converter with 5-V output) and the minimum hold-up capacitance required is calculated by
I
LOAD × 100 µs
VOUT
CHOLD_UP_MIN
=
(8)
Minimum hold-up capacitance required for 5.5-V drop in 100 µs is 100 µF. Note that the typical application circuit
shows the hold-up capacitor as optional because not all designs require hold-up capacitance.
10.2.3.5 Selection of Current Sense Resistor, RSNS
LM749x0-Q1 has integrated short circuit detection comparator with deafult sense threshold of 20-mV. For this
application, short circuit limit is set to 20-A. The sense resistor value based on short circuit comparator can be
calculated by 方程式9.
VSENSE
RSENSE
=
ISCP
(9)
Select a 1-mΩ with 1% tolerance to set short circuit protection limit of 20-A.
10.2.3.6 Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP
)
RSET is the resistor connected between VS and CS+ pins. This resistor scales the overcurrent protection
threshold voltage and coordinates with RILIM and RIMON to determine the overcurrent protection threshold and
current monitoring output. The recommended range of RSET is 50 Ω–100 Ω. RSET is selected as 50 Ω, 1% for
this design example.
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LM749x0-Q1 default short circuit threshold of 20-mV can be shifted to higher value as given by 方程式10.
SNS_SCP = (10.5 µA × RISCP) + 20 mV
V
(10)
For this application, ISCP pin is shorted directly to common drain point. User has a flexibility to populate suitable
value of RSCP resistor to adjust short circuit protection current limit and also gives flexibility in terms of selecting
different current sense resistor value.
An additional de-glitch filter (optional) consisting of RSCP and CSCP can be added from ISCP pin to CS- pin as
shown in 图 10-1 to avoid any false short circuit trigger in case of fast automotive transients such as Input Micro
cuts (LV124, E-10), AC superimpose (LV124, E-06), ISO7637-2 Pulse 2A.
10.2.3.7 Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON)
Selection
Programming the Overcurrent Protection Threshold –RILIM Selection
The RILIM sets the overcurrent protection (circuit breaker detection) threshold, whose value can be calculated
using 方程式11.
12 × RSET
R(ILIM)
=
R
SENSE × ILIM
(11)
To set 10 A as overcurrent protection threshold, RILIM value is calculated to be 60 kΩ. Choose the closest
available standard value: 60 kΩ, 1%.
Programming the Circuit Breaker Time –CTMR Selection
For the design example under discussion, overcurrent transients are allowed for 1-ms duration. This blanking
interval, TOC (or circuit breaker interval, TCB) can be set by selecting appropriate capacitor CTMR from TMR pin to
ground. The value of CTMR to set 1 ms for TOC can be calculated using 方程式12.
CTMR
T
(OC) = 1.2 ×
82.3 µA
(12)
Choose closest available standard value: 68 nF, 10%.
Programming Current Monitoring Output –RIMON Selection
Voltage at IMON pin VIMON is proportional to the output load current. This can be connected to an ADC of the
downstream system for monitoring the operating condition and health of the system. The RIMON must be
selected based on the maximum load current and the input voltage range of the ADC used. RIMON is set using 方
程式13.
0.9 × VSENSE × RIMON
VIMON
=
RSET
(13)
For this application example, VIMON is selected to be 2.7 V at full load current of 5 A. RIMON value of 30.1 kΩ,
1% is selected.
10.2.3.8 Overvoltage Protection and Battery Monitor
Resistors R1, R2 and R3, R4 connected from SW pin to ground is used to program the undervoltage and
overvoltage threshold. The resistor values required for setting the undervoltage threshold (VUVLO to 5.5 V) and
overvoltage threshold (VOV to 37.0 V) a are calculated by solving
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R2 × VUVSET
VUVLOF
=
(R1 + R2)
(14)
(15)
R4 × VOVSET
(R3 + R4)
VOVR
=
For minimizing the input current drawn from the battery through resistors R1, R2 and R3, it is recommended to
use higher value of resistance. Using high value resistors will add error in the calculations because the current
through the resistors at higher value will become comparable to the leakage current into the OV pin. Maximum
leakage current into the OV pin is 1 µA and choosing total ladder resistor < 120 kΩ ensures current through
resistors is 100 times greater than leakage through OV pin.
Based on the device electrical characteristics, VUVLOF is 0.55 V. Select R1 = 100 kΩ. Solving Equation 14 gives
R2 = 11.5 kΩ. Solving Equation 15 with R3 selected as 100 kΩ and VOVR = 0.6V gives R4 = 1.65 kΩ as
standard 1% resistor values closest to the calculated resistor values.
An optional capacitor CUV can be placed in parallel with R2 on UVLO resistor ladder in order to filter out any fast
undervoltage transients on battery lines to avoid false UVLO trigger.
For this application example separate resistor ladder is selected to program overvoltage and undervoltage
threshold. However common resistor ladder from SW pin to ground can also be used as shown in 图9-9.
10.2.4 MOSFET Selection: Blocking MOSFET Q1
For selecting the blocking MOSFET Q1, important electrical parameters are the maximum continuous drain
current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), the
maximum source current through body diode and the drain-to-source ON resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. This would include all the automotive transient events and any anticipated fault
conditions. It is recommended to use MOSFETs with VDS voltage rating of 60 V along with a single bidirectional
TVS or a VDS rating 40-V maximum rating along with two unidirectional TVS connected back-back at the input.
The maximum VGS LM74900-Q1 can drive is 14 V, so a MOSFET with 15-V minimum VGS rating should be
selected. If a MOSFET with < 15-V VGS rating is selected, a zener diode can be used to clamp VGS to safe level,
but this would result in increased IQ current.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred, but selecting a MOSFET based
on low RDS(ON) may not be beneficial always. Higher RDS(ON) will provide increased voltage information to
LM74900-Q1's reverse comparator at a lower reverse current. Reverse current detection is better with increased
RDS(ON). Choosing a MOSFET with < 50-mV forward voltage drop at maximum current is a good starting point.
For active rectification of AC super imposed ripple on the battery supply voltage, gate-source charge QGS of Q1
must be selected to meet the required AC ripple frequency. Maximum gate-source charge QGS (at 4.5-V VGS) for
active rectification every cycle is
1.3mA
QGS_MAX
=
FAC_RIPPLE
(16)
Where 1.3 mA is minimum charge pump current at 7-V VDGATE-VA, FAC_RIPPLE is frequency of the AC ripple
superimposed on the battery and QGS_MAX is the QGS value specified in manufacturer datasheet at 6-V VGS. For
active rectification at FAC_RIPPLE = 30 KHz, QGS_MAX = 43 nC.
Based on the design requirements, BUK7Y4R8-60E MOSFET is selected and its ratings are:
• 60-V VDS(MAX) and ±20-V VGS(MAX)
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• RDS(ON) 5.0-mΩtypical at 5-V VGS and 2.9-mΩrated at 10-V VGS
• MOSFET QGS 17.4 nC
Thermal resistance of the MOSFET should be considered against the expected maximum power dissipation in
the MOSFET to ensure that the junction temperature (TJ) is well controlled.
10.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
The VDS rating of the MOSFET Q2 should be sufficient to handle the maximum system voltage along with the
input transient voltage. For this 12-V design, transient overvoltage events are during suppressed load dump 35
V 400 ms and ISO 7637-2 pulse 2 A 50 V for 50 µs. Further, ISO 7637-2 Pulse 3B is a very fast repetitive pulse
of 100 V 100 ns that is usually absorbed by the input and output ceramic capacitors and the maximum voltage
on the 12-V battery can be limited to < 40 V the minimum recommended input capacitance of 0.1 µF. The 50-V
ISO 7637-2 Pulse 2 A can also be absorbed by input and output capacitors and its amplitude could be reduced
to 40-V peak by placing sufficient amount of capacitance at input and output. However for this 12-V design,
maximum system voltage is 50 V and a 60-V VDS rated MOSFET is selected.
The VGS rating of the MOSFET Q2 should be higher than that maximum HGATE-OUT voltage 15 V.
Inrush current through the MOSFET during input hot-plug into the 12-V battery is determined by output
capacitance. External capacitor on HGATE, CDVDT is used to limit the inrush current during input hot-plug or
start-up. The value of inrush current determined by 方程式2 need to be selected to ensure that the MOSFET Q2
is operating well within its safe operating area (SOA). To limit inrush current to 0.5 A, CDVDT value of 10.0 nF is
chosen.
Duration of inrush current is calculated by 方程式17.
VIN × COUT
TINRUSH
=
IINRUSH
(17)
Calculated inrush current duration is 2.5 ms with 0.5-A inrush current.
MOSFET BUK7Y4R8-60E having 60-V VDS and ±20-V VGS rating is selected for Q2. Power dissipation during
inrush is well within the MOSFET's safe operating area (SOA).
10.2.6 TVS Selection
A 600-W SMBJ TVS such as SMBJ33CA is recommended for input transient clamping and protection. For
detailed explanation on TVS selection for 12-V battery systems, refer to TVS Selection for 12-V Battery Systems.
10.2.7 Application Curves
图10-6. Start-Up 12 V With EN Pulled to VS
图10-7. Start-Up 12 V With EN Going Low to High
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ZHCSO86A –DECEMBER 2022 –REVISED JUNE 2023
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图10-9. Inrush Current With No Load at Output
图10-8. Reverse Input Voltage –14 V
图10-11. Device Start-Up With Output Short Circuit
图10-10. Output Short Circuit Protection (On-The-
(TIMER Duration 1 ms)
Fly)
图10-13. Output Overcurrent Protection (TIMER
图10-12. Output Overcurrent Protection (TIMER
Duration 1 ms): Auto Retry
Duration 1 ms)
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图10-14. Overvoltage Protection
图10-15. Overvoltage Recovery
图10-17. Undervoltage Lockout (UVLO) Protection
图10-16. Overvoltage Clamp Response (OV
(VIN_UVLO = 5.5 V)
Resistor Ladder Referred to VOUT)
图10-18. Undervoltage Lockout (UVLO) Recovery
图10-19. SLEEP Mode Entry (SLEEP = Low, EN =
High)
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图10-21. SLEEP Mode Exit (SLEEP = High, EN =
图10-20. SLEEP Mode Overcurrent Protection (250
High)
mA Typical)
图10-22. Load Transient 100 mA to 5 A
10.3 Addressing Automotive Input Reverse Battery Protection Topologies With LM749x0-Q1
The LM749x0-Q1 dual gate drive architecture can address various MOSFET control topologies such as ideal
diode FET only, high-side switch controller only, dual OR-ing with load disconnect, and priority power muxing.
This enables system designers to use LM749x0-Q1 as a plug and place component to meet various automotive
front end protection solutions with a common controller. For additional details on overview of different automotive
reverse battery protection topologies that can be addressed using LM749x0-Q1, refer to Addressing Automotive
Reverse Battery Protection Toplogies using LM749x0-Q1
10.4 Power Supply Recommendations
10.4.1 Transient Protection
When the external MOSFETs turn OFF during the conditions such as overvoltage cut-off, reverse current
blocking, overcurrent cut-off, EN causing an interruption of the current flow, the input line inductance generates a
positive voltage spike on the input and output inductance generates a negative voltage spike on the output. The
peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output
of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to
address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device.
• Using large PCB GND plane.
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• Use of a Schottky diode across the output and GND to absorb negative spikes.
• A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 8.
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(18)
where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during EMC testing such as
automotive ISO7637 pulses.
RSENSE
Q1
Q2
VBATT
VOUT
RSET
RISCP
COUT
CVS
0.1µF
*
*
CIN
0.1µF
CCAP
0.1µF
ISCP
VS
CAP
C
DGATE
CS+
CS-
HGATE
OUT
A
SW
SLEEP_OV
R1
R4
VEXT
RFLT
UVLO
OV
LM74900/910-Q1
FLT
EN
R3
R4
ON
OFF
ON
TMR
CT
IMON
SLEEP
ILIM
RLIM
GND
OFF
RMON
* Optional Components for Transient Suppression
图10-23. Typical Application Diagram
10.4.2 TVS Selection for 12-V Battery Systems
In selecting the TVS, important specifications are breakdown voltage and clamping voltage. The breakdown
voltage of the TVS for positive transients must be higher than 24-V jump start voltage and 35-V suppressed load
dump voltage and less than the maximum ratings of LM749x0-Q1 (65 V). The breakdown voltage of TVS for
negative transients must be beyond than maximum reverse battery voltage –16 V, so that the TVS– is not
damaged due to long time exposure to reverse connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V
with a generator impedance of 10 Ω. This action translates to 15 A flowing through the TVS–, and the voltage
across the TVS is close to its clamping voltage.
The next criterion is that the absolute maximum rating of cathode to anode voltage of the LM749x0-Q1 (85 V)
and the maximum VDS rating MOSFET are not exceeded. In the design example, 60-V rated MOSFET is
chosen and maximum limit on the cathode to anode voltage is 60 V.
During ISO 7637-2 pulse 1, the anode of LM749x0-Q1 is pulled down by the ISO pulse, clamped by TVS– and
the MOSFET Q1 is turned off quickly to prevent reverse current from discharging the bulk output capacitors.
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When the MOSFET turns off, the cathode to anode voltage seen is equal to (TVS Clamping voltage + Output
capacitor voltage). If the maximum voltage on output capacitor is 16 V (maximum battery voltage), then the
clamping voltage of the TVS–must not exceed, (60 V –16) V = –44 V.
The SMBJ33CA TVS diode can be used for 12-V battery protection application. The breakdown voltage of 36.7
V meets the jump start, load dump requirements on the positive side and 16-V reverse battery connection on the
negative side. During ISO 7637-2 pulse 1 test, the SMBJ33CA clamps at –44 V with 12 A of peak surge current
as shown in and it meets the clamping voltage ≤ 44 V. SMBJ series of TVS' are rated up to 600-W peak pulse
power levels and are sufficient for ISO 7637-2 pulses.
10.5 Layout
10.5.1 Layout Guidelines
• For the ideal diode stage, connect A, DGATE, and C pins of LM749x0-Q1 close to the MOSFET SOURCE,
GATE and, DRAIN pins.
• For the load disconnect stage, connect HGATE and OUT pins of LM749x0-Q1 close to the MOSFET GATE
and SOURCE pins.
• The high current path of for this solution is through the MOSFET, therefore it is important to use thick and
short traces for source and drain of the MOSFET to minimize resistive losses.
• The DGATE pin of the LM749x0-Q1 must be connected to the MOSFET GATE with short trace.
• Place transient suppression components close to LM749x0-Q1.
• Place the decopuling capacitor, CVS close to VS pin and chip GND.
• The charge pump capacitor across CAP and VS pins must be kept away from the MOSFET to lower the
thermal effects on the capacitance value.
S
D
D
D
D
RSENSE
S
Q1
Q2
S
ISCP
G
HGATE
CVCAP
VIN PLANE
CVS
GND
21
VOUT PLANE
24
23
22
20
19
DGATE
A
1
2
3
4
18
17
16
ISCP
NC
SLEEPOV
SW
Exposed
Thermal Pad
R1
UVLO
CIN
15
14
13
OUT
R2
COUT
OV
EN
5
6
HGATE
ON/OFF
Control
GND
7
8
9
10
11
12
RIMON
VFLT
RILIM
SLEEP
CTMR
RFLT
ON/OFF
Control
Signal Via
Bottom Layer
GND PLANE
图10-24. Example Layout
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English Data Sheet: SNOSDE6
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74900QRGERQ1
LM74910QRGERQ1
ACTIVE
VQFN
VQFN
RGE
24
24
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LM
74900Q
Samples
Samples
ACTIVE
RGE
NIPDAU
LM
74910Q
PLM74900QRGERQ1
PLM74910QRGERQ1
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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21-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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21-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM74900QRGERQ1
LM74910QRGERQ1
VQFN
VQFN
RGE
RGE
24
24
3000
3000
330.0
330.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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21-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM74900QRGERQ1
LM74910QRGERQ1
VQFN
VQFN
RGE
RGE
24
24
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024T
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
4.1
3.9
PIN 1 INDEX AREA
(0.1) MIN
(0.13)
A
-
A
2
5
.
0
0
0
SECTION A-A
TYPICAL
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
2.1 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
7
12
A
(0.16) TYP
20X 0.5
6
A
13
2X
SYMM
25
2.5
1
18
0.3
0.2
24X
24
19
0.5
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
24X
0.3
4228214/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024T
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.1)
SYMM
24
19
24X (0.6)
18
1
24X (0.25)
25
SYMM
(3.8)
(0.8)
20X (0.5)
6
13
(
0.2) TYP
VIA
7
12
(0.8)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228214/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGE0024T
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.57)
TYP
24
19
24X (0.6)
25
18
1
24X (0.25)
(0.57)
TYP
SYMM
(3.8)
4X
0.94)
20X (0.5)
(
6
13
EXPOSED METAL
TYP
12
7
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
THERMAL PAD 25:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
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