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LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

LM76002/LM76003 3.5V 至 60V、2.5A/3.5A 同步

降压稳压器

1 特性

2 应用

1

•

集成同步整流

•

电信基础设施

输入电压 3.5V 至 60V（最大值 65V）

资产和机群管理系统

视频监控

输出电流：

可编程逻辑控制器

–

LM76002：2.5A

LM76003：3.5A

3 说明

•

输出电压 1V 至 95% V_IN

稳压静态电流 15µA

宽电压转换范围

LM76002/LM76003 稳压器是一款易于使用的同步降压

直流/直流转换器，能驱动高达 2.5A (LM76002) 或

3.5A (LM76003) 的负载电流，输入电压最高可达

60V。LM76002/LM76003 解决方案尺寸极小，但能提

供优异的效率和输出精度。采用峰值电流模式控制。可

调特性（例如可调开关频率、同步、FPWM 选项、电

源正常状态标志、精密使能端、可调式软启动和跟踪）

可为各种应用提供灵活且简单易用的解决方案。轻负

载时的自动频率折返和可选的外部偏置电源可以提高效

率。该器件需要极少的外部组件，其引脚专为简化

PCB 布局而设计，可提供优异的 EMI (CISPR22) 和热

性能。保护功能包括输入欠压锁定、热关断、逐周期

电流限制和短路保护。LM76002/LM76003 器件采用

WQFN 30 引脚无引线式封装，且具有可湿性侧面。

–

t_ON-MIN= 65ns（典型值）

t_OFF-MIN= 95ns（典型值）

•

系统级特性

–

与外部时钟保持同步

电源正常状态标志

精密使能端

可调软启动（默认为 6.3ms）

电压跟踪功能

•

引脚可选式 FPWM 运行

可调频率范围：300kHz 至 2.2MHz

在轻负载架构下实现高效率 (PFM)

保护功能

器件信息⁽¹⁾

–

逐周期电流限制

器件型号

LM76002

LM76003

封装

封装尺寸（标称值）

具有断续模式的短路保护

过热关断保护

使用 LM76002/LM76003 并借助 WEBENCH^®电源

WQFN (30)

6.00mm × 4.00mm

•

设计器创建定制设计方案

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

空白

简化原理图

效率与输出电流

（V_OUT= 5V，f_SW= 400kHz，自动模式）

BOOT

SW

PVIN

EN

V_IN

100

90

80

70

60

50

40

C_BOOT

C_IN

V_OUT

C_OUT

L

PGND

LM76003

SS/TRK

RT

BIAS

30

R_FBT

V_IN= 8 V

V_IN= 12 V

20

SYNC/MODE

V_IN= 13.5 V

V_IN= 24 V

FB

10

0

VCC

R_FBB

AGND

0.001

0.01

0.1

Load Current (A)

1

5

C_VCC

D034

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAK0

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 24

8.1 Application Information............................................ 24

8.2 Typical Applications ............................................... 24

Power Supply Recommendations...................... 42

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Timing Characteristics............................................... 8

6.7 Switching Characteristics.......................................... 8

6.8 System Characteristics ............................................. 9

6.9 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

8

9

10 Layout................................................................... 42

10.1 Layout Guidelines ................................................. 42

10.2 Layout Example .................................................... 45

10.3 Thermal Design..................................................... 46

11 器件和文档支持 ..................................................... 47

11.1 器件支持................................................................ 47

11.2 接收文档更新通知 ................................................. 47

11.3 支持资源................................................................ 47

11.4 商标....................................................................... 47

11.5 静电放电警告......................................................... 47

11.6 Glossary................................................................ 47

12 机械、封装和可订购信息....................................... 47

7

4 修订历史记录

Changes from Original (October 2018) to Revision A

Page

•

Deleted "Operating" from "Junction temperature row" in Abs Max ...................................................................................... 5

Deleted Operating junction temperature, T_J, from ROC table................................................................................................ 5

Changed 图 17 ..................................................................................................................................................................... 18

Updated Power Good and Overvoltage Protection (PGOOD) section................................................................................. 20

Updated Power Good description......................................................................................................................................... 20

Updated title of component selection table. ......................................................................................................................... 25

2

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

5 Pin Configuration and Functions

RNP Package

30-Pin WQFN

Top View

NC

30

NC

29

28

27

26 PGND

SW

1

2

3

4

5

25

24

23

22

PGND

NC

SW

PVIN

BOOT

21

20

19

18

6

7

DAP

NC

VCC

PVIN

NC

8

BIAS

9

EN

17 SYNC/MODE

16 PGOOD

RT

10

11

SS/TRK

13

14

15

12

FB

AGND AGND AGND

3

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

Switching output of the regulator. Internally connected to source of the HS FET and drain of

the LS FET. Connect to power inductor and boot-strap capacitor.

1, 2, 3, 4, 5

SW

P

Boot-strap capacitor connection for high-side driver. Connect a high-quality 470-nF

capacitor from this pin to the SW pin.

6

BOOT

NC

7, 19, 23, 27,

28, 29, 30

Not internally connected. Connect to ground copper on PCB to improve heat-sinking of the

device and board level reliability.

—

Output of internal bias supply. Used as supply to internal control circuits. Connect a high-

quality 2.2-µF capacitor from this pin to GND. TI does not recommended loading this pin by

external circuitry.

8

VCC

P

Optional BIAS LDO supply input. TI recommends tying this to V_OUTwhen 3.3 V ≤ V_OUT≤ 18

V, or tying to an external 3.3-V or 5-V rail if available, to improve efficiency. When used,

place a 1-µF capacitor from this terminal to ground. Tie to ground when not in use.

9

BIAS

RT

P

A

Switching frequency setting pin. Place a resistor from this pin to ground to set the switching

frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground.

10

Soft-start-control pin. Leave this pin floating to use the 6.3-ms internal soft-start ramp. An

external capacitor can be connected from this pin to ground to extend the soft-start time. A

2-µA current sourced from this pin can charge the capacitor to provide the ramp. Connect

to external ramp for tracking. Do not short to ground.

11

SS/TRK

A

Feedback input for output voltage regulation. Connect a resistor divider to set the output

voltage. Never short this terminal to ground during operation.

12

16

FB

A

Open-drain power-good flag output. Connect to suitable voltage supply through a current

limiting resistor. High = V_OUTregulation OK, Low = V_OUTregulation fault. PGOOD = Low

when EN = Low.

PGOOD

Synchronization input and mode setting pin. Do not float, tie to ground if not used. Tie to

ground: DCM/PFM operation under light loads, improved efficiency; tie to logic high: forced

PWM under light loads, constant switching frequency over load; tie to external clock source:

synchronize switching action to the clock, forced PWM under light loads. Triggers on the

rising edge of external clock.

17

SYNC/MODE

A

Precision-enable input to regulator. Do not float. High = on, Low = off. Can be tied to V_IN

Precision-enable input allows adjustable UVLO by external resistor divider.

.

18

EN

A

Analog ground. Ground reference for internal references and logic. All electrical parameters

are measured with respect to this pin. Connect to system ground on PCB.

13, 14, 15

AGND

G

Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass

capacitors C_IN. C_INmust be placed right next to this pin and PGND and connected with

short traces.

20, 21, 22

24, 25, 26

EP

PVIN

PGND

DAP

P

G

Power ground, connected to the source of LS FET internally. Connect to system ground,

DAP/EP, AGND, ground side of C_INand C_OUT. Path to C_INmust be as short as possible.

Low impedance connection to AGND. Connect to system ground on PCB. Major heat

dissipation path for the die. Must be used for heat sinking by soldering to ground copper on

PCB. Thermal vias are preferred.

—

(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

4

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range of –40°C to +125°C (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

–0.1

–0.3

–3.5

–0.3

–40

MAX

UNIT

PVIN to PGND

EN to AGND

65

V_IN+ 0.3

FB, RT, SS/TRK to AGND

PGOOD to AGND

SYNC to AGND

5

Input voltages

20

V

5.5

BIAS to AGND

Lower of (V_IN+ 0.3) or 30

AGND to PGND

0.3

V_IN+ 0.3

65

SW to PGND

SW to PGND less than 10-ns transients

BOOT to SW

Output voltages

V

5.5

VCC to AGND

5.5

Junction temperature, T_J

Storage temperature, T_stg

150

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended

OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

60

UNIT

PVIN to PGND

3.5

0

EN

V_IN

4.5

18

FB

0

PGOOD

0

Input voltages

V

BIAS input not used

0

0.3

Lower of (V_IN

+

BIAS input used

AGND to PGND

0

0.3) or 24

–0.1

0.1

95% of V_IN

2.5

Output voltage V_OUT

I_OUT, LM76002

I_OUT, LM76003

1

0

V

A

Output current

3.5

(1) Recommended operating rating indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics .

5

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

6.4 Thermal Information

LM76002/LM76003

THERMAL METRIC⁽¹⁾

RNP (WQFN)

UNIT

30 PINS

29.6

17.6

9.1

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

9.0

R_θJC(bot)

1.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (PVIN PINS)

Operating input voltage

range

V_IN

3.5

60

10

12

V

V_EN= 0 V

T_J= 25℃

Shutdown quiescent current;

I_SD

1.2

0.9

µA

measured at PVIN pin⁽¹⁾

Operating quiescent current V_EN= 2 V, V_FB= 1.5 V, V_BIAS= 3.3 V

from V_IN(non-switching)

I_{Q_NONSW}

external

ENABLE (EN PIN)

Enable input high level for

V_CCoutput

V_{EN_VCC_H}

V_{EN_VCC_L}

V_{EN_VOUT_H}

V_ENrising

1.2

V

Enable input low level for

V_CCoutput

V_ENfalling

0.3

Enable input high level for

V_OUT

V_ENrising

1.14

1.204

1.25

200

Enable input hysteresis for

V_OUT

V_{EN_VOUT_HYS}

V_ENfalling hysteresis

–150

1.4

mV

nA

I_{LKG_EN}

Enable input leakage current V_EN= 2 V

INTERNAL LDO (VCC PIN, BIAS PIN)

PWM operation

PFM operation

V_CCrising

3.29

3.1

V

V_CC

Internal V_CCvoltage

2.96

3.14

–565

3.11

–63

3.27

3.25

V

Internal V_CCundervoltage

lockout

V_{CC_UVLO}

V_CCfalling hysteresis

V_BIASrising

mV

V

V_{BIAS_ON}

Input changeover

V_BIASfalling hysteresis

mV

Operating quiescent current

from external V_BIAS(non-

switching)

V_EN= 2 V, V_FB= 1.5 V, V_BIAS= 3.3 V

external

I_{BIAS_NONSW}

21

50

µA

VOLTAGE REFERENCE (FB PIN)

V_FB

Feedback voltage

PWM mode

V_FB= 1 V

0.987

1.006

0.2

1.017

60

V

Input leakage current at FB

I_{LKG_FB}

nA

(1) Shutdown current includes leakage current ofthe switching transistors.

6

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HIGH SIDE DRIVER (BOOT PIN)

BOOT - SW undervoltage

lockout

V_{BOOT_UVLO}

1.6

2.2

2.7

V

CURRENT LIMITS AND HICCUP

LM76002

LM76003

LM76002

LM76003

LM76002

LM76003

3.2

4.35

2.3

4.2

5.5

5.3

6.8

4.2

5.3

Short-circuit, high-side

current limit

(2)

I_{HS_LIMIT}

A

3.2

(2)

I_{LS_LIMIT}

Low-side current limit

Negative current limit

3.4

4.2

–2.5

–3.3

0.42

0.05

I_{NEG_LIMIT}

V_HICCUP

I_{L_ZC}

Hiccup threshold on FB pin

Zero cross-current limit

0.38

1.8

0.46

2.2

V

A

SOFT START (SS/TRK PIN)

I_SSC

Soft-start charge current

2

µA

Soft-start discharge

resistance

R_SSD

UVLO, TSD, OCP; or EN = 0 V

kΩ

POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION

Power-good overvoltage

threshold

V_{PGOOD_OV}

% of FB voltage

106%

86%

110%

113%

93%

Power-good undervoltage

threshold

V_{PGOOD_UV}

% of FB voltage

90%

2.5%

1.3

V_{PGOOD_HYS}

V_{PGOOD_VALID}

Power-good hysteresis

Minimum input voltage for

proper PGOOD function

50-µA pullup to PGOOD pin, V_EN= 0 V,

T_J= 25°C

2

V

V_EN= 2.5 V

V_EN= 0 V

40

30

100

90

R_PGOOD

Power-good on-resistance

Ω

MOSFETS

High-side MOSFET on-

resistance

(3)

R_{DS_ON_HS}

I_OUT= 1 A, V_BIAS= V_OUT= 3.3 V

95

45

150

85

mΩ

Low-side MOSFET on-

resistance

(3)

R_{DS_ON_LS}

THERMAL SHUTDOWN

Thermal shutdown threshold Shutdown threshold

Recovery threshold

160

135

(4)

T_SD

°C

(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers,

the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.

(3) Measured at pins.

(4) Ensured by design.

7

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

6.6 Timing Characteristics

MIN

NOM

MAX

UNIT

CURRENT LIMITS AND HICCUP

Number of switching cycles

before hiccup is tripped

(1)

N_OC

128

46

Cycles

ms

Overcurrent hiccup retry delay

time

t_OC

SOFT START (SS/TRK PIN)

CSS = OPEN, from EN rising

edge to PGOOD rising edge

t_SS

Internal soft-start time

3.5

6.3

ms

POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION

PGOOD rising edge deglitch

delay

t_{PGOOD_RISE}

t_{PGOOD_FALL}

80

140

200

µs

PGOOD falling edge deglitch

delay

(1) Ensured by design.

6.7 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM LIMITS (SW PINS)

t_ON-MIN

t_OFF-MIN

t_ON-MAX

Minimum switch on-time

Minimum switch off-time

Maximum switch on-time

65

95

8

95

130

ns

µs

HS timeout in dropout

3.8

11.4

OSCILLATOR (RT and SYNC PINS)

f_OSCInternal oscillator frequency

R_T= Open

440

270

500

300

560

330

kHz

Minimum adjustable frequency by

R_Tor SYNC

R_T=133 kΩ, 0.1%

f_ADJ

Maximum adjustable frequency by

R_Tor SYNC

R_T= 17.4 kΩ, 0.1%

1980

0.4

2200

2420

2

V_{SYNC_HIGH}

V_{SYNC_LOW}

Sync input high level threshold

Sync input low level threshold

V

Mode input high level threshold for

FPWM

V_{MODE_HIGH}

V_{MODE_LOW}

t_{SYNC_MIN}

0.42

0.4

80

V

Mode input low level threshold for

AUTO mode

Sync input minimum on- and off-

time

ns

8

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

6.8 System Characteristics

The following specifications apply to the circuit found in the typical Simplified Schematic with appropriate modifications (see

表 2). These parameters are not tested in production and represent typical performance only. Unless otherwise stated the

following conditions apply: T_A= 25°C, V_IN= 24 V, V_OUT= 3.3 V, f_SW= 500 kHz.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output voltage offset at no load V_IN= 3.8 V to 36 V, V_SYNC= 0 V, auto mode

V_{FB_PFM}

2%

in auto mode

I_OUT= 0 A

Minimum input to output

V_drop

voltage differential to maintain V_OUT= 5 V, I_OUT= 1.5 A, f_SW= 2.2 MHz

specified accuracy

0.4

V

Operating quiescent current

(switching)

V_EN= 3.3 V, I_OUT= 0 A, R_T= open, V_BIAS

V_OUT= 3.3 V, R_FBT= 1 Meg

=

I_{Q_SW}

15

0.5

0.7

µA

LM76002 :

V_SYNC= 0 V, I_OUT= 10 mA

I_{PEAK_MIN}

Minimum inductor peak current

A

LM76003 :

V_SYNC= 0 V, I_OUT= 10 mA

f_SW= 500 kHz, I_OUT= 1 A

f_SW= 2.2 MHz, I_OUT= 1 A

While in frequency foldback

7

Operating quiescent current

from external V_BIAS(switching)

I_{BIAS_SW}

D_MAX

t_DEAD

mA

ns

25

Maximum switch duty cycle

97.5%

Dead time between high-side

and low-side MOSFETs

4

9

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

6.9 Typical Characteristics

Unless otherwise specified, V_IN= 24 V. Curves represent most likely parametric norm at specified condition.

140

130

120

110

100

90

1800

1700

1600

1500

1400

1300

1200

1100

1000

900

V_IN= 24 V

V_IN= 3.5 V

V_IN= 60 V

80

70

800

700

60

50

600

500

40

400

300

HS Switch

LS Switch

30

20

200

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

D002

图 1. High-Side and Low-Side Switch R_DS-ON

图 2. Shutdown Quiescent Current

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

6

5.5

5

Temp = -40èC

Temp = 25èC

Temp = 125èC

HS Limit

LS Limit

4.5

4

3.5

3

0

6

12

18

24

30

36

Input Voltage (V)

42

48

54

60

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D003

D004

图 3. Feedback Voltage

图 4. LM76003 High-Side and Low-Side Current Limits

2500

5

4.5

4

HS Limit

LS Limit

2250

2000

1750

1500

1250

1000

750

FREQ = 300 kHz

FREQ = 1 MHz

FREQ = 2.2 MHz

3.5

3

500

2.5

250

2

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D005

D006

图 5. LM76002 High-Side and Low-Side Current Limits

图 6. Switching Frequency Set by R_TResistor

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Typical Characteristics (接下页)

Unless otherwise specified, V_IN= 24 V. Curves represent most likely parametric norm at specified condition.

550

540

530

520

510

500

490

480

470

460

450

1.4

1.2

1

0.8

0.6

0.4

0.2

V_EN_V_OUTRising

V_EN_V_OUTFalling

V_EN_V_CCRising

V_EN_V_CCFalling

V_IN= 12 V

V_IN= 3.5 V

V_IN= 60 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D007

D008

图 7. Switching Frequency With R_TOpen

图 8. Enable Threshold

115

110

105

100

95

OV Tripping

OV Recovery

UV Recovery

UV Tripping

90

85

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D009

图 9. PGOOD Threshold

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7 Detailed Description

7.1 Overview

The LM76002/LM76003 regulator is an easy-to-use synchronous step-down DC-DC converter that operates from

3.5-V to 60-V supply voltage. The device is capable of delivering up to 2.5-A or 3.5-A DC load current with

exceptional efficiency and thermal performance in a very small solution size.

The LM76002/LM76003 employs fixed-frequency peak-current-mode control with configurable discontinuous

conduction mode (DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency

across the load range. The device can also be configured as forced-PWM (FPWM) operation to keep constant

switching frequency over the load range. The device is internally compensated, which reduces design time and

requires fewer external components. The switching frequency is programmable from 300 kHz to 2.2 MHz by an

external resistor. The LM76002/LM76003 is also capable of synchronization to an external clock operating within

the 300-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to meet a wide

range of design requirements. It can be optimized to very small solution size with higher frequency or to very

high efficiency with lower switching frequency. It has very small minimum HS MOSFET on-time (t_ON-MIN) and

minimum off-time (t_OFF-MIN) to provide wide range of voltage conversion. Automated frequency foldback is

employed under t_ON-MINor t_OFF-MINcondition to further extend the operation range.

The LM76002/LM76003 also features a power-good (PGOOD) flag, precision enable, internal or adjustable soft-

start rate, start-up with pre-bias voltage, and output voltage tracking. It provides a both flexible and easy-to-use

solution for wide range of applications. Protection features include thermal shutdown, V_CCundervoltage lockout,

cycle-by-cycle current limiting, and short-circuit hiccup protection.

The family requires very few external components and has a pinout designed for simple, optimum PCB layout for

EMI and thermal performance. The LM76002/LM76003 device is available in a 30-pin WQFN lead-less package.

7.2 Functional Block Diagram

EN

VCC

BIAS

LDO

PVIN

I_SSC

Internal

SS

V_BOOT

Precision

Enable

BOOT

VCC

SS/TRK

HS I Sense

I_CMD

+

EA

+

V_BOOT

REF

œ

R_C

C_C

œ

+

UVLO

FB

UVLO

FB

OV/UV

Detector

SW

PFM

Detector

CONTROL LOGIC

PGood

PGOOD

TSD

HICCUP

Detector

+

œ

Slope Comp

Oscillator

CLK

LS I Sense

I_CMD

AGND

FPWM

SYNC/

MODE

RT

PGND

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7.3 Feature Description

7.3.1 Fixed-Frequency, Peak-Current-Mode Control

The following operation description of the LM76002/LM76003 refers to the Functional Block Diagram and to the

waveforms in 图 10. The LM76002/LM76003 supplies a regulated output voltage by turning on the internal high

side (HS) and low side (LS) NMOS switches with varying duty cycle (D). During high-side switch on-time t_ON, the

SW pin voltage V_SWswings up to approximately V_IN, and the inductor current i_Lincrease with linear slope. The

HS switch is off by the control logic. During the HS switch off-time, t_OFF, the LS switch is turned on. Inductor

current discharges through the LS switch, which forces the V_SWto swing below ground by the voltage drop

across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. The control

parameter of buck converter is defined as duty cycle D = t_ON/ t_SW. In an ideal buck converter, where losses are

ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = V_OUT/ V_IN.

V_SW

D = t_ON/ T_SW

V_IN

t_ON

t_OFF

t

0

-V_D

T_SW

i_L

I_LPK

I_OUT

ûi_L

t

0

图 10. SW Node and Inductor Current Waveforms in

Continuous Conduction Mode

The LM76002/LM76003 synchronous buck converter employs peak current-mode control topology. A voltage-

feedback loop is used to get accurate DC-voltage regulation by adjusting the peak current command based on

voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current to

control the on-time of the HS switch. The voltage feedback loop is internally compensated, which allows

command for fewer external components, makes it easy to design, and provides stable operation with almost any

combination of output capacitors. The regulator operates with fixed switching frequency in continuous conduction

mode (CCM) and discontinuous conduction mode (DCM). At very light load, the LM76002/LM76003 operates in

PFM to maintain high efficiency, and the switching frequency decreases with reduced load current.

7.3.2 Light Load Operation Modes — PFM and FPWM

DCM operation is employed in the LM76002/LM76003 when the inductor current valley reaches zero. The

LM76002/LM76003 is in DCM when load current is less than half of the peak-to-peak inductor current ripple in

CCM. In DCM, the LS switch is turned off when the inductor current reaches zero. Switching loss is reduced by

turning off the LS FET at zero current, and the conduction loss is lowered by not allowing negative current

conduction. Power conversion efficiency is higher in DCM than CCM under the same conditions.

In DCM, the HS switch on-time reduces with lower load current. When either the minimum HS switch on-time

(t_ON-MIN) or the minimum peak inductor current (I_PEAK-MIN) is reached, the switching frequency decreases to

maintain regulation. At this point, the LM76002/LM76003 operates in PFM. In PFM, switching frequency is

decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is

further reduced in PFM operation due to less frequent switching actions.

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Feature Description (接下页)

In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The

lower the frequency is in PFM, the more DC offset is needed at V_OUT. See Typical Characteristics for typical DC

offset at very light load. If the DC offset on V_OUTis not acceptable for a given application, TI recommends a static

load at output to reduce or eliminate the offset. Lowering values of the feedback divider R_FBTand R_FBBcan also

serve as a static load. In conditions with low V_INand/or high frequency, the LM76002/LM76003 may not enter

PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once

the LM76002/LM76003 is operating in PFM mode at higher V_IN, it remains in PFM operation when V_INis

reduced.

Alternatively, the device can run in a forced pulse-width-modulation (FPWM) mode where the switching

frequency does not lower with load, and no offset is added to affect the V_OUTaccuracy unless the minimum on-

time of the converter is reached.

7.3.3 Adjustable Output Voltage

The voltage regulation loop in the LM76002/LM76003 regulates the FB voltage to be the same as the internal

reference voltage. The output voltage of the LM76002/LM76003 is set by a resistor divider to program the ratio

from V_OUTto V_FB. The resistor divider is connected from the output node to ground with the mid-point connecting

to the FB pin.

V

OUT

R

FBT

FBB

FB

R

图 11. Output Voltage Setting

The voltage reference system produces a precise ±1% voltage reference over temperature. TI recommends

using divider resistors with 1% tolerance or better with temperature coefficient of 100 ppm or lower. Selection of

R_FBTequal or lower than 100 kΩ is also recommended. R_FBBcan be calculated by 公式 1:

V_FB

R_FBB

=

R_FBT

V_OUT- V_FB

(1)

Larger R_FBTand R_FBBvalues reduce the current that goes through the divider, thus helping to increase light load

efficiency. However, larger values also make the feedback path more susceptible to noise. If efficiency at very

light load is not critical in a certain application, TI recommends R_FBT= 10 kΩ to 100 kΩ. If the resistor divider is

not connected properly, output voltage cannot be regulated because the feedback loop is broken. If the FB pin is

shorted to ground or disconnected, the output voltage is driven close to V_INbecause the regulator detects very

low voltage on the FB node. The load connected to V_OUTcould be damaged in this case. It is important to route

the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout.

The minimum output voltage achievable equals VFB, with R_FBBopen. The maximum V_OUTis limited by the

maximum duty cycle at a given frequency:

D_MAX= 1 – (t_{OFF_MIN}/ T_SW

)

where

•

t_{OFF_MIN}is the minimum off time of the HS switch

T_SW= 1 / f_SWis the switching period

(2)

Ideally, without frequency foldback, V_{OUT_MAX}= V_{IN_MIN}× D_MAX

Maximum output voltage with frequency foldback can be estimated using 公式 3:

t_{ON_MAX}

V_{OUT _MAX}= V

ì

- I_OUT

ì

R

(

+ DCR

)

IN_MIN

DS_ON_HS

t_{ON_MAX}+ t_{OFF_MIN}

(3)

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Feature Description (接下页)

7.3.4 Enable (EN Pin) and UVLO

System UVLO by EN and V_{CC_UVLO}voltage on the EN pin (V_EN) controls the ON/OFF functionality of the

LM76002/LM76003. Applying a voltage less than 0.3 V to the EN input shuts down the operation of the

LM76002/LM76003. In shutdown mode the quiescent current drops to typically 1.2 µA at V_IN= 24 V.

The internal LDO output voltage V_CCis turned on when V_{EN_VOUT_H}is higher than 1.15 V. The

LM76002/LM76003 switching action and output regulation are enabled when V_ENis greater than 1.204 V

(typical). The LM76002/LM76003 supplies regulated output voltage when enabled and output current up to 2.5

A/3.5 A. The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation

of the LM76002/LM76003 is to connect the EN pin to PVIN pins directly. This allows self-start-up of the

LM76002/LM76003 when V_INis within the operation range.

Many applications may benefit from the employment of an enable divider R_ENTand R_ENB(see 图 12) to establish

a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power

as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such

as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.

VIN

R_ENT

ENABLE

R_ENB

图 12. V_INUVLO

With a selected R_ENT, the R_ENBcan be calculated by:

V_{EN_ VOUT _H}ì R_ENT

R_ENB

=

V_{IN_ON_H}- V_{EN_VOUT_H}

where

•

V_{IN_ON_H}is the desired supply voltage threshold to turn on this device

V_{EN_VOUT_H}could be taken from device data sheet

(4)

Note that the divider adds to supply quiescent current by V_IN/ (R_ENT+ R_ENB). Small R_ENTand R_ENBvalues add

more quiescent current loss. However, large divider values make the node more sensitive to noise. R_ENTin the

hundreds of kΩ range is a good starting point.

7.3.5 Internal LDO, VCC UVLO, and Bias Input

The LM76002/LM76003 has an internal LDO generating VCC voltage for control circuitry and MOSFET drivers.

The nominal voltage for VCC is 3.29 V. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as

close as possible to the pin and properly grounded. Do not load or short the VCC pin to ground during operation.

Shorting the VCC pin to ground during operation may damage the device.

An UVLO prevents the LM76002/LM76003 from operating until the VCC voltage exceeds V_{CC_UVLO}. The V_{CC_UVLO}

threshold is 3.14 V and has approximately 575 mV of hysteresis, so the device operates until V_CCdrops below

2.575 V (typical). Hysteresis prevents the device from turning off during power up if V_INdroops due to input

current demands.

The LDO can generate V_CCfrom two inputs: the supply voltage V_INand the BIAS input. The LDO power loss is

calculated by I_LDO× (V_INLDO– V_OUTLDO). The higher the difference between the input and output voltages of the

LDO, the more losses occur to supply the same LDO output current. The BIAS input is designed to reduce the

difference of the input and output voltages of the LDO to improve efficiency, especially at light load. TI

recommends tying the BIAS pin to V_OUTwhen the output voltage is equal to or greater than 3.3 V. Tie the BIAS

pin to ground for applications less than 3.3 V. BIAS can also tie to external voltage source if available to improve

efficiency. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor be used to bypass the

BIAS pin to ground. If there is high-frequency noise or voltage spikes present on V_OUT(during transient events or

fault conditions), TI recommends connecting a resistor (1 to 10 Ω) between V_OUTand BIAS.

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Feature Description (接下页)

The V_CCvoltage is typically 3.27 V. When the LM76002/LM76003 is operating in PFM mode with frequency

foldback, V_CCvoltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve

efficiency at very light loads. 图 13 shows an example of V_CCvoltage change with mode change.

3.5

Auto Mode

FPWM Mode

3.4

3.3

3.2

3.1

3

2.9

2.8

2.7

2.6

2.5

0.001

0.01

0.1

Load Current (A)

1

5

D010

图 13. V_CCVoltage Change With Mode Change

V_CCvoltage has an internal undervoltage lockout threshold, V_{CC_UVLO}. When V_CCvoltage is higher than V_{CC_UVLO}

rising threshold, the device is active and in normal operation if V_EN> V_{EN_VOUT_H}. If VCC voltage droops below

V_{CC_UVLO}falling threshold, the V_OUTis shut down.

7.3.6 Soft Start and Voltage Tracking (SS/TRK)

The LM76002/LM76003 has a flexible and easy-to-use start-up rate control pin: SS/TRK. The soft-start feature is

to prevent inrush current impacting the LM76002/LM76003, and its supply when power is first applied. Soft start

is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up.

The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM76002/LM76003

employs the internal soft-start control ramp and starts up to the regulated output voltage in 6.3 ms typically. In

applications with a large amount of output capacitors, higher V_OUT, or other special requirements, the soft-start

time can be extended by connecting an external capacitor C_SSfrom SS/TRK pin to AGND. Extended soft-start

time further reduces the supply current required to charge up output capacitors and supply any output loading.

An internal current source (I_SSC= 2.2 μA) charges C_SSand generates a ramp from 0 V to VFB to control the

ramp-up rate of the output voltage. For a desired soft-start time t_SS, the capacitance for C_SScan be found by 公式

5:

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Feature Description (接下页)

C_SS= I_SSC× t_SS

where

•

C_SS= soft-start capacitor value (µF)

I_SSC= soft-start charging current (µA)

t_SS= desired soft-start time (s)

(5)

The soft-start capacitor C_SSis discharged by an internal FET when V_OUTis shut down by hiccup protection or

ENABLE = logic low. When a large C_SSis applied, and EN is toggled low only for a short period of time, C_SSmay

not be fully discharged. The next soft-start ramp follows internal soft-start ramp before reaching the leftover

voltage on CSS and then follows the ramp programmed by C_SS. If this is not acceptable for a certain application,

an R-C low-pass filter can be added to EN to slow down the shutting down of VCC, allowing more time to

discharge C_SS

.

The LM76002/LM76003 is capable of start-up into pre-biased output conditions. When the inductor current

reaches zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also called

diode emulation mode. It is built in by the DCM operation in light loads. With a pre-biased output voltage, the

LM76002/LM76003 waits until the soft-start ramp allows regulation above the pre-biased voltage and then follows

the soft-start ramp to the regulation level. When an external voltage ramp is applied to the SS/TRK pin, the

LM76002/LM76003 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp.

A resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate of

the output voltage. The final voltage detected by the SS/TRK pin must not fall below 1.2 V to avoid abnormal

operation

V_OUTtracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage

ramp. V_FBalways follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. 图

14 shows resistive divider connection if external ramp tracking is desired.

EXT RAMP

R_TRT

SS/TRK

R_TRB

图 14. Soft-Start Tracking External Ramp

图 15 shows the case when V_OUTramps more slowly than the internal ramp, while 图 16 shows when V_OUT

ramps faster than the internal ramp. Faster start-up time may result in inductor current tripping current protection

during start-up. Use with special care.

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

V_OUT

图 15. Tracking With Longer Start-up Time Than The Internal Ramp

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Feature Description (接下页)

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

V_OUT

图 16. Tracking With Shorter Start-up Time Than The Internal Ramp

The LM76002/LM76003 is capable of start-up into pre-biased output conditions. During start-up the device sets

the minimum inductor current to zero to avoid discharging a pre-biased load.

7.3.7 Adjustable Switching Frequency (RT) and Frequency Synchronization

The switching frequency of the LM76002/LM76003 can be programmed by the impedance R_Tfrom the RT pin to

ground. The frequency is inversely proportional to the R_Tresistance. The RT pin can be left floating, and the

LM76002/LM76003 operates at 500-kHz default switching frequency. The RT pin is not designed to be shorted to

ground.

For an desired frequency, R_Tcan be found by:

38400

R_T(kW) =

Frequency(kHz) - 14.33

(6)

120

110

100

90

80

70

60

50

40

30

20

10

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Frequency (kHz)

RT_F

图 17. Switching Frequency vs RT

表 1. Switching Frequency vs RT

SWITCHING FREQUENCY (kHz)

RT RESISTANCE (kΩ)

300

400

134.42

99.57

79.07

52.20

38.96

25.85

19.34

17.57

500

750

1000

1500

2000

2200

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The LM76002/LM76003 switching action can also be synchronized to an external clock from 300 kHz to 2.2 MHz.

TI recommends connecting an external clock to the SYNC pin with appropriate termination resistor. Ground the

SYNC pin if not used.

SYNC

EXT CLOCK

R_TERM

图 18. Frequency Synchronization

The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,

duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the

external clock fails at logic high or low, the LM76002/LM76003 switches at the frequency programmed by the R_T

resistor after a time-out period. TI recommends connecting a resistor R_Tto the RT pin so that the internal

oscillator frequency is the same as the target clock frequency when the LM76002/LM76003 is synchronized to an

external clock. This allows the regulator to continue operating at approximately the same switching frequency if

the external clock fails.

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the

circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch

transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows

use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient

response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching

frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.

It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,

and circuit size requirement. The choice of switching frequency may also be limited if an operating condition

triggers t_ON-MINor t_OFF-MIN

.

7.3.8 Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions

Minimum on-time, t_ON-MIN, is the smallest duration of time that the HS switch can be on. t_ON-MINis typically 70 ns

in the LM76002/LM76003. Minimum off-time, t_OFF-MIN, is the smallest duration that the HS switch can be off. t_OFF-

is typically 100 ns in the LM76002/LM76003. In CCM operation, t_ON-MINand t_OFF-MINlimits the voltage

MIN

conversion range given a selected switching frequency. The minimum duty cycle allowed is:

D_MIN= t_ON-MIN× f_SW

(7)

And the maximum duty cycle allowed is:

D_MAX= 1 – t_OFF-MIN× f_SW

(8)

Given fixed t_ON-MINand t_OFF-MIN, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LM76002/LM76003, frequency foldback scheme is employed to extend the maximum duty cycle

when t_OFF-MINis reached. The switching frequency decreases once longer duty cycle is needed under low V_IN

conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by

RT or the synchronization clock. Such a wide range of frequency foldback allows the LM76002/LM76003 output

voltage to stay in regulation with a much lower supply voltage V_IN. This leads to a lower effective dropout voltage.

See Typical Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size and efficiency. The maximum operational supply voltage can be found by:

V_{IN_MAX}= V_OUT/ (f_SW× t_ON-MIN

)

(9)

At lower supply voltage, the switching frequency decreases once t_OFF-MINis tripped. The minimum V_INwithout

frequency foldback can be approximated by:

V_{IN_MIN}= V_OUT/ (f_SW× t_OFF-MIN

)

(10)

Considering power losses in the system with heavy load operation, V_IN-MINis higher than the result calculated in

公式 10. With frequency foldback, V_IN-MINis lowered by decreased f_SW. When the device is operating in auto

mode at voltages near maximum rated input voltage and light load conditions, an increased output voltage ripple

during load transient may be observed. For this reason TI recommends that device operating point be calculated

with sufficient operational margin so that minimum on-time condition is not triggered.

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7.3.9 Internal Compensation and C_FF

The LM76002/LM76003 is internally compensated with R_C= 600 kΩ and C_C= 35 pF as shown in the Functional

Block Diagram. The internal compensation is designed such that the loop response is stable over the entire

operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase

margin can be low with all ceramic capacitors. TI recommends placing an external feed-forward cap C_FFin

parallel with the top resistor divider R_FBTfor optimum transient performance.

V_OUT

R_FBT

C_FF

FB

R_FBB

图 19. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FFin parallel with R_FBTplaces an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by 公式 11:

f_Z-CFF= 1 / (2π × R_FBT× C_FF

)

(11)

An additional pole is also introduced with C_FFat the frequency of 公式 12:

f_P-CFF= 1 / (2π × C_FF× (R_FBT// R_FBB))

(12)

Select the C_FFso that the bandwidth of the control loop without the C_FFis centered between f_Z-CFFand f_P-CFF. The

zero f_Z-CFFadds phase boost at the crossover frequency and improves transient response. The pole f_P-CFFhelps

maintaining proper gain margin at frequency beyond the crossover.

Electrolytic capacitors have much larger ESR and the ESR zero frequency would be low enough to boost the

phase up around the crossover frequency.

f_Z-ESR= 1 / (2π × ESR × C_OUT

)

(13)

Designs using mostly electrolytic capacitors at the output may not need any C_FF. The C_FFcreates a time constant

with R_FBTthat couples in the attenuated output voltage ripple to the FB node. If the C_FFvalue is too large, it can

couple too much ripple to the FB and affect V_OUTregulation. It could also couple too much transient voltage

deviation and falsely trip PGOOD thresholds. Therefore, calculate C_FFbased on output capacitors used in the

system. At cold temperatures, the value of C_FFmight change based on the tolerance of the chosen component.

This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be

added to the output or the value of C_FFcan be reduced. See Feed-Forward Capacitor for the calculation of C_FF.

7.3.10 Bootstrap Voltage and VBOOT UVLO (BOOT Pin)

The driver of the power switch (HS switch) requires bias higher than V_INwhen the HS switch is ON. The

capacitor connected between C_BOOTand SW works as a charge pump to boost voltage on the BOOT pin to (V_SW

+ V_CC). The boot diode is integrated on the LM76002/LM76003 die to minimize physical size. TI recommends a

0.47-µF, 6.3-V or higher capacitor for C_BOOT. The V_{BOOT_UVLO}threshold is typically 2.2 V. If the C_BOOTcapacitor is

not charged above this voltage with respect to SW, the device initiates a charging sequence using the low-side

FET.

7.3.11 Power Good and Overvoltage Protection (PGOOD)

The LM76002/LM76003 has a built-in power-good flag shown on PGOOD pin to indicate whether the output

voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails. The

PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage

below 12 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical range of pullup

resistor value is 10 kΩ to 100 kΩ. When the FB voltage is outside the power-good band, +6% above and –7%

below the internal reference V_REFtypically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled

to ground. When the FB is 2% (typical) closer to FB than the PGOOD threshold, the PGOOD switch is turned off,

and the pin is pulled up to the voltage connected to the pullup resistor. Both rising and falling edges of the

power-good flag have a built-in 220-µs (typical) deglitch delay. To pull up PGOOD pin to a voltage higher than

15V, a resistor divider can be used to divide the voltage down.

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V_PU

R_PGT

PGOOD

R_PGB

图 20. PGOOD Resistor Divider

For given pullup voltage V_PUand desired voltage on PGOOD pin is V_PGand with R_PGTchosen, value for R_PGB

can be calculated using 公式 14:

V_PG

R_PGB

=

R_PGT

V_PU- V_PG

(14)

7.3.12 Overcurrent and Short-Circuit Protection

The LM76002/LM76003 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak

and valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current-mode control. The

HS switch current is sensed when the HS is turned on after a blanking time. The HS switch current is compared

to the either the minimum of a fixed current set point (I_SC) or the output of the voltage regulation loop minus slope

compensation every switching cycle. The slope compensation increases with duty cycle and tends to lower the

HS current limit above 60% duty cycle as it lowers below I_SC. See Typical Characteristics.

When the LS switch is turned on, the current going through it is also sensed and monitored. Before turning off

the LS switch at the end of every clock cycle, the LS current is compared to the LS current limit. If the LS current

limit is exceeded, the LS MOSFET stays on, and the HS switch is not turned on. The LS switch is kept ON so

that inductor current keeps ramping down, until the inductor current ramps below I_LSLIMIT. The LS switch is turned

off once the LS current falls below the limit, and the HS switch is turned on again after a dead time.

If the current of the LS switch is higher than the LS current limit for 128 consecutive cycles, and the feedback

voltage falls 60% below regulation, hiccup current-protection mode is activated. In hiccup mode, the regulator is

shut down and kept off for 40 ms typically before the LM76002/LM76003 tries to start again. If overcurrent or a

short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reduces

power dissipation under severe overcurrent conditions, and prevents overheating and potential damage to the

device. Under non-severe overcurrent conditions when the feedback voltage has not fallen 60% below regulation,

the LM76002/LM76003 reduces the switching frequency and keeps the inductor current valley clamped at the LS

current limit level. This operation mode allows slight overcurrent operation during load transients without tripping

hiccup.

If tracking was used for initial sequencing the device attempts to restart using the internal soft-start circuit until

the tracking voltage is reached.

7.3.13 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction

temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device from

switching until the junction temperature drops to approximately 135°C. When the junction temperature falls below

135°C, the LM76002/LM76003 attempts to soft start.

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7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical on/off control for the LM76002/LM76003. When the EN pin voltage is below 0.3 V

(typical), both the regulator and the internal LDO have no output voltages, and the device is in shutdown mode.

In shutdown mode the quiescent current drops to typically 1.2 µA. The LM76002/LM76003 also employs UVLO

protection. If V_CCvoltage is below the UVLO level, the output of the regulator is turned off.

7.4.2 Standby Mode

The internal LDO has a lower EN threshold than the regulator. When the EN pin voltage is above below 1.1 V

(maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the V_CC

voltage at 3.29 V typically. The precision enable circuitry is ON once V_CCis above the UVLO. The internal

MOSFETs remain in tri-state unless the voltage on EN pin goes above the precision enable threshold. The

LM76002/LM76003 also employs UVLO protection. If V_CCvoltage is below the UVLO level, the output of the

regulator is turned off.

7.4.3 Active Mode

The LM76002/LM76003 is in active mode when the EN pin and UVLO high threshold levels are satisfied. The

simplest way to enable the operation of the LM76002/LM76003 is to connect the EN pin to VIN, which allows self

start-up of the LM76002/LM76003 when the input voltage is in the operation range: 3.5 V to 60 V. See Enable

(EN Pin) and UVLO for details on setting these operating levels.

In active mode, depending on the load current, the LM76002/LM76003 will be in one of five sub modes:

1. CCM with fixed switching frequency with load between half of I_MINPKto full load.

2. DCM when the load current is lower than half of the inductor current ripple.

3. Light load mode where the device uses pulse frequency modulation (PFM) and lowers the switching

frequency at load under half of I_MINPKto improve efficiency.

4. Foldback mode when switching frequency is reduced to maintain output regulation with supply voltages that

cause the minimum t_ONor t_OFFto be exceeded.

5. Forced-pulse-width modulation (FPWM) is similar to CCM with fixed switching frequency, but extends the

fixed frequency range of operation from full to no load.

7.4.4 CCM Mode

CCM operation is employed in the LM76002/LM76003 when the load current is higher than ½ of the peak-to-

peak inductor current. If the load current is decreased, the device enters DCM mode. In CCM operation, the

frequency of operation is constant and fixed unless the minimum t_ONor t_OFFare exceeded which causes the part

to enter fold back mode (refer to Internal LDO, VCC UVLO, and Bias Input for details). In these cases, PWM is

still maintained, but the frequency of operation is folded back (reduced) to maintain proper regulation.

7.4.5 DCM Mode

DCM operation is employed in the LM76002/LM76003 when the load current is lower than ½ of the peak-to-peak

inductor current. In DCM operation (also known as diode emulation mode), the LS FET is turned off when the

inductor current drops below 0 A to keep operation as efficient as possible by reducing switching losses and

preventing negative current conduction. In PWM operation, the frequency of operation is constant and fixed

unless the load current is reduced below I_{PEAK_MIN}, which causes the part to enter light load mode, or if the

minimum t_ONor t_OFFare exceeded, which cause the device to enter foldback mode.

7.4.6 Light Load Mode

At light output current loads, PFM is activated for the highest efficiency possible. When the inductor current does

not reach I_{PEAK_MIN}during a switching cycle, the on-time is increased, and the switching frequency reduces as

needed to maintain proper regulation. The on-time has a maximum value of 8 µs to avoid large output voltage

ripple in dropout conditions. Efficiency is greatly improved by reducing switching and gate-drive losses. During

light-load mode of operation the LM76002/LM76003 operates with a minimum quiescent current of 10 to 15 µA

(typical).

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Device Functional Modes (接下页)

7.4.7 Foldback Mode

Foldback protection modes are entered when the duty cycle exceeds the minimum on- and off-times of the

device. At very high duty cycles, where the minimum off-time is not satisfied, the frequency folds back to allow

more time for the peak current command to be reached. The maximum on-time is 8 µs, which limits the

maximum duty cycle in dropout to 98%. At very low duty cycles when the minimum on-time is reached, the

device maintains regulation by dropping the frequency to allow more time for the inductor current to discharge

the output capacitor. Foldback mode is exited once the minimum on-time and off-times are satisfied.

7.4.8 Forced Pulse-Width-Modulation Mode

FPWM is employed when the FPWM pin is pulled high, or the device is synchronized to an external clock. In this

mode, diode emulation is turned off, and the device emains in CCM over the full load range. In FPWM operation,

the frequency of operation is constant and fixed unless the minimum t_ONor t_OFFare exceeded, which cause the

device to enter foldback mode. In these cases, PWM operation is still maintained, but the frequency of operation

is folded back (reduced) to maintain proper regulation. DC accuracy is at a minimum in FPWM mode.

7.4.9 Self-Bias Mode

For highest efficiency of operation, TI recommends that the BIAS pin be connected directly to V_OUTwhen 3.3 V ≤

V_OUT≤ 24 V. In this self-bias mode of operation, the difference between the input and output voltages of the

internal LDO are reduced, and therefore the total efficiency of the LM76002/LM76003 is improved. These

efficiency gains are more evident during light load operation. During this mode of operation, the

LM76002/LM76003 operates with a minimum quiescent current of 15 µA (typical). See Internal LDO, VCC UVLO,

and Bias Input for more details.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM76002/LM76003 is a step-down DC-DC converter. It is typically used to convert a higher DC voltage to a

lower DC voltage with a maximum output current of 3.5 A. The following design procedure can be used to select

component values for the LM76002/LM76003. Alternately, the WEBENCH® software may be used to generate a

complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive

database of components when generating a design (see Custom Design With WEBENCH® Tools).

8.2 Typical Applications

The LM76002/LM76003 only requires a few external components to convert from a wide range of supply voltage

to output voltage, as shown in 图 21:

L

V_IN

PVIN

SW

V_OUT

C_OUT

C_IN

C_BOOT

PGND

C_FF

R_FBT

BOOT

FB

EN

VCC

R_FBB

C_VCC

SS/TRK

BIAS

RT

C_BIAS

LM76003

PGOOD

SYNC

AGND

Tie BIAS to PGND

when V_OUT< 3.3 V

图 21. LM76002/LM76003 Basic Schematic

The LM76002/LM76003 also integrates a full list of features to aid system design requirements, such as VCC

UVLO, programmable soft start, start-up tracking, programmable switching frequency, clock synchronization, and

a power-good indication. Each system can select the features needed in a specific application. A comprehensive

schematic with all features utilized is shown in 图 22:

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Typical Applications (接下页)

L

V_OUT

V_IN

SW

PVIN

R_ENT

C_IN

C_OUT

PGND

EN

C_BOOT

R_FBT

C_FF

V_IN

PVIN

BOOT

FB

C_IN

R_ENB

R_ENT

PGND

EN

B

VCC

R_FBB

C_VCC

SS/TRK

RT

R_ENB

C_SS

SS/TRK

BIAS

LM76003

C_SS

R_T

C_BIAS

RT

LM76003

R_T

PGOOD

PGND

SYNC

AGND

R_PG

PG

P

R_SYNC

SYNC

AGND

Tie BIAS to PGND when

V_OUT< 3.3 V

R_SYNC

图 22. LM76002/LM76003 Comprehensive Schematic

The external components must fulfill the requirements of the application, but also the stability criteria of the

device control loop. The LM76002/LM76003 is optimized to work within a range of external components.

Inductance and capacitance of the LC output filter each create poles that have to be considered in the control of

the converter. 表 2 can be used to simplify the output filter component selection.

表 2. Typical Component Selection

f_SW(kHz)

300

V_OUT(V)

1

L (µH)

2.5

1.5

0.68

0.47

6.8

4.7

2.5

1.2

10

C_OUT(µF)

680

470

200

120

200

150

88

R_FBT(kΩ)

100

R_FBB(kΩ)

OPEN

43.5

25

500

1

1000

2200

300

1

3.3

5

500

1000

2200

300

44

150

100

66

500

5

6.8

3.3

1.5

22

25

1000

2200

300

5

25

5

44

25

12

24

66

9.09

4.37

500

15

44

1000

2200

300

6.8

3.3

47

22

40

500

27

33

1000

2200

15

22

6.8

22

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8.2.1 Design Requirements

Detailed Design Procedure is based on a design example. For this design example, use the parameters listed in

表 3 as the input parameters.

表 3. Design Example Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

VALUE

3.5 V to 60 V

3.3 V

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

400 mV

30 mV

3.5 A

500 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM76002/03 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the LM76002/LM76003 device is externally adjustable using a resistor divider network. In

the application circuit of 图 22, this divider network is comprised of top feedback resistor R_FBTand bottom

feedback resistor R_FBB. 公式 15 is used to determine the output voltage of the converter:

V_FB

R_FBB

=

R_FBT

V_OUT- V_FB

(15)

Choose the value of the R_FBTto be around 1 MΩ to minimize quiescent current during light load operation or

100kΩ to improve noise immunity. With the desired output voltage set to be 3.3 V and with a V_FB= 1 V, the R_FBB

value can then be calculated using 公式 15. The formula yields a value of 434.78 kΩ. Choose the closest

available value of 432 kΩ for the R_FBB, or a combination of two resistors (432 kΩ + 2.74 kΩ) to increase initial

accuracy.

8.2.2.3 Switching Frequency

The default switching frequency of the LM76002/LM76003 device is set at 500 kHz. If the R_Tis left open, the

LM76002/LM76003 switches at 500 kHz in CCM mode. Use 公式 16 to calculate the required value for R_Tin

order to operate the LM76002/LM76003 at different frequencies.

38400

R_T(kW) =

Frequency(kHz) - 14.33

(16)

The unit for the result is kΩ.

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8.2.2.4 Input Capacitors

The LM76002/LM76003 device requires an input decoupling and, depending on the application, a bulk input

capacitor. The typical recommended value for the high frequency decoupling capacitor is 10 μF to 22 μF. TI

recommends a high-quality ceramic type X5R or X7R with sufficiency voltage rating. The voltage rating must be

greater than the maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of

twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required,

especially if the LM76002/LM76003 circuit is not located within approximately 5 cm from the input voltage source.

This capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable. The

optimum value for this capacitor is four times the ceramic input capacitance with ESR close to the characteristic

impedance of the LC filter formed by the application input inductance and ceramic input capacitors.

For this design, two 4.7-μF, X7R dielectric capacitors rated for 100 V are used for the input decoupling

capacitance. A single capacitor has equivalent series resistance (ESR) of approximately 3 mΩ, and an RMS

current rating of 3 A. Include a capacitor with a value of 47 nF for high-frequency filtering and place it as close as

possible to the device pins.

注

DC-Bias Effect: High capacitance ceramic capacitors have a DC-bias derating effect,

which has a strong influence on the final effective capacitance. Therefore, choose the right

capacitor value carefully. Package size and voltage rating in combination with dielectric

material are responsible for differences between the rated capacitor value and the

effective capacitance.

8.2.2.5 Inductor Selection

The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is

based on the desired peak-to-peak ripple current, Δi_Lthat flows in the inductor along with the load current. As

with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance

means lower ripple current and hence lower output voltage ripple. Lower inductance results in smaller, less

expensive devices. An inductance that gives a ripple current of 20% to 40% of the maximum output current is a

good starting point. (Δi_L= (1/5 to 2/5) × I_OUT). The peak-to-peak inductor current ripple can be found by 公式 17

and the range of inductance can be found by 公式 18 with the typical input voltage used as V_IN.

(V_IN- V_OUT)ìD

Di_L=

L ì f_SW

(17)

(V_IN- V_OUT)ìD

0.4ìf_SWìI_L-MAX

(V_IN- V_OUT)ìD

0.2ìf_SWìI_L-MAX

Ç L Ç

(18)

D is the duty cycle of the converter which in a buck converter it can be approximated as D = V_OUT/ V_IN,

assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance

value comes out in micro henries. The inductor ripple current ratio is defined by:

Di_L

I_OUT

r =

(19)

The second criterion is the inductor saturation-current rating. The inductor must be rated to handle the maximum

load current plus the ripple current:

I_L-PEAK= I_LOAD-MAX+ Δ i_L/ 2

(20)

The LM76002/LM76003 has both valley current limit and peak current limit. During an instantaneous short, the

peak inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should

be higher than the HS current limit. TI recommends selection of an inductor with a larger core saturation margin

and preferably a softer roll off of the inductance value over load current.

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In general, it is preferable to choose lower inductance in switching power supplies, because it usually

corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,

too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at

the full load could be falsely triggered. It also generates more conduction loss because the RMS current is

slightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also

implies larger output voltage ripple with the same output capacitors. With peak-current-mode control, it is not

recommended to have an inductor current ripple that is too small. Enough inductor current ripple improves signal-

to-noise ratio on the current comparator and makes the control loop more immune to noise.

Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core

losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and

preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when

the peak design current is exceeded. The hard saturation results in an abrupt increase in inductor ripple current

and consequent output voltage ripple. Do not allow the core to saturate.

For the design example, a standard 10-μH inductor from Wurth, Coiltronics, or Vishay can be used for the 3.3-V

output with plenty of current rating margin.

8.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. TI generally recommends using as little output

capacitance as possible to keep cost and size down. Choose the output capacitor(s), C_OUT, with care as it

directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load

current transients.

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going

through the equivalent series resistance (ESR) of the output capacitors:

ΔV_OUT-ESR= Δi_L× ESR

(21)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

ΔV_OUT-C= Δi_L/ (8 × f_SW× C_OUT

)

(22)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,

output capacitors provide the required charge before the inductor current can slew to the appropriate level. The

initial output voltage step is equal to the load current step multiplied by the ESR. V_OUTcontinues to droop until

the control loop response increases or decreases the inductor current to supply the load. To maintain a small

overshoot or undershoot during a transient, small ESR, and large capacitance are desired. But these also come

with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output

voltage deviation.

For a given input and output requirement, 公式 23 gives an approximation for an absolute minimum output cap

required:

2

»

…

ÿ

Ÿ

≈

’

÷

◊

1

r

Å

C_OUT

>

ì

ì(1+ D ) + D ì(1+ r)

(

)

∆

÷

(f_SWìr ì DV_OUT/ I_OUT

)

12

Ÿ

⁄

«

(23)

Along with this for the same requirement, calculate the maximum ESR as per 公式 24

D'

1

≈

’

ESR <

ì

+ 0.5

∆

«

÷

◊

f_SWì C_OUT

r

where

•

r = Ripple ratio of the inductor ripple current (Δi_L/ I_OUT

ΔV_O= target output voltage undershoot

D’ = 1 – duty cycle

)

f_SW= switching frequency

I_OUT= load current

(24)

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A general guideline for C_OUTrange is that C_OUTshould be larger than the minimum required output capacitance

calculated by 公式 23, and smaller than 10 times the minimum required output capacitance or 1 mF. In

applications with V_OUTless than 3.3 V, it is critical that low ESR output capacitors are selected. This limits

potential output voltage overshoots as the input voltage falls below the device normal operating range. To

optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback

resistor. For this design example, three 47-µF, 10-V, X7R ceramic capacitors are used in parallel.

8.2.2.7 Feed-Forward Capacitor

The LM76002/LM76003 is internally compensated and the internal R-C values are 400 kΩ and 50 pF,

respectively. Depending on the V_OUTand frequency F_S, if the output capacitor C_OUTis dominated by low ESR

(ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feed-

forward capacitor C_FFcan be added in parallel with R_FBT. C_FFis chosen such that phase margin is boosted at the

crossover frequency without C_FF. A simple estimation for the crossover frequency without C_FF(f_x) is shown in 公

式 25, assuming C_OUThas very small ESR.

15.46

f_X

=

V_OUTì C_OUT

(25)

The 公式 26 for C_FFwas tested:

1

C_FF

=

ì

2pf_x

R_FBTì(R_FBT/ /R_FBB

)

(26)

If capacitors with high ESR are used C_FFis not required. The C_FFcapacitor creates a time constant with R_FBTthat

couples the attenuated output voltage ripple to the FB node. Using a value that is too large for C_FFmay couple

too much ripple to FB node and affect output voltage regulation. For capacitors with medium ESR (20 – 200 mΩ)

公式 26 can be used as quick starting point. For the application in this design example, a 47-pF C0G capacitor is

used.

8.2.2.8 Bootstrap Capacitors

Every LM76002/LM76003 design requires a bootstrap capacitor, C_BOOT. The recommended bootstrap capacitor

is 0.47 μF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the BOOT

pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for

temperature stability.

8.2.2.9 VCC Capacitors

The VCC pin is the output of an internal LDO for LM76002/LM76003. The input for this LDO comes from either

VIN or BIAS (please refer to functional block diagram for LM76002/LM76003). To insure stability of the part,

place a 1-µF to 2.2-µF, 10-V capacitor for this pin. Never short VCC pin to ground during operation.

8.2.2.10 BIAS Capacitors

For an output voltage 3.3 V and greater, connect the BIAS pin to the output in order to increase light load

efficiency. The BIAS pin is one of the two inputs for the VCC LDO. When BIAS voltage is below V_BIAS-ON

threshold, the input for the VCC LDO is internally connected to VIN. Because this is an LDO, the voltage

differences between the input and output affects the efficiency of the LDO. If necessary, a capacitor with a value

of 1 μF can be added close to the BIAS pin as an input capacitor for the LDO.

8.2.2.11 Soft-Start Capacitors

The SS pin can be left floating, and the LM76002/LM76003 implements a soft-start time of 6.3 ms. In order to

use an external soft-start capacitor, the capacitor must be sized so that the soft-start time is greater than 6.3 ms.

Use 公式 27 to calculate the soft-start capacitor value:

C_SS= I_SSC× t_SS

(27)

With a desired soft-start time of 11 ms, a soft-start charging current of 2 µA, and an internal V_REFof 1 V, 公式 27

yields a soft start capacitor value of 22 nF.

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8.2.2.12 Undervoltage Lockout Setpoint

The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand R_ENB. R_ENT

is connected between the PVIN pin and the EN pin of the LM76002/LM76003. R_ENBis connected between the

EN pin and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and

one for power down or brownouts when the input voltage is falling. 公式 28 can be used to determine the V_IN

UVLO level.

V_{IN-UVLO-RISING}= V_ENH× (R_ENB+ R_ENT) / R_ENB

(28)

The EN rising threshold (V_ENH) for LM76002/LM76003 is set to be 1.218 V (typical). Choose the value of R_ENBto

be 100 kΩ to minimize input current from the supply. If the desired V_INUVLO level is at 5 V, then the value of

R_ENTcan be calculated using 公式 29:

R_ENT= (V_{IN-UVLO-RISING}/ V_ENH– 1) × R_ENB

(29)

公式 29 yields a value of 315 kΩ. The resulting falling UVLO threshold, can be calculated by 公式 30, where EN

falling threshold (V_ENL) is 0.99 V (typical).

V_{IN-UVLO-FALLING}= V_ENL× (R_ENB+ R_ENT) / R_ENB

(30)

8.2.2.13 PGOOD

A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 18 V. If it is

desired to pull up the PGOOD pin to a voltage higher than 18 V, a resistor can be added from the PGOOD pin to

ground to divide the voltage detected by the PGOOD pin to a value no higher than 18 V.

8.2.2.14 Synchronization

The LM76002/LM76003 switching action can synchronize to an external clock from 300 kHz to 2.2 MHz. TI

recommends connecting an external clock to the SYNC pin with a 50-Ω to 100-Ω termination resistor. Ground the

SYNC pin if not used.

30

LM76002, LM76003

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ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

8.2.3 Application Curves

Unless otherwise specified the following conditions apply:

100

90

80

70

60

50

40

100

95

90

85

80

75

70

65

60

55

50

30

V_IN= 8 V

V_IN= 12 V

V_IN= 18 V

V_IN= 24 V

V_IN= 8 V

20

V_IN= 12 V

V_IN= 18 V

V_IN= 24 V

10

0

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D011

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 500 kHz

FPWM Mode

图 23. LM76003 Efficiency

图 24. LM76003 Efficiency

100

90

80

70

60

50

40

30

20

10

0

95

90

85

80

75

70

65

60

55

50

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D014

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

图 25. LM76003 Efficiency

图 26. LM76003 Efficiency

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D016

V_OUT= 5 V

f_SW= 1000 kHz

Auto Mode

V_OUT= 5 V

f_SW= 1000 kHz

FPWM Mode

图 27. LM76003 Efficiency

图 28. LM76003 Efficiency

31

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Unless otherwise specified the following conditions apply:

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

10

0

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D018

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

图 29. LM76003 Efficiency

图 30. LM76003 Efficiency

120

100

80

60

40

20

0

100

80

60

40

20

0

V_IN= 24 V

V_IN= 48 V

V_IN= 60 V

V_IN= 24 V

V_IN= 48 V

V_IN= 60 V

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D020

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

V_OUT= 12 V

f_SW= 500 kHz

FPWM Mode

图 31. LM76003 Efficiency

图 32. LM76003 Efficiency

120

100

80

60

40

20

0

120

100

80

60

40

20

0

V_IN= 32 V

V_IN= 48 V

V_IN= 60 V

V_IN= 32 V

V_IN= 48 V

V_IN= 60 V

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D022

V_OUT= 24 V

f_SW= 300 kHz

Auto Mode

V_OUT= 24 V

f_SW= 300 kHz

FPWM Mode

图 33. LM76003 Efficiency

图 34. LM76003 Efficiency

32

LM76002, LM76003

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ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Unless otherwise specified the following conditions apply:

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

10

0

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

Load Current (A)

2

2.5

3

D024

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

图 35. LM76002 Efficiency

图 36. LM76002 Efficiency

3.4

3.38

3.36

3.34

3.32

3.3

V_IN= 8 V

3.38

3.36

3.34

3.32

3.3

V_IN= 12 V

V_IN= 18 V

V_IN= 24 V

V_IN= 12 V

V_IN= 18 V

V_IN= 24 V

3.28

3.26

3.24

3.22

3.2

3.28

3.26

3.24

3.22

3.2

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D012

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_OUT= 3.3 V

f_SW= 500 kHz

FPWM Mode

图 37. LM76003 Load and Line Regulation

图 38. LM76003 Load and Line Regulation

5.2

5.16

5.12

5.08

5.04

5

5.1

5.08

5.06

5.04

5.02

5

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

4.96

4.92

4.88

4.84

4.8

4.98

4.96

4.94

4.92

4.9

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D015

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

图 39. LM76003 Load and Line Regulation

图 40. LM76003 Load and Line Regulation

33

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Unless otherwise specified the following conditions apply:

5.2

5.1

5.08

5.06

5.04

5.02

5

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

5.16

5.12

5.08

5.04

5

4.96

4.92

4.88

4.84

4.8

4.98

4.96

4.94

4.92

4.9

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D017

V_OUT= 5 V

f_SW= 1000 kHz

Auto Mode

V_OUT= 5 V

f_SW= 1000 kHz

FPWM Mode

图 41. LM76003 Load and Line Regulation

图 42. LM76003 Load and Line Regulation

5.2

5.1

5.08

5.06

5.04

5.02

5

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

5.16

5.12

5.08

5.04

5

4.96

4.92

4.88

4.84

4.8

4.98

4.96

4.94

4.92

4.9

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D019

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

图 43. LM76003 Load and Line Regulation

图 44. LM76003 Load and Line Regulation

12.4

12.35

12.3

12.4

12.35

12.3

V_IN= 24 V

V_IN= 48 V

V_IN= 60 V

V_IN= 24 V

V_IN= 48 V

V_IN= 60 V

12.25

12.2

12.25

12.2

12.15

12.1

12.15

12.1

12.05

12

12.05

12

11.95

11.9

11.95

11.9

11.85

11.8

11.85

11.8

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D021

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

V_OUT= 12 V

f_SW= 500 kHz

FPWM Mode

图 45. LM76003 Load and Line Regulation

图 46. LM76003 Load and Line Regulation

34

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Unless otherwise specified the following conditions apply:

24.5

24.4

24.3

24.2

24.1

24

V_IN= 32 V

V_IN= 48 V

V_IN= 60 V

V_IN= 32 V

V_IN= 48 V

V_IN= 60 V

24.4

24.3

24.2

24.1

24

23.9

23.8

23.7

23.6

23.9

23.8

23.7

23.6

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

2

Load Current (A)

2.5

3

3.5

4

D023

V_OUT= 24 V

f_SW= 300 kHz

Auto Mode

V_OUT= 24 V

f_SW= 300 kHz

FPWM Mode

图 47. LM76003 Load and Line Regulation

图 48. LM76003 Load and Line Regulation

5.2

5.16

5.12

5.08

5.04

5

5.1

5.08

5.06

5.04

5.02

5

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

4.96

4.92

4.88

4.84

4.8

4.98

4.96

4.94

4.92

4.9

0.001

0.01

0.1

Load Current (A)

1

5

0

0.5

1

1.5

Load Current (A)

2

2.5

3

D025

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

图 49. LM76002 Load and Line Regulation

图 50. LM76002 Load and Line Regulation

3.5

3.4

3.3

3.2

3.1

3

5.6

5.4

5.2

5

4.8

4.6

4.4

4.2

4

2.9

2.8

2.7

2.6

2.5

I_LOAD= 10 mA

I_LOAD= 1 A

I_LOAD= 2.5 A

I_LOAD= 3.5 A

I_LOAD= 10 mA

I_LOAD= 1 A

I_LOAD= 2.5 A

I_LOAD= 3.5 A

3.8

3

3.5

4

4.5

Input Voltage (V)

5

5.5

6

6.5

4.5

4.75

5

5.25

5.5

Input Voltage (V)

5.75

6

6.25

6.5

D026

D027

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

图 51. LM76003 Dropout Curve

图 52. LM76003 Dropout Curve

35

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Unless otherwise specified the following conditions apply:

5.6

5.4

5.2

5

5.4

5.2

5

4.8

4.6

4.4

4.8

4.6

4.4

4.2

4

I_LOAD= 10 mA

I_LOAD= 1 A

I_LOAD= 2.5 A

I_LOAD= 3.5 A

I_LOAD= 10 mA

I_LOAD= 1 A

I_LOAD= 2.5 A

I_LOAD= 3.5 A

4.2

4

3.8

4.5

4.75

5

5.25

5.5

Input Voltage (V)

5.75

6

6.25

6.5

4.5

4.75

5

5.25

5.5

Input Voltage (V)

5.75

6

6.25

6.5

D028

D029

V_OUT= 5 V

f_SW= 1000 kHz

Auto Mode

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

图 53. LM76003 Dropout Curve

图 54. LM76003 Dropout Curve

12.4

12.2

12

5.6

5.4

5.2

5

11.8

11.6

11.4

11.2

11

4.8

4.6

4.4

4.2

4

I_LOAD= 100 mA

I_LOAD= 1 A

I_LOAD= 2.5 A

I_LOAD= 3.5 A

I_LOAD= 100 mA

I_LOAD= 1 A

I_LOAD= 2.5 A

10.8

10.6

3.8

4.5

4.75

5

5.25

5.5

Input Voltage (V)

5.75

6

6.25

6.5

11.5

12

12.5

13 13.5

Input Voltage (V)

14

14.5

15

D030

D031

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

图 55. LM76002 Dropout Curve

图 56. LM76003 Dropout Curve

25

24.5

24

V_SW

(5 V/DIV)

I_INDUCTOR

23.5

23

(500 mA/

DIV)

V_OUT

I_LOAD= 100 mA

I_LOAD= 1 A

(20 mV/DIV)

22.5

I_LOAD= 2.5 A

I_LOAD= 3.5 A

Time (1 ms/DIV)

22

23.5

24

24.5

25 25.5

Input Voltage (V)

26

26.5

27

D032

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_OUT= 24 V

f_SW= 300 kHz

Auto Mode

图 57. LM76003 Dropout Curve

图 58. LM76003 Switching Waveform and Output Ripple

36

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Unless otherwise specified the following conditions apply:

V_SW

(5 V/DIV)

I_INDUCTOR

(500 mA/

DIV)

(500 mA/

DIV)

V_OUT

(20 mV/DIV)

Time (2 µs/DIV)

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

V_IN= 12 V

100-mA Load

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

图 59. LM76003 Switching Waveform and Output Ripple

图 60. LM76003 Switching Waveform and Output Ripple

Enable

(2 V/DIV)

V_SW

(5 V/DIV)

V_OUT

(2 V/DIV)

I_INDUCTOR

(500 mA/

DIV)

PGOOD

(2 V/DIV)

V_OUT

I_INDUCTOR

(20 mV/DIV)

(2 A/DIV)

Time (2 µs/DIV)

Time (5 ms/DIV)

V_IN= 12 V

100-mA Load

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

V_IN= 12 V

No Load

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

图 61. LM76003 Switching Waveform and Output Ripple

图 62. LM76003 Start-up Waveform

Enable

(2 V/DIV)

Enable

(2 V/DIV)

V_OUT

(2 V/DIV)

V_OUT

(2 V/DIV)

PGOOD

(2 V/DIV)

PGOOD

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

Time (5 ms/DIV)

V_IN= 12 V

No Load

V_OUT= 3.3 V

f_SW= 500 kHz

FPWM Mode

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

图 63. LM76003 Start-up Waveform

图 64. LM76003 Start-up Waveform

37

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Unless otherwise specified the following conditions apply:

Enable

(2 V/DIV)

Enable

(2 V/DIV)

V_OUT

(2 V/DIV)

V_OUT

(2 V/DIV)

PGOOD

(2 V/DIV)

PGOOD

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

Time (5 ms/DIV)

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

V_IN= 12 V

3.5-A Load

V_OUT= 3.3 V

f_SW= 500 kHz

图 65. LM76003 Start-up Waveform

图 66. LM76003 Start-up Waveform

Enable

(2 V/DIV)

Enable

(2 V/DIV)

V_OUT

(2 V/DIV)

V_OUT

(2 V/DIV)

PGOOD

(2 V/DIV)

PGOOD

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

Time (5 ms/DIV)

V_IN= 12 V

V_OUT= 5 V

f_SW= 500 kHz

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

3.5-A Load

图 67. Start-up Waveform

图 68. LM76002 Start-up Waveform

Enable

(2 V/DIV)

Enable

(2 V/DIV)

V_OUT

(2 V/DIV)

V_OUT

(2 V/DIV)

PGOOD

(2 V/DIV)

PGOOD

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

Time (5 ms/DIV)

V_IN= 12 V

2.5-A Load

V_OUT= 5 V

f_SW= 500 kHz

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

图 69. LM76002 Start-up Waveform

图 70. LM76003 Start-up With Pre-Biased Output

38

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Unless otherwise specified the following conditions apply:

V_OUT

Enable

(2 V/DIV)

(1 V/DIV)

V_OUT

(2 V/DIV)

I_INDUCTOR

(2 A/DIV)

PGOOD

(2 V/DIV)

V_SW

(5 V/DIV)

I_INDUCTOR

(2 A/DIV)

Time (5 ms/DIV)

Time (50 ms/DIV)

V_IN= 12 V

No Load

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

V_IN= 12 V

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

图 71. LM76002 Start-up With Pre-Biased Output

图 72. LM76003 Short-Circuit Behavior With Hiccup

I_LOAD

(2 A/DIV)

I_INDUCTOR

(2 A/DIV)

V_OUT

(200 mV/

DIV)

(200 mV/

DIV)

Time (100 µs/DIV)

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 500 kHz

Auto Mode

V_IN= 12 V

V_OUT= 3.3 V

f_SW= 500 kHz

FPWM Mode

10 mA to 3.5 A to 10 mA

图 73. LM76003 Load Transient

图 74. LM76003 Load Transient

I_LOAD

(2 A/DIV)

I_INDUCTOR

(2 A/DIV)

V_OUT

(200 mV/

DIV)

(200 mV/

DIV)

Time (100 µs/DIV)

V_IN= 12 V

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_IN= 12 V

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

10 mA to 3.5 A to 10 mA

图 75. LM76003 Load Transient

图 76. LM76003 Load Transient

39

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Unless otherwise specified the following conditions apply:

I_LOAD

(2 A/DIV)

I_INDUCTOR

(2 A/DIV)

V_OUT

(200 mV/

DIV)

(200 mV/

DIV)

Time (100 µs/DIV)

V_IN= 12 V

V_OUT= 5 V

f_SW= 1000 kHz

Auto Mode

V_IN= 12 V

V_OUT= 5 V

f_SW= 1000 kHz

FPWM Mode

10 mA to 3.5 A to 10 mA

图 77. LM76003 Load Transient

图 78. LM76003 Load Transient

I_LOAD

(2 A/DIV)

I_INDUCTOR

(2 A/DIV)

V_OUT

(200 mV/

DIV)

(200 mV/

DIV)

Time (100 µs/DIV)

V_IN= 12 V

V_OUT= 5 V

f_SW= 2200 kHz

Auto Mode

V_IN= 12 V

V_OUT= 5 V

f_SW= 2200 kHz

FPWM Mode

10 mA to 3.5 A to 10 mA

图 79. LM76003 Load Transient

图 80. LM76003 Load Transient

I_LOAD

(2 A/DIV)

I_INDUCTOR

(2 A/DIV)

V_OUT

(500 mV/

DIV)

(500 mV/

DIV)

Time (100 µs/DIV)

V_IN= 24 V

V_OUT= 12 V

f_SW= 500 kHz

Auto Mode

V_IN= 24 V

V_OUT= 12 V

f_SW= 500 kHz

FPWM Mode

10 mA to 3.5 A to 10 mA

图 81. LM76003 Load Transient

图 82. LM76003 Load Transient

40

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Unless otherwise specified the following conditions apply:

I_LOAD

(1 A/DIV)

I_INDUCTOR

(2 A/DIV)

V_OUT

(200 mV/

DIV)

(200 mV/

DIV)

Time (100 µs/DIV)

V_IN= 12 V

V_OUT= 5 V

f_SW= 500 kHz

Auto Mode

V_IN= 12 V

V_OUT= 5 V

f_SW= 500 kHz

FPWM Mode

10 mA to 2.5 A to 10 mA

图 83. LM76002 Load Transient

图 84. LM76002 Load Transient

41

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

9 Power Supply Recommendations

The LM76002/LM76003 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This

input supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the LM76002 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the LM76002/LM76003 additional bulk capacitance

may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but

a 47-µF or 100-µF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

The performance of any switching converter depends as much upon the layout of the PCB as the component

selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and

minimum generation of unwanted EMI.

1. Place ceramic high frequency bypass C_INas close as possible to the LM76002/LM76003 PVIN and PGND

pins. Grounding for both the input and output capacitors should consist of localized top side planes that

connect to the PGND pins and PAD.

2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device

ground.

3. Minimize trace length to the FB pin. Both feedback resistors, R_FBTand R_FBBmust be located close to the FB

pin. Place C_FFdirectly in parallel with R_FBT. If V_OUTaccuracy at the load is important, make sure V_OUTsense

is made at the load. Route V_OUTsense path away from noisy nodes and preferably through a layer on the

other side of a shielding layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. Have a single

point ground connection to the plane. Route the ground connections for the feedback, soft start, and enable

components to the ground plane. This prevents any switched or load currents from flowing in the analog

ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output

voltage ripple behavior.

5. Make V_IN, V_OUTand ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

6. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125°C.

10.1.1 Layout Highlights

1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the

high di/dt paths during PC board layout as shown in the figure above. The high current loops that do not

overlap have high di/dt content that causes observable high frequency noise on the output pin if the input

capacitor C_INis placed at a distance away from the LM76002/LM76003. Therefore, place C_INas close as

possible to the LM76002/LM76003 PVIN and PGND pins. This minimizes the high di/dt area and reduce

radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top-

side plane that connects to the PGND pin.

2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components

should be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in

the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior.

3. Minimize trace length to the FB pin net. Place both feedback resistors, R_FBTand R_FBB, close to the FB pin.

Because the FB node is high impedance, maintain the copper area as small as possible. Route the traces

from R_FBT, R_FBBaway from the body of the LM76002/LM76003 to minimize possible noise pickup. Place C_ff

directly in parallel with R_FBT

.

4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a

42

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

Layout Guidelines (接下页)

separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provide

optimum output accuracy.

5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array (or greater)

with a minimum via diameter of 12 mil thermal vias spaced 46.8 mil apart. Ensure enough copper area is

used for heat-sinking to keep the junction temperature below 125°C.

10.1.2 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to

minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck

converters, the pulsing current path is from the V_INside of the input capacitors to HS switch, to the LS switch,

and then return to the ground of the input capacitors, as shown in 图 85.

BUCK

CONVERTER

L

PVIN

V_IN

C_IN

SW

V_OUT

C_OUT

PGND

High di/dt current

图 85. Buck Converter High di / dt Path

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the PVIN and PGND pins is the

key to EMI reduction. The SW pin connecting to the inductor should be as short as possible, and just wide

enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) should

be used for high current condution path to minimize parasitic resistance. The output capacitors should be place

close to the V_OUTend of the inductor and closely grounded to PGND pin and exposed PAD. Place the bypass

capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely grounded to PGND

and the exposed PAD.

10.1.3 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are

connected to the source of the internal LS switch; connect the PGND pins directly to the grounds of the input and

output capacitors. The PGND net contains noise at the switching frequency and may bounce due to load

variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the ground

plane. The other side of the ground plane contains much less noise — use for sensitive routes.

Provide adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a

minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat sinking.

Distribute the vias evenly under the PAD. Use as much copper as possible for system ground plane on the top

and bottom layers for the best heat dissipation. TI recommends using a four-layer board with the copper

thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough

copper thickness and proper layout provides low current conduction impedance, proper shielding and lower

thermal resistance.

The thermal characteristics of the LM76002/LM76003 are specified using the parameter R_θJA, which characterize

the junction temperature of the silicon to the ambient temperature in a specific system. Although the value of R_θJA

is dependant on many variables, it still can be used to approximate the operating junction temperature of the

device.

To obtain an estimate of the device junction temperature, one may use the following relationship:

43

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

Layout Guidelines (接下页)

T_J= P_D× R_θJA+ T_A

where

•

T_J= junction temperature in °C

P_D= V_IN× I_IN× (1 − efficiency) − 1.1 × I_OUT× DCR

DCR = inductor DC parasitic resistance in Ω

R_θJA= junction-to-ambient thermal resistance of the device in °C/W

T_A= ambient temperature in °C.

(31)

The maximum operating junction temperature of the LM76002/LM76003 is 125°C. R_θJAis highly related to PCB

size and layout, as well as environmental factors such as heat sinking and air flow. 图 86 shows measured

results of R_θJAwith different copper area on a 2-layer board and a 4-layer board.

30

1W @0 fpm - 2layer

28

1W @0 fpm - 4layer

26

2W @0 fpm - 2layer

2W @0 fpm - 4layer

24

22

20

18

16

14

12

10

20

30

30mm × 30mm

40

40mm × 40mm

50

50mm × 50mm

60

70

80

70mm ×70mm

Copper Area

图 86. Measured R_θJAvs PCB Copper Area on a 2-Layer Board and a 4-Layer Board

10.1.4 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

C_FFclose to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider and C_FFcloser to the FB pin reduces the

trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace

from V_OUTto the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to

the feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most

important when high value resistors are used to set the output voltage. TI recommends routing the voltage sense

trace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in between

the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage

feedback path from switching noises.

44

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

10.2 Layout Example

图 87. LM76002/LM76003 Layout

45

LM76002, LM76003

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

www.ti.com.cn

10.3 Thermal Design

When calculating module dissipation use the maximum input voltage and the average output current for the

application. Many common operating conditions are provided in the characteristic curves such that less common

applications can be derived through interpolation. In all designs, the junction temperature must be kept below the

rated maximum of 125°C. For the design case of V_IN= 12 V, V_OUT= 5 V, I_OUT= 3.5 A, f_SW= 2100 kHz, and T_A-

_MAX= 85°C, the device must detect a thermal resistance from exposed pad (case) to ambient (R_θCA):

T_J-MAX- T_A-MAX

R_qCA

<

- R_qCA

P

IC_LOSS

(32)

The typical thermal impedance from junction to case is 1.7°C/W. Use the 125°C power dissipation curves in

Typical Characteristics section to estimate the P_IC-LOSSfor the application being designed. In this application it is

3 W. The inductor losses must be subtracted from this number and can be estimated as:

125èC- 85èC

2.75 W

R_qCA

<

- 1.7èC/W < 12.84èC/W

(33)

To reach R_θCA= 12.84°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external

heat-sink, a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal

layers is:

500

èC ì cm²

Board Area_cm²Ç

ì

R_qCA

W

(34)

As a result, approximately 38.95 square cm of 2 oz. copper on top and bottom layers is the minimum required

area for the example PCB design. This is a 6.25 cm (2.45 inch) square. The PCB copper heat sink must be

connected to the pins of the device and to the exposed pad with multiple thermal vias to the bottom copper. For

an example of a high thermal performance PCB layout refer to AN-2020 Thermal Design By Insight, Not

Hindsight and the evaluation board documentation.

46

LM76002, LM76003

www.ti.com.cn

ZHCSH05A –OCTOBER 2017–REVISED OCTOBER 2019

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，以使用 LM76002 或 LM76003 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

47

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM76002RNPR

LM76002RNPT

LM76003RNPR

LM76003RNPT

WQFN

RNP

30

3000

250

330.0

180.0

330.0

180.0

16.4

4.25

6.25

0.95

8.0

16.0

Q1

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM76002RNPR

LM76002RNPT

LM76003RNPR

LM76003RNPT

WQFN

RNP

30

3000

250

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

38.0

35.0

38.0

35.0

3000

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RNP 30

4 x 6, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225831/A

www.ti.com

PACKAGE OUTLINE

RNP0030B

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

6.1

5.9

0.1 MIN

(0.05)

E

SCAL

C

T

SECTION A-A

TYPICAL

0.8 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

1.8 0.1

2X 1.5

(0.2) TYP

EXPOSED

THERMAL PAD

12

15

26X 0.5

11

16

SYMM

31

A

2X

5

4.5 0.1

1

26

0.3

30

27

30X

PIN 1 ID

(OPTIONAL)

0.2

0.1

0.05

SYMM

0.5

0.3

8X

C A B

C

0.65

0.45

22X

4222784/B 09/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RNP0030B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.8)

SYMM

8X (0.6)

30

27

22X (0.75)

1

26

30X (0.25)

(0.5) TYP

SYMM

(1.14)

TYP

31

(5.8)

(4.5)

(0.57)

(R0.05) TYP

(

0.2) TYP

VIA

16

11

12

(0.65) TYP

15

(3.65)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222784/B 09/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNP0030B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

8X (0.8)

27

8X (0.6)

30

22X (0.75)

1

26

31

30X (0.25)

8X

(0.94)

26X (0.5)

SYMM

(5.8)

(0.57)

TYP

(1.14)

TYP

METAL

TYP

16

11

(R0.05) TYP

12

15

SYMM

(0.5) TYP

(3.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 31:

74.3% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222784/B 09/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	LM76002
厂家：	TEXAS INSTRUMENTS
描述：	3.5V 至 60V、2.5A 同步降压转换器转换器
文件：	总56页 (文件大小：3301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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