LM76202-Q1 [TI]

具有集成 FET 的 4.2V 至 60V、2.2A 300uA IQ 汽车理想二极管;


型号：	LM76202-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有集成 FET 的 4.2V 至 60V、2.2A 300uA IQ 汽车理想二极管二极管
文件：	总37页 (文件大小：2277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

具有过压和过流保护的 LM76202-Q1 60V、2.2A 集成式理想二极管

1 特性

3 说明

•

符合面向汽车应用的 AEC-Q100 标准

LM76202-Q1 器件是一款功能丰富的紧凑型 60V 集成

式理想二极管，具有一整套保护特性。宽电源输入范

围允许控制 12V 和 24V 汽车电池驱动应用。此器件

可以承受并保护由高达 ±60V 的正负电源供电的负载。

负载、电源和器件保护还具有许多可编程特性，包括

过流保护、浪涌电流控制、过压保护和欠压阈值保护。

此器件内部可靠的保护控制模块以及 60V 额定电压简

化了针对 ISO 标准脉冲测试的系统设计。

–

温度等级 1：–40°C ≤ T_A≤ +125°C

AEC-Q100-012 A 级短路可靠性

HBM ESD 分类等级 2

CDM ESD 分类等级 C6

•

4.2V 至 60V 工作电压，最大值 62V

集成反向输入极性保护，低至 -60V

总 RON 为 150mΩ 的集成背对背 MOSFET

高达 65V 的瞬态抗扰度

借助关断引脚，可以从外部控制内部 FET 的启用和禁

用，还可以将器件置于低电流关断模式。为实现系统状

态监视和下游负载控制，此器件提供故障输出和精密电

流监视输出。MODE 引脚可用于在三种电流限制故障

响应（断路器、闭锁以及自动重试模式）之间灵活地对

器件进行配置。此器件可监视 V_(IN)和 V_(OUT)，以便在

V(IN) < (V(OUT)-10mV) 时提供反向电流阻断。该功能

可在输出端发生电池短路故障期间保护系统总线不受过

压影响，并且有助于在电源故障和欠压条件下满足保持

电压的要求。

0.1A 至 2.23A 可调节电流限制

（1A 时精确度为 ±5%）

•

ISO7637 和 ISO16750-2 测试期间的负载保护

电池短路和接地短路保护

反向电流阻断，可提供输出对电池短路保护

IMON 电流指示器输出（精度为 ±8.5%）

低静态电流（工作时为 285µA，关断时为 16µA）

可调节的 UVLO、OVP 切断、浪涌电流控制

出厂设置 38V 过压钳位选项

可选电流限制故障响应选项（自动重试、闭锁、CB

模式）

此器件采用 5mm × 4.4mm 16 引脚 HTSSOP，额定工

作温度范围为 -40°C 至 +125°C。

•

采用易于使用的 16 引脚 HTSSOP 封装

器件信息⁽¹⁾

2 应用

器件型号

封装

封装尺寸（标称值）

•

前置摄像头，后置摄像头

LM76202-Q1

HTSSOP (16)

5.00mm x 4.40mm

驾驶辅助 ECU

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

远程信息处理控制单元

蜂窝式模块资产跟踪

24V 条件下的 ISO16750-2 负载突降脉冲 5b 性能

简化原理图

V_OUT

C_OUT

OUT

150 mΩ

C_IN

R_FLTb

R₁

UVLO

OVP

FLT

Health Monitor

ON/OFF Control

Load Monitor

LM76202-Q1

V_IN

SHDN

dVdT

R₂

TVS

IMON

ILIM

MODE

RTN

GND

R_IMON

R_ILIM

C_dVdT

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSEM1

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.4 Device Functional Modes........................................ 24

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Application ................................................. 25

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Typical Characteristics.............................................. 8

Parameter Measurement Information ................ 11

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

10 Power Supply Recommendations ..................... 29

10.1 Transient Protection.............................................. 29

11 Layout................................................................... 30

11.1 Layout Guidelines ................................................. 30

11.2 Layout Example .................................................... 31

12 器件和文档支持 ..................................................... 32

12.1 文档支持................................................................ 32

12.2 接收文档更新通知 ................................................. 32

12.3 社区资源................................................................ 32

12.4 商标....................................................................... 32

12.5 静电放电警告......................................................... 32

12.6 Glossary................................................................ 32

13 机械、封装和可订购信息....................................... 32

4 修订历史记录

Changes from Original (March 2019) to Revision A

Page

•

将“预告信息”更改为“生产数据” ............................................................................................................................................... 1

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP With Exposed Thermal Pad

Top View

OUT

FLT

UVLO

PowerPAD™

Integrated Circuit

Package

dVdT

ILIM

OVP

MODE

IMON

GND

SHDN

RTN

Pin Functions

NAME

TYPE

DESCRIPTION

NO.

1, 2

Input supply voltage. See IN, OUT, RTN and GND Pins section.

Input for setting the programmable Undervoltage Lockout threshold. An undervoltage event

turns off the internal FET and asserts FLT to indicate power failure. If the Undervoltage

Lockout function is not needed, the UVLO terminal must be connected to the IN terminal.

See Undervoltage Lockout (UVLO) section.

UVLO

—

No internal connection. These pins can be connected to RTN for enhanced thermal

performance.

4, 13 NC

Input for setting the programmable Overvoltage Protection threshold. An overvoltage event

turns off the internal FET and asserts FLT to indicate the overvoltage fault. For fixed

overvoltage clamp response connect OVP to RTN externally. See Overvoltage Protection

(OVP) section.

OVP

MODE

SHDN

Mode selection pin for overload fault response. See the Device Functional Modes section.

Shutdown pin. Pulling SHDN low enters the device into low-power shutdown mode. Cycling

SHDN pin voltage resets the device that has latched off due to a fault condition. See Low

Current Shutdown Control (SHDN) section.

Reference for device internal control circuits. If reverse input polarity protection is not

required, this pin can be connected to GND. See IN, OUT, RTN and GND Pins section.

RTN

GND

—

Connect GND to system ground. See IN, OUT, RTN and GND Pins section.

Analog current monitor output. This pin sources a scaled down ratio of current through the

internal FET. A resistor from this pin to RTN converts current to proportional voltage. If pin is

unused, leave pin floating. See Current Monitoring section.

IMON

A resistor from this pin to RTN sets the overload and short-circuit current limit. See the

Overload and Short Circuit Protection section.

ILIM

dVdT

FLT

I/O

A capacitor from this pin to RTN sets output voltage slew rate. See the Hot Plug-In and In-

Rush Current Control section.

Fault event indicator. Indicator is an open drain output. If indicator is unused, leave indicator

floating. See FAULT Response section.

15,16 OUT

PowerPAD

Power output of the device. See IN, OUT, RTN and GND Pins section.

PowerPAD integrated circuit package must be connected to RTN plane on PCB using

multiple vias for enhanced thermal performance. PowerPAD is not internally connected to

RTN. Do not use the PowerPAD as the only electrical connection to RTN.

—

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

IN, IN-OUT

-62

-65

-0.3

-62

IN, IN-OUT (350ms transient), T_A= 25°C

[IN, OUT, FLT, UVLO, SHDN] to RTN

[OVP, dVdT, ILIM, IMON, MODE] to RTN

RTN

0.3

I_FLT, I_dVdT, I_SHDN

Sink current

Internally

limited

Internally

limited

I_dVdT, I_ILIM, I_IMON

Source Current

Operating junction temperature

Transient junction temperature

Storage Temperature

-40

-65

150

T_(TSD)

150

°C

T_J

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model

All pins

±1000

(CDM), per AEC Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

-60

NOM

MAX

UNIT

UVLO, OUT, FLT

Input voltage range

Resistance

OVP, dVdT, ILIM, IMON, SHDN

ILIM

5.36

120

kΩ

IMON

IN, OUT

dVdT

T_J

0.1

-40

µF

°C

External capacitance

Operating junction temperature range

125

6.4 Thermal Information

LM76202-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

16 PINS

38.6

22.7

18.2

0.5

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Y_JB

R_θJC(bot)

1.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

6.5 Electrical Characteristics

–40°C ≤ T_A= T_J≤ +125°C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF,

C_(dVdT)= OPEN.

(All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE

V_(IN)

Operating input voltage

4.2

3.89

4.14

305

V_PORR

Internal POR Threshold, Rising

Internal POR Hysteresis

V_PORHys

275

VIN = 24V,

Enabled: V_(SHDN)= 2 V

IQ_ON

Supply Current with device enabled

300

285

398

390

µA

VIN = 12V

Enabled: V_(SHDN)= 2 V,

IQ_OFF

I_VINR

Supply Current with device disabled

Reverse Input supply current

VIN = 24V, V_(SHDN)= 0 V

VIN = 12V, V_(SHDN)= 0 V

V_(IN)= -60 V, V_(OUT)= 0 V

µA

UNDERVOLTAGE LOCKOUT (UVLO) INPUT

V_(UVLOR)

I_(UVLO)

UVLO Threshold Voltage, Rising

UVLO Threshold Voltage, Falling

UVLO Input leakage current

1.175

1.08

1.19

1.1

1.25

1.126

100

0 V ≤ V_(UVLO)≤ 60 V

–100

LOW IQ SHUTDOWN (SHDNb) INPUT

V_(SHDN)

Output voltage

I_(SHDN)= 0.1µA

2.7

3.4

SHDN Threshold Voltage for Low

IQ Shutdown, Falling

V_(SHUTF)

0.45

V_(SHUTFR)

I_(SHDN)

SHDN Threshold, Rising

Input current

0.96

V_(SHDN)= 0.4 V

-10

µA

OVER VOLTAGE PROTECTION (OVP) INPUT

Factory Set OV Clamp Select

V_{(SEL_OVP)}

Threshold

180

200

37.5

1.19

240

V_OVC

Internal Over voltage clamp

V_(IN)> 42 V, I_(OUT)=10mA V_(OVP)= 0 V

Over-Voltage Threshold Voltage,

Rising

V_(OVPR)

1.175

1.225

Over-Voltage Threshold Voltage,

Falling

V_(OVPF)

I_(OVP)

1.085

–100

1.125

100

OVP Input Leakage Current

0V ≤ V_(OVP)≤ 4V

OUTPUT RAMP CONTROL (dVdT)

I_(dVdT)

dVdT Charging Current

V_(dVdT)= 0 V

4.7

5.82

25.5

µA

SHDN = 0 V, with I_(dVdT)= 10mA

sinking

R_(dVdT)

dVdT Discharging Resistance

dVdT to OUT Gain

GAIN_(dVdT)

△V_(OUT)/△V_(dVdT)

23.75

24.63

V/V

CURRENT LIMIT PROGRAMMING (ILIM)

V_(ILIM)

ILIM Bias Voltage

0.1

R_(ILIM)= 120 kΩ, V_(IN)-V_(OUT)=1V

R_(ILIM)= 12 kΩ, V_(IN)-V_(OUT)=1V

R_(ILIM)= 8 kΩ, V_(IN)-V_(OUT)=1V

R_(ILIM)= 5.36 kΩ, V_(IN)-V_(OUT)=1V

0.085

0.95

0.115

1.05

I_(OL)

1.425

2.11

1.5

2.23

1.575

2.35

Overload Current Limit

R_(ILIM)= OPEN, Open Resistor Current

Limit

I_{(OL_R-OPEN)}

I_{(OL_R-SHORT)}

0.055

0.095

R_(ILIM)= SHORT, Shorted Resistor

Current Limit

I_(CB)

Circuit breaker detection threshold

R_(ILIM)= 120 kΩ, MODE = open

R_(ILIM)= 5.36 kΩ, MODE = open

0.045

0.073

2.21

0.11

2.4

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

–40°C ≤ T_A= T_J≤ +125°C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF,

C_(dVdT)= OPEN.

(All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

R_(ILIM)= 120 kΩ, V_(IN)-V_(OUT)=5V

R_(ILIM)= 8 kΩ, V_(IN)-V_(OUT)=5V

R_(ILIM)= 5.36 kΩ, V_(IN)-V_(OUT)=5V

MIN

0.08

TYP

0.1

MAX UNIT

0.12

1.575

2.35

I_(SCL)

Short-Circuit Current Limit

1.425

2.11

1.5

2.23

1.87 x

I_(FASTRIP)

Fast-trip comparator threshold

I_(OL)

0.015

CURRENT MONITOR OUTPUT (IMON)

GAIN_(IMON)Gain Factor I_(IMON):I_(OUT)

PASS FET OUTPUT (OUT)

0.1A ≤ I_(OUT)≤ 2A

130

78.28

85 µA/A

0.1A ≤ I_(OUT)≤ 2A,T_J= 25°C

150

168

R_ON

IN to OUT Total ON Resistance

0.1A ≤ I_(OUT)≤ 2A_,-40°C ≤ T_J≤ 85°C

0.1A ≤ I_(OUT)≤ 2A_,-40°C ≤ T_J≤ 125°C

220

265

mΩ

V_(IN)= 60 V, V_(SHDN)= 0 V, V_(OUT)= 0

V, Sourcing

I_lkg(OUT)

OUT Leakage Current in Off State

µA

V_(IN)= 0 V, V_(SHDN)= 0 V, V_(OUT)= 24

V, Sinking

-11

-40

I_lkg(OUT)

µA

V_(IN)= -60 V, V_(SHDN)= 0 V, V_(OUT)= 0

V, Sinking

-18

-10

V_(IN)-V_(OUT)Threshold for Reverse

Protection Comparator, Falling

V_(REVTH)

V_(FWDTH)

-16.2

-5

V_(IN)-V_(OUT)Threshold for Reverse

Protection Comparator, Rising

110

FAULT FLAG (FLTb): ACTIVE LOW

R_(FLT)FLT Pull-Down Resistance

I_(FLT)FLT Input Leakage Current

THERMAL SHUT DOWN (TSD)

V_(OVP)= 2 V, I_(FLT)= 5mA sinking

350

0 V ≤ V_(FLT)≤ 60 V

–200

200

TSD Threshold, rising

157

°C

T_(TSD)

TSD hysteresis

10.1

MODE

MODE = 402 kΩ to RTN

Current limiting with latch

Circuit breaker mode with

auto-retry

MODE = Open

MODE_SEL

Thermal fault mode selection

Current limiting with auto-

retry

MODE = Short to RTN

6.6 Timing Requirements

–40°C ≤ T_A= T_J≤ +125°C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF,

C_(dVdT)= OPEN.

(All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

UVLO INPUT

UVLO↑ (100mV above V_(UVLOR)) to V_(OUT)= 100mV,

C_(dvdt)= Open

UVLO_t_ON(dly)

UVLO Turn On Delay

µs

80+14.

5 x

C_(dvdt)

UVLO↑ (100mV above V_(UVLOR)) to V_(OUT)= 100mV,

UVLO_t_ON(dly)

UVLO_t_off(dly)

C_(dvdt)≥ 10 nF, [C_(dvdt)in nF]

UVLO Turn-Off delay

UVLO↓ (100mV below V_(UVLOF)) to FLT ↓

SHUTDOWN INPUT

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

Timing Requirements (continued)

–40°C ≤ T_A= T_J≤ +125°C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF,

C_(dVdT)= OPEN.

(All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

350+14

.5 x

C_(dvdt)

SHDN ↑ (above V_(SHUTR)to V_(OUT)= 100mV,

SHDN_t_on(dly)

C_(dvdt)≥ 10 nF, [C_(dvdt)in nF]

SHUTDOWN Exit delay

µs

SHDN ↑ (above V_(SHUTR)to V_(OUT)= 100mV, C_(dvdt)

Open

SHDN_t_on(dly)

355

SHUTDOWN Entry delay SHDN_t_off(dly)

SHDN ↓ (below V_(SHUTF)to FLT ↓

OVP INPUT

OVP Exit delay

t_OVP(dly)

OVP ↓(20mV below V_(OVPF)) to V_(OUT)= 100mV

OVP↑ (20mV above V_(OVPR)) to FLT ↓

205

µs

OVP Disable delay

V_(IN)step from 24V to 60V in 50µs, Iload: 10mA, C_L:

0.1uF. OVP connected to RTN

OVP clamp delay

t_OVC(dly)

µs

CURRENT LIMIT

Fast-Trip Comparator

Delay

t_{FASTTRIP(dly)}

I_(OUT)= 1.5x I_(FASTRIP)

170

REVERSE CURRENT BLOCKING COMPARATOR

(V_(IN)-V_(OUT)) ↓ (100mV overdrive below V_(REVTH)) to

internal FET OFF

1.29

µs

t_REV(dly)

(V_(IN)-V_(OUT)) ↓ (10mV overdrive below V_(REVTH)) to

FLT ↓

RCB comparator delay

(V_(IN)-V_(OUT)) ↑ (10mV overdrive above V_(FWDTH)) to

FLT ↑

t_FWD(dly)

THERMAL SHUTDOWN

Retry Delay in TSD

t_retry

540

OUTPUT RAMP TIME

SHDN↑ to V_(OUT)= V_(IN)

1.6

Output Ramp Time

t_dVdT

SHDN↑ to V_(OUT)= V_(IN), with C_(dVdT)= 47nF

FAULT FLAG

FLT assertion delay in

circuit breaker mode

MODE = OPEN,Delay from I_(out)>I_(lim)to FLT ↓(and

internal FET turned off)

t_CB(dly)

Retry Delay in circuit

breaker mode

MODE= OPEN, C_(dVdT)= Open. I_(out)>I_(lim).Delay

from FLT ↓ to V_(dVdT)= 50mV (Rising)

t_CBretry(dly)

540

t_PGOODR

t_PGOODF

Delay for rising FLT edge

Delay for falling FLT edge

1.8

µs

PGOOD delay time

900

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

6.7 Typical Characteristics

T_A= 25 °C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF, C_(dVdT)= OPEN.

(Unless otherwise noted)

4.2

4.05

3.9

306

303

300

297

294

291

288

285

282

279

276

273

270

267

264

POR Threshold Rising (V)

POR Threshold Falling (V)

3.75

3.6

3.45

-60

-30

30 60

Temperature (°C)

120

150

10 15 20 25 30 35 40 45 50 55 60

Supply Voltage (V)

D001

D002

图 1. POR Threshold (V_POR) vs Temperature

图 2. Supply Current ON (IQ_ON) vs Supply Voltage (V_IN)

1.3

UVLO Threshold Rising (V)

UVLO Threshold Falling (V)

1.25

1.2

1.15

1.1

1.05

10 15 20 25 30 35 40 45 50 55 60

Supply Voltage (V)

-40

40 80

Temperature (°C)

120

160

D003

D004

图 3. Supply Current OFF (IQ_OFF) vs Supply Voltage (V_IN

)

图 4. UVLO Thresholds (V_UVLOR, V_UVLOF) vs Temperature

1.28

24.52

OVP Threshold Rising (V)

OVP Threshold Falling (V)

1.24

24.54

24.56

24.58

24.6

1.2

1.16

1.12

1.08

1.04

24.62

-40

40 80

Temperature (°C)

120

160

-50

-25

25 50

Temperature (°C)

100

125

D005

D006

图 5. OVP Thresholds (V_OVPR, V_OVPF) vs Temperature

图 6. GAIN_(dVdT)vs Temperature

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

Typical Characteristics (接下页)

T_A= 25 °C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF, C_(dVdT)= OPEN.

(Unless otherwise noted)

2.5

R_ILIM= 120k

R_ILIM= 12k

R_ILIM= 5.37k

1.5

0.5

50 75

R_ILIM(kOhm)

100

125

10 15 20 25 30 35 40 45 50 55 60

VIN (V)

D007

Dg0ra0p8

T_A= -40 to 125 °C

图 7. I_LIMvs R_ILIM

图 8. I_LIMAccuracy vs Supply Voltage

4.5

79.25

R_ILIM= 120k

R_ILIM= 12k

R_ILIM= 5.37k

78.75

78.5

78.25

3.5

2.5

77.75

77.5

77.25

1.5

0.5

76.75

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

D009

D010

图 9. I_LIMAccuracy vs Temperature with V_IN= 12 V

图 10. GAIN_(IMON)vs Temperature

180

240

220

200

180

160

140

120

100

160

140

120

100

0.25 0.5 0.75

1 1.25 1.5 1.75

I_OUT(A)

2.25

-40

-20

40 60

Temperature (°C)

100 120 140

D011

D012

图 11. I_MONvs I_OUT

图 12. R_ONvs Temperature

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Typical Characteristics (接下页)

T_A= 25 °C, V_(IN)= 12 V, V_(SHDN)= 2 V, R_(ILIM)= 120 kΩ, IMON = FLT = OPEN, C_(IN)= 0.1 μF, C_(OUT)= 1 μF, C_(dVdT)= OPEN.

(Unless otherwise noted)

-4

-4.5

-5

-5.5

-6

-6.5

-7

-5.5

-6

-7.5

-8

-6.5

-7

-8.5

-9

-7.5

-8

-9.5

-10

-10.5

-8.5

-9

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

D013

D014

V_(OUT)= 24 V

V_(IN)= 0 V

V_SHDN= 0 V

V_(OUT)= 0 V

V_(IN)= –24 V

V_SHDN= 0 V

图 13. I_lkg(OUT)vs Temperature with V_IN= 0 V

图 14. I_lkg(OUT)vs Temperature with V_IN= –24 V

11.6

11.4

11.2

95.4

95.2

94.8

94.6

94.4

94.2

10.8

10.6

10.4

10.2

93.8

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

D015

D016

图 15. V_REVTHvs Temperature

图 16. V_FWDTHvs Temperature

4.5

100000

10000

1000

100

R_ILIM= 120k

R_ILIM= 12k

R_ILIM= 5.37k

T_A= -40 èC

T_A= 25 èC

T_A= 85 èC

T_A= 105 èC

T_A= 125 èC

3.5

2.5

1.5

0.5

0.2

-40

-20

40 60

Temperature (°C)

100 120 140

5 6 7 8 10

Power Dissipation (W)

20 30 40 50 70 100

D017

D018

Taken on 2-layer PCB with 0.07-mm thick copper and copper area of

10.5 cm²connected to PowerPAD.

图 17. I_LIMAccuracy vs Temperature with V_IN= 24 V

图 18. Thermal Shutdown Time vs Power Dissipation

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

7 Parameter Measurement Information

V_(OUT)

V_UVLO

V_(UVLOF)-0.1 V

0.1 V

V_UVLO

FLT

V_(UVLOR)+0.1V

10%

time

UVLO_t_ON(dly)

UVLO_t_off(dly)

-20 mV

110 mV

V_{(IN) -}V_(OUT)

90%

FLT

10%

time

t_REV(dly)

time

t_FWD(dly)

I_(FASTRIP)

V_(OVPR)+0.1V

V_(OVP)

I_(SCL)

I_(OUT)

FLT

10%

time

t_OVP(dly)

t_FASTRIP(dly)

图 19. Timing Waveforms

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8 Detailed Description

8.1 Overview

LM76202-Q1 is an ideal diode with integrated back-to-back FETs and enhanced built-in protection circuitry. It

provides robust protection for all systems and applications powered from 4.2 V to 60 V. The device integrates

reverse battery input, reverse current, overvoltage, undervoltage, overcurrent and short circuit protection. The

precision overcurrent limit (±5% at 1A) helps to minimize over design of the input power supply, while the fast

response short circuit protection immediately isolates the load from input when a short circuit is detected. The

device allows the user to program the overcurrent limit threshold between 0.1 A and 2.23 A with an external

resistor. The device monitors the bus voltage for brown-out and overvoltage protection, asserting the FLTb pin to

notify downstream systems.

The device is designed to protect systems such as ADAS camera supplies against sudden output short to battery

events. The device monitors V(IN) and V(OUT) to provide true reverse blocking from output when output short to

battery fault condition or input power fail condition is detected. The internal robust protection control blocks of the

LM76202-Q1 device along with its ±60 V rating helps to simplify the system designs for the various ISO and

LV124 compliance ensuring complete protection of the load and the device.

The device monitors V_(IN)and V_(OUT)to provide true reverse current blocking when a reverse condition or input

power failure condition is detected. The LM76202-Q1 device is also designed to control redundant power supply

systems.

Additional features of the LM76202-Q1 device include:

•

Reverse input battery protection

Reverse current blocking

Current monitor output for health monitoring of the system

Electronic circuit breaker operation with overload timeout using MODE pin

A choice of latch off or automatic restart mode response during current limit fault using MODE pin

Over temperature protection to safely shutdown in the event of an overcurrent event

De-glitched fault reporting for brown-out and overvoltage faults

Look ahead overload current fault indication (see the Look Ahead Overload Current Fault Indicator section)

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

8.2 Functional Block Diagram

OUT

150 mΩ

-10 mV

PORb

Charge

Pump

+100 mV

4 V

3.72 V

X78.2 µ

Current

Sense

UVLOb

UVLO

1.19 V

1.1 V

REVERSE

SWEN

Gate Control Logic

IMON

Current Limit Amp

TSD

Thermal

Shutdown

Fast-Trip Comp

(Threshold=1.8 x I_OL)

1.19 V

1.1 V

OVP

1 V

OLR

V_{SEL_OVP}

SHDNb

Over Voltage clamp detect

24.6 x

ILIM

OVP

Short detect

Ramp Control

SWEN

Avdd

FLT

I_(LOAD)≥ I_(CB)

* Only for Latch Mode

OLR

SET

Timeout

5 µA

4 msec

timer

dVdT

RTN

85 Ω

UVLOb

PORb

TSD

CLR

1.8 msec

900 µs

R_dVdT

PORb

Fault Latch

Avdd

SHDNb

Gate Enhanced (t_PGOOD

)

OLR

400 kΩ

Avdd

Overload fault response

select detection

Reverse Input Polarity

Protection circuit

V_SHUTx

GND

SHDNb

RTN

LM76202-Q1

MODE

SHDN

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.3 Feature Description

8.3.1 Undervoltage Lockout (UVLO)

This section describes the undervoltage comparator input. When the voltage at UVLO pin falls below V_(UVLOF)

during input power fail or input undervoltage fault, the internal FET quickly turns off and FLT is asserted. The

UVLO comparator has a hysteresis of 90 mV. To set the input UVLO threshold, connect a resistor divider

network from IN supply to UVLO terminal to RTN as shown in 图 20.

V_(IN)

LM76202-Q1

R₁

UVLO

UVLOb

1.19 V

1.1 V

R₂

OVP

RTN

OVP

1.19 V

1.1 V

R₃

GND

图 20. UVLO and OVP Thresholds Set by R₁, R₂and R₃

If the undervoltage lockout (UVLO) function is not needed, the UVLO terminal must be connected to the IN

terminal. UVLO terminal must not be left floating.

The device also implements an internal power ON reset (POR) function on the IN terminal. The device disables

the internal circuitry when the IN terminal voltage falls below internal POR threshold V_(PORF). The internal POR

threshold has a hysteresis of 275 mV.

8.3.2 Overvoltage Protection (OVP)

The device incorporates circuitry to protect the system during overvoltage conditions. This device features an

overvoltage cut off functionality. A voltage more than V_(OVPR)on OVP pin turns off the internal FET and protects

the downstream load. To program the OVP threshold, connect a resistor divider from IN supply to OVP terminal

to RTN as shown in 图 21. OVP Overvoltage Cut-off response is shown in 图 22. OVP pin must not be left

floating. If OVP pin could be floating due to dry soldering, an additional zener diode at the output will be required

for protection from over voltage.

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

Feature Description (接下页)

V_(IN)

LM76202-Q1

UVLOb

R₁

UVLO

1.19 V

R₂

1.1 V

OVP

1.19 V

R₃

1.1 V

RTN

GND

图 21. OVP Threshold Setting

图 22. OVP Overvoltage Cut-Off

Programmable overvoltage clamp can also be achieved using LM76202-Q1 by connecting the resistor ladder

from Vout to OVP to RTN as shown in 图 23 . This results in clamping of output voltage close to OVP set-point

by resistors R1 and R2. as shown in 图 24. This scheme will also help in achieving minimal system Iq during off

state. For this OVP configurataion, use R1 > 90 kΩ.

V_(IN)

V_(OUT)

LM76202-Q1

UVLOb

UVLO

R₁

(>90 kꢀ )

1.19 V

1.1 V

OVP

R₂

OVP

1.19 V

1.1 V

RTN

GND

图 24. Programmable Overvoltage Clamp Response

图 23. Programmable OV Clamp

The LM76202-Q1 device also features an internally fixed 38 V overvoltage clamp (V_OVC) functionality. The OVP

terminal of theLM76202-Q1 device must be connected to the RTN terminal directly as shown in 图 25. The

LM76202-Q1 clamps the output voltage to V_OVC, when the input voltage exceeds 38 V. During the output voltage

clamp operation, the power dissipation in the internal MOSFET is P_D= (V_IN– V_OVC) × I_OUT. Excess power

dissipation for prolonged period can make the device to enter into thermal shutdown. 图 26 illustrates the

overvoltage clamp functionality.

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (接下页)

V_IN

V_(IN)

V_(OUT)

LM76202-Q1

UVLOb

V_OUT

UVLO

1.19 V

1.1 V

FLTb

I_IN

OVP

RTN

OVP

1.19 V

1.1 V

GND

图 26. Internal OV Clamp Response

图 25. Internal Fixed OV Clamp Setting

8.3.3 Reverse Battery Protection

To protect the electronic systems from reverse battery voltage due to miswiring, often a power component like a

schottky diode is added in series with the supply line as shown in 图 27. These additional discretes result in a

lossy and bulky protection solution. The LM76202-Q1 devices feature fully integrated reverse input supply

protection and does not need an additional diode. These devices can withstand a reverse voltage of –60 V

without damage. 图 28 illustrates the reverse input polarity protection functionality.

OUTPUT

INPUT

OUTPUT

LM76202-Q1

Hot-Swap Controller

GND

图 27. Reverse Battery Protection Circuits - Discrete vs LM76202-Q1

图 28. Reverse Input Supply Protection at –60 V

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

Feature Description (接下页)

8.3.4 Hot Plug-In and In-Rush Current Control

The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"

power source. This limits the voltage sag on the supply voltage and prevents unintended resets of the system

power. The controlled start-up also helps to eliminate conductive and radiative interferences. An external

capacitor connected from the dVdT pin to RTN defines the slew rate of the output voltage at power-on as shown

in 图 29 and 图 30.

LM76202-Q1

4 V

I_dVdT

dVdT

R_dVdT

SWENb

C_(dVdT)

RTN

GND

图 29. Output Ramp Up Time t_dVdTis Set by C_(dVdT)

The dVdT pin can be left floating to obtain a predetermined slew rate (t_dVdT) on the output. When the terminal is

left floating, the devices set an internal output voltage ramp rate of 23.9 V / 1.6 ms. A capacitor can be

connected from dVdT pin to RTN to program the output voltage slew rate slower than 23.9 V / 1.6 ms. Use 公式

1 and 公式 2 to calculate the external C_(dVdT)capacitance.

公式 1 governs slew rate at start-up.

C _dVdT

OUT

(

)

(

)

I_(dVdT)

´ ç

Gain _dVdT

(

)

where

•

I_(dVdT)= 4.7 µA (typical)

(

OUT

)

•

Gain_(dVdT)= dVdT to V_OUTgain = 24.6

(1)

(2)

(3)

The total ramp time (t_dVdT) of V_(OUT)for 0 to V_(IN)can be calculated using 公式 2.

t_dVdT= 8.7 × 10³× V_(IN)× C_(dVdT)

The inrush current can be calculated by 公式 3

I_INRUSH= C_OUT/[8.7 x 10³x C_dVdT

]

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (接下页)

VIN

C_dVdT= 22 nF

C_OUT= 47 µF

R_ILIM= 5.36 kΩ

图 30. Hot Plug-In and In-Rush Current Control at 24-V Input

8.3.5 Overload and Short Circuit Protection

The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current

is monitored during start-up and normal operation.

8.3.5.1 Overload Protection

The device offers following choices for the overload protection fault response:

•

Active current limiting (Auto-retry and Latch-off modes)

Electronic Circuit Breaker with overload timeout (Auto-retry mode)

See the configurations in 表 1 to select a specific overload fault response.

表 1. Overload Fault Response Configuration

MODE Pin Configuration

Open

Overload Protection Type

Electronic circuit breaker with auto-retry

Active current limiting with auto-retry

Shorted to RTN

A 402-kΩ resistor across MODE pin to RTN

Active current limiting with latch-off

8.3.5.1.1 Active Current Limiting

When the active current limiting mode is selected, during overload events, the device continuously regulates the

load current to the overcurrent limit I_(OL)programmed by the R_(ILIM)resistor as shown in 公式 4.

I_OL

R₍_ILIM

)

where

•

I_(OL)is the overload current limit in Ampere

R_(ILIM)is the current limit resistor in kΩ

(4)

During an overload condition, the internal current-limit amplifier regulates the output current to I_(LIM). The FLT

signal assert after a delay of t_PGOODF. The output voltage droops during the current regulation, resulting in

increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown

threshold (T_(TSD)), the internal FET is turn off. The device configured in latch-off mode stays latched off until it is

reset by either of the following conditions:

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

•

Cycling V_(IN)below V_(PORF)

Toggling SHDN

When the device is configured in auto-retry mode, it commences an auto-retry cycle t_CBretry(dly)ms after T_J<

[T_(TSD)– 10°C]. The FLT signal remains asserted until the fault condition is removed and the device resumes

normal operation. 图 31 and 图 32 illustrates the behavior of the system during current limiting with auto-retry

functionality.

IMON

V_OUT

FLTb

I_IN

Load transition from 22 Ω to

12 Ω

MODE pin connected to RTN

R_ILIM= 5.36 kΩ

R_ILIM= 8 kΩ

图 31. Auto-Retry MODE Fault Behavior

图 32. Response During Coming Out of Overload Fault

8.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN

In this mode, during overload events, the device allows the overload current to flow through the device until

I_(LOAD)< I_(FASTRIP). The circuit breaker threshold I_(CB)can be programmed using the R_(ILIM)resistor, as shown in 公

式 5.

I(CB) =

+ 0.03A

R₍_ILIM

)

where

•

I_(CB)is circuit breaker current threshold in A

R_(ILIM)is the current limit resistor in kΩ

(5)

The device commences an auto-retry cycle after a delay of t_CBretry(dly). The FLT signal remains asserted until the

fault condition is removed and the device resumes normal operation. 图 33 and 图 34 illustrate behavior of the

system during electronic circuit breaker with auto-retry functionality.

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

IMON

V_OUT

FLTb

I_IN

MODE left floating

Load Transition from 22 Ω to 12 Ω

Load Transition from 22 Ω to 12 Ω , R_ILIM= 8 kΩ

R_ILIM= 8 kΩ

图 33. Circuit Breaker Functionality

图 34. Zoomed at the Instance of Load Step

8.3.5.2 Short Circuit Protection

During a transient output short circuit event, the current through the device increases very rapidly. As the current-

limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip

comparator, with a threshold I_(FASTRIP). The fast-trip comparator turns off the internal FET after a duration of

t_{FASTTRIP(dly)}, when the current through the FET exceeds I_(FASTRIP)(I_(OUT)> I_(FASTRIP)), and terminates the rapid

short-circuit peak current. The fast-trip threshold is internally set to 87% higher than the programmed overload

current limit (I_(FASTRIP)= 1.87 × I_(OL)+ 0.015). The fast-trip circuit holds the internal FET off for only a few

microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output

current to I_(OL). Then the device behaves similar to overload condition. 图 35 and 图 36 illustrate the behavior of

the system when the current exceeds the fast-trip threshold.

VIN = 24 V, R_ILIM= 5.36 kΩ

图 35. Output Hot Short Functionality at 24-V Input

图 36. Zoomed at the Instance of Output Short

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

8.3.5.2.1 Start-Up With Short-Circuit On Output

When the device is started with a short-circuit on the output end, it limits the load current to the current limit I_(OL)

and behaves similarly to the overload condition. 图 37 illustrates the behavior of the device in this condition. This

feature helps in quick isolation of the fault and hence ensures stability of the DC bus.

V_IN

V_OUT

FLTb

I_IN

MODE pin connected to RTN

VIN = 24 V R_ILIM= 5.36 kΩ

图 37. Start-Up With Short on Output

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.3.5.3 FAULT Response

The FLT open-drain output asserts (active low) under following conditions:

•

Fault events such as undervoltage, overvoltage, overload, reverse current and thermal shutdown conditions

When the device enters low current shutdown mode when SHDN is pulled low

During start-up when the internal FET GATE is not fully enhanced (for example: V_OUThas not reached V_IN).

The FLT output does not assert in the event of reverse voltage on Input.

The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions

without the need for an external circuitry.

The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An

internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in

dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the

internal FET is fully enhanced and V_OUThas reached V_IN. The PGOOD signal has deglitch time incorporated to

ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising

deglitch delay is determined by t_PGOOD(degl)= Maximum {(900 + 20 × C_(dVdT)), t_PGOODR}, where C_(dVdT)is in nF and

t_PGOOD(degl)is in µs. FLT can be left open or connected to RTN when not used. V_(IN)falling below V_(PORF)resets

FLT.

8.3.5.3.1 Look Ahead Overload Current Fault Indicator

With the device configured in current limit operation and when the overload condition exists for more than

t_PGOODF, the FLT asserts to warn of impending turnoff of the internal FETs due to the subsequent thermal

shutdown event. 图 38 and 图 39 depict this behavior. The FLT signal remains asserted until the fault condition is

removed and the device resumes normal operation.

R_ILIM= 12 kΩ

MODE pin connected

to RTN

Load transient event

from 37 Ω to 15 Ω

R_ILIM= 12 kΩ

MODE pin connected

to RTN

Load transient event

from 37 Ω to 15 Ω

图 38. Look Ahead Overload Current Fault Indication

图 39. Output Turnoff Due to Thermal Shutdown With FLT

Asserted in Advance

8.3.5.4 Current Monitoring

The current source at IMON terminal is internally configured to be proportional to the current flowing from IN to

OUT. This current can be converted into a voltage using a resistor R_(IMON)from IMON terminal to RTN terminal.

The IMON voltage can be used as a means of monitoring current flow through the system. The maximum voltage

range (V_(IMONmax) for monitoring the current is limited to minimum of ([V_(IN)– 1.5 V, 4 V]) to ensure linear output.

This puts a limitation on maximum value of R_(IMON)resistor and is determined by 公式 6.

Min [(V(IN) - 1.5), 4 V]

(

IMONmax

)

1.8 ì I

(

LIM

)

ì GAIN

(

IMON

)

(6)

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

The output voltage at IMON terminal is calculated using 公式 7 and 公式 8.

For I_OUT> 50 mA,

(

IMON

)

= I

[

(

OUT

)

ìGAIN

(

IMON

)

ìR

(

IMON

)

]

Where,

•

GAIN_(IMON)is the gain factor I_(IMON):I_(OUT)

I_(OUT)is the load current

I_{(MON_OS)}= 2 µA (Typical)

(7)

For I_OUT< 50 mA (typical), IMON output current is close to I_{(MON_OS)}and 公式 8 provides the voltage output with

R_IMON

(

IMON

)

= (I(IMON _ OS))ìR(IMON)

(8)

This pin must not have a bypass capacitor to avoid delay in the current monitoring information.

In case of reverse input polarity fault, an external 100-kΩ resistor is recommended between IMON pin and ADC

input to limit the current through the ESD protection structures of the ADC.

8.3.5.5 IN, OUT, RTN and GND Pins

The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the

power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus

transients. The recommended input operating voltage range is 4.2 V to 60 V. Similarly all OUT pins must be

connected together and to the load. V_(OUT), in the ON condition, is calculated using 公式 9.

(

OUT

)

= V

(

)

- RON ì I

(

OUT

)

Where,

•

R_ONis the total ON resistance of the internal FETs.

(9)

The GND pin must be connected to the system ground. RTN is the device ground reference for all the internal

control blocks. Connect the device support components: R_(ILIM), C_(dVdT), R_(IMON), R_(MODE)and resistors for UVLO

and OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between

RTN and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection

feature. if negative input voltage is applied on IN pins with RTN pin connected to GND, the device can get

damaged.

8.3.5.6 Thermal Shutdown

The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction

temperature exceeds T_(TSD). After the thermal shutdown event, depending upon the mode of fault response, the

device either latches off or commences an auto-retry cycle 540 ms after T_J< [T_(TSD)– 10°C]. During the thermal

shutdown, the fault pin FLT pulls low to indicate a fault condition.

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.3.5.7 Low Current Shutdown Control (SHDN)

The internal FETs and hence the load current can be switched off by pulling the SHDN pin below V_(SHUTF)

threshold with a micro-controller GPIO pin as shown in 图 40. The device quiescent current reduces to 16 μA

(typical) in shutdown state. To assert SHDN low, the pull down must sink at least 10 µA at 400 mV. To enable

the device, SHDN must be pulled up to V_(SHUTR)threshold. Once the device is enabled, the internal FETs turns

on with dVdT mode.

LM76202-Q1

AVdd

R_pu

from µC

GPIO

SHDN

GND

SHDNb

V_SHUTR

V_SHUTF

OFF ON

图 40. Shutdown Control

8.4 Device Functional Modes

The device responds differently to overload and short circuit conditions. The operational differences are

explained in 表 2.

表 2. Device Operational Differences Under Different MODE Configurations

A 402-KΩ Resistor Connected

Between Mode And RTN Pins

(Current Limit With Latchoff)

Mode Connected To RTN

(Current Limit With Auto-Retry)

Mode Pin Configuration

Start-up

Mode Pin = Open

Inrush current controlled by dVdT

Inrush limited to I_(OL)level as set Inrush limited to I_(OL)level as set Inrush limited to I_(OL)level as set

by R_(ILIM)

Fault timer runs when current is

limited to I_(OL)

Fault timer expires after t_CB(dly)

causing the FETs to turnoff

If T_J> T_(TSD), device turns off

Device turns off if T_J> T_(TSD)

before timer expires

Overcurrent response

Current is limited to I_(OL)level as Current is limited to I_(OL)level as Current is allowed through the

set by R_(ILIM)

device if I_(LOAD)< I_(FASTTRIP)

Power dissipation increases as

V_(IN)– V_(OUT)increases

Power dissipation increases as

V_(IN)– V_(OUT)increases

Fault timer runs when the current

increases above I_(OL)

Fault timer expires after t_CB(dly)

causing the FETs to turnoff

Device turns off when T_J> T_(TSD)Device turns off when T_J> T_(TSD)Device turns off if T_J> T_(TSD)

before timer expires

Device attempts restart 540 ms

after T_J< [T_(TSD)– 10°C]

Device remains off

Device attempts restart 540 ms

after T_J< [T_(TSD)– 10°C].

Short-circuit response

Fast turnoff when I_(LOAD)> I_(FASTRIP)

Quick restart and current limited to I_(OL), follows standard start-up

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The device is an automotive ideal diode, typically used for load protection in automotive applications. It can

operate from 24-V battery with programmable current limit, overvoltage, undervoltage and reverse polarity

protections. The device provides robust protection against reverse current and transients (such as ISO 7637-2

Pulse 1 and ISO 16750-2 Pulse 5b) due to cables and switches in different automotive systems such as an ECU.

The device also provides robust protection for output short to battery, output short to GND, reverse battery and

input overvoltage.

The Detailed Design Procedure section can be used to select component values for the device.

9.2 Typical Application

OUT

VIN: 4.2 V - 60 V

OUT

FLT

C_IN

1 µF

C_OUT

47 µF

150 mΩ

R_FLTb

100 k

R₁

121 k

UVLO

OVP

SMBJ54A

SMBJ26A

Health Monitor

R₃

LM76202-Q1

ON/OFF Control

SHDN

IMON

dVdT

Load

Monitor

⁽¹⁾OVP

R₂

4.42 k

MODE

RTN

ILIM

R_IMON

20 k

C_dVdT

12 nF

GND

R_ILIM

5.36 k

R₄

(1) OVP connection for Programmable over voltage clamp. See Overvoltage Protection (OVP).

图 41. 24-V, 2-A Ideal Diode Load Protection Circuit for Automotive ECU

9.2.1 Design Requirements

表 3 shows the Design Requirements for LM76202-Q1. In addition to below requirements, the circuit is designed

to provide protection for transients as per ISO 7637-2 Pulse 1 and ISO 16750-2 Pulse 5b.

表 3. Design Requirements

DESIGN PARAMETER

Typical input voltage

EXAMPLE VALUE

4.2 to 60 V

4 V

V_(IN)

V_(UV)

V_(OV)

I_(LIM)

Undervoltage lockout set point

Overvoltage cutoff set point

Current limit

33.8 V

2.23 A

C_(OUT)

I_(LOAD)

Load capacitance

47 µF

Load current

2 A

9.2.2 Detailed Design Procedure

9.2.2.1 Step by Step Design Procedure

To begin the design process, the designer must know the following parameters:

•

Operating voltage range

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

•

Maximum output capacitance

Start-up time

Maximum current limit

Transient voltage levels

9.2.2.2 Setting Undervoltage Lockout and Overvoltage Set Point for Operating Voltage Range

To provide operation in cold crank conditions for automotive batteries, the UVLO is set to POR value (4 V) by

connecting UVLO to IN pin and OVP threshold is set from resistors connected from IN pins to provide protection

from transient during ISO 16750 Pulse 5b. During the ISO 16750 5b transient, output voltage is cut-off at 33.8 V

and provides protection to load from high input voltage during the transient. The overvoltage threshold is

calculated by 公式 10.

V_OVPR= R₂/(R₁+ R₂) × V_OV

where

•

Overvoltage threshold rising, V_OVPR= 1.19 V

V_OVis overvoltage protection voltage (= 33.8 V)

(10)

However, the leakage current due to external active components connected at resistor string can add error to

these calculations. So, the resistor string current, I(R₂₃) must be chosen to be 20x greater than the leakage

current of OVP pin.

9.2.2.3 Programming the Current-Limit Threshold—R_(ILIM)Selection

The R_(ILIM)resistor at the ILIM pin sets the over load current limit, this can be set using 公式 4.

R_(ILIM)= 5.36 kΩ was selected to set I_LIMto 2.23 A.

9.2.2.4 Programming Current Monitoring Resistor—R_IMON

The voltage at IMON pin V_(IMON)represents the voltage proportional to the load current. This can be connected to

an ADC of the downstream system for health monitoring of the system. The R_(IMON)must be configured based on

the maximum input voltage range of the ADC used. R_(IMON)is set using 公式 11.

V(IMONmax)

I^(LIM)ì75 ì10^-6

R(^IMON)=

(11)

For current monitoring up-to a current of 2.2 A, and considering the operating input voltage range of ADC from 0

V to 4 V, V_(IMONmax)is 4 V and R_(IMON)is selected as 20 kΩ.

9.2.2.5 Limiting the Inrush Current

To limit the inrush current and power dissipation during start-up, an appropriate value of C_dVdTmust be selected.

The inrush current during start-up is estimated by 公式 12. A 12nF capacitance is selected for C_dVdTto keep

inrush current less than 0.5 A.

I_INRUSH= C_OUT/ [8.7 × 10³× C_dVdt

]

(12)

9.2.2.5.1 Selection of Input TVS for Transient Protection

To protect the device and the load from input transients exceeding the absolute maximum ratings of the device, a

TVS diode is required at input of the device. To meet the requirements of protection for ISO 16750 pulse 5b and

ISO 7637 pulse 1 as per 表 4, SMBJ54A and SMBJ26A are selected for protection from transients.

表 4. Input TVS Selection for Transients

ISO 7637 Pulse 1

and Reverse Battery

Parameter

ISO 16750 Pulse 5b

Maximum Transient Voltage of Pulse

(V_T)

A bidirectional TVS is required to protect

from positive and negative transients

65 V

-600V

R_i= Source impedance.

For ISO 16750 Pulse 5b; R_i= 1Ω

For ISO 7637 Pulse 1;R_i= 50 Ω

Pulse Current through TVS (I_Pulse

)

(V_T- V_C)/(R_i)

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

表 4. Input TVS Selection for Transients (接下页)

ISO 7637 Pulse 1

and Reverse Battery

Parameter

ISO 16750 Pulse 5b

To keep input voltage below absolute

maximum rating of the device. See 公式 13

for V_C

Clamping voltage of TVS (V_C) at Pulse

current I_Pulse

< 65 V

> –(65 - V_OUT-Max) V

To operate with maximum operating input

voltage and to protect from maximum

reverse battery voltage

Breakdown voltage of TVS (V_BR

)

> 60V

> 28V

V_C= V_BR+ I_Pulse× [V_Clamp-max- V_BR]/[I_PP- I_T]

where

•

V_Cis the clamping voltage of TVS at I_Pulsecurrent through it.

V_BRis break down voltage of TVS with I_Ttest current through it.

V_Clamp-maxis maximum clamping voltage of TVS at peak pulse current I_PP

V_BR, I_T, V_Clamp-maxand I_PPare the specifications of the TVS diode.

(13)

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

9.2.3 Application Curves

图 42. Protection from Output Short to GND [V_IN= 24 V,

图 43. Protection from Output short to Battery [V_IN

ILIM = 2.23 A, MODE = RTN]

Floating, V_OUT= 24 V, ILIM = 2.23 A, MODE = RTN ]

图 44. Protection from ISO 7637-2 Pulse 1 [24 V Battery,

Transient Voltage = –600 V , R_LOAD= 28 Ω]

图 45. Protection from ISO 16750-2 Pulse 5b [24 V Battery,

Transient Voltage = 65 V , R_LOAD= 28 Ω]

图 46. Protection from Reverse Battery [V_IN= -24 V, V_OUT

图 47. Protection from OverVoltage at Input [V_IN= 36 V,

R_LOAD= 28 Ω, ILIM = 2.23 A ]

0 V, ILIM = 2.23 A ]

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

10 Power Supply Recommendations

The device is designed for the supply voltage range of 4.2 V ≤ V_IN≤ 60 V. Power supply must be rated higher

than the current limit set to avoid voltage droops during overcurrent and short circuit conditions.

10.1 Transient Protection

In case of short circuit and over load current limit, when the device interrupts current flow, input inductance

generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the

output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the

input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps

are not taken to address the issue.

Typical methods for addressing transients include:

•

Minimizing lead length and inductance into and out of the device

Using large PCB GND plane

Schottky diode across the output to absorb negative spikes

A ceramic capacitor at input (C_(IN)) with value more than 1µF to absorb the energy and dampen the

transients.

The approximate value of input capacitance can be estimated with 公式 14.

L _IN

( )

V_{spike Absolute}= V _IN+ I _Load

(

)

( )

(

)

C _IN

( )

where

•

V_(IN)is the nominal supply voltage

I_(LOAD)is the load current

L_(IN)equals the effective inductance seen looking into the source

C_(IN)is the capacitance present at the input

(14)

Automotive applications could require additional Transient Voltage Suppressor (TVS) to prevent transients from

exceeding the Absolute Maximum Ratings of the device. These transients include ISO 7637 Pulse 1, Output

short to battery, Output short to GND and reverse battery at input.

The circuit implementation with optional protection components (TVS Diode at Input and schottky diode at

output) is shown in 图 48. For protection from automotive transients similar to ISO 7637 Pulse 1, Output short to

battery , output short to GND and reverse battery, use C_IN≥ 1 µF and C_OUT≥ 3.3 µF. For selection of TVS diode

and other components, see Application Information.

INPUT

OUT

OUTPUT

C_IN

C_OUT

R₄

R₁

R₂

(≥ 1 µF)

150 mꢀ

(≥ 3.3 µF)

UVLO

FLT

LM76202-Q1

OVP

MODE

dVdT

SHDN

IMON

ILIM

GND

RTN

R₃

R_ILIM

R_IMON

C_dVdT

^*Optional components needed for suppression of transients

图 48. Circuit Implementation for Automotive Transient Protection

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

•

For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN

terminal and GND. Use C_IN≥ 1 µF for automotive transient protection. See Transient Protection.

•

The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care

must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the

GND terminal of the device. See 图 49 for PCB layout example with HTSSOP package.

•

High current carrying power path connections must be as short as possible and must be sized to carry atleast

twice the full-load current.

•

RTN, which is the reference ground for the device must be a copper plane or island.

Locate all the device support components R_(ILIM), C_(dVdT), R_(IMON), and MODE, UVLO, OVP resistors close to

their connection pin. Connect the other end of the component to the RTN with shortest trace length.

•

The trace routing for the R_ILIMand R_(IMON)components to the device must be as short as possible to reduce

parasitic effects on the current limit and current monitoring accuracy. These traces must not have any

coupling to switching signals on the board.

Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the

device they are intended to protect, and routed with short traces to reduce inductance. For example, a

protection Schottky diode is recommended to address negative transients due to switching of inductive loads,

and it must be physically close to the OUT and GND pins.

•

Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater

cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane

directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase

heat sinking in higher current applications. Designs that do not need reverse input polarity protection can

have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the

PCB ground plane.

LM76202-Q1

www.ti.com.cn

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

11.2 Layout Example

Top Layer

Bottom layer GND plane

Via to Bottom Layer

Track in bottom layer

Top Layer RTN Plane

Bottom Layer RTN Plane

BOTTOM Layer GND Plane

Top Layer

Power GND Plane

High

Frequency

Bypass cap

OUT

VOUT PLANE

VIN PLANE

FLT

UVLO

N.C

PWP

OVP

dVdT

MODE

SHDN

RTN

ILIM

IMON

EP Blue

GND

TOP Layer

RTN Plane

BOTTOM Layer RTN Plane

图 49. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB

LM76202-Q1

ZHCSJE7A –MARCH 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

《LM76202-Q1 EVM 用户指南》

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM76202QPWPRQ1

ACTIVE

HTSSOP

PWP

2000 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

M76202Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM76202QPWPRQ1

HTSSOP PWP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Sep-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 16

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

LM76202QPWPRQ1

2000

Pack Materials-Page 2

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

LM76202-Q1 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E