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LM8261M5X/NOPB [TI]

Single, 30-V, 21-MHz operational amplifier | DBV | 5 | -40 to 85;
LM8261M5X/NOPB
型号： LM8261M5X/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Single, 30-V, 21-MHz operational amplifier | DBV | 5 | -40 to 85

放大器 光电二极管 运算放大器 放大器电路
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DAC081S101  
www.ti.com  
SNAS323C –JUNE 2005–REVISED FEBRUARY 2013  
DAC081S101 8-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output  
Check for Samples: DAC081S101  
1
FEATURES  
DESCRIPTION  
The DAC081S101 is a full-featured, general purpose  
8-bit voltage-output digital-to-analog converter (DAC)  
that can operate from a single +2.7V to 5.5V supply  
and consumes just 175 µA of current at 3.6 Volts.  
The on-chip output amplifier allows rail-to-rail output  
swing and the three wire serial interface operates at  
clock rates up to 30 MHz over the specified supply  
voltage range and is compatible with standard SPI™,  
QSPI, MICROWIRE and DSP interfaces. Competitive  
devices are limited to 20 MHz clock rates at supply  
voltages in the 2.7V to 3.6V range.  
23  
•
Guaranteed Monotonicity  
Low Power Operation  
•
•
•
•
•
•
•
Rail-to-Rail Voltage Output  
Power-on Reset to Zero Volts Output  
SYNC Interrupt Facility  
Wide Power Supply Range (+2.7V to +5.5V)  
Small Packages  
Power Down Feature  
The supply voltage for the DAC081S101 serves as its  
voltage reference, providing the widest possible  
output dynamic range. A power-on reset circuit  
ensures that the DAC output powers up to zero volts  
and remains there until there is a valid write to the  
APPLICATIONS  
•
•
•
•
Battery-Powered Instruments  
Digital Gain and Offset Adjustment  
Programmable Voltage & Current Sources  
Programmable Attenuators  
device.  
A
power-down feature reduces power  
consumption to less than a microWatt.  
The low power consumption and small packages of  
the DAC081S101 make it an excellent choice for use  
in battery operated equipment.  
The DAC081S101 is a direct replacement for the  
AD5300 and is one of a family of pin compatible  
DACs, including the 10-bit DAC101S101 and the 12-  
bit DAC121S101. The DAC081S101 operates over  
the extended industrial temperature range of −40°C  
to +105°C.  
Table 1. Key Specifications  
VALUE  
Resolution  
8 bits  
DNL  
+0.04, -0.02 LSB (typ)  
3 µs (typ)  
Output Settling Time  
Zero Code Error  
Full-Scale Error  
3.8mV (typ)  
−0.07 %FS (typ)  
Normal Mode  
0.63 mW (3.6V) / 1.41 mW (5.5V) typ  
0.14 µW (3.6V) / 0.33 µW (5.5V) typ  
Power Consumption  
Pwr Down Mode  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SPI is a trademark of Motorola, Inc..  
2
3
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  
DAC081S101  
SNAS323C –JUNE 2005–REVISED FEBRUARY 2013  
www.ti.com  
Pin Configuration  
SOT  
VSSOP  
8
7
6
5
1
2
3
4
V
V
GND  
1
2
3
6
5
4
SYNC  
SCLK  
A
OUT  
D
NC  
NC  
IN  
GND  
SCLK  
SYNC  
V
V
A
D
OUT  
IN  
Block Diagram  
V
A
GND  
POWER-ON  
RESET  
DAC081S101  
REF(+) REF(-)  
8-BIT DAC  
DAC  
REGISTER  
BUFFER  
V
OUT  
8
8
POWER-DOWN  
CONTROL  
LOGIC  
INPUT  
CONTROL  
LOGIC  
1k  
100k  
SCLK  
SYNC  
D
IN  
Pin Descriptions  
SOT-23  
Pin No.  
VSSOP  
Pin No.  
Name  
Description  
VOUT  
GND  
VA  
1
2
3
4
8
1
DAC Analog Output Voltage.  
Ground reference for all on-chip circuitry.  
Power supply and Reference input. Should be decoupled to GND.  
Serial Data Input. Data is clocked into the 16-bit shift register on the falling  
edges of SCLK after the fall of SYNC.  
DIN  
4
5
7
6
Serial Clock Input. Data is clocked into the input shift register on the falling  
edges of this pin.  
SCLK  
Frame synchronization input for the data input. When this pin goes low, it  
enables the input shift register and data is transferred on the falling edges  
of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is  
brought high before the 16th clock, in which case the rising edge of SYNC  
acts as an interrupt and the write sequence is ignored by the DAC.  
SYNC  
NC  
6
5
2, 3  
No Connect. There is no internal connection to these pins.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
2
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Product Folder Links: DAC081S101  
DAC081S101  
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SNAS323C –JUNE 2005–REVISED FEBRUARY 2013  
(1)(2)  
Absolute Maximum Ratings  
Supply Voltage, VA  
6.5V  
−0.3V to (VA + 0.3V)  
10 mA  
Voltage on any Input Pin  
Input Current at Any Pin(3)  
Package Input Current(3)  
20 mA  
Power Consumption at TA = 25°C  
See(4)  
ESD Susceptibility(5)  
Human Body Model  
Machine Model  
2500V  
250V  
Soldering Temperature, Infrared,  
(6)  
10 Seconds  
235°C  
Storage Temperature  
−65°C to +150°C  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see  
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics  
may degrade when the device is not operated under the listed test conditions.  
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified  
(3) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should  
be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power  
supplies with an input current of 10 mA to two.  
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by  
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula  
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe  
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).  
Obviously, such conditions should always be avoided.  
(5) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO  
Ohms.  
(6) See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering  
surface mount devices.  
(1)(2)  
Operating Ratings  
Operating Temperature Range  
−40°C ≤ TA ≤ +105°C  
+2.7V to 5.5V  
(3)  
Supply Voltage, VA  
Any Input Voltage(4)  
−0.1 V to (VA + 0.1 V)  
0 to 1500 pF  
Output Load  
SCLK Frequency  
Up to 30 MHz  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see  
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics  
may degrade when the device is not operated under the listed test conditions.  
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified  
(3) To guarantee accuracy, it is required that VA be well bypassed.  
(4) The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not  
damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV.  
For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions.  
I/O  
TO INTERNAL  
CIRCUITRY  
GND  
Package Thermal Resistances  
Package  
8-Lead VSSOP  
6-Lead SOT  
θJA  
240°C/W  
250°C/W  
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SNAS323C –JUNE 2005–REVISED FEBRUARY 2013  
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Electrical Characteristics  
Values shown in this table are design targets and are subject to change before product release.  
The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 4 to 251. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.  
Units  
(Limits)  
(1)  
(1)  
Parameter  
Test Conditions  
Typical  
Limits  
STATIC PERFORMANCE  
Resolution  
8
8
Bits (min)  
Bits (min)  
LSB (max)  
LSB (min)  
LSB (max)  
LSB (min)  
mV (max)  
%FSR (max)  
%FSR (max)  
µV/°C  
Monotonicity  
INL  
Integral Non-Linearity  
+0.16  
−0.12  
+0.04  
−0.02  
+3.8  
+0.75  
−0.75  
+0.1  
−0.1  
+15  
DNL  
Differential Non-Linearity  
ZE  
FSE  
GE  
Zero Code Error  
Full-Scale Error  
Gain Error  
IOUT = 0  
IOUT = 0  
−0.07  
−0.10  
−20  
−1.0  
±1.0  
All ones Loaded to DAC register  
ZCED  
Zero Code Error Drift  
VA = 3V  
VA = 5V  
−0.7  
ppm/°C  
TC GE  
Gain Error Tempco  
−1.0  
ppm/°C  
OUTPUT CHARACTERISTICS  
0
VA  
V (min)  
V (max)  
(2)  
Output Voltage Range  
VA = 3V, IOUT = 10 µA  
VA = 3V, IOUT = 100 µA  
VA = 5V, IOUT = 10 µA  
VA = 5V, IOUT = 100 µA  
VA = 3V, IOUT = 10 µA  
VA = 3V, IOUT = 100 µA  
VA = 5V, IOUT = 10 µA  
VA = 5V, IOUT = 100 µA  
RL = ∞  
2.0  
5.0  
mV  
mV  
mV  
mV  
V
ZCO  
FSO  
Zero Code Output  
Full Scale Output  
3.0  
5.4  
2.986  
2.976  
4.976  
4.970  
1500  
1500  
1.3  
V
V
V
pF  
pF  
Ohm  
Maximum Load Capacitance  
DC Output Impedance  
RL = 2kΩ  
VA = 5V, VOUT = 0V,  
Input code = FFh  
−63  
−50  
74  
mA  
mA  
mA  
mA  
VA = 3V, VOUT = 0V,  
Input code = FFh  
IOS  
Output Short Circuit Current  
VA = 5V, VOUT = 5V,  
Input code = 00h  
VA = 3V, VOUT = 3V,  
Input code = 00h  
53  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average  
Outgoing Quality Level).  
(2) This parameter is guaranteed by design and/or characterization and is not tested in production.  
4
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SNAS323C –JUNE 2005–REVISED FEBRUARY 2013  
Electrical Characteristics (continued)  
Values shown in this table are design targets and are subject to change before product release.  
The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 4 to 251. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.  
Units  
(Limits)  
(1)  
(1)  
Parameter  
Test Conditions  
Typical  
Limits  
LOGIC INPUT  
IIN  
Input Current(3)  
±1  
0.8  
0.5  
2.4  
2.1  
3
µA (max)  
V (max)  
V (max)  
V (min)  
VA = 5V  
VA = 3V  
VA = 5V  
VA = 3V  
VIL  
Input Low Voltage(3)  
VIH  
CIN  
Input High Voltage(3)  
Input Capacitance(3)  
V (min)  
pF (max)  
POWER REQUIREMENTS  
VA = 5.5V  
VA = 3.6V  
VA = 5.5V  
VA = 3.6V  
VA = 5.0V  
VA = 3.0V  
VA = 5.0V  
VA = 3.0V  
VA = 5.0V  
VA = 3.0V  
VA = 5.5V  
VA = 3.6V  
VA = 5.5V  
VA = 3.6V  
VA = 5.5V  
VA = 3.6V  
VA = 5.0V  
VA = 3.0V  
VA = 5.0V  
VA = 3.0V  
VA = 5.0V  
VA = 3.0V  
VA = 5.5V  
VA = 3.6V  
VA = 5V  
256  
174  
221  
154  
142  
107  
83  
328  
224  
294  
200  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
mW (max)  
mW (max)  
mW (max)  
mW (max)  
µW (max)  
µW (max)  
µW (max)  
µW (max)  
µW (max)  
µW (max)  
µW (max)  
µW (max)  
%
Normal Mode  
fSCLK = 30 MHz  
Normal Mode  
fSCLK = 20 MHz  
Normal Mode  
fSCLK = 0  
IA  
Supply Current (output unloaded)  
All PD Modes,  
fSCLK = 30 MHz  
42  
56  
All PD Modes,  
fSCLK = 20 MHz  
28  
0.06  
0.04  
1.41  
0.63  
1.22  
0.55  
0.71  
0.32  
0.42  
0.13  
0.28  
0.08  
0.33  
0.14  
91  
1.0  
1.0  
All PD Modes,  
(3)  
fSCLK = 0  
1.80  
0.81  
1.62  
0.72  
Normal Mode  
fSCLK = 30 MHz  
Normal Mode  
fSCLK = 20 MHz  
Normal Mode  
fSCLK = 0  
Power Consumption (output  
unloaded)  
PC  
All PD Modes,  
fSCLK = 30 MHz  
All PD Modes,  
fSCLK = 20 MHz  
5.5  
3.6  
All PD Modes,  
(3)  
fSCLK = 0  
IOUT / IA  
Power Efficiency  
ILOAD = 2mA  
VA = 3V  
94  
%
(3) This parameter is guaranteed by design and/or characterization and is not tested in production.  
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AC and Timing Characteristics  
Values shown in this table are design targets and are subject to change before product release.  
The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 4 to 251. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.  
Units  
(Limits)  
Parameter  
Test Conditions  
Typical  
Limits  
fSCLK  
ts  
SCLK Frequency  
30  
5
MHz (max)  
Output Voltage Settling Time  
40h to C0h code  
change, RL = 2kΩ  
CL ≤ 200 pF  
3
µs (max)  
(1)  
SR  
Output Slew Rate  
Glitch Impulse  
1
12  
0.5  
6
V/µs  
nV-sec  
nV-sec  
µs  
Code change from 80h to 7Fh  
Digital Feedthrough  
VA = 5V  
VA = 3V  
tWU  
Wake-Up Time  
39  
µs  
1/fSCLK  
SCLK Cycle Time  
SCLK High time  
SCLK Low Time  
33  
13  
13  
ns (min)  
ns (min)  
ns (min)  
tH  
tL  
5
5
Set-up Time SYNC to SCLK Rising  
Edge  
tSUCL  
−15  
0
ns (min)  
tSUD  
tDHD  
Data Set-Up Time  
Data Hold Time  
2.5  
2.5  
0
5
4.5  
3
ns (min)  
ns (min)  
ns (min)  
ns (min)  
ns (min)  
ns (min)  
VA = 5V  
tCS  
SCLK fall to rise of SYNC  
SYNC High Time  
VA = 3V  
−2  
9
1
2.7 ≤ VA ≤ 3.6  
3.6 ≤ VA ≤ 5.5  
20  
10  
tSYNC  
5
(1) This parameter is guaranteed by design and/or characterization and is not tested in production.  
Specification Definitions  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB, which is VREF / 256 = VA / 256.  
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital  
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.  
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFh) loaded  
into the DAC and the value of VA x 255 / 256.  
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and  
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.  
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register  
changes. It is specified as the area of the glitch in nanovolt-seconds.  
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line  
through the input to output transfer function. The deviation of any given code from this straight line is measured  
from the center of that code value. The end point method is used. INL for this product is specified over a limited  
range, per the Electrical Tables.  
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is  
LSB = VREF / 2n  
(1)  
where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 8 for the  
DAC081S101.  
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output  
stability maintained.  
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MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when  
the output code increases.  
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is  
1/2 of VA.  
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from  
the power supply. The difference between the supply and output currents, is the power consumed by the device  
without a load.  
SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value after the input code is  
updated.  
WAKE-UP TIME is the time for the output to settle to within 1/2 LSB of the final value after the device is  
commanded to the active mode from any of the power down modes.  
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 00h has been  
entered.  
Transfer Characteristic  
FSE  
255 x V  
256  
A
GE = FSE - ZE  
FSE = GE + ZE  
OUTPUT  
VOLTAGE  
ZE  
0
0
255  
DIGITAL INPUT CODE  
Figure 1. Input / Output Transfer Characteristic  
Timing Diagram  
1
f
CLK  
SCLK  
1
2
13  
14  
15  
16  
t
L
t
SUCL  
t
SYNC  
t
H
t
CS  
SYNC  
t
DHD  
D
IN  
DB15  
DB0  
t
SUD  
Figure 2. DAC081S101 Timing  
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Typical Performance Characteristics  
fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated  
DNL at VA = 3.0V  
DNL at VA = 5.0V  
Figure 3.  
Figure 4.  
INL at VA = 3.0V  
INL at VA = 5.0V  
Figure 5.  
Figure 6.  
TUE at VA = 3.0V  
TUE at VA = 5.0V  
Figure 7.  
Figure 8.  
8
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Typical Performance Characteristics (continued)  
fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated  
DNL  
INL  
vs.  
VA  
vs.  
VA  
Figure 9.  
Figure 10.  
3V DNL  
vs.  
fSCLK  
5V DNL  
vs.  
fSCLK  
Figure 11.  
Figure 12.  
3V DNL  
vs.  
Clock Duty Cycle  
5V DNL  
vs.  
Clock Duty Cycle  
Figure 13.  
Figure 14.  
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Typical Performance Characteristics (continued)  
fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated  
3V DNL  
5V DNL  
vs.  
Temperature  
vs.  
Temperature  
Figure 15.  
Figure 16.  
3V INL  
vs.  
fSCLK  
5V INL  
vs.  
fSCLK  
Figure 17.  
Figure 18.  
3V INL  
vs.  
Clock Duty Cycle  
5V INL  
vs.  
Clock Duty Cycle  
Figure 19.  
Figure 20.  
10  
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Typical Performance Characteristics (continued)  
fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated  
3V INL  
5V INL  
vs.  
Temperature  
vs.  
Temperature  
Figure 21.  
Figure 22.  
Zero Code Error  
Zero Code Error  
vs.  
Clock Duty Cycle  
vs.  
fSCLK  
Figure 23.  
Figure 24.  
Zero Code Error  
vs.  
Temperature  
Full-Scale Error  
vs.  
fSCLK  
Figure 25.  
Figure 26.  
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Typical Performance Characteristics (continued)  
fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated  
Full-Scale Error  
Full-Scale Error  
vs.  
Temperature  
vs.  
Clock Duty Cycle  
Figure 27.  
Figure 28.  
Supply Current  
Supply Current  
vs.  
Temperature  
vs.  
VA  
Figure 29.  
Figure 30.  
5V Glitch Response  
Power-On Reset  
Figure 31.  
Figure 32.  
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Typical Performance Characteristics (continued)  
fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated  
3V Wake-Up Time  
5V Wake-Up Time  
Figure 33.  
Figure 34.  
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DAC081S101  
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FUNCTIONAL DESCRIPTION  
DAC SECTION  
The DAC081S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor  
string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding  
is straight binary with an ideal output voltage of:  
VOUT = VA x (D / 256)  
(2)  
where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any  
value between 0 and 255.  
RESISTOR STRING  
The resistor string is shown in Figure 35. This string consists of 4096 equal valued resistors with a switch at each  
junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch  
is closed, connecting the proper node to the amplifier. This configuration guarantees that the DAC is monotonic.  
V
A
R
R
R
To Output Amplifier  
R
R
Figure 35. DAC Resistor String  
OUTPUT AMPLIFIER  
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even  
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For  
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the  
amplifier are described in the Electrical Tables.  
SERIAL INTERFACE  
The three-wire interface is compatible with SPI, QSPI and MICROWIRE as well as most DSPs. See the Timing  
Diagram for information on a write sequence.  
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked  
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is  
clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register  
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be  
brought high for the minimum specified time before the next write sequence as a falling edge of SYNC is used to  
initiate the next write cycle.  
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Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write  
sequences to minimize power consumption.  
INPUT SHIFT REGISTER  
The input shift register, Figure 36, has sixteen bits. The first two bits are "don't cares" and are followed by two  
bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the  
serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing  
Diagram, Figure 2.  
MSB  
LSB  
X
X
PD1PD0 D7 D6 D5 D4 D3 D2 D1 D0  
DATA BITS  
X
X
X
X
0
0
1
1
0
1
0
1
Normal Operation  
1 kW to GND  
Power-Down Modes  
100 kW to GND  
High Impedance  
Figure 36. Input Register Contents  
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th  
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and  
the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation  
or in the output voltage.  
POWER-ON RESET  
The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC  
register is filled with zeros and the output voltage is 0 Volts and remains there until a valid write sequence is  
made to the DAC.  
POWER-DOWN MODES  
The DAC081S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the  
control register.  
Table 2. Modes of Operation  
DB13  
DB12  
Operating Mode  
0
0
1
1
0
1
0
1
Normal Operation  
Power-Down with 1kΩ to GND  
Power-Down with 100kΩ to GND  
Power-Down with Hi-Z  
When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of  
these bits the supply current drops to its power-down level and the output is pulled down with either a 1kΩ or a  
100KΩ resistor, or is in a high impedance state, as described in Table 2.  
The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the  
power-down modes. However, the contents of the DAC register are unaffected when in power-down, so when  
coming out of power down the output voltage returns to the same voltage it was before entering power down.  
Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled  
low. The time to exit power-down (Wake-Up Time) is typically tWU µsec as stated in the A.C. and Timing  
Characteristics Table.  
APPLICATION INFORMATION  
The simplicity of the DAC081S101 implies ease of use. However, it is important to recognize that any data  
converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply  
Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.  
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DSP/MICROPROCESSOR INTERFACING  
Interfacing the DAC081S101 to microprocessors and DSPs is quite simple. The following guidelines are offered  
to hasten the design process.  
ADSP-2101/ADSP2103 Interfacing  
Figure 37 shows a serial interface between the DAC081S101 and the ADSP-2101/ADSP2103. The DSP should  
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control  
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.  
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.  
ADSP-2101/  
DAC081S101  
ADSP2103  
SYNC  
DIN  
SCLK  
TFS  
DT  
SCLK  
Figure 37. ADSP-2101/2103 Interface  
80C51/80L51 Interface  
A serial interface between the DAC081S101 and the 80C51/80L51 microcontroller is shown in Figure 38. The  
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line  
P3.3. This line is taken low when data is to transmitted to the DAC081S101. Since the 80C51/80L51 transmits 8-  
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must  
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of  
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the  
80C51/80L51 transmits data with the LSB first while the DAC081S101 requires data with the MSB first.  
80C51/80L51  
P3.3  
DAC081S101  
SYNC  
TXD  
RXD  
SCLK  
DIN  
Figure 38. 80C51/80L51 Interface  
68HC11 Interface  
A serial interface between the DAC081S101 and the 68HC11 microcontroller is shown in Figure 39. The SYNC  
line of the DAC081S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.  
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration  
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the  
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB  
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the  
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.  
68HC11  
DAC081S101  
SYNC  
PC7  
SCK  
SCLK  
MOSI  
DIN  
Figure 39. 68HC11 Interface  
Microwire Interface  
Figure 40 shows an interface between a Microwire compatible device and the DAC081S101. Data is clocked out  
on the rising edges of the SCLK signal.  
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MICROWIRE  
DEVICE  
DAC081S101  
CS  
SK  
SO  
SYNC  
SCLK  
DIN  
Figure 40. Microwire Interface  
USING REFERENCES AS POWER SUPPLIES  
Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage.  
Since the DAC081S101 consumes very little power, a reference source may be used as the supply voltage. The  
advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise  
regulators can also be used for the power supply of the DAC081S101. Listed below are a few power supply  
options for the DAC081S101.  
LM4130  
The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the  
DAC081S101. Its primary disadvantage is the lack of 3V and 5V versions. However, the 4.096V version is useful  
if a 0 to 4.095V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1µF capacitor  
and the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise. The LM4130 comes in a  
space-saving 5-pin SOT23.  
Input  
Voltage  
LM4130-4.1  
C2  
C1  
2.2 mF  
0.1 mF  
DAC081S101  
V
OUT  
= 0V to 4.080V  
SYNC  
DIN  
SCLK  
Figure 41. The LM4130 as a power supply  
LM4050  
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the  
DAC081S101. It does not come in a 3 Volt version, but 4.096V and 5V versions are available. It comes in a  
space-saving 3-pin SOT-23.  
Input  
Voltage  
R
V
Z
0.47 mF  
DAC081S101  
SYNC  
DIN  
SCLK  
LM4050-4.1  
or  
LM4050-5.0  
V
OUT  
= 0V to 5V  
Figure 42. The LM4050 as a power supply  
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The minimum resistor value in the circuit of Figure 42 should be chosen such that the maximum current through  
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at  
its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the  
DAC081S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its  
minimum current for regulation plus the maximum DAC081S101 current in full operation. The conditions for  
minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value  
at its maximum due to tolerance, and the DAC081S101 draws its maximum current. These conditions can be  
summarized as  
R(min) = ( VIN(max) − VZ(min) / (IA(min) + IZ(max))  
(3)  
and  
R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min) )  
(4)  
where VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over  
temperature, IZ(max) is the maximum allowable current through the LM4050, IZ(min) is the minimum current  
required by the LM4050 for proper regulation, IA(max) is the maximum DAC081S101 supply current, and IA(min)  
is the minimum DAC081S101 supply current.  
LP3985  
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good  
choice for applications that do not require a precision reference for the DAC081S101. It comes in 3.0V, 3.3V and  
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency  
noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes  
in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.  
Input  
Voltage  
LP3985  
0.1 mF  
1 mF  
0.01 mF  
DAC081S101  
SYNC  
V
OUT  
= 0V to 5V  
DIN  
SCLK  
Figure 43. Using the LP3985 regulator  
An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF  
ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output. Careful interpretation  
and understanding of the capacitor specification is required to ensure correct device operation.  
LP2980  
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon  
grade. It is available in 3.0V, 3.3V and 5V versions, among others.  
V
IN  
OFF  
Input  
Voltage  
V
OUT  
LP2980  
ON /  
1 mF  
DAC081S101  
SYNC  
V
OUT  
= 0V to 5V  
DIN  
SCLK  
Figure 44. Using the LP2980 regulator  
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Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor  
must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The  
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid  
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to  
their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic  
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at  
low temperatures.  
BIPOLAR OPERATION  
The DAC081S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar  
output may be obtained with the circuit in Figure 45. This circuit will provide an output voltage range of ±5 Volts.  
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.  
10 pF  
R
2
+5V  
+5V  
R
1
+
-
10 mF  
0.1 mF  
±5V  
+
DAC081S101  
-5V  
SYNC  
V
OUT  
DIN  
SCLK  
Figure 45. Bipolar Operation  
The output voltage of this circuit for any code is found to be  
VO = (VA x (D / 256) x ((R1 + R2) / R1) - VA x R2 / R1)  
(5)  
(6)  
where D is the input code in decimal form. With VA = 5V and R1 = R2,  
VO = (10 x D / 256) - 5V  
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 3.  
Table 3. Some Rail-to-Rail Amplifiers  
AMP  
PKGS  
Typ VOS  
Typ ISUPPLY  
PDIP-8  
SOT-23-5  
LMC7111  
0.9 mV  
25 µA  
SO-8  
SOT-23-5  
LM7301  
LM8261  
0.03 mV  
0.7 mV  
620 µA  
1 mA  
SOT-23-5  
LAYOUT, GROUNDING, AND BYPASSING  
For best accuracy and minimum noise, the printed circuit board containing the DAC081S101 should have  
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.  
Both of these planes should be located in the same board layer. There should be a single ground plane. A single  
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a  
single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground  
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate  
ground planes must be connected in one place, preferably near the DAC081S101. Special care is required to  
guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a  
continuous return path below their traces.  
The DAC081S101 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to  
the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the  
0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC081S101 should only be  
used for analog circuits.  
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the  
board. The clock and data lines should have controlled impedances.  
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REVISION HISTORY  
Changes from Revision B (February 2013) to Revision C  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 19  
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PACKAGE OPTION ADDENDUM  
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11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
DAC081S101CIMK  
ACTIVE  
SOT  
SOT  
DDC  
6
6
1000  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 105  
-40 to 105  
X65C  
DAC081S101CIMK/NOPB  
ACTIVE  
DDC  
1000  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
X65C  
DAC081S101CIMKX  
ACTIVE  
ACTIVE  
SOT  
SOT  
DDC  
DDC  
6
6
3000  
3000  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 105  
-40 to 105  
X65C  
X65C  
DAC081S101CIMKX/NOPB  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
DAC081S101CIMM/NOPB  
ACTIVE  
VSSOP  
DGK  
8
1000  
Green (RoHS  
& no Sb/Br)  
CU SN  
Level-1-260C-UNLIM  
-40 to 105  
X64C  
DAC081S101CIMMX  
ACTIVE  
ACTIVE  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
3500  
3500  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 105  
-40 to 105  
X64C  
X64C  
DAC081S101CIMMX/NOPB  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
21-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
DAC081S101CIMK  
SOT  
DDC  
DDC  
DDC  
DDC  
6
6
6
6
1000  
1000  
3000  
3000  
178.0  
178.0  
178.0  
178.0  
8.4  
8.4  
8.4  
8.4  
3.2  
3.2  
3.2  
3.2  
3.2  
3.2  
3.2  
3.2  
1.4  
1.4  
1.4  
1.4  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
Q3  
DAC081S101CIMK/NOPB SOT  
DAC081S101CIMKX  
SOT  
SOT  
DAC081S101CIMKX/NOP  
B
DAC081S101CIMM/NOPB VSSOP  
DAC081S101CIMMX VSSOP  
DGK  
DGK  
DGK  
8
8
8
1000  
3500  
3500  
178.0  
330.0  
330.0  
12.4  
12.4  
12.4  
5.3  
5.3  
5.3  
3.4  
3.4  
3.4  
1.4  
1.4  
1.4  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
DAC081S101CIMMX/NOP VSSOP  
B
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
21-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
DAC081S101CIMK  
DAC081S101CIMK/NOPB  
DAC081S101CIMKX  
SOT  
SOT  
SOT  
SOT  
DDC  
DDC  
DDC  
DDC  
6
6
6
6
1000  
1000  
3000  
3000  
210.0  
210.0  
210.0  
210.0  
185.0  
185.0  
185.0  
185.0  
35.0  
35.0  
35.0  
35.0  
DAC081S101CIMKX/NOP  
B
DAC081S101CIMM/NOPB  
DAC081S101CIMMX  
VSSOP  
VSSOP  
VSSOP  
DGK  
DGK  
DGK  
8
8
8
1000  
3500  
3500  
210.0  
367.0  
367.0  
185.0  
367.0  
367.0  
35.0  
35.0  
35.0  
DAC081S101CIMMX/NOP  
B
Pack Materials-Page 2  
IMPORTANT NOTICE  
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