LM8325-1 [TI]
LM8325-1 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface; LM8325-1移动I / O伴侣支持键盘扫描， I / O扩展，PWM和ACCESS总线主机接口
| 型号： | LM8325-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM8325-1 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface |
| 文件： | 总60页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM8325-1
LM8325-1 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and
ACCESS.bus Host Interface
Literature Number: SNLS347
September 14, 2011
LM8325-1
Mobile I/O Companion Supporting Keyscan, I/O Expansion,
PWM, and ACCESS.bus Host Interface
Any pin programmed as an input can also sense hardware
interrupts. The interrupt polarity (“high to low” or “low to high”
1.0 General Description
The LM8325-1 GenI/O - Expander and Keypad Controller is
a dedicated device to unburden a host processor from scan-
ning a matrix-addressed keypad and to provide flexible and
general purpose, host programmable input/output functions.
Three independent PWM timer outputs are provided for dy-
namic LED brightness modulation.
transition) is thereby programmable.
The LM8325-1 follows a predefined register based set of
commands. Upon startup (power - on) a configuration file
must be sent from the host to setup the hardware of the de-
vice.
It communicates with a host processor through an I2C-com-
patible ACCESS.bus serial interface. It can communicate in
Standard (100 kHz) - and Fast-Mode (400 kHz) in slave Mode
only.
2.0 Applications
Cordless Phones
■
■
Smart Handheld Devices
Keyboard Applications
All available input/output pins can alternately be used as an
input or an output in a keypad matrix or as a host pro-
grammable general purpose input or output.
■
3.0 LM8325-1 Function Blocks
30170401
© 2011 National Semiconductor Corporation
301704
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•
•
Three PWM outputs with dedicated script buffer for up to
32 commands
Register-based command interpreter with auto increment
address
4.0 Features
4.1 KEY FEATURES
•
•
•
Internal RC oscillator, no external clock required
Internal PWM clock generation, no external clock required
Programmable I2C-compatible ACCESS.bus address
4.2 HOST-CONTROLLED FEATURES
•
•
•
•
•
PWM scripting for three PWM outputs
(Default 0x88)
Period of inactivity that triggers entry into HALT mode
Debounce time for reliable key event polling
Configuration of general purpose I/O ports
Various initialization options (keypad size, etc.)
•
•
•
•
Support for Keypad matrices of up to of 8 x 12 keys, plus
8 special function (SF) keys, for a full 104 key support
I2C-compatible ACCESS.bus slave interface at 100 kHz
(Standard-Mode) and 400 kHz (Fast-Mode)
Three host-programmable PWM outputs for smooth LED
brightness modulation
4.3 KEY DEVICE FEATURES
•
•
•
•
•
•
1.8V ± 10% single-supply operation
On-chip power-on reset (POR)
Watchdog timer
Dedicated slow clock input for 32 kHz to 2MHz
−40°C to +85°C temperature range
25-pin MICRO-ARRAY package
Supports general-purpose I/O expansion on pins not
otherwise used for keypad or PWM output
•
•
•
15 byte Key event buffer
Multiple Key event storage
Key events, errors, and dedicated hardware interrupts
request host service by asserting an IRQ output
•
•
Automatic HALT Mode for low power operation
Wake-up from HALT mode on any interface (rising edge,
falling edge or pulse)
5.0 Pin Assignments
30170402
FIGURE 1. LM8325-1 Pinout — Top View
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Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 LM8325-1 Function Blocks ............................................................................................................... 1
4.0 Features ........................................................................................................................................ 2
4.1 KEY FEATURES ...................................................................................................................... 2
4.2 HOST-CONTROLLED FEATURES ............................................................................................. 2
4.3 KEY DEVICE FEATURES ......................................................................................................... 2
5.0 Pin Assignments ............................................................................................................................. 2
6.0 Signal Descriptions .......................................................................................................................... 6
6.1 DEVICE PIN FUNCTIONS ........................................................................................................ 6
6.2 PIN CONFIGURATION AFTER RESET ...................................................................................... 6
7.0 Typical Application Setup ................................................................................................................. 8
7.1 FEATURES ............................................................................................................................. 8
7.1.1 Hardware ...................................................................................................................... 8
7.1.2 Communication Layer ..................................................................................................... 8
8.0 Halt Mode ...................................................................................................................................... 9
8.1 HALT MODE DESCRIPTION ..................................................................................................... 9
8.2 ACCESS.BUS ACTIVITY .......................................................................................................... 9
9.0 LM8325-1 Programming Interface .................................................................................................... 10
9.1 ACCESS.BUS COMMUNICATION ........................................................................................... 10
9.1.1 Starting a Communication Cycle ..................................................................................... 10
9.1.2 Communication Initialized from Host (Restart from Sleep Mode) ......................................... 11
9.1.3 ACCESS.Bus Communication Flow ................................................................................ 11
9.1.4 Auto Increment ............................................................................................................ 11
9.1.5 Reserved Registers and Bits .......................................................................................... 11
9.1.6 Global Call Reset ......................................................................................................... 11
10.0 Keyscan Operation ...................................................................................................................... 13
10.1 KEYSCAN INITIALIZATION ................................................................................................... 13
10.2 KEYSCAN INITIALIZATION EXAMPLE ................................................................................... 13
10.3 KEYSCAN PROCESS ........................................................................................................... 14
10.4 READING KEYSCAN STATUS BY THE HOST ........................................................................ 14
10.5 MULTIPLE KEY PRESSES ................................................................................................... 16
11.0 PWM Timer ................................................................................................................................ 16
11.1 OVERVIEW OF PWM FEATURES ......................................................................................... 16
11.2 OVERVIEW ON PWM SCRIPT COMMANDS ........................................................................... 16
11.2.1 RAMP COMMAND ..................................................................................................... 17
11.2.2 SET_PWM COMMAND ............................................................................................... 17
11.2.3 GO_TO_START COMMAND ....................................................................................... 17
11.2.4 BRANCH COMMAND ................................................................................................. 17
11.2.5 TRIGGER COMMAND ................................................................................................ 18
11.2.6 END COMMAND ........................................................................................................ 18
12.0 LM8325-1 Register Set ................................................................................................................. 19
12.1 KEYBOARD REGISTERS AND KEYBOARD CONTROL ........................................................... 19
12.1.1 KBDSETTLE - Keypad Settle Time Register ................................................................... 19
12.1.2 KBDBOUNCE - Debounce Time Register ...................................................................... 19
12.1.3 KBDSIZE - Set Keypad Size Register ............................................................................ 19
12.1.4 KBDDEDCFG - Dedicated Key Register ........................................................................ 20
12.1.5 KBDRIS - Keyboard Raw Interrupt Status Register .......................................................... 20
12.1.6 KBDMIS - Keypad Masked Interrupt Status Register ....................................................... 21
12.1.7 KBDIC - Keypad Interrupt Clear Register ....................................................................... 21
12.1.8 KBDMSK - Keypad Interrupt Mask Register .................................................................... 21
12.1.9 KBDCODE0 - Keyboard Code Register 0 ....................................................................... 22
12.1.10 KBDCODE1 - Keyboard Code Register 1 ..................................................................... 22
12.1.11 KBDCODE2 - Keyboard Code Register 2 ..................................................................... 22
12.1.12 KBDCODE3 - Keyboard Code Register 3 ..................................................................... 23
12.1.13 EVTCODE - Key Event Code Register ......................................................................... 23
12.2 PWM TIMER CONTROL REGISTERS .................................................................................... 23
12.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers .............................................. 23
12.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers ................................. 24
12.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers ................................................... 24
12.2.4 TIMSWRES - PWM Timer Software Reset Registers ....................................................... 24
12.2.5 TIMRIS - PWM Timer Interrupt Status Register ............................................................... 25
12.2.6 TIMMIS - PWM Timer Masked Interrupt Status Register .................................................. 26
12.2.7 TIMIC - PWM Timer Interrupt Clear Register .................................................................. 26
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12.2.8 PWMWP - PWM Timer Pattern Pointer Register ............................................................. 27
12.2.9 PWMCFG - PWM Script Register .................................................................................. 27
12.3 INTERFACE CONTROL REGISTERS ..................................................................................... 28
12.3.1 I2CSA - I2C-Compatible ACCESS.bus Slave Address Register ......................................... 28
12.3.2 MFGCODE - Manufacturer Code Register ..................................................................... 28
12.3.3 SWREV - Software Revision Register ............................................................................ 28
12.3.4 SWRESET - Software Reset ........................................................................................ 28
12.3.5 RSTCTRL - System Reset Register .............................................................................. 28
12.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register ................................................. 29
12.3.7 CLKMODE - Clock Mode Register ................................................................................ 29
12.3.8 CLKCFG - Clock Configuration Register ........................................................................ 30
12.3.9 CLKEN - Clock Enable Register ................................................................................... 30
12.3.10 AUTOSLP - Autosleep Enable Register ....................................................................... 30
12.3.11 AUTOSLPTI - Auto Sleep Time Register ...................................................................... 31
12.3.12 IRQST - Global Interrupt Status Register ...................................................................... 31
12.4 GPIO FEATURE CONFIGURATION ....................................................................................... 32
12.4.1 GPIO Feature Mapping ............................................................................................... 32
12.4.2 IOCGF - Input/Output Pin Mapping Configuration Register ............................................... 32
12.4.3 IOPC0 - Pull Resistor Configuration Register 0 ............................................................... 32
12.4.4 IOPC1 - Pull Resistor Configuration Register 1 ............................................................... 33
12.4.5 IOPC2 - Pull Resistor Configuration Register 2 ............................................................... 34
12.4.6 GPIOOME0 - GPIO Open Drain Mode Enable Register 0 ................................................. 34
12.4.7 GPIOOMS0 - GPIO Open Drain Mode Select Register 0 .................................................. 35
12.4.8 GPIOOME1 - GPIO Open Drain Mode Enable Register 1 ................................................. 35
12.4.9 GPIOOMS1 - GPIO Open Drain Mode Select Register 1 .................................................. 35
12.4.10 GPIOOME2 - GPIO Open Drain Mode Enable Register 2 ............................................... 35
12.4.11 GPIOOMS2 - GPIO Open Drain Mode Select Register 2 ................................................ 36
12.5 GPIO DATA INPUT/OUTPUT ................................................................................................. 36
12.5.1 GPIOPDATA0 - GPIO Data Register 0 .......................................................................... 36
12.5.2 GPIOPDATA1 - GPIO Data Register 1 .......................................................................... 37
12.5.3 GPIOPDATA2 - GPIO Data Register 2 .......................................................................... 38
12.5.4 GPIOPDIR0 - GPIO Port Direction Register 0 ................................................................. 39
12.5.5 GPIOPDIR1 - GPIO Port Direction Register 1 ................................................................. 39
12.5.6 GPIOPDIR2 - GPIO Port Direction Register 2 ................................................................. 39
12.6 GPIO INTERRUPT CONTROL ............................................................................................... 39
12.6.1 GPIOIS0 - Interrupt Sense Configuration Register 0 ........................................................ 39
12.6.2 GPIOIS1 - Interrupt Sense Configuration Register 1 ........................................................ 40
12.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2 ........................................................ 40
12.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 ............................................... 40
12.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 ............................................... 40
12.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 ............................................... 41
12.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0 ......................................................... 41
12.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1 ......................................................... 41
12.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2 ......................................................... 41
12.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0 ................................................................ 42
12.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1 ................................................................ 42
12.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2 ................................................................ 42
12.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0 .................................................................. 42
12.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1 .................................................................. 42
12.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2 .................................................................. 43
12.7 GPIO INTERRUPT STATUS .................................................................................................. 43
12.7.1 GPIORIS0 - Raw Interrupt Status Register 0 .................................................................. 43
12.7.2 GPIORIS1 - Raw Interrupt Status Register 1 .................................................................. 43
12.7.3 GPIORIS2 - Raw Interrupt Status Register 2 .................................................................. 43
12.7.4 GPIOMIS0 - Masked Interrupt Status Register 0 ............................................................. 44
12.7.5 GPIOMIS1 - Masked Interrupt Status Register 1 ............................................................. 44
12.7.6 GPIOMIS2 - Masked Interrupt Status Register 2 ............................................................. 44
12.8 GPIO WAKE-UP CONTROL .................................................................................................. 44
12.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0 ..................................................................... 44
12.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1 ..................................................................... 45
12.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2 ..................................................................... 45
13.0 Absolute Maximum Ratings ........................................................................................................... 46
14.0 Electrical Characteristics ............................................................................................................... 46
15.0 Register ..................................................................................................................................... 49
15.1 REGISTER MAPPING .......................................................................................................... 49
15.1.1 Keyboard Registers .................................................................................................... 49
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15.1.2 PWM Timer Registers ................................................................................................. 49
15.1.3 System Registers ....................................................................................................... 50
15.1.4 Global Interrupt Registers ............................................................................................ 50
15.1.5 GPIO Registers .......................................................................................................... 51
16.0 Physical Dimensions .................................................................................................................... 57
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6.0 Signal Descriptions
6.1 DEVICE PIN FUNCTIONS
TABLE 1. KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS
Ball
C2
A4
D1
D2
C5
A5
E1
E2
A2
B3
A3
B4
E5
C4
D5
B5
B2
A1
B1
C1
D4
Function 0
Slow Clock Input
Supply Voltage
Main I2C - Clk
Main I2C - data
Keypad-I/O X0
Keypad-I/O X1
Keypad-I/O X2
Keypad-I/O X3
Keypad-I/O X4
Keypad-I/O X5
Keypad-I/O X6
Keypad-I/O X7
Keypad-I/O Y0
Keypad-I/O Y1
Keypad-I/O Y2
Keypad-I/O Y3
Keypad-I/O Y4
Keypad-I/O Y5
Keypad-I/O Y6
Keypad-I/O Y7
Keypad-I/O Y8
Function 1
Function 2
Function 3
Pin Count
Ball Name
CLKIN
VCC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCL
SDA
Genio0
Genio1
Genio2
Genio3
Genio4
Genio5
Genio6
Genio7
Genio8
Genio9
Genio10
Genio11
Genio12
Genio13
Genio14
Genio15
Genio16
KPX0
KPX1
KPX2
KPX3
KPX4
KPX5
KPX6
KPX7
KPY0
KPY1
KPY2
KPY3
KPY4
KPY5
KPY6
KPY7
KPY8
PWM2
KPY9
PWM1
KPY10
PWM0
IRQN
KPY11
PWM2
GND
ClockOut
Genio19
PWM2
PWM1
PWM0
PWM2
E4
D3
E3
Keypad-I/O Y9
Keypad-I/O Y10
Interrupt
Genio17
Genio18
1
1
1
Keypad-I/O Y11
C3
Ground
TOTAL
1
25
6.2 PIN CONFIGURATION AFTER RESET
Upon power-up or RESET the LM8325-1 will have defined states on all pins. Table 2 provides a comprehensive overview on the
states of all functional pins.
TABLE 2. Pin Configuration after Reset
Pins
KPX0
KPX1
KPX2
KPX3
KPX4
KPX5
KPX6
KPX7
Pin States
Full Buffer mode with an on-chip pull up resistor enabled.
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Pins
KPY0
Pin States
KPY1
KPY2
KPY3
KPY4
KPY5
Full Buffer mode with an on-chip pull down resistor enabled.
KPY6
KPY7
KPY8 / PWM2
KPY9 / PWM1
KPY10 / PWM0
Open Drain mode with no pull resistor enabled, driven low (IRQN).
(Note: The IRQN is driven low after Power-On Reset due to PORIRQ signal. The value
0x01 must be written to the RSTINTCLR register (0x84) to release the IRQN pin.)
KPY11 / IRQN / PWM2
SCL
SDA
Open Drain mode with no pull resistor enabled.
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7.0 Typical Application Setup
30170403
FIGURE 2. LM8325-1 in a Typical Setup with Standard Handset Keypad
7.1 FEATURES
The following features are supported with the application example shown in example above:
7.1.1 Hardware
Hardware
•
4 x 8 keys and 8 Special Function (SF) keys for 40 keys.
•
ACCESS.bus interface for communication with a host device.
- communication speeds supported are: 100 kHz and 400 kHz fast mode of operation.
•
•
•
•
•
Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host.
Sophisticated PWM function block with 3 independent channels to control color LED.
External clock input for accurate PWM clock (not used).
Two host programmable dedicated general-purpose output pins (GPIOs) supporting IO-expansion capabilities for host device.
Two host programmable dedicated general-purpose input pins with wake-up supporting IO-expansion capabilities for host
device.
7.1.2 Communication Layer
•
•
•
Versatile register-based command integration supported from on-chip command interpreter.
Keypad event storage.
Individual PWM script file storage and execution control for 3 PWM channels.
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Halt mode is entered when no key-press event, key-release
event, or ACCESS.bus activity is detected for a certain period
of time (by default, 1020 milliseconds). The mechanism for
entering Halt mode is always enabled in hardware, but the
host can program the period of inactivity which triggers entry
into Halt mode using the autosleep function. (See Table 51.)
8.0 Halt Mode
8.1 HALT MODE DESCRIPTION
The fully static architecture of the LM8325-1 allows stopping
the internal RC clock in Halt mode, which reduces power con-
sumption to the minimum level. Figure 3 shows the current in
Halt mode at the maximum VCC (1.98V) from 25°C to +85°
C.
8.2 ACCESS.BUS ACTIVITY
When the LM8325-1 is in Halt mode, only activity on the
ACCESS.bus interface that matches the LM8325-1 Slave Ad-
dress will cause the LM8325-1 to exit from Halt mode. How-
ever, the LM8325-1 will not be able to acknowledge the first
bus cycle immediately following wake-up from Halt mode. It
will respond with a negative acknowledgement, and the host
should then repeat the cycle. A peripheral that is continuously
active can share the bus since this activity will not prevent the
LM8325-1 from entering Halt mode.
30170404
FIGURE 3. Halt Current vs. Temperature at 1.98V
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mission protocol. All functions can be controlled by configur-
ing one or multiple registers. Please refer to Section 12.0
LM8325-1 Register Set for the complete register set.
9.0 LM8325-1 Programming
Interface
The LM8325-1 operation is controlled from a host device by
a complete register set, accessed via the I2C-compatible
ACCESS.bus interface. The ACCESS.bus communication is
based on a READ/WRITE structure, following the I2C trans-
9.1 ACCESS.BUS COMMUNICATION
Figure 4 shows a typical read cycle initiated by the host.)
30170405
FIGURE 4. Master/Slave Serial Communication (Host to LM8325-1)
TABLE 3. Definition of Terms used in Serial Command Example
Term
S
Bits
Description
START Condition (always generated from the master device)
Slave address of LM8325-1 sent from the host
ADDRESS
7
This bit determines if the following data transfer is from master to slave (data write) or from slave
to master (data read).
0: Write
R/W
1
1: Read
An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge
status is actually provided from the slave and indicates to the master, that the byte transfer was
successful.
ACK
REG
1
8
The first byte after sending the slave address is the REGISTER byte which contains the physical
address the host wants to read from or write to.
RS
Repeated START condition
DATA
8
1
The DATA field contains information to be stored into a register or information read from a register.
Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data
from a slave. The NACK status will actually be assigned from the master in order to signal the
end of a communication cycle transfer
NACK
P
STOP condition (always generated from the master device)
All actions associated with the non-shaded boxes in Figure
4 are controlled from the master (host) device.
initializes a hardware interrupt from LM8325-1 to the
host.
2. The host device wants to set a GENIO port, read from a
GENIO port, configure a GENIO port, and read the status
from a register or initialize any other function which is
supported from the LM8325-1. In case a GENIO shall be
read it will be most likely, that the LM8325-1 device will
be residing in “sleep mode”. In this mode the system
clock will be off to establish the lowest possible current
consumption. If the host device starts the communication
under this condition the LM8325-1 device will not be able
to acknowledge the first attempt of sending the slave
address. The LM8325-1 will wake up because of the
START condition but it can’t establish the internal timing
to scan the first byte received. The master device must
therefore apply a second attempt to start the
All actions associated with the shaded boxes in Figure 4 are
controlled from the slave (LM8325-1) device.
The master device can send subsequent REGISTER ad-
dresses separated by Repeated START conditions. A STOP
condition must be set from the master at the very end of a
communication cycle.
It is recommended to use Repeated START conditions in
multi-Master systems when sending subsequent REGISTER
addresses. This technique will make sure that the master de-
vice communicating with the LM8325-1 will not loose bus
arbitration.
9.1.1 Starting a Communication Cycle
There are two reasons for the host device to start communi-
cation to the LM8325-1:
communication with the LM8325-1 device.
1. The LM8325-1 device has set the IRQN line low in order
to signal a key - event or any other condition which
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9.1.2 Communication Initialized from Host (Restart from Sleep Mode)
30170406
FIGURE 5. Host Starts Communication While LM8325-1 is in Sleep Mode
•
In the timing diagram shown in Figure 5 the LM8325-1 resides in sleep mode. Since the LM8325-1 device can’t acknowledge
the slave address the host must generate a STOP condition followed by a second START condition.
•
•
•
On the second attempt the slave address is being acknowledged from the LM8325-1 device because it is in active mode now.
The host can send different WRITE and/or READ commands subsequently after each other.
The host must finally free the bus by generating a STOP condition.
9.1.3 ACCESS.Bus Communication Flow
A typical protocol access sequence to the LM8325-1 starts
with the I2C-compatible ACCESS.bus address, followed by
REG, the register to access (see Figure 4). After a REPEAT-
ED START condition the host reads/writes a data byte from/
to this address location. If more than one byte is transmitted,
the LM8325-1 automatically increments the address pointer
for each data byte by 1. The address pointer keeps the status
until the STOP condition is received.
The LM8325-1 will only be driven in slave mode. The maxi-
mum communication speed supported is Fast Mode (FS)
which is 400 kHz. The device can be heavily loaded as it is
processing different kind of events caused from the human
interface and the host device. In such cases the LM8325-1
may temporarily be unable to accept new commands and da-
ta sent from the host device.
The LM8325-1 always uses auto increments unless other-
wise noted.
Please Note: “It is a legitimate measure of the slave device to
hold SCL line low in such cases in order to force the master
device into a waiting state!. It is therefore the obligation of the
host device to detect such cases. Typically there is a control
bit set in the master device indicating the Busy status of the
bus. As soon as the SCL line is released the host can continue
sending commands and data.”
Please refer to Table 5 and Table 5 for the typical
ACCESS.bus flow of reading and writing multiple data bytes.
9.1.5 Reserved Registers and Bits
The LM8325-1 includes reserved registers for future imple-
mentation options. Please use value 0 on a write to all re-
served register bits.
Further Remarks:
•
In systems with multiple masters it is recommended to
separate commands with Repeat START conditions
rather than sending a STOP - and another START -
condition to communicate with the LM8325-1 device.
9.1.6 Global Call Reset
The LM8325-1 supports the Global Call Reset as defined in
the I2C Specification, which can be used by the host to reset
all devices connected to interface. The Global call reset is a
single byte ACCESS.bus/I2C write of data byte 0x06 to slave
address 0x00.
The Global Call Reset changes the I2C-compatible
ACCESS.bus Slave address of the LM8325-1 back to its de-
fault value of 0x88.
•
•
Delays enforced by the LM8325-1 during very busy
phases of operation should typically not exceed a duration
of 100 usec.
Normally the LM8325-1 will clock stretch after the
acknowledge bit Is transmitted; however, there are some
conditions where the LM8325-1 will clock stretch between
the SDA Start bit and the first rising edge of SCL.
9.1.4 Auto Increment
In order to improve multi-byte register access, the LM8325-1
supports the auto increment of the address pointer.
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TABLE 4. Multi-Byte Write with Auto Increment
I2C Com.
S
Step
1
Master/Slave
Value
Address Pointer
Comment
START condition
I2C-compatible ACCESS.bus Address
M
M
M
S
2
ADDR.
R/W
0x88
0
3
Write
4
ACK
REG
ACK
DATA
ACK
DATA
ACK
P
Acknowledge
5
M
S
0xAA
0xAA
0xAA
0xAA
0xAB
0xAB
0xAC
Register Address, used as Address Pointer
Acknowledge
6
7
M
S
0x01
0
Write Data to Address in Pointer
Acknowledge, Address pointer incremented
Write Data to address 0xAB
Acknowledge, Address pointer incremented
STOP condition
8
9
M
S
0x05
0
10
11
M
TABLE 5. Multi-Byte Read with Auto Increment
I2C Com.
S
Step
1
Master/Slave
Value
Address Pointer
Comment
START condition
I2C-compatible ACCESS.bus Address
M
M
M
S
2
ADDR.
R/W
0x88
0
3
Write
4
ACK
REG
ACK
RS
Acknowledge
5
M
S
0xAA
0xAA
0xAA
0xAA
0xAA
Register Address, used as Address pointer
Acknowledge
6
7
M
M
M
S
Repeated Start
I2C-compatible ACCESS.bus Address
8
ADDR.
R/W
0x88
1
9
Read
10
11
12
13
14
15
ACK
DATA
ACK
DATA
NACK
P
0
0xAA
0xAA
0xAB
0xAB
0xAC
Acknowledge
S
0x01
0
Read Data from Address in Pointer
Acknowledge, Address Pointer incremented
Read Data from Address in Pointer
No Acknowledge, stops transmission
STOP condition
M
S
0x05
0
M
M
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12
10.0 Keyscan Operation
10.1 KEYSCAN INITIALIZATION
30170407
FIGURE 6. Keyscan Initialization
10.2 KEYSCAN INITIALIZATION EXAMPLE
•
Keypad matrix configuration is 8 rows x 8 columns.
Table 6 shows all the LM8325-1 register configurations to ini-
tialize keyscan:
TABLE 6. Keyscan Initialization Example
Access
Register name
adress
Value
Comment
Type
byte
byte
byte
byte
word
byte
word
word
byte
byte
CLKEN
KBDSETTLE
KBDBOUNCE
KBDSIZE
KBDDEDCFG
IOCFG
0x8A
0x01
0x02
0x03
0x04
0xA7
0xAA
0xAC
0x08
0x09
0x01
0x80
enable keyscan clock
set the keyscan settle time to 12 msec
set the keyscan debounce time to 12 msec
set the keyscan matrix size to 8 rows x 8 columns
configure KPX[7:2] and KPY[7:2] pins as keyboard matrix
write default value to enable all pins as keyboard matrix
configure pull-up resistors for KPX[7:0]
configure pull-down resistors for KPY[7:0]
clear any pending interrupts
0x80
0x88
0xFC3F
0xF8
IOPC0
0xAAAA
0x5555
0x03
IOPC1
KBDIC
KBDMSK
0x03
enable keyboard interrupts
13
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10.3 KEYSCAN PROCESS
the device sets the RAW keyboard event interrupt REVTINT.
The RSINT interrupt is set anytime the keyboard status has
changed.
The LM8325-1 keyscan functionality is based on a specific
scanning procedure performed in a 4ms interval. On each
scan all assigned key matrix pins are evaluated for state
changes.
Depending on the interrupt masking for the keyboard events
(KBDMSK) and the masked interrupt handling (KBDMIS), the
pin IRQN/KPY11/PWM2 will follow the IRQST.KBDIRQ sta-
tus, which is set as soon as one interrupt in KBDRIS is set.
In case a key event has been identified, the event is stored in
the key event FIFO, accessible via the EVTCODE register. A
key event can either be a key press or a key release. In ad-
dition, key presses are also stored in the KBDCODE[3:0]
registers. As soon as the EVTCODE FIFO includes a event,
Figure 7 shows the basic flow of a scanning process and
which registers are affected.
30170408
FIGURE 7. Example Keyscan Operation for
1 Key Press and Release
10.4 READING KEYSCAN STATUS BY THE HOST
host first reads the KBDCODE to get possible key press
events and afterwards reads the complete event list by read-
ing the EVTCODE register until all events are captured (0x7F
indicates end of buffer).
In order to keep track of the keyscan status, the host either
needs to regularly poll the EVTCODE register or needs to re-
act on the Interrupt signalled by the IRQN/KPY11/PWM2 pin,
in case the ball is configured for interrupt functionality. (See
Section 12.4 GPIO FEATURE CONFIGURATION).
Reading KBDCODE clears the RSINT interrupt bit if all key-
boards events are emptied. In the same way, REVTINT is
cleared in case the EVTCODE FIFO reaches its empty state
on read.
Figure 8 gives an example on which registers to read to get
the keyboard events from the LM8325-1 and how they influ-
ence the interrupt event registers. The example is based on
the assumption that the LM8325-1 has indicated the keyboard
event by the IRQN/KPY11/PWM2 pin.
The event buffer content and the REVTINT and RELINT (lost
event) interrupt bits are also cleared if the KBDIC.EVTIC bit
is set.
Since the interrupt pin has various sources, the host first
checks the IRQST register for the interrupt source. If KBDIRQ
is set, the host can check the KBDMIS register to define the
exact interrupt source. KBDMIS contains the masked status
of KBDRIS and reflects the source for raising the interrupt pin.
The interrupt mask is defined by KBDMSK. The complete
status of all pending keyboard interrupts is available in the raw
interrupt register KBDRIS.
Interrupt bits in the masked interrupt register KBDMIS follow
the masked KBDRIS status.
In order to support efficient Multi-byte reads from EVTCODE,
the autoincrement feature is turned off for this register. There-
fore the host can continuously read the complete EVTCODE
buffer by sending one command.
After evaluating the interrupt source the host starts reading
the EVTCODE or KBDCODE register. In this example the
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30170409
FIGURE 8. Example Host Reacting to
Interrupt for Keypad Event
15
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10.5 MULTIPLE KEY PRESSES
KBDCODE3 accordingly. The four registers signal the last
multi key press events.
The LM8325-1 supports up to four simultaneous key presses.
Any time a single key is pressed KBDCODE0 is set with the
appropriate key code. If a second key is pressed, the key is
stored in KBDCODE1 and the MULTIKEY flag of KBDCODE0
is set. Additional key presses are stored in KBDCODE2 and
All events are stored in parallel in the EVTCODE register for
the complete set of events.
All KBDCODE[3:0] registers are cleared on read.
30170410
FIGURE 9. Example Keyscan Operation for 2 Key Press Events
and 1 Key Release Event
•
The execution of any pre-programmed task is self-
sustaining and does not require further interaction from the
host.
64-byte script buffer for each PWM for up to 32
consecutive instructions.
Direct addressing within script buffer to support multiple
PWM tasks in one buffer.
11.0 PWM Timer
The LM8325-1 supports a timer module dedicated to smooth
LED control techniques (lighting controls).
•
•
The PWM timer module consists of three independent timer
units of which each can generate a PWM output with a fixed
period and automatically incrementing or decrementing vari-
able duty cycle. The timer units are all clocked with a slow
(32.768 kHz) clock whereas the interface operates with the
main system clock.
11.2 OVERVIEW ON PWM SCRIPT COMMANDS
The commands listed in Table 7 are dedicated to the slow
PWM timers.
11.1 OVERVIEW OF PWM FEATURES
Please note: The PWM Script commands are not part of the
command set supported by the LM8325-1 command inter-
preter. These commands must be transferred from the host
with help of the register-based command set.
•
Each PWM can establish fixed — or variable — duty-cycle
signal sequences on its output.
Each PWM can trigger execution of any pre-programmed
task on another PWM channel.
•
TABLE 7. PWM Script Commands
Command
RAMP
15
0
14
PRESCALE
1
13 12
11
10
9
8
7
6
5
4
3
2
1
0
STEPTIME
0
SIGN
INCREMENT
PWMVALUE
SET_PWM
GO_TO_
START
0
0
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16
Command
BRANCH
END
15
1
14
0
13 12
11
10
9
8
7
6
5
4
3
2
1
0
1
LOOPCOUNT
ADDR
STEPNUMBER
1
1
0
1
1
INT
X
TRIGGER
1
1
WAITTRIGGER
SENDTRIGGER
0
11.2.1 RAMP COMMAND
the direction of a RAMP (up or down). The STEPTIME field
and the PRESCALE bit determine the duration of one step.
Based on a 32.768 kHz clock, the minimum time resulting
from these options would be 0.49 milliseconds and the max-
imum time for one step would be 1 second.
A RAMP command will vary the duty cycle of a PWM output
in either direction (up or down). The INCREMENT field spec-
ifies the amount of steps for the RAMP. The maximum amount
of steps which can be executed with one RAMP Command is
126 which is equivalent to 50%. The SIGN bit field determines
TABLE 8. RAMP Command Bit and Building Fields
15
14
13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
PRESCALE
STEPTIME
SIGN
INCREMENT
TABLE 9. Description of Bit and Building Fields of the RAMP Command
Bit or Field
PRESCALE
STEPTIME
SIGN
Value
Description
Divide the 32.768 kHz clock by 16
0
1
1 - 63
0
Divide the 32.768 kHz clock by 512
Number of prescaled clock cycles per step
Increment RAMPcounter
1
Decrement RAMPcounter
Number of steps executed by this instruction; a value of 0 functions as a
WAIT determined by STEPTIME.
INCREMENT
0 - 126
11.2.2 SET_PWM COMMAND
following the SET_PWM command will finally establish the
desired duty cycle on the PWM output.
The SET_PWM command will set the starting duty cycle MIN
SCALE or FULL SCALE (0% or 100%). A RAMP command
TABLE 10. SET_PWM Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
DUTYCYCLE
TABLE 11. Description of Bit and Building Fields of the SET_PWM Command
Bit or Field
Value
0
Description
Duty cycle is 0%.
DUTYCYCLE
255
Duty cycle is 100%.
11.2.3 GO_TO_START COMMAND
The GO_TO_START command jumps to the first command
in the script command file.
TABLE 12. GO_TO_START Command Bit and Building Fields
15
14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
0
11.2.4 BRANCH COMMAND
gives the option of looping for a specified number of repeti-
tions.
The BRANCH command jumps to the specified command in
the script command file. The branch is executed with either
absolute or relative addressing. In addition, the command
Please note: Nested loops are not allowed.
TABLE 13. BRANCH Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
LOOPCOUNT
ADDR
STEPNUMBER
17
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TABLE 14. Description of Bit and Building Fields of the BRANCH Command
Bit or Field
Value
Description
Loop until a STOP PWM SCRIPT command is issued by the host.
Number of loops to perform.
0
1 - 63
0
LOOPCOUNT
Absolute addressing
ADDR
1
Relative addressing
Depending on ADDR:
STEPNUMBER
0 - 63
ADDR = 0; Addr to jump to
ADDR = 1 - Number of backward steps
11.2.5 TRIGGER COMMAND
On trigger it will clear the trigger(s) and continue to the next
command.
Triggers are used to synchronize operations between PWM
channels. A TRIGGER command that sends a trigger takes
sixteen 32.768 kHz clock cycles, and a command that waits
for a trigger takes at least sixteen 32.768 kHz clock cycles.
When a trigger is sent, it is stored by the receiving channel
and can only be cleared when the receiving channel executes
a TRIGGER command that waits for the trigger.
A TRIGGER command that waits for a trigger (or triggers) will
stall script execution until the trigger conditions are satisfied.
TABLE 15. TRIGGER Command Bit and Building Fields
11 10
WAITTRIGGER
15
14
13
12
9
8
7
6
5
4
3
2
1
0
1
1
1
SENDTRIGGER
0
TABLE 16. Description of Bit and Building Fields
Field
Value
000xx1
000x1x
0001xx
000xx1
000x1x
0001xx
Description
Wait for trigger from channel 0
Wait for trigger from channel 1
Wait for trigger from channel 2
Send trigger to channel 0
WAITTRIGGER
SENDTRIGGER
Send trigger to channel 1
Send trigger to channel 2
11.2.6 END COMMAND
Please note: If a PWM channel is waiting for the trigger (last
executed command was "TRIGGER") and the script execu-
tion is halted then the "END" command can’t be executed
because the previous command is still pending. This is an
exception - in this case the IRQ signal will not be asserted.
The END command terminates script execution. It will only
assert an interrupt to the host if the INT bit is set to “1”.
When the END command is executed, the PWM output will
be set to the level defined by PWMCFG.PWMPOL for this
channel. Also, the script counter is reset back to the beginning
of the script command buffer.
TABLE 17. END Command Bit and Building Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
1
INT
0
TABLE 18. Description of Bit and Building Fields of the END Command
Field
Value
Description
0
1
No interrupt will be sent.
Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended.
INT
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18
12.0 LM8325-1 Register Set
12.1 KEYBOARD REGISTERS AND KEYBOARD
CONTROL
Keyboard selection and control registers are mapped in the
address range from 0x01 to 0x10. This paragraph describes
the functions of the associated registers down to the bit level.
12.1.1 KBDSETTLE - Keypad Settle Time Register
TABLE 19. KBDSETTLE - Keypad Settle Time Register
Address Type Register Function
Register - Name
KBDSETTLE
0x01
R/W
Initial time for keys to settle, before the key-scan process is started.
Bit - Name
Bit
Default
Bit Function
The default value 0x80 : 0xBF sets a time target of 12 msec
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00 : no settle time
12.1.2 KBDBOUNCE - Debounce Time Register
TABLE 20. KBDBOUNCE - Debounce Time Register
Register - Name
Address
Type
Register Function
KBDBOUNCE
0x02
R/W
Time between first detection of key and final sampling of key
Bit - Name
Bit
Default
Bit Function
The default value 0x80 : 0xBF sets a time target of 12 msec
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00: no debouncing time
12.1.3 KBDSIZE - Set Keypad Size Register
TABLE 21. KBDSIZE - Set Keypad Size Register
Register - Name
Address
Type
Register Function
KBDSIZE
0x03
R/W
Defines the physical keyboard matrix size
Bit - Name
Bit
Default
Bit Function
Number of rows in the keyboard matrix
0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key
inputs if scanning is enabled by CLKEN.KBEN
0x1: (illegal value)
ROWSIZE[3:0]
7:4
0x2
0x2 - 0x8: Number of rows in the matrix
Number of columns in the keyboard matrix
0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key
inputs if scanning is enabled by CLKEN.KBEN
0x1: (illegal value)
COLSIZE[3:0]
3:0
0x2
0x2 - 0xC: Number of columns in the matrix
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12.1.4 KBDDEDCFG - Dedicated Key Register
TABLE 22. KBDDEDCFG - Dedicated Key Register
Register - Name
Address
Type
Register Function
Defines if a key is used as a standard keyboard/GPIO pin or whether
it is used as dedicated key input.
KBDDEDCFG
0x04
R/W
Bit - Name
Bit
Default
Bit Function
Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2.
Bit=0: the dedicated key function applies.
ROW[7:2]
15:10
0x3F
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [11:10] corresponds to ball KPY11 : KPY10.
Bit=0: the dedicated key function applies.
COL[11:10]
COL[9:2]
9:8
7:0
0x03
0xFF
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be
configured individually.
Bit=0: the dedicated key function applies.
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
12.1.5 KBDRIS - Keyboard Raw Interrupt Status Register
TABLE 23. KBDRIS - Keyboard Raw Interrupt Status Register
Register - Name
Address
Type
Register Function
KBDRIS
0x06
R
Returns the status of stored keyboard interrupts.
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Raw event lost interrupt.
More than 8 keyboard events have been detected and caused the
event buffer to overflow. This bit is cleared by setting bit EVTIC of the
KBDIC register.
RELINT
3
2
0x0
Raw keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this
interrupt.
REVTINT
0x0
Raw key lost interrupt indicates a lost key-code.
This interrupt is asserted when RSINT has not been cleared upon
detection of a new key press or key release, or when more than 4 keys
are pressed simultaneously.
RKLINT
RSINT
1
0
0x0
0x0
Raw scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed.
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12.1.6 KBDMIS - Keypad Masked Interrupt Status
Register
TABLE 24. KBDMIS - Keypad Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
Returns the status on masked keyboard interrupts after masking with
the KBDMSK register.
KBDMIS
0x07
R
Bit - Name
Bit
Default
Bit Functions
(reserved)
7:4
(reserved)
Masked event lost interrupt.
More than 8 keyboard events have been detected and caused the
event buffer to overflow. This bit is cleared by setting bit EVTIC of the
KBDIC register.
MELINT
3
2
0x0
Masked keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this
interrupt.
MEVTINT
0x0
Masked key lost interrupt.
Indicates a lost key-code. This interrupt is asserted when RSINT has
not been cleared upon detection of a new key press or key release,
or when more than 4 keys are pressed simultaneously.
MKLINT
MSINT
1
0
0x0
0x0
Masked scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed, after masking process.
12.1.7 KBDIC - Keypad Interrupt Clear Register
TABLE 25. KBDIC - Keypad Interrupt Clear Register
Register - Name
Address
Default
Register Function
KBDIC
0x08
W
Setting these bits clears Keypad active Interrupts
Bit - Name
Bit
Default
Bit Function
Switches off scanning of special function (SF) keys, when keyboard
has no special function layout.
SFOFF
7
0: keyboard layout and SF keys are scanned
1: only keyboard layout is scanned, SF keys are not scanned
(reserved)
EVTIC
6:2
1
(reserved)
Clear event buffer and corresponding interrupts REVTINT and
RELINT by writing a 1 to this bit position
Clear RSINT and RKLINT interrupt bits by writing a 1 to this bit
position.
KBDIC
0
12.1.8 KBDMSK - Keypad Interrupt Mask Register
TABLE 26. KBDMSK - Keypad Interrupt Mask Register
Register - Name
Address
Type
Register Function
Configures masking of keyboard interrupts. Masked interrupts do not
trigger an event on the Interrupt output.
In case the interrupt processes registers KBDCODE[3:0], MSKELINT
and MSKEINT should be set to 1. When the Event FIFO is processed,
MSKLINT and MSKSINT should be set. For keyboard polling
operations, all bits should be set and the polling operation consists of
reading out the EVTCODE.
KBDMSK
0x09
R/W
Bit - Name
Bit
Default
Bit Function
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Register - Name
Address
Type
Register Function
(reserved)
7:4
(reserved)
0: keyboard event lost interrupt RELINT triggers IRQ line
1: keyboard event lost interrupt RELINT is masked
0: keyboard event interrupt REVINT triggers IRQ line
1: keyboard event interrupt REVINT is masked
0: keyboard lost interrupt RKLINT triggers IRQ line
1: keyboard lost interrupt RKLINT is masked
MSKELINT
MSKEINT
MSKLINT
MSKSINT
3
2
1
0
0x0
0x0
0x1
0x1
0: keyboard status interrupt RSINT triggers IRQ line
1: keyboard status interrupt RSINT is masked
12.1.9 KBDCODE0 - Keyboard Code Register 0
Please note: Reading out all key code registers (KBDCODE0
to KBDCODE3) will automatically reset the keyboard scan in-
terrupt RSINT the same way as an active write access into bit
KBDIC of the interrupt clear register does. Reading 0x7F from
the KBDCODE0 register means that no key was pressed.
The key code detected by the keyboard scan can be read from
the registers KBDCODE0: KBDCODE3. Up to 4 keys can be
detected simultaneously. Each KBDCODE register includes
a bit (MULTIKEY) indicating if another key has been detected.
TABLE 27. KBDCODE0 - Keyboard Code Register 0
Register - Name
Address
Default
Register Function
KBDCODE0
0x0B
R
Holds the row and column information of the first detected key
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
if this bit is 1 another key is available in KBDCODE1 register
ROW index of detected key (0 to 7)
KEYROW[2:0]
KEYCOL[3:0]
6:4
3:0
0x7
0xF
Column index of detected (0 to 11, 12 for special function key.
12.1.10 KBDCODE1 - Keyboard Code Register 1
TABLE 28. KBDCODE1 - Keyboard Code Register 1
Register - Name
Address
Default
Register Function
KBDCODE1
0x0C
R
Holds the row and column information of the second detected key
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
if this bit is 1 another key is available in KBDCODE2 register
ROW index of detected key (0 to 7)
KEYROW[2:0]
KEYCOL[3:0]
6:4
3:0
0x7
0xF
Column index of detected key (0 to 11, 12 for special function key.
12.1.11 KBDCODE2 - Keyboard Code Register 2
TABLE 29. KBDCODE2 - Keyboard Code Register 2
Register - Name
Address
Default
Register Function
KBDCODE2
0x0D
R
Holds the row and column information of the third detected key
Bit - Name
MULTIKEY
Bit
7
Default
0x0
Bit Function
if this bit is 1 another key is available in KBDCODE3 register
ROW index of detected key (0 to 7)
KEYROW[2:0]
KEYCOL[3:0]
6:4
3:0
0x7
0xF
Column index of detected key (0 to 11, 12 for special function key.
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12.1.12 KBDCODE3 - Keyboard Code Register 3
TABLE 30. KBDCODE3 - Keyboard Code Register 3
Register - Name
Address
Default
Register Function
KBDCODE3
0x0E
R
Holds the row and column information of the forth detected key
Bit - Name
Bit
Default
Bit Function
if this bit is set to “1” then more than 4 keys are pressed
simultaneously.
MULTIKEY
7
0x0
KEYROW[2:0]
KEYCOL[3:0]
6:4
3:0
0x7
0xF
ROW index of detected key (0 to 7)
Column index of detected key (0 to 11, 12 for special function key.
12.1.13 EVTCODE - Key Event Code Register
TABLE 31. EVTCODE - Key Event Code Register
Register - Name
Address
Default
Bit Function
With this register a FIFO buffer is addressed storing up to 15
consecutive events.
Reading the value 0x7F from this address means that the FIFO buffer
is empty. See further details below.
EVTCODE
0x10
R
NOTE: Auto increment is disabled on this register. Multi-byte read will
always read from the same address.
Bit - Name
Bit
Default
Bit Function
This bit indicates, whether the keyboard event was a key press or a
key release event.
0: key was pressed
1: key was released
RELEASE
7
0x0
KEYROW[2:0]
KEYCOL[3:0]
6:4
3:0
0x7
0xF
Row index of key that is pressed or released.
Column index of key that is pressed (0...11, 12 for special function
key) or released.
12.2 PWM TIMER CONTROL REGISTERS
timer control registers are mapped in the range from 0x60 to
0x7F. This paragraph describes the functions of the associ-
ated registers down to the bit level.
The LM8325-1 provides three host-programmable PWM out-
puts useful for smooth LED brightness modulation. All PWM
12.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers
TABLE 32. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers
Register - Name
TIMCFG0
Address
0x60
Type
Register Function
This register configures interrupt masking and handles PWM start/
stop control of the associated PWM channel.
TIMCFG1
0x68
R/W
TIMCFG2
0x70
Bit - Name
(x = 0, 1 or 2)
Bit
Default
Bit Function
Interrupt mask for PWM CYCIRQx (see register TIMRIS)
CYCIRQxMSK
(reserved)
4
0x0
0x0
0: interrupt enabled
1: interrupt masked
(reserved)
3:0
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12.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers
TABLE 33. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers
Register - Name
PWMCFG0
Address
0x61
Type
Register Function
This register defines interrupt masking and the output behavior for the
associated PWM channel.
PGEx is used to start and stop the PWM script execution.
PWMCFG1
0x69
R/W
PWMENx sets the PWM output to either reflect the generated pattern
or the value configured in PWMPOLx.
PWMCFG2
0x71
Bit - Name
(x = 0, 1 or 2)
Bit
Default
Bit Function
Mask for CDIRQx
CDIRQxMSK
PGEx
3
0x0
0: CDIRQx enabled
1: CDIRQx disabled/masked
Pattern Generator Enable. Start/Stop PWM command processing for
this channel. Script execution is started always from beginning.
0: Pattern Generator disabled
2
0x0
1: Pattern Generator enabled
0: PWM disabled. PWM timer output assumes value programmed in
PWMPOL.
PWMENx
1
0
0x0
0x0
1: PWM enabled
Off-state of PWM output, when PWMEN=0.
0: PWM off-state is low
PWMPOLx
1: PWM off-state is high
12.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale
Registers
TABLE 34. TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers
Register - Name
Address
Type
Register Function
TIMSCAL0
0x62
These registers determine the divider of the CLKIN external clock.
The resulting clock is only used for PWM Generation. The value
should only be changed while PWM is stopped. Since all 3 PWM
channels use the same slow clock, TIMSCAL0 affects all 3 PWM
channels. TIMSCAL1 and 2 are directly linked to TIMSCAL0.
TIMSCAL1
TIMSCAL2
0x6A
0x72
R/W
Bit - Name
Bit
Default
Bit Function
SCAL[7:0]
7:0
0x0
CLKIN is divided by (SCAL+1).
12.2.4 TIMSWRES - PWM Timer Software Reset Registers
TABLE 35. TIMSWRES - PWM Timer Software Reset Registers
Register - Name
Address
Type
Register Function
Reset control on all PWM timers
A reset forces the pattern generator to fetch the first pattern and stops
it. Each reset stops all state-machines and timer.
TIMSWRES
0x78
W
Patterns stored in the pattern configuration register remain unaffected.
Interrupts on each timer are not cleared, they need to be cleared
writing into register TIMIC
Bit - Name
Bit
Default
Bit Function
(reserved)
7:3
(reserved)
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Register - Name
Address
Type
Register Function
Software reset of timer 2.
0: no action
SWRES2
2
1: Software reset on timer 2, needs not to be written back to 0.
Software reset of timer 1.
SWRES1
SWRES0
1
0
0: no action
1: Software reset on timer 1, needs not to be written back to 0.
Software reset of timer 0.
0: no action
1: software reset on timer 0, needs not to be written back to 0.
12.2.5 TIMRIS - PWM Timer Interrupt Status Register
TABLE 36. TIMRIS - PWM Timer Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the raw interrupt status from the PMW timers 0,1
and 2.
CYCIRQx - Interrupt from the timers when PWM cycle is complete
(applies to the current PWM command residing in the active command
register of a PWM block).
TIMRIS
0x7A
R
CDIRQx - Interrupt from the pattern generator when PWM pattern
code is complete (applies to a completed task residing in the script
buffer of a PWM block).
Bit - Name
Bit
Default
0x0
Bit Functions
(reserved)
(reserved)
7:6
Raw interrupt status for CDIRQ timer2
0: no interrupt pending
CDIRQ2
CDIRQ1
5
4
3
2
1
0
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer1
0: no interrupt pending
0x0
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer0
0: no interrupt pending
CDIRQ0
0x0
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer2
0: no interrupt pending
CYCIRQ2
CYCIRQ1
CYCIRQ0
0x0
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer1
0: no interrupt pending
0x0
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer0
0: no interrupt pending
0x0
1: unmasked interrupt generated
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12.2.6 TIMMIS - PWM Timer Masked Interrupt Status
Register
TABLE 37. TIMMIS - PWM Timer Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the masked interrupt status from the PMW timers
0,1 and 2. The raw interrupt status (TIMRIS) is masked with the
associated TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK
bits to get the masked interrupt status of this register.
CYCIRQ - Interrupt from the timers when PWM cycle is complete
(applies to the current PWM command residing in the active command
register of a PWM block)
TIMMIS
0x7B
R
CDIRQ - Interrupt from the pattern generator when PWM pattern code
is complete (applies to a completed task residing in the script buffer
of a PWM block)
Bit - Name
Bit
Default
Bit Function
(reserved)
7:6
(reserved)
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CDIRQ timer2.
0: no interrupt pending
CDIRQ2
CDIRQ1
5
4
3
2
1
0
0x0
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CDIRQ timer1.
0: no interrupt pending
0x0
0x0
0x0
0x0
0x0
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CDIRQ timer0.
0: no interrupt pending
CDIRQ0
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CYCIRQ timer2.
0: no interrupt pending
CYCIRQ2
CYCIRQ1
CYCIRQ0
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CYCIRQ timer1.
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt
ball, when set. Status for CYCIRQ timer0.
0: no interrupt pending
1: interrupt generated
12.2.7 TIMIC - PWM Timer Interrupt Clear Register
TABLE 38. TIMIC - PWM Timer Interrupt Clear Register
Register - Name
Address
Type
Register Function
This register clears timer and pattern interrupts.
CYCIRQ - Interrupt from the timers when PWM cycle is complete
(applies to the current PWM command residing in the active command
register of a PWM block).
TIMIC
0x7C
W
CDIRQ - Interrupt from the pattern generator when PWM pattern code
is complete (applies to a completed task residing in the script buffer
of a PWM block)
Bit - Name
Bit
Default
Bit Function
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Register - Name
Address
Type
Register Function
(reserved)
7:6
(reserved)
Clears interrupt CDIRQ timer2.
CDIRQ2
CDIRQ1
5
4
3
2
1
0
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer1.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer0.
CDIRQ0
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer2.
0: no effect
CYCIRQ2
CYCIRQ1
CYCIRQ0
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer1.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer0.
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
12.2.8 PWMWP - PWM Timer Pattern Pointer Register
TABLE 39. PWMWP - PWM Timer Pattern Pointer Register
Register - Name
Address
Type
Register Function
Pointer to the pattern position inside the configuration register, which
will be overwritten by the next write access to be PWMCFG register.
NOTE: 1 pattern consist of 2 bytes and not the byte position (low or
high). It is incremented by 1 every time a full PWMCFG register access
(word) is performed.
PWMWP
0x7D
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
7
0x0
(reserved)
0 ≤ POINTER < 32 : timer0 patterns 0 to 31
32 ≤ POINTER < 64 : timer1 patterns 0 to 31
64 ≤ POINTER < 96 : timer2 patterns 0 to 31
96 ≤ POINTER < 128: not valid
POINTER[6:0]
6:0
0x0
12.2.9 PWMCFG - PWM Script Register
TABLE 40. PWMCFG - PWM Script Register
Register - Name
Address
Type
Register Function
Two byte pattern storage register for a PWM script command indexed
by PWMWP. PWMWP is automatically incremented.
To be applied by two consecutive parameter bytes in one I2C Write
Transaction.
PWMCFG
0x7E
W
NOTE:
Autoincrement is disabled on this register. Address will stay at 0x7E
for each word access.
Bit - Name
CMD[15:8]
CMD[7:0]
Bit
15:8
7:0
Default
Bit Function
High byte portion of a PWM script command
Low byte portion of a PWM script command
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12.3 INTERFACE CONTROL REGISTERS
NOTE: I2CSA and MFGCODE use the same address. They
just differentiate in the access type:
The following section describes the functions of special con-
trol registers provided for the main controller.
•
•
Write - I2CSA
Read - MFGCODE
The manufacturer code MFGCODE and the software revision
number SWREV tell the main device which configuration file
has to be used for this device.
12.3.1 I2CSA - I2C-Compatible ACCESS.bus Slave Address Register
TABLE 41. I2CSA - I2C-Compatible ACCESS.bus Slave Address Register
Register - Name
Address
Type
Register Function
I2C-compatible ACCESS.bus Slave Address.
The address is internally applied after the next I2C STOP.
I2CSA
0x80
W
Bit - Name
SLAVEADDR[7:1]
(reserved)
Bit
7:1
0
Default
Bit Function
7-bit address field for the I2C-compatible ACCESS.bus slave address.
(reserved)
0x44
12.3.2 MFGCODE - Manufacturer Code Register
TABLE 42. MFGCODE - Manufacturer Code Register
Register - Name
Address
Type
Register Function
Manufacturer code of the LM8325-1
MFGCODE
0x80
R
Bit - Name
Bit
Default
Bit Function
MFGBIT
7:0
0x00
8 - bit field containing the manufacturer code
12.3.3 SWREV - Software Revision Register
TABLE 43. SWREV - Software Revision Register
Register - Name
Address
Type
Register Function
Software revision code of the LM8325-1.
NOTE: writing the SW revision with the inverted value triggers a reset
(see SWRESET)
SWREV
0x81
R
Bit - Name
Bit
Default
Bit Function
SWBIT
7:0
0x84
8 - bit field containing the SW Revision number.
12.3.4 SWRESET - Software Reset
TABLE 44. SWRESET - Software Reset Register
Register - Name
Address
Type
Register Function
Software reset
NOTE: the reset is only applied if the supplied parameter has the
inverted value as SWBIT.
SWRESET
0x81
W
Reading this register provides the software revision. (see SWREV)
Bit - Name
Bit
Default
Bit Function
SWBIT
7:0
Reapply inverted value for software reset.
12.3.5 RSTCTRL - System Reset Register
will reset the slave address back to 88H. During an active
reset of a module, the LM8325-1 blocks the access to the
module registers. A read will return 0, write commands are
ignored.
This register allows to reset specific blocks of the LM8325-1.
For global reset of the IOExpander the I2C command 'General
Call reset' is used (see Section 9.1.6 Global Call Reset). This
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TABLE 45. RSTCTRL - System Reset Register
Register - Name
Address
Type
Register Function
RSTCTRL
0x82
R/W
Software reset of specific parts of the LM8325-1
Bit - Name
Bit
Default
Bit Function
(reserved)
7:5
(reserved)
Interrupt controller reset. Does not change status on IRQN ball. Only
controls IRQ module register. Interrupt status read out is not possible
when this bit is set.
IRQRST
4
0x0
0: interrupt controller not reset
1: interrupt controller reset
Timer reset for Timers 0, 1, 2
0: timer not reset
TIMRST
(reserved)
KBDRST
3
2
1
0x0
0x0
0x0
1: timer is reset
(reserved)
Keyboard interface reset
0: keyboard is not reset
1: keyboard is reset
GENIO reset
GPIRST
0
0x0
0: GENIO not reset
1: GENIO is reset.
12.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt
Register
TABLE 46. RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Register - Name
Address
Type
Register Function
This register allows to de-assert the POR/No Init Interrupt set every
time the device returns from RESET (either POR, HW or SW Reset),
the IRQN line is assigned active (low) and the IRQST.PORIRQ bit is
set.
RSTINTCLR
0x84
W
Bit - Name
Bit
Default
Bit Function
reserved
7:1
(reserved)
1: Clears the PORIRQ Interrupt signalled in IRQST register.
0: is ignored
IRQCLR
0
12.3.7 CLKMODE - Clock Mode Register
TABLE 47. CLKMODE - Clock Mode Register
Register - Name
Address
Type
Register Function
This register controls the current operating mode of the LM8325-1
device
CLKMODE
0x88
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
7:2
(reserved)
Writing to 00 forces the device to immediately enter sleep mode,
regardless of any autosleep configuration. Reading this bit returns the
current operating mode, which should always be 01.
00: SLEEP Mode
MODCTL[1:0]
1:0
0x01
01: Operation Mode
1x: Future modes
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12.3.8 CLKCFG - Clock Configuration Register
TABLE 48. CLKCFG - Clock Configuration Register
Register - Name
Address
Type
Register Function
Configures clock sources and power options of the device.
Note: Don't change while a PWM script is in progress
CLKCFG
0x89
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
7
0x0
(reserved)
00: (reserved)
CLKSRCSEL[1:0]
6:5
0x2
01: use external generated clock from CLKIN pin as PWM slow clock
1x: use internally generated PWM slow clock
(reserved)
(reserved)
4:0
0x00
12.3.9 CLKEN - Clock Enable Register
TABLE 49. CLKEN - Clock Enable Register
Register - Name
Address
Type
Register Function
Controls the clock to different functional units. It shall be used to
enable the functional blocks globally and independently.
CLKEN
0x8A
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:3
PWM Timer 0, 1, 2 clock enable
0: Timer 0, 1, 2 clock disabled
1: Timer 0, 1, 2 clock enabled.
(reserved)
TIMEN
(reserved)
KBDEN
2
1
0
0x0
Keyboard clock enable (starts/stops key scan)
0: Keyboard clock disabled
1: Keyboard clock enabled
0x0
12.3.10 AUTOSLP - Autosleep Enable Register
TABLE 50. AUTOSLP - Autosleep Enable Register
Register - Name
Address
Type
Register Function
AUTOSLP
0x8B
R/W
This register controls the Auto Sleep function of the LM8325-1 device
Bit - Name
Bit
Default
Bit Function
(reserved)
7:1
(reserved)
Enables automatic sleep mode after a defined activity time stored in
the AUTOSLPTI register
ENABLE
0
0x00
1: Enable entering auto sleep mode
0: Disable entering auto sleep mode
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12.3.11 AUTOSLPTI - Auto Sleep Time Register
TABLE 51. AUTOSLPTI - Auto Sleep Time Register
Register - Name
Address
Type
Register Function
This register defines the activity time. If this time passes without any
processing events then the device enters into sleep-mode, but only if
AUTOSLP.ENABLE bit is set to 1.
AUTOSLPTIL
AUTOSLPTIH
0x8C
0x8D
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
15:11
(reserved)
Values of UPTIME[10:0] match to multiples of 4ms:
0x00: no autosleep, regardless if AUTOSLP.ENABLE is set
0x01: 4ms
UPTIME[10:8]
UPTIME[7:0]
10:8
7:0
0x00
0xFF
0x02: 8ms
0x7A: 500 ms
0xFF: 1020 ms (default after reset)
0x100: 1024 ms
0x7FF: 8188 ms
12.3.12 IRQST - Global Interrupt Status Register
TABLE 52. IRQST - Global Interrupt Status Register
Register - Name
Address
Type
Register Function
Returns the interrupt status from various on-chip function blocks. If
any of the bits is set and an IRQN line is configured, the IRQN line is
asserted active
IRQST
0x91
R
Bit - Name
Bit
Default
Bit Function
Supply failure on VCC.
Also power-on is considered as an initial supply failure. Therefore,
after power-on, the bit is set.
PORIRQ
7
0x1
0: no failure recorded
1: Failure, device was completely reset and requires re-programming.
Keyboard interrupt (further key selection in keyboard module)
KBDIRQ
(reserved)
TIM2IRQ
6
5:4
3
0x0
0: inactive
1: active
(reserved)
Timer2 expiry (CDIRQ or CYCIRQ)
0x0
0x0
0x0
0x0
0: inactive
1: active
Timer1 expiry (CDIRQ or CYCIRQ)
TIM1IRQ
TIM0IRQ
GPIOIRQ
2
1
0
0: inactive
1: active
Timer0 expiry (CDIRQ or CYCIRQ)
0: inactive
1: active
GPIO interrupt (further selection in GPIO module)
0: inactive
1: active
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12.4 GPIO FEATURE CONFIGURATION
12.4.1 GPIO Feature Mapping
configuration for keypad or PWM/interrupt usage is defined
by the following registers:
•
KBDSIZE and KBDDEDCFG
The LM8325-1 has a flexible IO structure which allows to dy-
namically assign different functionality to each ball. The func-
tionality of each ball is determined by the complete configu-
ration of the balls.
Both registers define a ball as either part of the keypad
matrix or as dedicated key input. These settings have
highest priority and will overwrite settings made in other
registers.
—
In general the following priority is given:
•
IOCFG
•
•
Keypad
GPIO/PWM/Interrupt
This register is used to define the usage of KPY[11:8]
if not configured to be part of the keymatrix, to be used
as GPIO.
—
With this, each ball will be available as GPIO, PWM or inter-
rupt unless it is specified to be part of the keypad matrix. The
TABLE 53. Ball Configuration Options
BALL
Module connectivity
GPIOSEL
BALLCFG
0x0
0x1
0x2
0x3
0x4
-
0x5
-
0x6
-
0x7
-
KPX[7:0]
KPY[7:0]
not used
not used
GPIO[7:0]
GPIO[15:8]
PWM2
(Note 1)
KPY8/PWM2
not used
GPIO16
(reserved)
-
KPY9/PWM1
KPY10/PWM0
not used
not used
GPIO17
GPIO18
PWM1
PWM0
-
-
-
-
-
-
-
-
-
-
-
-
IRQN/KPY11/
PWM2
PWM2
(Note 1)
see IOCFG
GPIO19
PWM2
-
-
-
-
-
Note 1: PWM2 functionality is mutally exclusive — one pin at a time only (KPY8 or KPY11) depending on interrupt enable Bit 4 of IOCFG.
12.4.2 IOCGF - Input/Output Pin Mapping Configuration
Register
TABLE 54. IOCGF - Input/Output Pin Mapping Configuration Register
Register - Name
Address
Type
Register Function
Configures usage of KPY[11:8] if not used for Keypad. On each write
to this register, BALLCFG defines the column of Table 53 to configure.
IOCFG
0xA7
W
Bit - Name
Bit
Default
Bit Function
Configures the IRQN/KPY11/PWM2 ball
Bit 4: Interrupt enabled
GPIOSEL
7:4
Bit [7:5]: not used
(reserved)
BALLCFG
3
(reserved)
2:0
Select column to configure, see Ball configuration options
12.4.3 IOPC0 - Pull Resistor Configuration Register 0
TABLE 55. IOPC0 - Pull Resistor Configuration Register 0
Register - Name
Address
Type
Register Function
IOPC0*
OxAA
R/W
Defines the pull resistor configuration for balls KPX[7:0]
Bit - Name
Bit
Default
Bit Function
Resistor enable for KPX7 ball
00: no pull resistor at ball
KPX7PR[1:0]
15:14
0x2
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX6 ball
00: no pull resistor at ball
KPX6PR[1:0]
13:12
0x2
01:pull down resistor programmed
1x: pull up resistor programmed
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Register - Name
Address
Type
Register Function
Resistor enable for KPX5 ball
00: no pull resistor at ball
KPX5PR[1:0]
11:10
0x2
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX4 ball
00: no pull resistor at ball
KPX4PR[1:0]
KPX3PR[1:0]
KPX2PR[1:0]
KPX1PR[1:0]
KPX0PR[1:0]
9:8
7:6
5:4
3:2
1:0
0x2
0x2
0x2
0x2
0x2
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX3 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX2 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX1 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX0 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
* written values of 0x2 and 0x3 will always be read back as 0x3
12.4.4 IOPC1 - Pull Resistor Configuration Register 1
TABLE 56. IOPC1 - Pull Resistor Configuration Register 1
Register - Name
Address
Type
Register Function
IOPC1**
0xAC
R/W
Defines the pull resistor configuration for balls KPY[7:0]
Bit - Name
Bit
Default
Bit Function
Resistor enable for KPY7 ball
00: no pull resistor at ball
KPY7PR[1:0]
15:14
13:12
11:10
9:8
0x1
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY6 ball
00: no pull resistor at ball
KPY6PR[1:0]
KPY5PR[1:0]
KPY4PR[1:0]
KPY3PR[1:0]
0x1
0x1
0x1
0x1
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY5 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY4 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY3 ball
00: no pull resistor at ball
7:6
01:pull down resistor programmed
1x: pull up resistor programmed
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Register - Name
Address
Type
Register Function
Resistor enable for KPY2 ball
00: no pull resistor at ball
KPY2PR[1:0]
5:4
0x1
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY1 ball
00: no pull resistor at ball
KPY1PR[1:0]
KPY0PR[1:0]
3:2
1:0
0x1
0x1
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY0 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
** written values of 0x2 and 0x3 will always be read back as 0x3
12.4.5 IOPC2 - Pull Resistor Configuration Register 2
TABLE 57. IOPC2 - Pull Resistor Configuration Register 2
Register - Name
Address
Type
Register Function
IOPC2***
0xAE
R/W
Defines the pull resistor configuration for balls KPY[11:8]
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
15:8
0x5A
Resistor enable for KPY11 ball
00: no pull resistor at ball
KPY11PR[1:0]
KPY10PR[1:0]
KPY9PR[1:0]
KPY8PR[1:0]
7:6
5:4
3:2
1:0
0x0
0x1
0x1
0x1
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY10 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY9 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY8 ball
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
*** written values of 0x2 and 0x3 will always be read back as 0x3
12.4.6 GPIOOME0 - GPIO Open Drain Mode Enable
Register 0
TABLE 58. GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Register - Name
Address
Type
Register Function
Configures KPX[7:0] for Open Drain or standard output functionality.
The Open Drain drive source is configured by GPIOOMS0.
GPIOOME0
0xE0
R/W
Bit - Name
Bit
Default
Bit Function
Open Drain Enable on KPX[7:0]
0: full buffer
KPX[7:0]ODE
7:0
0x0
1: open drain functionality
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12.4.7 GPIOOMS0 - GPIO Open Drain Mode Select
Register 0
TABLE 59. GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Register - Name
Address
Type
Register Function
Configures the Open Drain drive source on KPX[7:0] if selected by
GPIOOME0.
GPIOOMS0
0xE1
R/W
Bit - Name
Bit
Default
Bit Function
0: Only nmos transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z
KPX[7:0]ODM
7:0
0x0
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z
12.4.8 GPIOOME1 - GPIO Open Drain Mode Enable
Register 1
TABLE 60. GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Register - Name
Address
Type
Register Function
Configures KPY[7:0] for Open Drain or standard output functionality.
The Open Drain drive source is configured by GPIOOMS1.
GPIOOME1
0xE2
R/W
Bit - Name
Bit
Default
Bit Function
Open Drain Enable on KPY[7:0]
0: full buffer
KPY[7:0]ODE
7:0
0x0
1: open drain functionality
12.4.9 GPIOOMS1 - GPIO Open Drain Mode Select
Register 1
TABLE 61. GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Register - Name
Address
Type
Register Function
Configures the Open Drain drive source on KPY[7:0] if selected by
GPIOOME1.
GPIOOMS1
0xE3
R/W
Bit - Name
Bit
Default
Bit Function
0: Only nmos transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z
KPY[7:0]ODM
7:0
0x0
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z
12.4.10 GPIOOME2 - GPIO Open Drain Mode Enable
Register 2
TABLE 62. GPIOOME2 - GPIO Open Drain Mode Enable Register 2
Register - Name
Address
Type
Register Function
Configures KPY[11:8] for Open Drain or standard output functionality.
The Open Drain drive source is configured by GPIOOMS2.
GPIOOME2
0xE4
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
0x0
(reserved)
Open Drain Enable on KPY[11:8]
0: full buffer
KPY[11:8]ODE
3:0
0x8
1: open drain functionality
Note: KPY11/IRQN ball defaults to Open Drain Mode Enable after
reset.
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12.4.11 GPIOOMS2 - GPIO Open Drain Mode Select
Register 2
TABLE 63. GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Register - Name
Address
Type
Register Function
Configures the Open Drain drive source on KPY[11:8] if selected by
GPIOOME2.
GPIOOMS2
0xE5
R/W
Bit - Name
Bit
Default
Bit Function
(reserved
7:4
(reserved
0: Only nmos transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z
KPY[11:8]ODM
3:0
0x0
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z
12.5 GPIO DATA INPUT/OUTPUT
30170411
12.5.1 GPIOPDATA0 - GPIO Data Register 0
TABLE 64. GPIOPDATA0 - GPIO Data Register 0
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPX[7:0]. Every data I/O
is masked with the associated MASK register.
If one of the I/Os is defined as output (see Table 67) values written to
this register are masked with MASK and then applied to the associated
pin.
GPIODATA0
0xC0
R/W
If one of the I/Os is defined as input (see Table 67) values read from
this register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
Bit Function
Mask Status for KPX7 when enabled as GPIO
1: KPX7 enabled
MASK7
15
0x0
0: KPX7 disabled
Mask Status for KPX6 when enabled as GPIO
1: KPX6 enabled
MASK6
MASK5
MASK4
MASK3
14
13
12
11
0x0
0x0
0x0
0x0
0: KPX6 disabled
Mask Status for KPX5 when enabled as GPIO
1: KPX5 enabled
0: KPX5 disabled
Mask Status for KPX4 when enabled as GPIO
1: KPX4 enabled
0: KPX4 disabled
Mask Status for KPX3 when enabled as GPIO
1: KPX3 enabled
0: KPX3 disabled
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Register - Name
Address
Type
Register Function
Mask Status for KPX2 when enabled as GPIO
1: KPX2 enabled
MASK2
10
0x0
0: KPX2 disabled
Mask Status for KPX1 when enabled as GPIO
1: KPX1 enabled
MASK1
MASK0
9
8
0x0
0x0
0: KPX1 disabled
Mask Status for KPX0 when enabled as GPIO
1: KPX0 enabled
0: KPX0 disabled
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
7
6
5
4
3
2
1
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Pin Status for KPX7 when enabled as GPIO
Pin Status for KPX6 when enabled as GPIO
Pin Status for KPX5 when enabled as GPIO
Pin Status for KPX4 when enabled as GPIO
Pin Status for KPX3 when enabled as GPIO
Pin Status for KPX2 when enabled as GPIO
Pin Status for KPX1 when enabled as GPIO
Pin Status for KPX0 when enabled as GPIO
12.5.2 GPIOPDATA1 - GPIO Data Register 1
TABLE 65. GPIOPDATA1 - GPIO Data Register 1
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPY[7:0]. Every data I/O
is masked with the associated MASK register.
If one of the I/Os is defined as output (see Table 68) values written to
this register are masked with MASK and then applied to the associated
pin.
GPIODATA1
0xC2
R/W
If one of the I/Os is defined as input (see Table 68) values read from
this register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
Bit Function
Mask Status for KPY7 when enabled as GPIO
1: KPY7 enabled
MASK15
15
0x0
0: KPY7 disabled
Mask Status for KPY6 when enabled as GPIO
1: KPY6 enabled
MASK14
MASK13
MASK12
MASK11
MASK10
MASK9
14
13
12
11
10
9
0x0
0x0
0x0
0x0
0x0
0x0
0: KPY6 disabled
Mask Status for KPY5 when enabled as GPIO
1: KPY5 enabled
0: KPY5 disabled
Mask Status for KPY4 when enabled as GPIO
1: KPY4 enabled
0: KPY4 disabled
Mask Status for KPY3 when enabled as GPIO
1: KPY3 enabled
0: KPY3 disabled
Mask Status for KPY2 when enabled as GPIO
1: KPY2 enabled
0: KPY2 disabled
Mask Status for KPY1 when enabled as GPIO
1: KPY1 enabled
0: KPY1 disabled
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Register - Name
Address
Type
Register Function
Mask Status for KPY0 when enabled as GPIO
1: KPY0 enabled
MASK8
8
0x0
0: KPY0 disabled
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
7
6
5
4
3
2
1
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Pin Status for KPY7 when enabled as GPIO
Pin Status for KPY6 when enabled as GPIO
Pin Status for KPY5 when enabled as GPIO
Pin Status for KPY4 when enabled as GPIO
Pin Status for KPY3 when enabled as GPIO
Pin Status for KPY2 when enabled as GPIO
Pin Status for KPY1 when enabled as GPIO
Pin Status for KPY0 when enabled as GPIO
DATA8
12.5.3 GPIOPDATA2 - GPIO Data Register 2
TABLE 66. GPIOPDATA2 - GPIO Data Register 2
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPY[11:8]. Every data I/
O is masked with the associated MASK register.
If one of the I/Os is defined as output (see Table 69) values written to
this register are masked with MASK and then applied to the associated
pin.
GPIODATA2
0xC4
R/W
If one of the I/Os is defined as input (see Table 69) values read from
this register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
15:12
0x0
Mask Status for KPY11 when enabled as GPIO
1: KPY11 enabled
MASK19
MASK18
MASK17
MASK16
11
10
9
0x0
0x0
0x0
0x0
0: KPY11 disabled
Mask Status for KPY10 when enabled as GPIO
1: KPY10 enabled
0: KPY10 disabled
Mask Status for KPY9 when enabled as GPIO
1: KPY9 enabled
0: KPY9 disabled
Mask Status for KPY8 when enabled as GPIO
1: KPY8 enabled
8
0: KPY8 disabled
reserved
DATA19
DATA18
DATA17
DATA16
7:4
3
0x0
0x0
0x0
0x0
0x0
(reserved)
Pin Status for KPY11 when enabled as GPIO
Pin Status for KPY10 when enabled as GPIO
Pin Status for KPY9 when enabled as GPIO
Pin Status for KPY8 when enabled as GPIO
2
1
0
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12.5.4 GPIOPDIR0 - GPIO Port Direction Register 0
TABLE 67. GPIOPDIR0 - GPIO Port Direction Register 0
Address Type Register Function
R/W Port direction for KPX[7:0]
Register - Name
GPIODIR0
0xC6
Bit
Bit - Name
Default
Bit Function
Direction bits for KPX[7:0]
0: input mode
KPX[7:0]DIR
7:0
0x00
1: output mode
12.5.5 GPIOPDIR1 - GPIO Port Direction Register 1
TABLE 68. GPIOPDIR1 - GPIO Port Direction Register 1
Register - Name
Address
Type
Register Function
GPIODIR1
0xC7
R/W
Port direction for KPY[7:0]
Bit - Name
Bit
Default
Bit Function
Direction bits for KPY[7:0]
0: input mode
KPY[7:0]DIR
7:0
0x00
1: output mode
12.5.6 GPIOPDIR2 - GPIO Port Direction Register 2
TABLE 69. GPIOPDIR2 - GPIO Port Direction Register 2
Register - Name
Address
Type
Register Function
GPIODIR2
0xC8
R/W
Port direction for KPY[11:8]
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Direction bits for KPY[11:8]
0: input mode
KPY[11:8]DIR
3:0
0x08
1: output mode
12.6 GPIO INTERRUPT CONTROL
12.6.1 GPIOIS0 - Interrupt Sense Configuration Register
0
TABLE 70. GPIOIS0 - Interrupt Sense Configuration Register 0
Register - Name
Address
Type
Register Function
Interrupt type on KPX[7:0]
GPIOIS0
0xC9
R/W
Bit - Name
Bit
Default
Bit Function
Interrupt type bits for KPX[7:0]
0: edge sensitive interrupt
1: level sensitive interrupt
KPX[7:0]IS
7:0
0x0
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12.6.2 GPIOIS1 - Interrupt Sense Configuration Register
1
TABLE 71. GPIOIS1 - Interrupt Sense Configuration Register 1
Address Type Register Function
0xCA R/W Interrupt type on KPY[7:0]
Register - Name
GPIOIS1
Bit - Name
Bit
Default
Bit Function
Interrupt type bits for KPY[7:0]
KPY[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
12.6.3 GPIOIS2 - Interrupt Sense Configuration Register
2
TABLE 72. GPIOIS2 - Interrupt Sense Configuration Register 2
Register - Name
Address
Type
Register Function
GPIOIS2
0xCB
R/W
Interrupt type on KPY[11:8]
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Interrupt type bits for KPY[11:8]
0: edge sensitive interrupt
1: level sensitive interrupt
KPY[11:8]IS
3:0
0x0
12.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration
Register 0
TABLE 73. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPX[7:0] is triggered on both edges
or on a single edge. See Table 76 for the edge configuration.
GPIOIBE0
0xCC
R/W
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for KPX[7:0]
0: interrupt generated at the active edge
1: interrupt generated after both edges
KPX[7:0]IBE
7:0
0x0
12.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration
Register 1
TABLE 74. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPY[7:0] is triggered on both edges
or on a single edge. See Table 77 for the edge configuration.
GPIOIBE1
0xCD
R/W
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for KPY[7:0]
0: interrupt generated at the configured edge
1: interrupt generated after both edges
KPY[7:0]IBE
7:0
0x0
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12.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration
Register 2
TABLE 75. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPY[11:8] is triggered on both edges
or on a single edge. See Table 78 for the edge configuration.
GPIOIBE2
0xCE
R/W
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved
7:4
Interrupt both edges bits for KPY[11:8]
0: interrupt generated at the active edge
1: interrupt generated after both edges
KPY[11:8]IBE
3:0
0x0
12.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0
TABLE 76. GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Register - Name
Address
Type
Register Function
GPIOIEV0
0xCF
R/W
Select Interrupt edge for KPX[7:0].
Bit - Name
Bit
Default
Bit Function
Interrupt edge select from KPX[7:0]
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
KPX[7:0]EV
7:0
0xFF
12.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1
TABLE 77. GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Register - Name
Address
Type
Register Function
GPIOIEV1
0xD0
R/W
Select Interrupt edge for KPY[7:0].
Bit - Name
Bit
Default
Bit Function
Interrupt edge select from KPY[7:0]
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
KPY[7:0]EV
7:0
0xFF
12.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2
TABLE 78. GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Register - Name
Address
Type
Register Function
GPIOIEV2
0xD1
R/W
Select Interrupt edge for KPY[11:8].
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Interrupt edge select from KPY[11:8]
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
KPY[11:8]EV
3:0
0xFF
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12.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0
TABLE 79. GPIOIE0 - GPIO Interrupt Enable Register 0
Address Type Register Function
R/W Enable/disable interrupts on KPX[7:0]
Register - Name
GPIOIE0
0xD2
Bit
Bit - Name
Default
Bit Function
Interrupt enable on KPX[7:0]
KPX[7:0]IE
7:0
0x0
0: disable interrupt
1: enable interrupt
12.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1
TABLE 80. GPIOIE1 - GPIO Interrupt Enable Register 1
Register - Name
Address
Type
Register Function
GPIOIE1
0xD3
R/W
Enable/disable interrupts on KPY[7:0]
Bit - Name
Bit
Default
Bit Function
Interrupt enable on KPY[7:0]
0: disable interrupt
KPY[7:0]IE
7:0
0x0
1: enable interrupt
12.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2
TABLE 81. GPIOIE2 - GPIO Interrupt Enable Register 2
Register - Name
Address
Type
Register Function
GPIOIE2
0xD4
R/W
Enable/disable interrupts on KPY[11:8]
Bit - Name
Bit
Default
Bit Function
(reserved)
(reserved)
7:4
Interrupt enable on KPY[11:8]
0: disable interrupt
KPY[11:8]IE
3:0
0x0
1: enable interrupt
12.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0
TABLE 82. GPIOIC0 - GPIO Clear Interrupt Register 0
Register - Name
Address
Type
Register Function
GPIOIC0
0xDC
W
Clears the interrupt on KPX[7:0]
Bit - Name
Bit
Default
Bit Function
Clear Interrupt on KPX[7:0]
0: no effect
KPX[7:0]IC
7:0
1: Clear corresponding interrupt
12.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1
TABLE 83. GPIOIC1 - GPIO Clear Interrupt Register 1
Register - Name
Address
Type
Register Function
GPIOIC1
0xDD
W
Clears the interrupt on KPY[7:0]
Bit - Name
Bit
Default
Bit Function
Clear Interrupt on KPY[7:0]
0: no effect
KPY[7:0]IC
7:0
1: Clear corresponding interrupt
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12.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2
TABLE 84. GPIOIC2 - GPIO Clear Interrupt Register 2
Register - Name
Address
Type
Register Function
GPIOIC2
0xDE
W
Clears the interrupt on KPY[11:8]
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Clear Interrupt on KPY[11:8]
0: no effect
KPY[11:8]IC
3:0
1: Clear corresponding interrupt
12.7 GPIO INTERRUPT STATUS
12.7.1 GPIORIS0 - Raw Interrupt Status Register 0
TABLE 85. GPIORIS0 - Raw Interrupt Status Register 0
Register - Name
Address
Type
Register Function
Raw interrupt status on KPX[7:0]
GPIORIS0
0xD6
R
Bit - Name
Bit
Default
Bit Function
Raw Interrupt status data on KPX[7:0]
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
KPX[7:0]RIS
7:0
0x0
12.7.2 GPIORIS1 - Raw Interrupt Status Register 1
TABLE 86. GPIORIS1 - Raw Interrupt Status Register 1
Register - Name
Address
Type
Register Function
Raw interrupt status on KPY[7:0]
GPIORIS1
0xD7
R
Bit - Name
Bit
Default
Bit Function
Raw Interrupt status data on KPY[7:0]
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
KPY[7:0]RIS
7:0
0x0
12.7.3 GPIORIS2 - Raw Interrupt Status Register 2
TABLE 87. GPIORIS2 - Raw Interrupt Status Register 2
Register - Name
Address
Type
Register Function
Raw interrupt status on KPY[11:8]
GPIORIS2
0xD8
R
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Raw Interrupt status data on KPY[11:8]
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
KPY[11:8]RIS
3:0
0x0
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12.7.4 GPIOMIS0 - Masked Interrupt Status Register 0
TABLE 88. GPIOMIS0 - Masked Interrupt Status Register 0
Address Type Register Function
Masked interrupt status on KPX[7:0]
Register - Name
GPIOMIS0
0xD9
Bit
R
Bit - Name
Default
Bit Function
Masked Interrupt status data on KPX[7:0]
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
KPX[7:0]MIS
7:0
0x0
12.7.5 GPIOMIS1 - Masked Interrupt Status Register 1
TABLE 89. GPIOMIS1 - Masked Interrupt Status Register 1
Register - Name
Address
Type
Register Function
Masked interrupt status on KPY[7:0]
GPIOMIS1
0xDA
R
Bit - Name
Bit
Default
Bit Function
Masked Interrupt status data on KPY[7:0]
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
KPY[7:0]MIS
7:0
0x0
12.7.6 GPIOMIS2 - Masked Interrupt Status Register 2
TABLE 90. GPIOMIS2 - Masked Interrupt Status Register 2
Register - Name
Address
Type
Register Function
Masked interrupt status on KPY[11:8]
GPIOMIS2
0xDB
R
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Masked Interrupt status data on KPY[11:8]
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
KPY[11:8]MIS
3:0
0x0
12.8 GPIO WAKE-UP CONTROL
12.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0
TABLE 91. GPIOWAKE0 - GPIO Wake-Up Register 0
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPX[7:0]
GPIOWAKE0
0xE9
R/W
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit - Name
Bit
Default
Bit Function
Bit 7: KPX7
...
KPX[7:0]WAKE
7:0
0x0
Bit 0: KPX0
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12.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1
TABLE 92. GPIOWAKE1 - GPIO Wake-Up Register 1
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[7:0]
GPIOWAKE1
0xEA
R/W
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit - Name
Bit
Default
Bit Function
Bit 7: KPY7
...
KPY[7:0]WAKE
7:00
0x0
Bit 0: KPY0
12.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2
TABLE 93. GPIOWAKE2 - GPIO Wake-Up Register 2
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[11:8]
GPIOWAKE2
0xEB
R/W
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
(reserved)
Bit 3: KPY11
...
KPY[11:8]WAKE
3:0
0x0
Bit 0: KPY8
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Maximum Input Current Without
Latchup
13.0 Absolute Maximum Ratings (Note
±100 mA
1)
ESD Protection Level
(Human Body Model)
(Machine Model)
(Charge Device Model)
2kV
200V
750V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Supply Voltage (VCC
)
100 mA
100 mA
−65°C to +140°C
−0.3V to 2.2V
−0.2V to VCC +0.2V
Voltage at Generic IOs
Voltage at Backdrive/Overvoltage
IOs
−0.3V to +.4.25V
14.0 Electrical Characteristics
TABLE 94. DC ELECTRICAL CHARACTERISTICS
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
(Temperature: −40°C ≤ TA ≤ +85°C, unless otherwise specified)
Parameter
Conditions
Min
Typ
Max Units
Operating Voltage (VCC
)
Core Supply Voltage
1.62
1.98
3.60
V
V
Maximum Input voltage for Backdrive/Overvoltage IOs
Internal Clock = ON, all internal functional
blocks running
No loads on pins,
Supply Current (IDD) (Note 2)
1.9
3.0
40
mA
VCC = 1.8V, TC = 0.5 µs
TA = 25°C
Sleep Mode HALT Current (IHALT) (Note 3)
VCC = 1.8V, TA = 25°C;
<9
1
µA
Internal Clock = OFF, no internal functional
blocks running
IDLE Current
Internal Clock = ON, no internal functional
blocks running
mA
TABLE 95. AC Electrical Characteristics
(Temperature: −40°C ≤ TA ≤ +85°C)
Data sheet specification limits are guaranteed by design, test, or statistical analysis.
Parameter Conditions
System Clock Frequency
Min
Typ
Max
Units
MHz
ns
Internal RC
21
48
System Clock Period (mclk)
1.62V ≤ VCC ≤ 1.98V
1.62V ≤ VCC ≤ 1.98V
Internal RC Oscillator (tC)
0.5
μs
Internal RC Oscillator Frequency Variation
±7
%
ACCESS.bus Input Signals
Bus Free Time Between Stop and Start
Condition (tBUFi) (Note 4)
16
SCL Setup Time (tCSTOsi) (Note 4)
SCL Hold Time (tCSTRhi) (Note 4)
SCL Setup Time (tCSTRsi) (Note 4)
Before Stop Condition
After Start Condition
Before Start Condition
8
8
8
2
Data High Setup Time (tDHCsi) (Note 4, Note Before SCL Rising Edge (RE)
mclk
5)
5)
Data Low Setup Time (tDLCsi) (Note 4, Note Before SCL RE
2
SCL Low Time (tSCLlowi) (Note 4)
After SCL Falling Edge (FE)
After SCL FE
12
12
0
SCL High Time (tSCLhighi) (Note 4, Note 5)
SDA Hold Time (tSDAhi) (Note 4)
After SCL FE
SDA Setup Time (tSDAsi) (Note 4, Note 5)
Before SCL RE
2
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Parameter
ACCESS.bus Output Signals
SDA Hold Time (tSDAho) (Note 4)
Conditions
After SCL Falling Edge
Min
Typ
Typ
Max
Max
Units
2
mclk
TABLE 96. GENERAL GPIO CHARACTERISTICS
Characteristics for all pins except CLKIN, IRQN/KPY11/PWM2, SDA, and SCL in GPIO mode.
Parameter
VIH (Min. Input High Voltage)
VIL (Max. Input Low Voltage)
Conditions
Min
Units
0.7xVCC
V
V
0.3xVCC
−16
VCC = 1.62
ISource
ISink
mA
VOH = 0.7xVCC
VCC = 1.62
16
mA
mA
VOL = 0.3xVCC
Allowable Sink current per pin (Note 6)
IPU (Weak Pull-UP Current) (Note 7)
IPD (Weak Pull-Down Current) (Note 7)
16
VOUT = 0V
-30
30
-160
160
VOUT = VCC
µA
ns
GPIO output disabled
Vpin = 0 to VCC
IOZ (Input Leakage Current)
±2
15
tRise/Fall (Max. Rise and Fall times) (Note 4)
CLOAD = 50 pF
TABLE 97. BACKDRIVE/OVERVOLTAGE I/O DC CHARACTERISTICS
Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL
Parameter
VIH (Min. Input High Voltage)
VIL (Max. Input Low Voltage)
Conditions
Min
Typ
Max
Units
0.7xVCC
V
0.3xVCC
-6
VCC = 1.62V
VOH = 1.5V
ISource
mA
mA
mA
VCC = 1.62V
VOL = 0.4V
ISink1 (as GPIO)
ISink2 (as ACCESS.bus)
ISink3 (as ACCESS.bus)
12
3
VCC = 1.62V
VOL = 0.4V
VCC = 1.62V
VOL = 0.6V
4
mA
mA
Allowable Sink current per pin (Note 6)
IPU (Weak Pull-UP Current) (Note 7)
IPD (Weak Pull-Down Current) (Note 7)
12
-40
40
VOUT = 0V
-7
7
VOUT = VCC
GPIO output disabled
VCC = 1.62V to 1.98V
Vpin = 0 to VCC
µA
µA
IOZ1 (Input Leakage Current) (Note 8)
±2
Vpin = VCC to 3.6V
±10
0 ≤ VCC ≤ 0.5V
Vpin = 0 to 3.6V
IOZ2 (Input Backdrive Leakage Current)
±10
TABLE 98. BACKDRIVE/OVERVOLTAGE I/O AC CHARACTERISTICS
Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL
Parameter Conditions
Min
Typ
Max
Units
tRise/Fall
CLOAD=50 pF @ 1MHz
70
(Max. Rise and Fall time) (Note 4)
ns
tFall
CLOAD=10 pF to 100 pF
VIHmin to VILmax
10
120
(Max. Fall time) as ACCESS.bus (SDA, SCL
only) (Note 4)
47
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics tables.
Note 2: Supply and IDLE current is measured with inputs connected to VCC and outputs driven low but not connected to a load.
Note 3: In sleep mode, the internal clock is switched off. Supply current in sleep mode is measured with inputs connected to VCC and outputs driven low but not
connected to a load.
Note 4: Guaranteed by design, not tested.
Note 5: The ACCESS.bus interface implements and meets the timings necessary for interface to the I2C and SMBus protocols at logic levels. The bus drivers
have open-drain outputs for bidirectional operation. Due to Internal RC Oscillator Frequency Variation, this specification may not meet the AC timing and current/
voltage drive requirements of the full-bus specifications.
Note 6: The sum of all I/O sink/source current must not exceed the maximum total current into VCC and out of GND as specified in the absolute maximum ratings.
Note 7: This is the internal weak pull-up (pull-down) current when driver output is disabled. If enabled, during receiving mode, this is the current required to switch
the input from one state to another.
Note 8: IOZ1 for CLKIN is max 60 µA if VPIN > VCC because the weak pull-down is enabled.
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15.0 Register
15.1 REGISTER MAPPING
15.1.1 Keyboard Registers
Table 99 shows the register map for keyboard functionality. In addition to Global Call Reset (see Section 9.1.6 Global Call Re-
set) or Software Reset using SWRESET (see Table 44), these registers are reset to 0x00 values by a module reset using
RSTCTRL.KBDRST and should be rewritten for desired settings (see RSTCTRL - Table 45).
TABLE 99. Register Map for Keyboard Functionality
Register File
Address
Next RF
Address
Register Name
KBDSETTLE
KBDBOUNCE
KBDSIZE
Description
Register Type ACCESS Size Default value
Keypad Settle
Time
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
R/W
R/W
R/W
R/W
R/W
R
byte
byte
byte
byte
byte
byte
byte
byte
byte
0x80
0x80
0x22
0xFF
0xFF
0x00
0x00
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Keypad Debounce
Time
Keypad Size
Configuration
Keypad Dedicated
Key 0
KBDDEDCFG0
KBDDEDCFG1
KBDRIS
Keypad Dedicated
Key 1
Keypad Raw
Interrupt Status
Keypad Masked
Interrupt Status
KBDMIS
R
Keypad Interrupt
Clear
KBDIC
W
Keypad Interrupt
Mask
KBDMSK
R/W
0xF3
KBDCODE0
KBDCODE1
KBDCODE2
KBDCODE3
EVTCODE
Keypad Code 0
Keypad Code 1
Keypad Code 2
Keypad Code 3
Key Event Code
0x0B
0x0C
0x0D
0x0E
0x10
R
R
R
R
R
byte
byte
byte
byte
byte
0x7F
0x7F
0x7F
0x7F
0x7F
0x0C
0x0D
0x0E
0x0F
0x10
15.1.2 PWM Timer Registers
Table 100 shows the register map for PWM Timer functionality. In addition to Global Call Reset (see Section 9.1.6 Global Call
Reset) or Software Reset using SWRESET (see Table 44), these registers are reset to default values by a module reset using
RSTCTRL.TIMRST (see Table 45).
TABLE 100. Register Map for PWM Timer Functionality
Register File
Address
Next RF
Address
Register Name
TIMCFG0
Description
Register Type ACCESS Size Default value
PWM Timer
Configuration 0
0x60
0x61
0x62
0x68
0x69
R/W
R/W
R/W
R/W
R/W
byte
byte
byte
byte
byte
0x00
0x00
0x00
0x00
0x00
0x61
0x62
0x63
0x69
0x6A
PWM
Configuration 0
PWMCFG0
TIMSCAL0
TIMCFG1
PWM Timer
Prescaler 0
PWM Timer
Configuration 1
PWM
Configuration 1
PWMCFG1
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Register File
Address
Next RF
Address
Register Name
TIMSCAL1
TIMCFG2
PWMCFG2
TIMSCAL2
TIMSWRES
TIMRIS
Description
Register Type ACCESS Size Default value
PWM Timer
Prescaler 1
0x6A
0x70
0x71
0x72
0x78
0x7A
0x7B
0x7C
0x7D
0x7E
R/W
R/W
R/W
R/W
W
byte
byte
byte
byte
byte
byte
byte
byte
byte
word
0x00
0x00
0x00
0x00
0x6B
0x71
0x72
0x73
0x79
0x7B
0x7C
0x7D
0x7E
0x7F
PWM Timer
Configuration 2
PWM
Configuration 2
PWM Timer
Prescaler 2
PWM Timer SW
Reset
PWM Timer
Interrupt Status
R
0x00
0x00
PWM Timer
Masked Int. Status
TIMMIS
R
Timer Interrupt
Clear
TIMIC
W
PWM Command
Write Pointer
PWMWP
R/W
W
0x00
PWM Command
Script
PWMCFG
15.1.3 System Registers
Table 101 shows the register map for general system registers. These registers are not affected by any of the module resets
addressed by RSTCTRL (see Table 45). These registers can only be reset to default values by a Global Call Reset (see Sec-
tion 9.1.6 Global Call Reset) or by a complete Software Reset using SWRESET (seeTable 44).
TABLE 101. Register Map for System Control Functionality
Register Name
Description
Register File
Address
Register Type ACCESS Size Default value
Next RF
Address
I2C-compatible
ACCESS.bus
Slave Address
I2CSA
0x80
W
R
byte
byte
0x88
0x81
Manufacturer
Code
MFGCODE
0x80
0x00
0x83
0x81
SWREV
SWRESET
RSTCTRL
SW Revision
SW Reset
0x81
0x81
0x82
R
W
byte
byte
byte
0x82
0x82
0x83
System Reset
R/W
0x00
Clear No Init/
Power On
Interrupt
RSTINTCLR
0x84
W
byte
0x85
CLKMODE
CLKCFG
Clock Mode
0x88
0x89
0x8A
0x8B
0x8C
R/W
R/W
R/W
R/W
R/W
byte
byte
byte
byte
word
0x01
0x40
0x89
0x8A
0x8B
0x8C
0x8D
Clock
Configuration
CLKEN
Clock Enable
0x00
Auto Sleep
Enable
AUTOSLP
AUTOSLPTI
0x00
Auto Sleep Time
0x00FF
15.1.4 Global Interrupt Registers
Table 102 shows the register map for global interrupt functionality. In addition to Global Call Reset (see Section 9.1.6 Global Call
Reset) or Software Reset using SWRESET (see Table 44), these registers are reset to default values by a module reset using
RSTCTRL.IRQRST (see Table 45).
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TABLE 102. Register Map for Global Interrupt Functionality
Register Name
Description
Register File
Address
Register Type ACCESS Size Default value
Next RF
Address
Global Interrupt
Status
IRQST
0x91
R
byte
0x80
0x92
15.1.5 GPIO Registers
Table 103 shows the register map for GPIO functionality. In addition to Global Call Reset (see Section 9.1.6 Global Call Reset) or
Software Reset using SWRESET (see Table 44), these registers are reset to 0x00 values by a module reset using
RSTCTRL.GPIRST and should be rewritten for desired settings (see Table 45).
TABLE 103. Register Map for GPIO Functionality
Register Name
Description
Register File
Address
Register Type ACCESS Size Default value
Next RF
Address
I/O Pin Mapping
Configuration
IOCFG
IOPC0
IOPC1
IOPC2
0xA7
0xAA
0xAC
0xAE
W
byte
word
word
word
0xA8
0xAB
0xAD
0xAF
Pull Resistor
Configuration 0
R/W
R/W
R/W
0xAAAA
0x5555
Pull Resistor
Configuration 1
Pull Resistor
Configuration 2
0x5A15
0x00
GPIODATA0
GPIOMASK0
GPIODATA1
GPIOMASK1
GPIODATA2
GPIOMASK2
GPIO I/O Data 0
GPIO I/O Mask 0
GPIO I/O Data 1
GPIO I/O Mask 1
GPIO I/O Data 2
GPIO I/O Mask 2
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
R/W
W
byte
byte
byte
byte
byte
byte
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
R/W
W
0x00
0x00
R/W
W
GPIO I/O
Direction 0
GPIODIR0
GPIODIR1
GPIODIR2
GPIOIS0
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
0x00
0x00
0x08
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0x00
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
GPIO I/O
Direction 1
GPIO I/O
Direction 2
GPIO Int Sense
Config 0
GPIO Int Sense
Config 1
GPIOIS1
GPIO Int Sense
Config 2
GPIOIS2
GPIO Int Both
Edges Config 0
GPIOIBE0
GPIOIBE1
GPIOIBE2
GPIOIEV0
GPIOIEV1
GPIOIEV2
GPIOIE0
GPIO Int Both
Edges Config 1
GPIO Int Both
Edges Config 2
GPIO Int Edge
Select 0
GPIO Int Edge
Select 1
GPIO Int Edge
Select 2
GPIO Interrupt
Enable 0
51
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Register Name
Description
Register File
Address
Register Type ACCESS Size Default value
Next RF
Address
GPIO Interrupt
Enable 1
GPIOIE1
GPIOIE2
0xD3
0xD4
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE9
0xEA
0xEB
R/W
R/W
R
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xD4
0xD5
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xEA
0xEB
0xEC
GPIO Interrupt
Enable 2
GPIO Raw Int
Status 0
GPIORIS0
GPIORIS1
GPIORIS2
GPIOMIS0
GPIOMIS1
GPIOMIS2
GPIOIC0
GPIO Raw Int
Status 1
R
GPIO Raw Int
Status 2
R
GPIO Masked Int
Status 0
R
GPIO Masked Int
Status 1
R
GPIO Masked Int
Status 2
R
GPIO Interrupt
Clear 0
W
GPIO Interrupt
Clear 1
GPIOIC1
W
GPIO Interrupt
Clear 2
GPIOIC2
W
GPIO Open Drain
Mode Enable 0
GPIOOME0
GPIOOMS0
GPIOOME1
GPIOOMS1
GPIOOME2
GPIOOMS2
GPIOWAKE0
GPIOWAKE1
GPIOWAKE2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x08
0x00
0x00
0x00
0x00
GPIO Open Drain
Mode Select 0
GPIO Open Drain
Mode Enable 1
GPIO Open Drain
Mode Select 1
GPIO Open Drain
Mode Enable 2
GPIO Open Drain
Mode Select 2
GPIO Wakeup
Enable 0
GPIO Wakeup
Enable 1
GPIO Wakeup
Enable 2
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53
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55
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56
16.0 Physical Dimensions inches (millimeters) unless otherwise noted
Micro Array Package
Order Number LM8325-1GRA25A
NS Package Number GRA25A
57
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Notes
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