LM98620VHB/NOPB [TI]
具有 LVDS 输出的 10 位 70 MSPS 6 通道图像信号处理器 | PFC | 80 | 0 to 70;
| 型号： | LM98620VHB/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 LVDS 输出的 10 位 70 MSPS 6 通道图像信号处理器 | PFC | 80 | 0 to 70 功率因数校正 商用集成电路 |
| 文件： | 总71页 (文件大小：1144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM98620
SNAS426C –FEBRUARY 2008–REVISED MAY 2014
LM98620 10-Bit 70 MSPS 6 Channel Imaging Signal Processor with LVDS Output
1 Features
2 Applications
1
•
3.3 V Single Supply Operation
CDS or S/H Processing
35 MHz Channel Rate
•
•
•
High Performance Digital Color Copiers
Scanners
•
•
•
Other Image Processing Applications
Enhanced ESD Protection on Timing, Control and
LVDS Pins
3 Description
The LM98620 is a fully integrated, 10-Bit, 70 MSPS
signal processing solution for high performance digital
color copiers, scanners, and other image processing
applications. High-speed signal throughput is
achieved with an innovative six channel architecture
utilizing Correlated Double Sampling (CDS), or
Sample and Hold (SH) type sampling. Gain settings
of 1x or 2x are available in the CDS/SH input stage.
Each channel has a dedicated 1x to 10x (8 bit) PGA
that allows accurate gain adjustment. The Digital
White Level auto calibration loop can automatically
set the PGA value to achieve a selected white target
level. Each channel also has a ±4 bit coarse and ±10-
bit fine analog offset correction DAC that allows offset
correction before the sample-and-hold amplifier.
These correction values can be controlled by an
automated Digital Black Level correction loop. The
PGA and offset DACs for each channel are
programmed independently allowing unique values of
gain and offset for each of the six channels. A 2-to-1
multiplexing scheme routes the signals to three 70
MHz high performance ADCs. The fully differential
processing channels achieve exceptional noise
immunity, having a very low noise floor of –68.5dB.
The 10-bit analog-to-digital converters have excellent
dynamic performance, making the LM98620
transparent in the image reproduction chain.
•
•
Low Power CMOS Design
12 Terminal to 16 Terminal (Selectable) LVDS
Serialized Data Output
•
•
•
4-Wire Serial Interface
2 Channel Symmetrical Architecture
Independent Gain and Offset Correction for Each
Channel
•
•
•
•
Digital Black Level Calibration for Each Channel
Digital White Level Calibration for Each Channel
Programmable Input Clamp
Key Specifications
–
Maximum Input Level:
–
–
1.2 Vp-p (CDS Gain = 1.0)
0.58 Vp-p (CDS Gain = 2.1)
–
Input Sample Rate:
–
–
5 to 35 MSPS - 6ch mode
10 to 35 MSPS - 3ch mode
–
–
–
–
–
–
–
–
PGA Gain Range: 1x to 10x (0 to 20 dB)
CDS/SH Gain Settings: 1x or 2.1x
Total Channel Gain: 1x to 21x (0 to 26 dB)
PGA Gain Resolution: 8 bits - Analog
ADC Resolution: 10 bits
Device Information(1)
ADC Sampling Rate: 10 to 70 MSPS
SNR: 68.5 dB (Gain = 1x)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM98620
TQFP (80)
12.00 mm × 12.00 mm
Offset DAC Range:
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
–
–
±111 mV or ±59.5 mV - FDAC
±281 mV - CDAC
Simplified Schematic
–
Offset DAC Resolution:
Red
–
–
±10 bits - FDAC
±4 bits - CDAC
CDAC
+/- 4
FDAC
+/- 10
1x or 2.1 x gain
Black Level Loop
White Level Loop
–
–
Supply Voltage: 3.0 V to 3.6 V
8
8
CDS/
SH
OSR1
OSR2
PGA
PGA
Power Dissipation: 1.02 W (typical)
M
U
X
10
10
ADC
CDS/
SH
Black Level Loop
White Level Loop
+/- 10
+/- 4
FDAC
CDAC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM98620
SNAS426C –FEBRUARY 2008–REVISED MAY 2014
www.ti.com
Table of Contents
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 21
7.4 Device Functional Modes........................................ 31
7.5 Programming........................................................... 35
7.6 Register Maps ........................................................ 46
Applications and Implementation ...................... 58
8.1 Application Information............................................ 58
8.2 Typical Applications ................................................ 59
Power Supply Recommendations...................... 62
9.1 Over Voltage Protection on OS Inputs.................... 62
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 Handling Ratings....................................................... 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements, AFE/ADC Timing .................. 9
6.7 Timing Requirements, Serial Interface Timing........ 10
6.8 Timing Requirements, LVDS Output Timing........... 11
6.9 LVDS TIming........................................................... 15
6.10 User Input Based Timing ...................................... 17
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
8
9
10 Layout................................................................... 63
10.1 Layout Guidelines ................................................. 63
10.2 Layout Examples................................................... 64
11 Device and Documentation Support ................. 65
11.1 Trademarks........................................................... 65
11.2 Electrostatic Discharge Caution............................ 65
11.3 Glossary................................................................ 65
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 65
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C
Page
•
Added data sheet flow and layout to conform with new TI standards. Added the following sections: Applications and
Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
•
Added footnote "When the input voltage..." to Absolute Maximum Ratings table.................................................................. 5
Changes from Revision A (December 2013) to Revision B
Page
•
Changed format of data sheet to conform with TI standards. ............................................................................................... 1
Changes from Original (February 2008) to Revision A
Page
•
Added sections to make full data sheet from template. ........................................................................................................ 1
2
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SNAS426C –FEBRUARY 2008–REVISED MAY 2014
5 Pin Configuration and Functions
80 Pin
PFC Package
(Top View)
SHD/HOLD
VDDD
VSSD
CLPIN
BLKCLP
AGCONB
OVPB
MCLK
GPI1
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VREFBOUT
VREFTOUT
VDDA
2
3
4
VREF
5
VSSA
6
VSSD
7
VDDD
8
SDO
9
SENB
LM98620
80-PIN TQFP
(Top View)
10
11
12
13
14
15
16
17
18
19
20
SDI
GPI2
SCLK
GPI3
RESETB
TESTO_0
TESTO_1
VREG1
VDDLVDS
VDDLVDS
VREG2
VSSLVDS
VSSLVDS
GPI4
GPI5
VSSD
VDDD
IBIAS
VREG1
VSSD
VDDD
VREG2
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Pin Functions
PIN
PULLUP
PULLDOWN
TYPE(1)
DESCRIPTION
NAME
SHD/HOLD
VDDD
NUMBER
1
DI
PI
PI
DI
DI
DI
Data Clamp Pulse/Hold Input
2, 15, 19, 54
Digital Power Supply
VSSD
3, 14, 18, 55
Digital Power Supply Ground
CLPIN
4
5
Input Pulse that Invokes the Input Clamp Switch
Input Pulse that Invokes the Black Calibration Loop
BLKCLP
PD 108 kΩ
PU 108 kΩ
Input Pulse that Invokes the White Calibration Loop. Tie high to disable
White Clamp. Pulse Low to initiate White Clamp. (Active Low)
AGC_ONB
6
DI
Over Voltage Protection Enable (Active Low). Enables OS input
protections switches to ground during system power up. Should be tied
high after AFE and CCD voltages have stabilized.
OVPB
7
MCLK
8
DI
DI
Master Clock Input
GPI1-5
9 to 13
General Purpose Inputs 1 – 5, mapped into LVDS output data
AO
Optional IBIAS resistor connection. To minimize device to device power
consumption variation, connect an 11k Ω 1% resistor to VSSA. If no
resistor is used, the internal bias and power supply currents will be
subject to normal device to device variation.
IBIAS
16
VREG1
17, 46
PO
Decoupling connection for VREG1 – Approx. 1.8 V output(2)
Decoupling connection for VREG2 – Approx. 1.8 V output(2)
VREG2
20, 27, 33, 43
21, 22
23, 24
25, 26
28, 34, 41, 42
29, 30
31, 32
35, 36
37, 38
39, 40
44, 45
47
PO
DO
DO
DO
PI
TXCLK1
TXOUTC1
TXOUTB1
VSSLVDS
TXOUTA1
TXCLK2
TXOUTC2
TXOUTB2
TXOUTA2
VDDLVDS
TESTO_1
TESTO_0
RESETB
SCLK
Differential LVDS Output Clock 1
Differential LVDS Output Data C1
Differential LVDS Output Data B1
LVDS Power Supply Ground
DO
DO
DO
DO
DO
PI
Differential LVDS Output Data A1
Differential LVDS Output Clock 2
Differential LVDS Output Data C2
Differential LVDS Output Data B2
Differential LVDS Output Data A2
LVDS Power Supply
DO
DO
DI
Digital Test Output
48
Digital Test Output
49
PU 108 kΩ
PU 108 kΩ
Master Reset Input(Active Low)
Serial Clock for the 4-wire Serial Interface
Serial Data for the 4-wire Serial Interface
Serial Enable (Active Low) for the 4-wire Serial Interface
Serial Output Data for the 4-wire Serial Interface
50
DI
SDI
51
DI
SENB
52
DI
SDO
53
DO
PI
56, 65, 69, 73,
77
VSSA
Analog Power Supply Ground
VREF
VDDA
57
AO
PI
Reference Voltage Bypass – Approx. 1.2 V output(2)
Analog Power Supply
58, 67, 71, 75
AO
Top Reference Bypass. Connect to bypass capacitors (see Applications
and Implementation) and VREFTINx. – Approx. 2.23 V output.(2)
VREFTOUT
59
(1) KEY: A – Analog, D – Digital, P – Power, I – Input, O – Output, PD – Pull-down resistor to VSSD. PU – Pull-up resistor to VDDD.
(2) Voltages provided for debugging only. Not a guaranteed specification.
4
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SNAS426C –FEBRUARY 2008–REVISED MAY 2014
Pin Functions (continued)
PIN
PULLUP
PULLDOWN
TYPE(1)
DESCRIPTION
NAME
NUMBER
AO
Bottom Reference Bypass. Connect to bypass capacitors (see
Applications and Implementation) and VREFBINx. – Approx. 0.98 V
output.(3)
VREFBOUT
60
VREFBIN2
VREFTIN2
VREFBIN1
VREFTIN1
OSR1
61
62
63
64
66
68
70
72
74
76
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
Bottom Reference Input Voltage for the ADC. Connect to VREFBOUT.
Top Reference Input Voltage for the ADC. Connect to VREFTOUT.
Bottom Reference Input Voltage for the AFE. Connect to VREFBOUT.
Top Reference Input Voltage for the AFE. Connect to VREFTOUT.
Input Voltage 1 for the Red Channel
OSR2
Input Voltage 2 for the Red Channel
OSG1
Input Voltage 1 for the Green Channel
OSG2
Input Voltage 2 for the Green Channel
OSB1
Input Voltage 1 for the Blue Channel
OSB2
Input Voltage 2 for the Blue Channel
External Clamp Voltage (Connect to VCLP_INT or customer supplied
reference voltage
VCLP_EXT
78
AO
DI
Internally Generated V-Clamp Voltage. Connect to bypass capacitors
and VCLK_EXT. – Approx. 1.65 V output(3)
VCLP_INT
79
80
SHP/SAMPLE
Pedestal Clamp Pulse/Sample Input.
(3) Voltages provided for debugging only. Not a guaranteed specification.
6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
MAX
4.2
UNIT
V
Supply Voltage
Voltage at any Pin (except VREG1, VREG2)
Voltage at VREG1, VREG2
VDDA + 0.3
2.1
V
V
Continuous Input Current at any Pin(2)
Continuous Input Package Current(2)
Maximum Junction Temperature (Powered)
Specified Ambient Temperature Range
Maximum Junction Temperature
±25
mA
mA
°C
°C
°C
±50
TJ_ABS_MAX = +135
0 ≤ T A ≤ +70
TJ_OP_MAX = +110
(1) Absolute maximum ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
(2) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (GND - 0.3 V) or V IN > (VDDA + 0.3 V)), the DC current at
that pin should be limited to ±25 mA. The 50 mA DC maximum package input current means that a maximum of two pins can
simultaneously have input currents that equal 25 mA.
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6.2 Handling Ratings
MIN
MAX
150
UNIT
Tstg
Storage temperature range
–65
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(3)
2500
(1)(2)
V(ESD)
Electrostatic discharge
Machine Model (MM)
250
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(4)
1000
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. Charged
device model (CDM) simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated
assembler) then rapidly being discharged.
(a) Higher 7500V human body model rating and 750V machine model rating for the following pins: SHP, SHD, CLPIN, BLKCLP,
AGC_ONB, OVPB, MCLK, RESETB, SENB, SCLK, SDI, SDO, TXCLK1, TXCLK2, TXOUTA1, TXOUTB1, TXOUTC1, TXOUTA2,
TXOUTB2, TXOUTC2.
(3) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(4) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
+3.0
+3.0
+3.0
NOM
MAX
+3.6
+3.6
+3.6
UNIT
Analog Supply Voltage Range
Digital Supply Voltage Range
LVDS Supply Voltage Range
V
V
V
V
VDDD ≥ VDDA,
VDDD ≥ VDDLVDS
DC Power Supply Voltage Relationships(1)
Voltage at any Digital I/O pin
Voltage at any Analog Input pin
Voltage at any LVDS I/O pin
0
0
VDDD
V
V
V
VDDA
VDDLV
DS
0
(1) Static voltage levels on VDDD must be at the same voltage or slightly higher than VDDLVDS or VDDA. Therefore, driving all three
power supplies from a common linear voltage regulator is recommended. Please see Figure 1.
V
IN
V
DDD
Vreg
+
+
V
DDA
+
+
V
DDLVDS
+
Figure 1. Recommended Setup
6
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6.4 Thermal Information
LM98620VHB
THERMAL METRIC(1)
TQFP
80 PINS
32
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
The following specifications apply for VDDA = VDDD = VDDLVDS = 3.3 V; FMCLK = FADCCLK= 70 Ms/s; 6 Channel Mode
unless otherwise noted.
TA = TMIN to TMAX
TA = +25°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ADC/AFE
Resolution
No missing codes
10
bits
-0.6%
to
0.8%
Gain = 1x
Gain = 6x
-1.5%
1.8%
INL
Integral Non-Linearity
-1.4%
to
1.4%
-0.4 to
0.4
Gain = 1x
Gain = 6x
-0.99
1.6
DNL
SNR
Differential Non-Linearity
Signal-to-Noise Ratio(1)
lsb
dB
-0.6 to
0.7
Gain = 1x
68.5
58.5
Gain = 6x
Negative Polarity:
• Peak-to-peak, CDS gain = 1x
• Peak-to-peak, CDS gain = 2.1x
Positive Polarity:
1.12
0.54
1.28
0.62
1.2
V
Analog Input Range (OSx
Inputs)
0.58
• Peak-to-peak, CDS gain = 1x
1.2
V
GND < Vin < VDDA
Source Follower Enabled – OVP
off
Analog Input Leakage
(Osx inputs)
–250
0.79
200
±25
nA
(2)
RCLAMP
Input Clamp Impedance
Conversion Ratio
(See
)
43
Ω
CDS/SH Gain Setting = 1x
PGA gain setting = Min
0.91
0.85
lsb/mV
Conversion Ratio Color to
Color(3) Error
0.24%
0.13%
Conversion Ratio Ch1 to
Ch2 Error
R1,B1 to G1; R1,G1 to B1, and
so forth. R2, B2, to G2; R2, G2,
to B2, and so forth.
Crosstalk – Color to Color
Crosstalk – Ch1 to Ch1
0.07%
0.2%
Gain = 20x setting
R1 to R2, R2 to R1, G1 to G2, G2
to G1, B1 to B2, B2 to B1
Gain = 20x setting
(1) SNR = 20log(1024/Output Noise(lsb rms)) with input = DC.
(2) This parameter specified by simulation and/or bench evaluation and not production tested.
(3) For conversion ratio min/max, variation and error, Conversion ratio is: (Digital Max – Digital Min)/(Vin Max – Vin Min). Measured at gain
setting of 1x
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
The following specifications apply for VDDA = VDDD = VDDLVDS = 3.3 V; FMCLK = FADCCLK= 70 Ms/s; 6 Channel Mode
unless otherwise noted.
TA = TMIN to TMAX
TA = +25°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Active Mode:
• Total Power
• IDDA
1119
240
58
1020
mW
mA
mA
mA
Power Consumption
• IDDD
• IDDLVDS
41
Power-Down Mode:
• MCLK Active
• MCLK Stopped
Power Consumption
191
47
159
23
mW
mW
PGA (8 bits) Gain = 283/(283-M)
PGA Gain Range(4)
PGA Stepsize
Gain at max setting/
Gain at min setting
19.5
20.9
20
dB
dB
0.3
Mono-
tonic
PGA Monotonicity
PGA Error (Difference from
ideal curve)
<0.6%
CDS/SH
6.4
2.1
dB
CDS/SH Gain
Gain at 2.1x / Gain at 1x
2
2.13
V/V
Offset FDAC (±10 bits)
DAC Full Scale (input
referred)
Large FDAC range
Small FDAC range
103
54
120
66
111
±mV
59.5
Mono-
tonic
DAC Monotonicity
Offset CDAC (± 4 bits)
DAC Full Scale (input
referred)
259
302
281
±mV
Mono-
tonic
DAC Monotonicity
BLACK CALIBRATION LOOP
Target Output Level
127
0
lsb
lsb
WHITE CALIBRATION LOOP
Target Output Level
512
2.0
1023
2,4,8,
16,32
#
Window Size
Pixels
LOGIC I/O DC PARAMETERS
SHP, SHD, CLPIN, BLKCLP,
VIH
VIL
Logic Input High Threshold AGC_ONB, OVPB, MCLK, GPIn,
SCLK, SDI, SENB
V
V
SHP, SHD, CLPIN, BLKCLP,
AGC_ONB, OVPB, MCLK, GPIn,
SCLK, SDI, SENB
Logic Input Low Threshold
0.8
IIN
Logic Input Leakage
–100
3.3
100
±25
3.5
2.9
nA
V
VDDD = 3.6 V, Iout = –0.5 mA
VDDD = 3.0 V, Iout = –0.5 mA
VOH
Logic Output Voltage High
2.7
(4) PGA gain range is: [(ADC_OUT(PGA @ 1111111111)) / (ADC_OUT(PGA @ 0000000000))]
8
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
The following specifications apply for VDDA = VDDD = VDDLVDS = 3.3 V; FMCLK = FADCCLK= 70 Ms/s; 6 Channel Mode
unless otherwise noted.
TA = TMIN to TMAX
TA = +25°C
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
0.3
MIN
TYP
0.15
0.15
1.4
MAX
VDDD = 3.6 V, Iout = 1.6 mA
VDDD = 3.0 V, Iout = 1.6 mA
VOL
Logic Output Voltage Low
Power On Reset Threshold
V
V
0.3
VREB
LVDS DC PARAMETERS
VOD
Differential Output Voltage
210
420
17
300
2.5
mV
mV
Change in Diff. Output
Voltage
Δ VOD
VOS
Offset Voltage
1.17
1.28
13
1.2
2.5
5
V
ΔVOS
Change in Offset Voltage
mV
TXCLKx
6.7
8.9
I OS
Output Short Circuit Current
mA
TXOUTxx
7
6.6 Timing Requirements, AFE/ADC Timing
TA = TMIN to TMAX
MIN TYP MAX
TA = +25°C
TEST CONDITIONS
UNIT
MIN TYP MAX
fMCLK
MCLK frequency
MCLK Duty Cycle
6 channel mode
3 channel mode
10
10
70
35
MHz
DC
40%
60%
SMAX
Input Sampling Rate –
maximum
35
MS/s
MS/s
SMIN
Input Sampling Rate –
minimum
5
10
2
tRESET
RESETB Pulse Width
RESETB Clear Time(1)
tMCLK
tMCLK
t
3
5
RESET_CLR
tMNS
Min Sample Falling Edge
Setting
SH2b (tSHD = 8.2 ns), MCLK= ADCCLK/2):
• ADCCLK = 20 MHz
4
Decimal
Setting
14
• ADCCLK = 70 MHz
12
tMXS
Max Sample Falling Edge
Setting
SH2b (tSHD = 8.2 ns), MCLK = ADCCLK/2:
• ADCCLK = 20 MHz
• ADCCLK = 70 MHz
27
23
29
25
Decimal
Setting
tMXE
Sample Falling Edge Max
Error
SH2b, Register 0x36 = Min to Max (MCLK = ADCCLK/2):
• ADCCLK = 20 MHz
+0.2/
–0.3
ns
ns
• ADCCLK = 70 MHz
+0.2/
–0.4
tSFED
Sample Falling Edge Delay
(MCLK rising edge to OSx
voltage step)
SH2b, Register 0x36 = 16d (MCLK = ADCCLK/2):
ADCCLK = 70 MHz
13
ns
ns
(1)
tSHD
SHP/SHD high period
(See
)
8.2
(1) This parameter specified by simulation and/or bench evaluation and not production tested.
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UNIT
Timing Requirements, AFE/ADC Timing (continued)
TA = TMIN to TMAX
MIN TYP MAX
TA = +25°C
TEST CONDITIONS
MIN TYP MAX
tMCS_MIN
MCLK high to SAMPLE high
SH3 Mode – ADC Rate MCLK
SH2a Mode
15
15.5
6
11
11.7
3.5
(minimum)
(2)
(See
)
ns
SH1b Mode
CDSb Mode
6
3.3
tHMC_MIN
HOLD high to MCLK high
SH3 Mode – ADC Rate MCLK
SH2a Mode
2.5
1.5
1
–1
(minimum)
–2.4
–4.5
–5.5
2
(2)
(See
)
ns
ns
SH1b Mode
CDSb Mode
1
tMCH_MIN
tAD
MCLK high to HOLD high
(Minimum)
SH3 Mode – ADC Rate MCLK
6
Aperture delay
5
ns
ns
Aperture delay variation
CLPIN/BLKCLP Pulse Width
0.6
tCLPIN
,
(high or low)
2
tMCLK
tBLKCLP
tIS
CLPIN/BLKCLP/GPIn Setup
CLPIN/BLKCLP/GPIn Hold
CLPIN neg. edge to BLKCLP
3
3
ns
ns
tIH
tC_B
6 Channel mode
3 Channel mode
16
10
start
(See
Pixels
(3)
)
(3)
tGPI_LAT
GPIn Latency (See
)
6 Channel – ADC Rate MCLK
6 Channel – Pixel Rate MCLK
3
1.5
3
tMCLK
3 Channel – ADC = Pixel Rate
MCLK
tLAT(1)
tLAT(2)
tLAT
6 Channel Mode
Channel 1 Latency
6 Channel Mode
Channel 2 Latency
ADC Rate MCLK
Pixel Rate MCLK
ADC Rate MCLK
Pixel Rate MCLK
ADC=Pixel Rate MCLK
11
5.5
12
6
tMCLK
tMCLK
tMCLK
3 Channel Mode Latency
11
(2) Measured with AFEPHASE = 11. For other AFEPHASE settings,these sample input timings will shift earlier with respect to MCLK as
follows. (tHMC will increase by these amounts, tMCH will decrease by these amounts):
(a) AFEPHASE = 10 – Earlier by ¼ pixel period
(b) AFEPHASE = 01 – Earlier by ½ pixel period
(c) AFEPHASE = 00 – Earlier by ¾ pixel period
(3) This parameter specified by simulation and/or bench evaluation and not production tested.
6.7 Timing Requirements, Serial Interface Timing
TEST CONDITIONS
TA = TMIN to TMAX
UNIT
MIN
50
20
20
5
TYP
MAX
tCP
SCLK period
ns
ns
tWH
SCLK High width
tWL
SCLK Low width
ns
tIS
SDI Setup time
ns
tIH
SDI Hold time
5
ns
tSENSC
tSCSEN
tSENW
tOD
SENB low before SCLK rising
SENB high after SCLK rising
SENB high width
5
ns
5
ns
5
tMCLK
ns
SDO Output delay
2
10
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6.8 Timing Requirements, LVDS Output Timing
TEST CONDITIONS
TA = TMIN to TMAX
TA = +25°C
UNIT
MIN
10
TYP
MAX
70
MIN
TYP
MAX
fTXCLK
tTXCLK
LLHT
LVDS TXCLK Frequency
LVDS TXCLK Period
MHz
ns
14.3
100
(1)
(1)
LVDS Low to High Transition (See
Time
)
0.75
0.75
250
ns
ns
ps
LHLT
LVDS High to Low Transition (See
Time
)
(2)
TCCS
TPPos0
TxOUT Channel to Channel
Skew
70 MHz TXCLK (See
)
Transmitter Output Pulse
Pos. Bit 0
70 MHz TXCLK(2)
10 MHz TXCLK(3)
70 MHz TXCLK(2)
10 MHz TXCLK(3)
70 MHz TXCLK(2)
10 MHz TXCLK(3)
70 MHz TXCLK(2)
10 MHz TXCLK(3)
-0.26
-0.44
1.47
8.56
3.64
24.1
5.42
37.9
7.56
52.5
9.56
67.7
11.82
81.8
0.1
0.48
2.46
20
-0.06
0
ns
ns
ns
ns
ns
ns
ns
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Transmitter Output Pulse
Pos. Bit 1
2
14.2
4.1
Transmitter Output Pulse
Pos. Bit 2
4.49
35.2
6.33
49.3
8.38
63.1
10.33
76.9
12.53
90.2
29.7
5.9
Transmitter Output Pulse
Pos. Bit 3
43.7
8
(2)
Transmitter Output Pulse
Pos. Bit 4
70 MHz TXCLK
10 MHz TXCLK(3)
70 MHz TXCLK(2)
10 MHz TXCLK(3)
70 MHz TXCLK(2)
10 MHz TXCLK(3)
57.9
10
Transmitter Output Pulse
Pos. Bit 5
72.4
12.2
85.9
Transmitter Output Pulse
Pos. Bit 6
(1) This parameter specified by simulation and/or bench evaluation and not production tested.
(2) TPPos0 to TPPos6 values are given for 70 MHz TXCLK frequency. These values are ensured by characterization and are not
production tested.
(3) TPPos0 to TPPos6 values are given for 10 MHz TXCLK frequency. These values are ensured by characterization and are not
production tested.
t
RESET_CLR
MCLK
Reset
Internal
VDDA
V
RES
Figure 2. Power on Reset (POR)
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t
t
RESET_CLR
RESET
MCLK
RESETB
Figure 3. RESETB Input Timing
90%
90%
10%
MCLK
10%
t
R
t
IH
t
IS
t
F
CLPIN/
BLKCLP/
GPIx
90%
10%
90%
10%
Note: CLPIN, BLKCLP and GPIx are all sampled or latched on the rising edge of MCLK
Figure 4. Input Setup and Hold Timing
Figure 5. Sample Falling Edge Delay
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Pixel(n)
Pixel(n+1)
OSR1/2
OSG1/2
OSB1/2
tAD
tAD
SAMPLE
HOLD
tSHD
tMCH
tCL tCH
tMCLK
tHMC
MCLK
tIH
tIS
tLAT(2)
tLAT(1)
GPI[5:1]
tGPI_LAT
Ch.1(n) Ch.2(n) Ch1.(n+1)Ch2.(n+1)
TXCLK+
Above timing relationships between SAMPLE, HOLD and MCLK are for AFEPHASE = 11.
For other AFEPHASE settings, the sampling timing can move earlier by ¼, ½ or ¾ pixel period with respect to
MCLK, but the latency as shown above will remain constant.
Figure 6. Output Latency and Timing – 6 Channel Mode – ADC Rate MCLK
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Pixel(n)
Pixel(n+1)
OSR1/2
OSG1/2
OSB1/2
tAD
tAD
SAMPLE
tSHD
HOLD
MCLK
tMCH
tHMC
tCL
tCH
tMCLK
mclk_int
GPI[5:1]
tIH
tIS
tLAT(2)
tLAT(1)
tGPI_LAT
Ch.1(n) Ch.2(n) Ch1.(n+1)Ch2.(n+1)
TXCLK+
Above timing relationships between SAMPLE, HOLD and MCLK are for AFEPHASE = 11.
For other AFEPHASE settings, the sampling timing can move earlier by ¼, ½ or ¾ pixel period with respect to
MCLK, but the latency as shown above will remain constant.
Figure 7. Output Latency and Timing – 6 Channel Mode – Pixel Rate MCLK
Pixel(n)
Pixel(n+1)
OSR1
OSG1
OSB1
tAD
SAMPLE
HOLD
tSHD
tMCH
tCH
tCL
tHMC
MCLK
tMCLK
tIH
tIS
tLAT
GPI[5:1]
tGPI_LAT
Data(n)
Data(n+1)
TXCLK+
Figure 8. Output Latency and Timing – 3 Channel Mode
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6.9 LVDS TIming
80%
20%
80%
20%
LLHT
LHLT
Figure 9. LVDS Transition Times
TCCS
TXOUTA1
TXOUTB1
TXOUTC1
TXOUTA2
TXOUTB2
TXOUTC2
TXCLK+
Vdiff=0
Measurements at Vdiff = 0V
TCCS measured between earliest and latest LVDS
edges and TxCLK Differential Low to High Edge
Figure 10. LVDS Channel to Channel Skew
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LVDS TIming (continued)
Pixel N-1
Pixel N
Pixel N+1
TX6
TX6
TX6
TX6
TX6
TX6
TX5
TX5
TX5
TX5
TX5
TX5
TX4
TX4
TX4
TX4
TX4
TX4
TX3
TX2
TX2
TX2
TX2
TX2
TX2
TX1
TX1
TX1
TX1
TX1
TX1
TX0
TX0
TX0
TX0
TX0
TX0
TXOUTA1
TXOUTB1
TXOUTC1
TXOUTA2
TXOUTB2
TXOUTC2
TXCLK+
TX3
TX3
TX3
TX3
TX3
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Figure 11. LVDS Output Pulse Positions
TXOUT
TXCLK
VOD
VOS
0V
Note: LVDS Output Ref erenced to 0V or V SSLV DS
Figure 12. LVDS DC Parameters
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6.10 User Input Based Timing
NOTE
Note: 4 (6 Channel Mode) or 2 (3 Channel Mode) AFEPHASE settings are available to
provide flexibility of sample timing.
For ease of use, AFEPHASE = 11 is the default setting in 6 channel mode, and AFEPHASE = X1 is the default
setting for 3 channel mode, as shown in select diagrams.
Specified values for these timings are measured at AFEPHASE = 11. For other AFEPHASE settings,these
sample input timings will shift earlier with respect to MCLK as follows:
•
•
•
AFEPHASE = 10 – Earlier by ¼ pixel period
AFEPHASE = 01 – Earlier by ½ pixel period
AFEPHASE = 00 – Earlier by ¾ pixel period
tMCS
tMCH
tHMC
CCD Output
MCLK
SAMPLE
HOLD
tSHD
(Assumes rising edges of external pulses are active)
Figure 13. SH3 Timing Mode – ADC Rate Clock Input
tMCS
tHMC
CCD Output
AFEPASE01
MCLK
SAMPLE
HOLD
tSHD
(Assumes rising edges of external pulses are active)
Figure 14. SH2 Timing Mode – ADC Rate Clock Input
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User Input Based Timing (continued)
tMCS
tHMC
CCD Output
AFEPASE01
MCLK
SAMPLE
HOLD
tSHD
(Assumes rising edges of external pulses are active)
Figure 15. SH2 Timing Mode – Pixel Rate Clock Input
tMCS
tMCS
tHMC
tHMC
CCD Output
AFEPASE01
MCLK
SHP
SHD
tSHD
tSHD
(Assumes external pulses are active high)
Figure 16. SH1b/CDSb Timing Mode – ADC Rate Clock Input
tMCS
tMCS
tHMC
tHMC
CCD Output
AFEPASE01
MCLK
SHP
SHD
tSHD
tSHD
(Assumes external pulses are active high)
Figure 17. SH1b/CDSb Timing Mode – Pixel Rate Clock Input
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7 Detailed Description
7.1 Overview
The PGA and offset DACs for each channel are programmed independently allowing unique values of gain and
offset for each of the six channels. A 2-to-1 multiplexing scheme routes the signals to three 70 MHz high
performance ADCs. The fully differential processing channels achieve exceptional noise immunity, having a very
low noise floor of –68.5dB. The 10-bit analog-to-digital converters have excellent dynamic performance, making
the LM98620 transparent in the image reproduction chain.
7.2 Functional Block Diagram
Red
CDAC
+/- 4
FDAC
+/- 10
1x or 2.1 x gain
Black Level Loop
White Level Loop
8
8
CDS/
SH
OSR1
OSR2
PGA
PGA
M
U
X
10
10
ADC
CDS/
SH
Black Level Loop
White Level Loop
+/- 10
+/- 4
FDAC
CDAC
Figure 18. Channel Block Diagram
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Functional Block Diagram (continued)
Red
Green
Blue
OSR1
TXOUTA1+
TXOUTA1-
10
10
10
See Channel Block Diagram for details
OSR2
TXOUTB1+
TXOUTB1-
TXOUTC1+
TXOUTC1-
TXCLK1+
TXCLK1-
OSG1
OSG2
LVDS
Serializer
See Channel Block Diagram for details
TXOUTA2+
TXOUTA2-
TXOUTB2+
TXOUTB2-
TXOUTC2+
TXOUTC2-
OSB1
OSB2
TXCLK2+
TXCLK2-
See Channel Block Diagram for details
GPI5
GPI4
GPI3
GPI2
GPI1
GP
Inputs
VCLP
1.8V
Regulator
Vreg
VCLP_EXT
VCLP_INT
RESETB
SHP/SAMPLE
SHD/HOLD
CLPIN
Vreftout
Vrefbout
Vref
Reference
Generator
Clamp Voltage
Buffer
Timing
and
Control
Inputs
BLKCLP
AGC_ONB
MCLK
SENB
SCLK
SDI
OVPB
Serial
Interface
SDO
Figure 19. Chip Block Diagram
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7.3 Feature Description
7.3.1 Input Clamping and Biasing Circuitry
Many sensor input signals will be at a different common mode voltage than that of the LM98620 input circuitry. In
these applications, AC coupling is used to block the DC voltage difference between the source and the AFE
inputs. Input clamp circuits are used to set the AFE input at the proper common mode voltage.
Initial coarse clamping should be done using the PIB (Passive Input Bias) and/or AIB (Active Input Bias) circuitry.
Setting the PIB enable bit connects 1 kΩ pull-up and pull-down resistors to the inputs to rapidly charge them to
VDDA/2. Setting the AIB bit connects the VCLPEXT reference voltage to the inputs via low impedance switches.
Either method will bring the input voltage very close to the desired level of VDDA/2.
The AIB and PIB must be disabled during normal operations.
During image capture, black level clamping is done by connecting the input pins to an internal reference voltage
through a low impedance switch. The clamp is turned on periodically to correct any droop in the DC input voltage
and minimize conversion errors.
The clamp switch will be turned on during the “Black” portion of the input signal when the input is at a known
voltage level. The clamp will connect the inputs to a reference level of approximately 1.65 V. Optionally, a
customer supplied reference voltage can be applied at the VCLPEXT pin. If an external reference is used, it must
be capable of driving the 6 OS coupling capacitors through 6 internal resistors of 20 Ω. The alternative is to use
a weaker buffer, with a large external capacitance (> the sum of the OS coupling capacitors). Clamp timing is
controlled by the CLPIN input signal in combination with the register bit ANDen and the internal SAMPLE timing
signal.
CLPIN can directly control the internal Clamp, or the combination of CLPIN and SAMPLE can be used. Clamping
only during SAMPLE ensures that the input is clamped to the “Black” level rather than the average of “Black”,
“Reset” and reset noise feed through signals.
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Feature Description (continued)
1 per OS input
Note: Switches are closed when control input = 1.
750Ω
1kΩ
4.7 uF
OS
OVP_ext
OVPB
To SH/CDS
CCD
1kΩ
OVP_int
0x01, b4
PIB
0x00, b6
RDIV
0x04, b7
VCLPEXT
10 uF
AIB
0x00, b7
ClpMode
0x02, b0
MUX
0
1
Configurationregister
control bits
SAMP CLK
CLPIN
R1
Vclamp
buffer
VCLPINT
R1
VCLPBuff
0x00, b2
Figure 20. Input Protection and Clamping and Biasing Circuitry
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Feature Description (continued)
Valid Pixels
CCD Power Up
Optical Black Pixels
Dummy Pixel(s)
Sensor
Outputs
V
/2
DDA
OSR1/2
OSG1/2
OSB1/2
0 V
(B)
(C)
0.7 V
(A)
CLPIN
(C)
BLKCLP
t
t
BLKCLP
CLPIN
MCLK
Internal
Sample
Timing
Clamp
switch
control
Clamp Control = 1
Clamp Control = 0
Clamp
switch
control
PIB and/or
AIB
(B)
OVPB
(A)
Note: Waveforms not to scale.
A. During initial system power up, the OVP clamp circuit will be enabled. This provides a path for current to flow as the
sensor is powered up, and the large common mode voltage output of the sensor reaches a steady state value. Once
the sensor voltages have stabilized, the OVP circuit can be disabled. At this point the OS inputs will still be
approximately 0.7 V above ground. Settling to 99% of final voltage will take approximately 18 ms for a 4.7 uF
capacitance, assuming a 750 Ω diode/switch impedance.
B. Then, the PIB and/or AIB circuits should be enabled to bring the OS inputs up to approximately VDDA/2 volts. After
the OS voltages have charged to this level, the PIB and AIB biasing should be turned off. Settling to within 1mV of
VDDA/2 will take approximately 18 ms for a 4.7 uF capacitance, assuming a 500 Ω charging resistance.
C. During image acquisition, accurate DC clamping is provided by the CLPIN switch. This switch is enabled when the
CLPIN input is asserted. In most applications, the Clamp Control bit (Register 0x03, b3) should be set to gate the
CLPIN signal with the internal sampling pulse. This will ensure that clamping is only done during the image portion of
the optical black pixels. Settling to 1mV for a 10mV ΔV between the pedestal and black will take: (1/(%dwell) x 1/(%
samp time) x Rsw x Cin x 5).
Settling Time = (1/(32/7600 pixels)) x 1/(50%) x 40 Ω x 4.7 uF x 5 = 447 ms.
Smaller input capacitors will result in proportionally smaller settling times for all clamping modes.
Figure 21. Input Protection Clamping and Biasing – Operation Example
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Feature Description (continued)
7.3.2 Input Signal Polarity Select
The LM98620 can accept input signals with negative polarity (default) as output by CCD type sensors, and (when
operated in the Sample and Hold modes) can also be configured to accept signals with positive polarity as output
by some CIS type sensors.
The input signal polarity selection is found at Page 0, Register 0x03, Bit 7 of the configuration registers.
Changing this bit from 0 (default) to 1 selects the positive polarity mode.
*Negative Polarity mode works in both CDS and Sample and Hold modes.
*Positive Polarity mode is only functional in the Sample and Hold modes.
7.3.3 Input Connections for 3 Channel Operation
For three channel only applications, the unused inputs should be connected with 10k Ω resistors to VCLP_EXT
to minimize noise coupling into the active inputs.
OSR1
OSR2
OSG1
OSG2
OSB1
OSB2
10 kꢀ
Figure 22. Unused Input Connection
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Feature Description (continued)
7.3.4 AFE References
A low noise reference structure is incorporated in the LM98620.
Outputs (VREFTOUT approx. 2.23 V, VREFBOUT approx. 0.98 V) and inputs (VREFTIN1, VREFTIN2,
VREFBIN1, VREFBIN2) are provided to allow decoupling capacitors to be connected. VREFTOUT should be
connected to VREFTIN1 and VREFTIN2. VREFBOUT should be connected to VREFBIN1 and VREFBIN2.
Recommended capacitance is 1.0 uF between the top and bottom reference source, with 0.1 uF to AGND from
both the top and bottom reference source. Connection and decoupling capacitor traces should all be as short as
possible, and digital signals should be kept away from this area. Internal connections from VREFTOUT to
VREFTIN1,2 and VREFBOUT to VREFBIN1,2 are present to reduce the impedance between outputs and inputs,
but external connections should still be used for the best performance.
VREFTOUT
0.1 µF
VREFTIN1
VREFTIN2
+
1 µF
0.1 µF
VREFBIN1
VREFBIN2
VREFBOUT
0.1 µF
Figure 23. Reference Decoupling Example
7.3.5 Offset Control
Analog offset is provided before the ADC.
Two offset DACs are used to provide a coarse (CDAC) and fine (FDAC) offset that is applied prior to the
CDS/SH stage.
•
•
The offset CDAC (Coarse DAC) provides ± 280 mV with ± 4 bits of resolution in offset binary format.
The offset FDAC (Fine DAC) provides ± 110 mV (Large FDAC range) or ± 59.5 mV (Small FDAC range) with
± 10 bits of resolution in offset binary format. The FDAC range is controlled by the FDAC range bit for each
color channel, in Register 0x03h, bits 3, 4, 5.
Table 1. The Offset CDAC and Offset FDAC
CDAC (5bit) OFFSET BINARY FORMAT
FDAC (11 bit) OFFSET BINARY FORMAT
Offset Voltage
Offset Voltage
Offset Voltage
(mV)
Hex.
Dec.
Hex.
Dec.
(mV)
(mV)
+280
+18.67
0
1F
11
10
0F
1
+15
+1
7FF
401
400
3FF
0
+1023
+1
110
0.108
0
59.5
0.058
0
0
0
–1
–18.67
–280
–280
–1
–0.108
–110
–110
–0.058
–59.5
–59.5
–15
–16
–1023
–1024
0
0
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Table 2. CDAC Step Sizes
CDS/SH+PGA Gain
CDAC LSB
ADC LSB
16
1x
1
1
1
10x
20x
159
317
Table 3. FDAC Step Sizes
FDAC Range
CDS/SH+PGA Gain
FDAC LSB
ADC LSB
1x
1x
1x
2x
2x
2x
1x
1
1
1
1
1
1
1 / 20
1 / 2
1
10x
20x
1x
1 / 11
0.91
1.8
10x
20x
7.3.6 Black Level Calibration (Offset)
Black level correction may be performed through one of two available methods: automatic or manual.
7.3.6.1 Manual Offset Adjustment
The manual method is intended for use with processing systems where the desired black level correction loop is
external to the LM98620. In this mode the external processor controls the Black Level Offset registers.
Offset adjustment should be done using the average data from multiple Black pixels. The offset will be adjusted
to set the Black pixel data as close as possible to the desired target value.
First the CDAC is adjusted until the error is reduced as much as possible given the CDAC step size for the
current channel gain. (1 CDAC lsb = (16 to 320) ADC lsb depending on gain). Once the error is minimized with
the CDAC, the FDAC is used to further converge the Black pixel data towards the target value.
After changing the channel gain, it may be desirable to repeat the offset adjustment.
7.3.6.2 Automatic Offset Adjustment
Note: During Automatic Offset Adjustment, the CDAC and FDAC register settings are Read Only.
During automatic black level calibration, the CDAC (coarse analog offset DAC) is used to bring the black level as
close to the target as possible given the CDAC resolution.
Then the FDAC (Fine analog offset DAC) is applied to further converge the output to the desired black level
target.
Two basic modes are available.
•
•
CDAC and FDAC enabled – Used to converge to accurate Black target level as quickly as possible.
FDAC Only mode – Used to maintain Black target level while avoiding large changes to offset. In FDAC only
mode, the CDAC value is fixed, and the automatic adjustments only affect the FDAC.
CDAC and FDAC mode should be used to set the gain after power up and between scanning operations. FDAC
Only mode should be used during scanning, to prevent large changes in offset from occurring in the image data.
Use of the automatic mode involves enabling the black level offset auto-calibration bit in the black level clamp
control register through the serial interface.
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The ADC output value is averaged over the programmed number of pixels and subtracted from the desired black
level code stored in the target black level register. The result of the subtraction may then be integrated by a
preset scaling factor, effectively smoothing any sharp transitions present in the black level signal, before the
resulting calculated offset is finally applied. The offset integration scaling factor is stored in the black level loop
control register. The integration scaling values range from offset/2 to offset/128.
High Speed mode can be enabled to provide rapid initial convergence, with slower, more accurate convergence
to the target value. High Speed mode is enabled by setting Register 0x23, Bit 1 = 1. The High Speed Mode
offset integration value is set at Register 0x23, Bit 4. Two other parameters control the regions of operation
around the target black value. The High Speed Mode Threshold and Hysteresis registers control the points
where the transition from High Speed Mode to normal mode is made. When operating in High Speed Mode, the
chip will transition to normal mode when Black Error < High Speed Threshold. When operating in Normal Mode,
the chip will transition to High Speed Mode when Black Error > (High Speed Threshold + Hysteresis).
In automatic mode, the black level is determined from the ADC output during the Optical Black Pixels. The
BLKCLP input pin is used to identify when the black pixels are being input to the IC. The rising edge of the
BLKCLP input signal signals the beginning of the Optical Black Pixels. Alternatively, the Auto BLKCLP Pulse
Generation (Register 0x23h, Bit 3) can be set to 1 to generate this signal internally. In that case, the BLKCLP
pulse will begin 16 (6 channel mode) or 10 (3 channel mode) pixels after the falling edge of the CLPIN signal.
Regardless of the source providing the BLKCLP start signal, the BLKCLP pulse duration is controlled by the Pixel
Averaging setting in the BLKCLP_CTRL Register (0x24h, Bits 5:3).
NOTE: tBLKCLP is controlled by BLKCLP_CTRL Register (0x24h, Bits 7:3)
Figure 24. Manual BLKCLP Example
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Valid Pixels
Valid Pixels
Optical Black Pixels
Dummy Pixels
OSR1/2
OSG1/2
OSB1/2
t
C_B
CLPIN
input
CLPIN
internal
BLKCLP
internal
t
t
BLKCLP
CLPIN
MCLK
Note: tBLKCLP is controlled by BLKCLP_CTRL Register (0x24h, Bits 7:3)
Figure 25. Automatic BLKCLP Example
7.3.7 Gain Control
The PGA provides a range from 1x to 10x gain with 8 bits of resolution. The gain curve is nominally:
Gain = 283/(283-M)
where
•
M is the 8 bit gain setting value from 0 to 255.
(1)
In addition, the CDS/SH stage provides a 1x or 2x gain, giving an overall channel gain or 1x to 20x (0 dB to 26
dB).
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7.3.8 White Level Calibration (AGC - Automatic Gain Control)
10
10
OSx
SH Gain
PGA
ADC
ADC Output
8
x1 or x2
Gain Control Logic
Note: CDS/SH Gain Bit Shared
between Even/Odd Channels
Target White Level
Figure 26. White Level Calibration (AGC - Automatic Gain Control)
During Automatic Gain Adjustment, the PGA and CDS/SH gain settings are Read Only.
The white calibration loop allows the LM98620 to automatically set the gain for the desired maximum ADC
output. A digital input pin or configuration register bit is used to start the loop. This would normally be done once
per page, or as needed for the particular system design. When triggered, the loop processes the output data
during the defined white pixel range. The pixel range can be selected from a minimum of 1 pixel to a maximum of
65535 pixels. The starting pixel can be selected via the PK_DET_ST register at 0x2Ah, 0x2Bh and is referred to
the rising edge of either the CLPIN or BLKCLP signal. The number of pixels is selected by the PK_DET_WID
register at 0x2Ch, 0x2Dh.
During processing, a moving window average is performed. The size of the window is set by the PK_AVE
register at 0x29, Bits 2:0. The window size is adjustable from 1 (no averaging) to 32 pixels. As each window
average is calculated, the value is compared to the previous Peak White value (at the start of the line, the initial
Peak White value is set to 0). If the new average is larger than the previous Peak White value, the Peak White
value is replaced with the new average value. The window position is then incremented by 1 pixel and the
process is repeated until the window average has processed all PK_DET_WID pixels.
If the AGC_ONB input is pulsed, the white calibration loop will operate for a fixed number of lines at the
beginning of the scan. This duration is selected via the AGCDuration register at 0x2Eh Valid settings are from 1
to 255 decimal. A duration setting of 0 will cause the loop to not run.
Figure 27. White Calibration Using AGC_ONB
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When the AGC_ONB input is pulsed, the register bit AGC_ON is set. The AGC_ON bit is cleared when the loop
is terminated, which is when the number of lines allocated for the loop are exhausted. The AGC_ONB pin should
be asserted for minimum of two pixels and should be deasserted before the loop is complete and the AGC_ON
register bit is cleared.
Register 0x01, Bit 5 selects the polarity of the AGC_ONB input. The default is 0 for active low.
When the AGC loop begins operation, the AGC STATUS at Register 0x33, will be automatically cleared (as long
as the serial interface mode bit at Register 0x01, Bit 3 is set to 1, MCLK present). At the end of the AGC loop
operation, the AGC STATUS register can be read to check that the loop successfully converged for all channels.
The status value should be 0x00 to indicate no Convergence Errors.
While the AGC loop is operating, a timing source is needed to provide a consistent reference point at the
beginning of each line of pixels. Register 0x28, Bit 5 is used to select either the CLPIN or BLKCLP as the timing
source. If Bit 5 = 0, the timing reference is the rising edge of CLPIN. If Bit 5 = 1, the timing reference is the rising
edge of BLKCLP. The register setting PK_DET_ST selects the number of pixel after this timing reference that
pixel averaging begins. The register setting PK_DET_WID selects the number of pixels after PK_DET_ST that
are processed.
The purpose of the white loop is to find the correct gain setting so the brightest white pixels are at a specific ADC
code target. The target value is set in the AGCTargetMSB and AGCTargetLSB registers. The target value is
calculated from the register value as shown:
AGC_TARG = 512d + (AGCTargetMSB[7:0]+AGCTargetLSB[7])
Table 4. White Loop Register Initialization
AGCTargetMSB
(REGISTER 0x2F)
AGCTargetLSB
(REGISTER 0x30)
AGC_TARG
BINARY
AGC_TARG
DECIMAL
11111111
11111111
10000000
10000000
00000000
00000000
1
0
1
0
1
0
1111111111
1111111110
1100000001
1100000000
1000000001
1000000000
1023
1022
769
768
513
512
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7.4 Device Functional Modes
7.4.1 AFEPHASEn Details for SHP/SHD Input Mode
The SHP (sample reference) and SHD (sample signal) inputs are combined with the selected AFEPHASEn
signal to generate the internal CLAMP and SAMPLE signals respectively. The SHP signal is ANDed with
AFEPHASEn. The SHD signal is ANDed with the inverted AFEPHASEn signal.
The best performance will be achieved by selecting the AFEPHASEn timing that has the high period completely
overlapping the SHP input timing, and the low period completely overlapping the SHD timing.
7.4.2 AFEPHASEn Details for SAMPLE and HOLD Input Mode
In Sample/Hold mode, the SAMPLE and HOLD inputs are used. The rising edge of SAMPLE defines the start of
the sample control pulse, and the rising edge of HOLD defines the end of the sample control pulse. This sample
control pulse is then gated by the low period of the AFEPHASEn signal to generate the resulting SAMPLE signal
used internally.
The AFEPHASEn signal which has the low period completely overlapping the sample control pulse will give the
best performance.
7.4.3 AFEPHASEn: 6 Channel and 3 Channel Modes
In 6 Channel Mode, there are two full cycles of ADCCLK for each sensor pixel period. This allows the two AFE
channels to be multiplexed into the single ADC. In this mode, there are 4 possible AFEPHASEn timings
available.
In 3 Channel Mode, there is only one cycle of MCLK and ADCCLK per pixel period. Because of this, there are
only 2 choices for AFEPHASEn, as shown in the following diagrams.
7.4.4 LM98620 AFEPHASE Synchronization
There are three main modes of operation for the LM98620
1. 6 channel mode using ADC Rate MCLK – Clock Doubler is bypassed
2. 6 channel mode using Pixel Rate MCLK – Clock Doubler is used
3. 3 channel mode using Pixel Rate MCLK – Clock Doubler is bypassed
In case #1, where an ADC rate (2x of pixel rate) clock is input, the LM98620 needs one additional signal to
ensure synchronization between the internal sampling phases and the pixel rate input signal.
This synchronization is done using the CLPIN input signal in combination with MCLK. The CLPIN input generates
an internal reset signal that sets the internal AFEPHASE state machine into a known relationship with MCLK and
CLPIN. This ensures the AFEPHASE sampling is synchronized to the host sensor timing.
The following diagrams indicate the phase relationship between MCLK and AFEPHASE when CLPIN is used for
synchronization:
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Device Functional Modes (continued)
T
(Note 1)
Typical
CCD Out
MCLK
mclk_int
(Notes 6,7)
CLPIN
4.5 MCLK
AFEPHASE
= 0,0
AFEPHASE
= 0,1
AFEPHASE
= 1,0
AFEPHASE
= 1,1
6.0 MCLK
(Note 2)
SAMPLE
Sample timing for
AFEPHASE = 1,1
HOLD
(Notes 3,4,5)
1) T = MCLK Period = 1/2 Pixel Period
2) Rising edge of SAMPLE must be at least 8 ns before rising edge of HOLD
3) Rising edge of HOLD can be up to tMCH after rising edge of MCLK (AFEPHASE = 1,1)
4) In SH1a,SH1b modes, the rising edge of HOLD can be up to tHMC before the rising edge of MCLK (AFEPHASE = 1,1)
5) In SH2 mode, HOLD can be up to tHMC ns before the rising edge of MCLK (AFEPHASE=1,1)
6) CLPIN must be high or low for at least 2 input MCLK cycles
7) CLPIN is latched by the rising or falling edge of MCLK selectable by Register 0x04h, Bit 5.
Figure 28. 6 Channel Mode – ADC Rate MCLK
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Device Functional Modes (continued)
T
Note 1
Typical
CCD Out
MCLK
mclk_int
CLPIN
(Notes 6,7)
2.75 MCLK
AFEPHASE
= 0,0
AFEPHASE
= 0,1
AFEPHASE
= 1,0
AFEPHASE
= 1,1
3.5 MCLK
SAMPLE
Note 2
Sample timing for
AFEPHASE = 1,1
HOLD
Notes 3,4,5
1) T = MCLK Period = Pixel Period
2) Rising edge of SAMPLE must be at least 8 ns before rising edge of HOLD
3) Rising edge of HOLD can be up to tMCH after falling edge of MCLK (AFEPHASE = 1,1)
4) In SH1a,SH1b modes, the rising edge of HOLD can be up to tHMC before the falling edge of MCLK (AFEPHASE = 1,1)
5) In SH2 mode, HOLD can be up to tHMC before the rising edge of MCLK (AFEPHASE=1,1)
6) CLPIN must be high or low for at least 2 input MCLK cycles
7) CLPIN is latched by the rising or falling edge of MCLK selectable by Register 0x04h, Bit 5.
Figure 29. 6 Channel Mode – Pixel Rate MCLK
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Device Functional Modes (continued)
T
Note 1
Typical
CCD Out
MCLK
CLPIN
(Notes 6,7)
3.5 MCLK
AFEPHASE
= X,0
AFEPHASE
= X,1
4.0 MCLK
SAMPLE
Sample timing for
Note 2
AFEPHASE =
X,1
HOLD
Notes 3,4,5
1) T = MCLK Period = Pixel Period
2) Rising edge of SAMPLE must be at least 8 ns before rising edge of HOLD
3) Rising edge of HOLD can be up to tMCH after falling edge of MCLK (AFEPHASE = 1,1)
4) In SH1a,SH1b modes, the rising edge of HOLD can be up to tHMC before the falling edge of MCLK (AFEPHASE = 1,1)
5) In SH2 mode, HOLD can be up to tHMC before the rising edge of MCLK (AFEPHASE=1,1)
6) CLPIN must be high or low for at least 2 input MCLK cycles
7) CLPIN is latched by the rising or falling edge of MCLK selectable by Register 0x04h, Bit 5.
Figure 30. 3 Channel Mode – Pixel = ADC Rate MCLK
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7.5 Programming
7.5.1 Using Black Pixel Average
In most applications, the Black Pixel Average bit should be set.
During loop operation, the ADC_MAX or average maximum ADC value is found during the white pixels. The
Black Pixel Average value is then subtracted from this ADC_MAX value to find the present white value. This
ADC_WHT value is then used for comparison to the target white pixel value TARG_WHT. This is done to
eliminate the effects that changes in the system gain will have on the Black Pixel Average value. As gain is
increased or decreased, the previously calibrated Black Pixel Average value will change also. When the white
loop operation is complete, the gain is set to provide the proper white level referenced to the Black Pixel Average
value. Then the Black Loop will be run once more to set the Black Pixel Average at the desired level, and the
White level will still be calibrated to the proper level.
In addition, the following registers should be initialized before starting the loop:
Table 5. White Loop Register Initialization
REGISTER
PK_DET_ST (0x2Ah, 0x2Bh)
PK_DET_WID (0x2Ch, 0x2Dh)
FUNCTION
Start of the white pixel averaging in pixels from rising edge of CLPIN or BLKCLP
Number of pixels in each line over which white pixels are averaged
Duration in number of lines the loop should run. If set to 0, the loop will not run. Valid
settings are 1 to 255.
AGCDuration (0x2Eh)
AGCTarget (0x2Fh, 0x30h)
AGCTolerance (0x31h)
AGC_BLKINT (0x32h)
AGC target, between 512 to 1023
Allowed error margin from the target value
Black Offset Integration, if used
Select reference edge CLPIN or BLKCLP rising edge, Enable/Disable
AGC_ONB Pin, Incremental Search Enable, Black Offset Enable
AGC_CONFIG (0x28h)
After all registers are initialized, the AGC_ON bit (0x28h, b0) can be set, or the AGC_ONB pin can be pulsed to
start the white loop.
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7.5.2 Sample Timing Control
Sample timing is controlled through the combination of the selected internal AFEPHASEn signal, and
programmed internal sample timing signals. Optionally, external sampling timing signals can be applied on the
SAMPLE/SHP and HOLD/SHD input pins.
The different input timing modes are selected by bits in Registers 0x00, 0x02, 0x04 and 0x05 as shown in
Table 6. Settings other than those shown are not valid:
Table 6. Input Timing Modes
REG
0x05[7]
REG
0x04[1]
REG
0x02[7]
REG
0x02[3:2]
REG
0x02[1]
REG
0x00[0]
MODE
DESCRIPTION
SH3
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
Sample and Hold mode, clocked
by SAMPLE and HOLD clocks(2)
SH2a
Sample and Hold mode, clocked
(3)
by SAMPLE and HOLD clocks
SH2b
(Default)
Sample and Hold mode,
clocked by DLL(3)
SH1a
SH1b
CDSa
CDSb
Sample and Hold mode, clocked
by AFEPHASE(3)
(1)
(See
)
Sample and Hold mode, clocked
by SHD(3)
CDS mode, sampled by
AFEPHASE(3)
CDS mode, sampled by SHP and
SHD clocks(3)
(1) AFEPHASE bits should be set to “11” in SH3 mode
(2) AFEPHASE is automatically set by the HOLD input timing
(3) AFEPHASE synchronizes with CLPIN input
7.5.3 DLL Based Sample Timing Settings
The internal DLL settings determine the position of internally generated sampling pulses. These pulses can only
be used for the SH2b timing mode. The register bits to select sampling modes are shown in Table 6.
Once SH2b mode is selected, the sample timing settings can be set. The timing settings consist of the following:
AFEPHASE – Register 0x02, Bits 3:2 – This sets the coarse sample timing framework with respect to the input
MCLK. In 6 channel modes, there are 4 possible AFEPHASE settings. Each setting is offset from the adjacent
ones by ¼ pixel period.
MCLK
AFEPHASE-00
AFEPHASE-01
AFEPHASE-10
AFEPHASE-11
Figure 31. 4 AFEPHASE Selections – Coarse Sample Timing Adjust – (Pixel Rate MCLK Shown)
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Sample Trailing Edge Position – Register 0x36, Bits 4:0
This sets the end of the sampling pulse. There are 32 DLL settings within one AFEPHASE cycle or pixel period.
The five bit values that correspond to these 32 settings as shown below:
*(Please note that the 5 bit digital code sequence has changed from that of sample silicon versions.
Initial version had the MSbit inverted from a normal sequence. A0 silicon has a normal sequence from
00000 to 11111)
•
•
•
•
•
•
•
00000: delay 0/32 of Tpixel from Pixel Clock
00001: delay 1/32 of Tpixel from Pixel Clock
…
01111: delay 15/32 of Tpixel from Pixel Clock
10000: delay 16/32 of Tpixel from Pixel Clock
…
11111: delay 31/32 of Tpixel from Pixel Clock
AFEPHASE
0
1516
31
Sample Trailing Edge Setting
Register 0x36, Bits 4:0
Internal Sample
Pulse
Sample Width Setting
Register 0x37, Bits 7:5
t
SHD MIN
TESTO_0
SH Sample
(Active High)
Delayed from internal
SH Sample Pulse
t
SHD MIN
Figure 32. 32 Possible Settings Within AFEPHASE Period
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7.5.4 Allowed Range of Sample Trailing Edge Settings (Typical)
NOTE: The 5 bit digital code sequence has changed from that of sample silicon versions
Table 7. Sample Trailing Edge Settings
REGISTER 0x36, Bits 4:0
FADCCLK
70 MHz
20 MHz
*MIN
12
*MAX
25
4
29
Sample Width – Register 0x37, Bits 7:5
This selects the width of the Sampling pulse. To achieve rated performance, this parameter must be set to give a
minimum of 8 ns width. The proper value can be calculated based on the operating frequency as follows:
Tbit = 1/32 x Tpixel
Min Width Setting = 8ns / Tbit
Min Width Setting = 8ns / (Tpixel/32) = 256 ns / Tpixel ns (rounded up to next even value)
Table 8. Minimum Width Settings
Fpixel (MHz)
Tpixel (ns)
100
MIN WIDTH SETTING
REGISTER 0x37, BITS 7:5
10
15
20
25
30
35
40
4
4
1
1
66.7
50
6
10
11
11
100
101
40
8
33.3
28.6
25
8
10
12
7.5.5 External Sample Timing Inputs
In modes SH1a and CDSa, the internal Sample or Clamp and Sample timing signals are generated from the
selected AFEPHASEn signal.
In modes SH1b and CDSb, the input SHD or SHD and SHP signals are ‘gated’ by the internal AFEPHASEn
signal to create the internal Sample and Clamp signals.
In mode SH2, the SAMPLE and HOLD timing signals are directly input to the sampling stage of the AFE.
Subsequent stages are still clocked by the selected AFEPHASEn and MCLK.
In mode SH3, the SAMPLE and HOLD timing signals are directly input to the sampling stage of the AFE, and are
also used to set the internal AFEPHASE timing for subsequent stages. In this mode, CLPIN is not required
to set the AFEPHASE timing.
Please refer to the following timing diagrams to see the recommended relationship between the sample timing
inputs and the internal AFEPHASEn signal.
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7.5.6 Test Mode Outputs
In test mode, the internal CLAMP and SAMPLE (CDS Mode) or SAMPLE (S/H Mode) timing signals are output
on the TESTO_0 and TESTO_1 pins. This enables easy confirmation of the actual internal timing configuration.
The TESTO pins are enabled by setting Register 0x00h, Bit 1, = 1. Otherwise these outputs are Tristate.
Table 9 describes the signals present on the TESTO_0 and TESTO_1 outputs in the different timing modes:
Table 9. Test Mode Outputs
SAMPLE MODE
SH2a, SH2b, SH3
SH1a, SH1b
TESTO_0
TESTO_1
SH Sample Signal
SH Sample Signal
Sample Signal Level
PGA SampleB (active low)
SH Sample Signal
CDSa, CDSb
Sample Reference Level
7.5.7 LVDS Data Output
AFE data is output on a serialized LVDS interface. Several different serializing modes are available, with 5 or 6
pairs used for data transfer.
6 pair modes allow the use of the standard, DS90CR218A, or DS90CR364 deserializer ICs.
5 pair modes permit usage with a single 5 channel deserializer. In this mode, the unused data pair can be left
open circuit to minimize power consumption and component cost. Also, to maximize layout flexibility, both
TXCLK pairs are active. The unused TXCLK pair can be left open circuit to again minimize power consumption.
7.5.8 LVDS Serialization
Pixel N-1
Pixel N
Pixel N+1
TX6
TX6
TX6
TX6
TX6
TX6
TX5
TX5
TX5
TX5
TX5
TX5
TX3
TX2
TX2
TX2
TX2
TX2
TX2
TX1
TX1
TX1
TX1
TX1
TX1
TX0
TX0
TX0
TX0
TX0
TX0
TX4
TX4
TX4
TX4
TX4
TX4
TXOUTA1
TXOUTB1
TXOUTC1
TXOUTA2
TXOUTB2
TXOUTC2
TXCLK+
TX3
TX3
TX3
TX3
TX3
Figure 33. LVDS Serialization
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Tx0
Table 10. Bit Formats
BIT
Tx6
Tx5
Tx4
Tx3
Tx2
Tx1
FORMAT 1 R-G-B
TXOUTA1+/-
TXOUTB1+/-
TXOUTC1+/-
TXOUTA2+/-
TXOUTB2+/-
TXOUTC2+/-
0
0
0
0
0
0
0
R[4]
R[5]
GPI[2]
B[4]
R[6]
GPI[3]
B[5]
R[7]
R[0]
B[6]
G[9]
G[2]
R[8]
R[1]
B[7]
B[0]
G[3]
R[9]
r[2]
GPI[5]
R[3]
B[9]
GPI[1]
B[3]
B[8]
B[1]
G[4]
G[6]
G[7]
G[0]
G[8]
G[1]
B[2]
GPI[4]
G[5]
TXCLK1+/-
TXCLK2+/-
1
1
0
0
0
1
1
FORMAT 1 B-G-R
TXOUTA1+/-
TXOUTB1+/-
TXOUTC1+/-
TXOUTA2+/-
TXOUTB2+/-
TXOUTC2+/-
TXCLK1+/- TXCLK2+/-
FORMAT 2a R-G-B
TXOUTA1+/-
TXOUTB1+/-
TXOUTC1+/-
TXOUTA2+/-
TXOUTB2+/-
TXOUTC2+/-
TXCLK1+/-
This mode swaps the Red Color and Blue Color data bits.
0
0
B[5]
GPI[2]
R[4]
G[7]
G[0]
1
0
B[6]
GPI[3]
R[5]
G[8]
G[1]
0
0
0
0
0
GPI[5]
B[3]
R[9]
R[2]
G[5]
1
B[4]
GPI[1]
R[3]
G[6]
GPI[4]
1
B[7]
B[0]
R[6]
G[9]
G[2]
0
B[8]
B[1]
R[7]
R[0]
G[3]
0
B[9]
B[2]
R[8]
R[1]
G[4]
1
0
0
0
0
0
0
0
R[3]
GPI[5]
G[5]
B[2]
R[2]
R[9]
G[4]
B[1]
B[8]
R[1]
R[8]
G[3]
B[0]
B[7]
R[0]
R[7]
G[2]
G[9]
B[6]
GPI[1]
R[6]
G[1]
G[8]
B[5]
GPI[2]
R[5]
G[0]
G[7]
B[4]
GPI[3]
R[4]
GPI[4]
G[6]
B[9]
B[3]
1
1
0
0
0
1
1
TXCLK2+/-
FORMAT 2a B-G-R
TXOUTA1+/-
TXOUTB1+/-
TXOUTC1+/-
TXOUTA2+/-
TXOUTB2+/-
TXOUTC2+/-
This mode swaps the Red Color and Blue Color data bits.
0
0
0
0
0
0
0
B[3]
B[2]
B[9]
G[4]
R[1]
R[8]
B[1]
B[8]
G[3]
R[0]
R[7]
B[0]
B[7]
G[2]
R[9]
R[6]
GPI[1]
B[6]
GPI[2]
B[5]
GPI[3]
B[4]
GPI[5]
G[5]
R[2]
R[9]
G[1]
G[8]
R[5]
G[0]
G[7]
R[4]
GPI[4]
G[6]
R[3]
TXCLK1+/-
TXCLK2+/-
1
1
0
0
0
1
1
FORMAT 2b R-G-B
TXOUTA1+/-
TXOUTB1+/-
TXOUTC1+/-
TXOUTA2+/-
TXOUTB2+/-
TXOUTC2+/-
R[3]
1
R[4]
1
R[5]
1
R[6]
GPI[1]
GPI[5]
B[6]
R[7]
R[0]
R[8]
R[1]
R[9]
R[2]
1
1
1
GPI[4]
B[7]
GPI[3]
B[8]
GPI[2]
B[9]
B[3]
G[6]
GPI[1]
B[4]
G[7]
G[0]
B[5]
G[8]
G[1]
G[9]
B[0]
B[1]
B[2]
G[2]
G[3]
G[4]
G[5]
TXCLK1+/-
TXCLK2+/-
1
1
0
0
0
1
1
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Table 10. Bit Formats (continued)
BIT
Tx6
Tx5
Tx4
Tx3
Tx2
Tx1
Tx0
FORMAT 2b B-G-R
TXOUTA1+/-
TXOUTB1+/-
TXOUTC1+/-
TXOUTA2+/-
TXOUTB2+/-
TXOUTC2+/-
TXCLK1+/- TXCLK2+/-
This mode swaps the Red Color and Blue Color data bits.
B[3]
1
B[4]
1
B[5]
1
B[6]
GPI[1]
GPI[5]
R[6]
B[7]
B[0]
GPI[4]
R[7]
R[0]
G[3]
0
B[8]
B[1]
GPI[3]
R[8]
R[1]
G[4]
1
B[9]
B[2]
GPI[2]
R[9]
R[2]
G[5]
1
1
1
1
R[3]
G[6]
GPI[1]
1
R[4]
G[7]
G[0]
1
R[5]
G[8]
G[1]
0
G[9]
G[2]
0
7.5.9 Output Data Test Pattern Generation
Special test patterns will be generated to help in testing data processing. Four basic types of waveform can be
generated and they are:
•
•
•
•
Fixed Pattern
Horizontal Gradiation Pattern
Vertical Gradiation Pattern (sub-scan)
Lattice Pattern
By varying the parameters, waveforms of different timing and amplitude can be created. Parameters for the test
patterns are programmable and the following registers are defined:
PK_DET_ST:
This register defines the start of the Valid Pixel region from the rising edge of CLPIN or
BLKCLP, in Pixels.
*PK_DET_ST = REG_PK_DET_ST + 6, or the register setting value plus 6.
PK_DET_WID:
PATSW:
This register defines the duration (pixels) of the Valid Pixel region.
Enable/Disable test pattern output.
Sets which test pattern mode is used
00 = Fixed code
PATMODE:
01 = Horizontal Gradiation
10 = Vertical Gradiation
11 = Lattice
PATREGSEL:
Test pattern can be initiated on a single color or all three colors at the same time. When
only one color is selected, the other colors are set to maximum 1023 code.
00 = All colors
01 = Red
10 = Green
11 = Blue
TESTPLVL:
Output code 0 to 1023. In Fixed Pattern it is code output during the Valid Pixel range.
During Horizontal Gradation and Vertical Gradation it is used as the initial code. In
Lattice Pattern it is the level during the Valid Pixel range except for the first pixel every
PATW pixels in the horizontal range and for first line every PATW lines.
PATW:
PATS:
Gradation pitch, this is interval at which the pattern Code Step provided in PATS register
is applied.
Pattern Code Step, this contains the code step increment applied every PATW interval.
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LINE_INT:
Test pattern output delay. This defines the delays in number of lines between Red to
Green and Green to Blue. This sequence is fixed, R->G->B, and when this register is 0,
all colors switch simultaneously. This delay is used only on the initial start and the
sequence of colors is fixed.
7.5.9.1 Fixed Pattern
Outputs fixed code in the TESTPLVL register during Valid Pixel range.
7.5.9.2 Horizontal Gradation
Code in the TESTPLVL is outputted initially in the PATW pixels of the Valid Pixel region, and then code is
incremented by PATS value every PATW pixels for the rest of the active region. If the code reaches the
maximum (less than or equal to 1023), it is reset to the initial value in TESTPLVL and pattern repeated. Same
sequence is repeated for the all the lines.
7.5.9.3 Vertical Gradation
Code in the TESTPLVL is outputted initially in the first PATW lines of the scan and fixed for all of the Valid Pixel
region, and then the code is incremented by PATS value every PATW lines and the new code is applied during
active region till the next increment. This is repeated till code reaches the maximum (less than or equal to 1023)
then the code is reset to the initial value and the sequence repeated.
7.5.9.4 Lattice Pattern
This is combination of Horizontal and Vertical Gradation pattern. Here the register PATW defines interval in
pixels for horizontal scan and in lines for the vertical scan. At start of the test the output is set to PATS level for
the whole first line and every line at PATW interval. In rest of the lines of the output goes to PATS for the first
pixel then goes TESTPLVL for PATW-1 pixels, then goes back to PATS for one pixel and then to TESTPLVL for
PATW-1 pixels, the cycle repeats till the end of line.
All test pattern generation continues once initiated by setting of PATSW till it is reset.
CLPIN/BLKLP
MCLK
TESTPLVL
ADC_OUT
0x000
PK_DET_ST
PK_DET_WID
PK__DET_ST
PK_DET_WID
TESTPLVL = Start Code
PK_DET_ST = Start of Pixel Area in # of Pixels
PK_DET_WID = Pixel Area Width in # of Pixels
FIXED TEST PATTERN
Figure 34. Fixed Test Pattern
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CLPIN/BLKLP
PATW
PATS
TESTPLVL
ADC_OUT
0x000
PK_DET_ST
PK_DET_WID
PK_DET_ST
PK_DET_WID
TESTPLVL = Start Code
PK_DET_ST = Start of Pixel Area in # of Pixels
PK_DET_WID = Pixel Area Width in # of Pixels
PATS = Pattern Step in Codes
PATW = Pattern Pitch in # of pixels
GRADATION (main scan) PATTERN
Figure 35. Gradiation (Main Scan) Pattern
CLPIN/BLKLP
PATW
PATW
PATS
PATS
TESTPLVL
0x000
ADC_OUT
PK_DET_ST
PK_DET_WID
TESTPLVL = Start Code
PK_DET_ST = Start of Pixel Area in # of Pixels
PK_DET_WID = Pixel Area Width in # of Pixels
PATW = Pattern Pitch in # of Lines
PATS = Pattern Step in # of Codes
GRADATION (sub scan) TEST PATTERN
Figure 36. Gradiation (Sub Scan) Pattern
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CLPIN/BLKLP
TESTPLVL
PATS
ADC_OUT
0x000
Valid Pixel Area
PATW
PK_DET_ST
PK_DET_WID
1 pixel
CLPIN/BLKLP
PK_DET_ST
Valid Pixel Area
Valid Pixel Area
Valid Pixel Area
PK_DET_WID
PATS
ADC_OUT
0x000
PATW in Lines
TESTPLVL = All of Valid Pixel area except where PATS is defined
PK_DET_ST = Start of Valid Pixel Area in # of Pixels
PK_DET_WID = Valid Pixel Area Duration in # of Pixels
LATTICE PATTERN
PATW = Pattern Pitch in # of pixels for the ma in scan, and in # of lines for the sub-scan
PATS = Pattern Step in # of Codes. Asserted for 1 pixel every PATW pixels in main scan
For 1 line every PATW lines during sub-scan
Figure 37. Lattice Pattern
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7.5.9.5 Serial Interface
The serial control interface is based on the common Microwire interface with a few specific timing details, as
shown below. Bits A5, A4, A3, A2, A1, A0 select the configuration register currently being written to or read
within the flat register space.
NOTE
After the device is powered up and a stable MCLK in the range of FMCLK Min to Max is
applied, the Serial Interface Mode (Register 0x01, Bit 3) must be set to 1 for Normal
Operation.
7.5.9.6 Serial Write
t
SENW
t
SCSEN
t
SENSC
tW
t
t
CP
W
SENB
SCLK
X
X
X
t
IH
t
IS
SDI
X
0
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
X
0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDO
HiZ
Figure 38. Serial Write
•
•
•
•
•
•
•
•
The positive edge of SCLK is used to receive data on SDI.
Last 15 bits of data before SEN toggled high will be loaded into AFE.
A command whose length is less than 15 bits will be discarded.
SDO will be Hi-Z during write operation.
At the second cycle shown above, either read or write command is possible.
The MODE bit must be “0” when writing to registers.
A Write command consists of one MODE bit, 6 address bits and 8 data bits.
While SEN is high, the AFE will accept either high or low with respect to SCLK and SDI.
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7.5.9.7 Serial Read
t
SENW
t
SENSC
t
SCSEN
t
t
W
CP
t
W
SENB
SCLK
X
X
t
IH
t
IS
SDI
X
1
A5 A4 A3 A2 A1 A0
X
1
A5 A4 A3 A2 A1 A0
X
SDO
D7 D6 D5 D4 D3 D2 D1 D0
t
OD
Figure 39. Serial Read
•
•
•
•
•
•
•
•
•
•
The positive edge of SCLK is used to receive data on SDI.
Last 15 bits of data before SEN goes high will be loaded.
Command whose length is less than 15 bits will be discarded.
Readout data will appear on SDO at the second cycle above.
The readout data is clocked at the positive edge of SCLK.
SDO is Hi-Z except when read out data appears on SDO.
At the second cycle shown above, either read or write command is possible.
The MODE bit must be “1” when reading from registers.
A Read command will contain one MODE bit, 6 address bits and 8 dummy data bits which are ignored.
While SEN is high, the AFE will accept either high or low with respect to SCLK and SDI.
7.6 Register Maps
Table 11. Configuration Registers Summary Table
HEX ADDRESS
(A5-A0)
REGISTER
NAME
COMMENTS
0x00 to 0x06
0x07
Configuration 0 – 6
Configuration settings
Device Revision
GA_R1
0x08
0x09
C_OFFS_R1
OS_R1 (Red Even) Channel Gain & Offset Registers (CDS / SH Gain is
NOT located here)
0x0A
F_OFFS_R1_MSB
F_OFFS_R1_LSB
GA_R2
0x0B
0x0C
0x0D
C_OFFS_R2
OS_R2 (Red Odd) Channel Gain & Offset Registers
0x0E
F_OFFS_R2_MSB
F_OFFS_R2_LSB
0x0F
0x10 to 0x13
0x14 to 0x17
0x18 to 0x1B
0x1C to 0x1F
0x20
OS_G1 (Green Even) Channel Gain & Offset Registers
OS_G2 (Green Odd) Channel Gain & Offset Registers
OS_B1 (Blue Even) Channel Gain & Offset Registers
OS_B2 (Blue Odd) Channel Gain & Offset Registers
TARG_BLK_R
TARG_BLK_G
TARG_BLK_B
0x21
0x22
0x23
Black Level Loop Control
0x24
Black Level Loop Settings
CDAC Threshold for BLK LP MSB
CDAC Threshold for BLK LP LSB
Black Loop Fast Mode
0x25
0x25
0x27
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Register Maps (continued)
Table 11. Configuration Registers Summary Table (continued)
HEX ADDRESS
(A5-A0)
REGISTER
NAME
COMMENTS
0x28
White Level Loop Control
0x29
PK_AVG
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
REG_PK_DET_ST_MSB
REG_PK_DET_ST_LSB
PK_DET_WID_MSB
PK_DET_WID_LSB
AGCDuration
AGCTargetMSB
AGCTargetLSB
AGCTolerance
AGC_BLKINT
AGC STATUS
TBD
0x31
0x32
0x33
0x34 to 0x37
0x38
Test Pattern Mode
Test Pattern Settings 1
Test Pattern Settings 2
PATW
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
PATS
LINE_INTVL
Reserved
Reserved
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Table 12. Configuration Registers Details
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x00 - 0x07 CONFIGURATION REGISTERS
0x00
ANLG_CONFG
0x2C
Main Configuration
[7] = Active Input Bias (AIB) - Used for initial DC biasing of OS inputs. Disabled
during image capture.
• (0:Disabled, 1:OSx connected to VREF_EXT during input clamping)
[6] = Passive Input Bias (PIB) - Used for initial DC biasing of OS inputs. Disabled
during image capture.
• (0:Disabled, 1:Osx connected to Vdd/2 resistor ladder during input clamping)
[5] = Source Follower Enable - Used to provide higher impedance at OS inputs.
Should be enabled for most applications.
• (0:Disabled, 1:Enabled)
[4] = Analog Power Down
• (0:Normal, 1:Powered Down)
[3] = Input Mode Select
• (0:3-channel; 1:6-channel)
• In 3-ch mode, OSR1, OSG1, OSB1 inputs are used.
[2] = VCLP Internal Buffer Disable
• (0:Enable VCLP Buffer, 1:Disable VCLP Buffer)
[1] = Sample Timing Pulses routed to TESTO outputs
• (0:Tristate, 1:Enable)
• CDSa & CDSb modes:
• SH SAMPLE Timing routed to TESTO_0
• SH CLAMP Timing routed to TESTO_1
• SH1a & SH1b modes:
• SH SAMPLE Timing routed to TESTO_0 & TESTO_1
• SH2 & SH3 modes:
• SH SAMPLE Timing routed to TESTO_0
• PGA SAMPLE Timing routed to TESTO_1
[0] = Sampling Mode Control
• See Table 6 in Sample Timing Control.
Interface Configuration
0x01
INTF_CONFG
0x04
[7:6] – Reserved
[5] = AGC_ON pin polarity
• 0 = Active LOW, 1= Active HIGH
[4] = OVP Input Protection Enable (clamp signal inputs to 1 diode drop)
• (0:*Disabled, 1:Enabled)
• *Only disabled if OVPB input pin is at logic 1.
[3] = Serial Interface Mode – Note: After the device is powered up and a stable
MCLK in the range of FMCLK Min to Max is applied, this value must be set to
1 for Normal Operation.
• (0:Startup-Default, 1:Normal Operation)
[2:1] = LVDS output format
• 00:Mode 1, 5 pair output
• 01:Mode 2a, 5 pair output
• 10:Mode 2b, 6 pair output
[0] = Red/Blue data swap
(0:normal, 1:R/B swapped)
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x02
CLP_CONFG Sample
Timing Control
0x9D
Clamp Control
[7] = Sampling Mode Control
• See Table 6 in Sample Timing Control.
[6] = SAMPLE edge selection
• (0: Rising, 1:Falling)
[5] = HOLD edge selection
• (0: Rising, 1:Falling)
[4] = SHP/SHD input polarity select
• (0:Active Low, 1:Active High)
[3:2] = AFEPHASEn setting (00 to 11)
• (Default is 11 in 6 channel mode)
• (Default is X1 in 3 channel mode) Value is 11, but upper bit is ignored in 3
channel mode.
[1] = Sampling Mode Control
• See Table 6 in Sample Timing Control.
[0] = Clamp Control
• (0:CLPIN input, 1:Clamp gated by internal sampling pulse)
FDAC Range, CDS Gain Selection
0x03
CDSG_CONFIG
0x00
CDS / SH Gain Enable
FDAC Range Select
[7] = Input Signal Polarity
• 0: Negative polarity
• 1: Positive polarity (Sample and Hold mode only)
[6] = Reserved (must be kept at the Power-on-Default value)
[5] = Blue Channel FDAC Range Select
[4] = Green Channel FDAC Range Select
[3] = Red Channel FDAC Range Select
• 0: 1 CDAC LSB = 321 FDAC LSBs (Range = ± 64 mV)
• 1: 1 CDAC LSB = 176 FDAC LSBs (Range = ±117 mV)
[2] = Blue Channels 1 & 2 Gain Enable (0:1x; 1:2.1x-typ)
[1] = Green Channels 1 & 2 Gain Enable (0:1x; 1:2.1x-typ)
[0] = Red Channels 1 & 2 Gain Enable (0:1x; 1:2.1x-typ)
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x04
Main Configuration 4
0x83
[7] = pbufen (passive buffer enable)
• 0: disable resistor divider at VCLP_ext
• 1: enable resistor divider at VCLP_ext
[6] = pd_ref
• Power down VREFT/VREFB buffer only
• 0: buffer = power up
• 1: buffer = power down
[5] = CLPIN Sampling Edge Select
• 0: sampled by the rising edge of MCLK
• 1: sampled by the falling edge of MCLK
[4] = Digital Inputs Sampling Edge Select
• 0: sampled by the rising edge of MCLK
• 1: sampled by the falling edge of MCLK
[3:2] = Clock Range Select (TXCLK and ADCCLK are the same frequency. In 6
channel mode, TXCLK and ADCCLK are 2x the pixel rate.)
• 11,10: TXCLK/ADCCLK running at 10MHz – 20MHz
• 01: TXCLK/ADCCLK running at 20MHz – 40MHz
• 00: TXCLK/ADCCLK running at 40MHz – 65MHz
[1] = Sampling Mode Control
• See Table 6 in Sample Timing Control. for details.
• 1: SH3 mode is disabled.
• 0: SH3 mode is enabled
[0] = clock doubler select
• 1: TXCLK and ADCCLK are 2x MCLK
• 0: TXCLK and ADCCLK are same freq. as MCLK
[7] = Sampling Mode
0x05
0x06
0x07
Main Configuration 5
SRESET
0xF7
0x00
0xA0
• 0: Sampling Clocks from SHP/SHD pins
• 1: Sampling Clocks from internal DLL [6:0] = Reserved (load with default
values)
Soft Reset
[1] – FSM Reset, programmable registers are not disturbed.
[0] – REG Reset, reset all FSM, except micro-wire interface, and programmable
registers
Device Revision
Read Only.
This number reflects the device revision and updated every time any major or
minor change is made to the silicon.
0x08 – 0x0F RED CHANNEL PGA GAIN, CDAC and FDAC OFFSETS
0x08
GA_R1
0x00
[7:0] = Red Channel 1 PGA Gain
• Gain = 283/(283 - [7:0])
• Gain range is from 1x to 10x
0x09
0x0A
C_OFFS_R1
F_OFFS_R1
0x10
0x80
[4:0] = Red Channel 1 Offset DAC Code
• Offset binary format
[7:0] = Red Channel 1 Fine Offset DAC code [10:3]
• Offset binary format
0x0B
0x0C
F_OFFS_R1 LSB
GA_R2
0x00
0x00
[7:5] = Red Channel 1 Fine Offset DAC code [2:0] [4:0] = Reserved
[7:0] = Red Channel 2 PGA Gain
• Gain = 283/(283 - [7:0])
• Gain range is from 1x to 10x
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x0D
0x0E
0x0F
C_OFFS_R2
0x10
0x80
0x00
[4:0] = Red Channel 2 Offset DAC Code
• Offset binary format
F_OFFS_R2
[7:0] = Red Channel 2 Fine Offset DAC code [10:3]
• Offset binary format
F_OFFS_R2 LSB
[7:5] = Red Channel 2 Fine Offset DAC code [2:0] [4:0] = Reserved
0x10 – 0x17 GREEN CHANNEL PGA GAIN, CDAC and FDAC OFFSETS
0x10
GA_G1
0x00
[7:0] = Green Channel 1 PGA Gain
• Gain = 283/(283 - [7:0])
• Gain range is from 1x to 10x
0x11
0x12
0x13
0x14
C_OFFS_G1
F_OFFS_G1
F_OFFS_G1 LSB
GA_G2
0x10
0x80
0x00
0x00
[4:0] = Green Channel 1 Offset DAC Code
• Offset binary format
[7:0] = Green Channel 1 Fine Offset DAC code [10:3]
• Offset binary format
[7:5] = Green Channel 1 Fine Offset DAC code [2:0]
[4:0] = Reserved
[7:0] = Green Channel 2 PGA Gain
• Gain = 283/(283 - [7:0])
• Gain range is from 1x to 10x
0x15
0x16
0x17
C_OFFS_G2
0x10
0x80
0x00
[4:0] = Green Channel 2 Offset DAC Code
• Offset binary format
F_OFFS_G2
[7:0] = Green Channel 2 Fine Offset DAC code [10:3]
• Offset binary format
F_OFFS_G2 LSB
[7:5] = Green Channel 2 Fine Offset DAC code [2:0] [4:0] = Reserved
0x18 – 0x1F BLUE CHANNEL PGA GAIN, CDAC and FDAC OFFSETS
0x18
GA_B1
0x00
[7:0] = Blue Channel 1 PGA Gain
• Gain = 283/(283 - [7:0])
• Gain range is from 1x to 10x
0x19
0x1A
C_OFFS_B1
F_OFFS_B1
0x10
0x80
[4:0] = Blue Channel 1 Offset DAC Code
• Offset binary format
[7:0] = Blue Channel 1 Fine Offset DAC code [10:3]
• Offset binary format
0x1B
0x1C
F_OFFS_B1 LSB
GA_B2
0x00
0x00
[7:5] = Blue Channel 1 Fine Offset DAC code [2:0] [4:0] = Reserved
[7:0] = Blue Channel 2 PGA Gain
• Gain = 283/(283 - [7:0])
• Gain range is from 1x to 10x
0x1D
C_OFFS_B2
0x10
[4:0] = Blue Channel 2 Offset DAC Code
• Offset binary format
0x1E
0x1F
F_OFFS_B2
0x80
0x00
[7:0] = Blue Channel 2 Fine Offset DAC code [10:3] • Offset binary format
[7:5] = Blue Channel 2 Fine Offset DAC code [2:0] [4:0] = Reserved
F_OFFS_B2 LSB
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x20 - 0x27 BLACK LEVEL OFFSET CALIBRATION REGISTERS
0x20
0x21
0x22
0x23
TARG_BLK_R
TARG_BLK_G
TARG_BLK_B
BLKCLP_CTL0
0x20
0x20
0x20
0x0C
[7] = Reserved
[6:0] = Target black level – Red Channel
[7] = Reserved
[6:0] = Target black level – Green Channel
[7] = Reserved
[6:0] = Target black level – Blue Channel
Black Level Loop Control
[7:6] = # of lines black clamp compensation applied.
• 00 – infinite # of lines (default)
• 01 – 16 lines
• 10 – 32 lines
• 11 – 64 lines
[5] = Reserved
[4] = High Speed Mode Offset Integration Select
• 1: Divide-by-2
• 0: Divide-by-4/3
[3] = Auto BLKCLP Pulse Generation (0:Disable, 1:Enable)
[2] = Auto black loop Enable (0:Disable. 1:Enable)
[1] = High Speed Mode Enable
[0] = Auto black loop mode
• 1: Update FDAC offset correction only
• 0: Update CDAC and FDAC Offset Corrections
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x24
BLKCLP_CTRL1
0x84
Digital Black Level Clamp Control
• [7:3] = Pixel Averaging
• 00000 4 pixels
• 00001 8 pixels
• 00010 12 pixels
• 00011 16 pixels
• 00100 20 pixels
• 00101 24 pixels
• 00110 28 pixels
• 10000 32 pixels
• 10001 64 pixels
• 10010 96 pixels
• 10011 128 pixels
• 10100 160 pixels
• 10101 192 pixels
• 10110 224 pixels
• 10111 256 pixels
• 11000 288 pixels
• 11001 320 pixels
• 11010 352 pixels
• 11011 384 pixels
• 11100 416 pixels
• 11101 448 pixels
• 11110 480 pixels
• 11111 512 pixels
• other combinations are Reserved
• [2:0] = Offset Integration
• 000:Divide-by-2
• 001:Divide-by-4
• 010:Divide-by-8
• 011:Divide-by-16
• 100:Divide-by-32
• 101:Divide-by-64
• 110:Divide-by-128
• Reserved
0x25
CDAC_THLD_MSB
0x50
CDAC Threshold for BLK LP MSB
Default value is 320d, so loop will change FDAC by 320 to compensate for change
of 1 in CDAC.
[7:0] = Threshold[9:2]
0x26
0x27
CDAC_THLD_LSB
High Speed Mode
0x40
0x88
CDAC Threshold for BLK LP LSB
[7:6] = Threshold[1:0]
[5:0] = Reserved. Set to 0.
[7:5] = High Speed Mode Hysteresis
[4:0] = High Speed Mode Threshold
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x28 – 0x37 WHITE LEVEL GAIN CALIBRATION REGISTERS
0x28
AGC_CONFG
0x40
[7] = Incremental Search Enable
• 0: Binary Search
• 1: Incremental Search
[6] = Black Offset Enable
• 0: Do not Use BLK_AVG during White Level Gain Calibration Loop
• 1: Use BLK_AVG as offset during White Level Gain Calibration Loop
(Recommended)
[5] = CLPIN or BLKCLP White Loop Trigger Select
• 0: CLPIN initiates White Loop each line
• 1: BLKCLP initiates White Loop each line
[4] = AGC_ON pin disable
• = 0 Enable use of AGC_ON pin
• = 1 Disable use of AGC_ON pin to start white calb. loop
[3:1] = Reserved
[0] = AGC_ON. Write to 1 to enable White Level Loop. (0:Ready, 1:Enabled)
White Loop can also be enabled by asserting AGC_ON pin if pin is enabled via.
Register 0x28, b4.
0x29
PK_AVE
0x04
Number of pixels in running average during white calibration loop
[2:0] =
• 000:No average (1 pixel)
• 001:2 pixels
• 010:4 pixels
• 011:8 pixels
• 100:16 pixels
• 101:32 pixels
0x2A
REG_PK_DET
_ST_M SB
0x00
Starting pixel for peak detection. 16 bit value. Number of pixels after rising edge
trigger event. (CLPIN or BLKCLP)
(0 to 65535)
Actual delay PK_DET_ST = REG_PK_DET_ST + 6
0x2B
0x2C
REG_PK_DET
_ST_L SB
0x00
0x00
PK_DET_WID_MSB
Duration of peak detection after PK_DET_ST. 16 bit value
(0 to 65535)
0x2D
0x2E
PK_DET_WID_LSB
AGCDuration
0x00
0x10
[7:0] = Number of lines for AGC to operate.
Loop will run continuously if AGC_ON pin is held high.
(0 to 255)
0x2F
AGCTargetMSB
0xE0
[7:0] = MSB of Target Value for AGC loop
(Default AGCTarget=960d)
AGC_TARG = 512d +
(AGCTargetMSB[7:0],AGCTargetLSB[7])
[7] = LSb of Target Value for AGC loop
[6:0] = Reserved
0x30
0x31
AGCTargetLSB
AGCTolerance
0x00
0x28
[7:6] = Reserved
[5:0] = Allowable error for AGC loop
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x32
AGC_BLKINT
0x00
AGC Offset Integration
[2:0] = Offset Integration setting for the Black Level Loop while the AGC is on (that
is, white level loop)
• 000:Divide-by-2
• 001:Divide-by-4
• 010:Divide-by-8
• 011:Divide-by-16
• 100:Divide-by-32
• 101:Divide-by-64
• 110:Divide-by-128
• Reserved
0x33
AGC STATUS
0x00
AGC Status – Read Only
[7:6] = 0
[5] = Convergence Error Blue Ch2
[4] = Convergence Error Blue Ch1
[3] = Convergence Error Green Ch2
[2] = Convergence Error Green Ch1
[1] = Convergence Error Red Ch2
[0] = Convergence Error Red Ch1
Must be kept with Power-on-default values.
Must be kept with Power-on-default values.
Must be kept with Power-on-default values.
[7:5] Reserved. Set to 000
[4:0] = Sample Pulse Falling Edge Position
• [4:0]: delay [4:0]/32 of Tpixel from Pixel Clock
• 00000: delay 0/32 of Tpixel from Pixel Clock
• 00001: delay 1/32 of Tpixel from Pixel Clock
• …
0x34
0x35
0x36
Reserved
0x32
0x54
0x1F
Reserved
DLL Sample Position
• 11111: delay 31/32 of Tpixel from Pixel Clock
[7:5] = Sample Pulse Width
• 000: 2/32 of Tpixel
0x37
DLL Sample Width
0x60
• 001: 4/32 of Tpixel
• 010: 6/32 of Tpixel
• 011: 8/32 of Tpixel
• 100: 10/32 of Tpixel
• 101: 12/32 of Tpixel
• 110: 14/32 of Tpixel
• 111: 16/32 of Tpixel
• [4:0] = Reserved
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Table 12. Configuration Registers Details (continued)
ADDRESS
(HEX)
DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
0x38 to 0x3F USER TEST PATTERNS REGISTERS
0x38
TEST_PAT_CTL
0x00
Test Pattern Mode
[7] = Test Pattern Enable (PATSW)
• (0:Normal Data Output, 1:Test Pattern Output Enabled) [6:5] = Test Pattern
Mode Select (PTRMODE)
• 00:Fixed Code
• 01:Gradation Pattern (Main Scanning).
• 10:Gradation Pattern (Sub Scanning)
• 11:Grid Pattern
[4:3] = Test Pattern Output Channel (PTRGBSEL)
• 00:All colors
• 01:Red (Other color data at 1023d)
• 10:Green (Other color data at 1023d)
• 11:Blue (Other color data at 1023d)
[2:0] = Reserved
0x39
0x3A
0x3B
0x3C
0x3D
TESTPLVL_MSB
TESTPLVL_LSB
PATW
0x00
0x00
0x00
0x00
0x00
[7:0] = 8 MSb of fixed output code (TESTPLVL)
[7:6] = 2 LSb of fixed output code (TESTPLVL)
[7:0] = Gradation Pattern Pitch (0 to 255 lines)
[7:0] = Gradation Pattern Increment Step (0 to 255)
PATS
LINE_INTVL
[3:0] = Test Pattern Output Color Delay, Red to Green, Green to Blue
(0 to 15 line delay)
0x3E
0x3F
Reserved
PAGE_SEL for Page
Control
0x00
Select Register Pages
• 0x00: Page 0
• 0x80: Page 128 (DLL features)
Table 13. DLL Configuration Registers Summary Table
HEX ADDRESS
(A5-A0)
REGISTER NAME
COMMENTS
0x00
OS_R1 Sample Falling Edge Position
0x01
OS_R2 Sample Falling Edge Position
0x02
OS_G1 Sample Falling Edge Position
0x03
OS_G2 Sample Falling Edge Position
0x04
OS_B1 Sample Falling Edge Position
0x05
OS_B2 Sample Falling Edge Position
Reserved
0x06
0x07
Reserved
0x08
Reserved
0x09
Reserved
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10 - 0x3E
0x3F
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Page Select
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Table 14. DLL Configuration Registers Details (Page 128)
ADDRESS
(HEX)
REGISTER
NAME
DEFAULT
(HEX)
DESCRIPTION
0x00 - 0x07 SAMPLE FALLING EDGE POSITION REGISTERS
0x00
OS_R1
Sample
Falling
Edge
0x1F
[7:5] = Reserved
[4:0] = OS_R1 Sample Falling Edge Position
• [4:0]: delay [4:0]/32 of Tpixel from Pixel Clock
• 00000: delay 0/32 of Tpixel from Pixel Clock
• 00001: delay 1/32 of Tpixel from Pixel Clock
• …
Position
• 11111: delay 31/32 of Tpixel from Pixel Clock
Same as OS_R1
0x01
OS_R2
Sample
Falling
Edge
0x1F
Position
0x02
0x03
0x04
OS_G1
Sample
Falling Edge
Position
0x1F
0x1F
0x1F
Same as OS_R1
Same as OS_R1
Same as OS_R1
OS_G2
Sample
Falling Edge
Position
OS_B1
Sample
Falling
Edge
Position
0x05
OS_B2
Sample
Falling
Edge
0x1F
Same as OS_R1
Position
0x06
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10 – 0x3E
0x3F
PAGE_SEL
for Page
Control
0x00
Select Register Pages
• 0x00: Page 0
• 0x80: Page 128 (DLL features)
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8 Applications and Implementation
8.1 Application Information
The white loop provides two different techniques for converging to the target value, Binary Search, and
Incremental Search.
The Binary Search algorithm is intended to provide a rapid convergence to the target value. During initial
operation, large changes in the channel gain are allowed. After each line, the allowed change is reduced
significantly. For final convergence, the algorithm switches to the Incremental Search mode, to achieve low error.
The Incremental or Linear Search algorithm is intended to provide a low error, but will converge more slowly than
the Binary method. The changes (if any) in channel gain are always done in 1 lsb increments to provide low
overshoot and high accuracy of convergence.
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8.2 Typical Applications
VCCD
All power supply voltages should be provided from clean linear
regulator outputs, NOT switching power supplies.
VDDD
C1
C2
C3
VDDLVDS
All power supply voltages should be provided from clean linear
regulator outputs, NOT switching power supplies.
C4
0.1u
0.1u 0.1u
0.1u
R1 R2 R3
C5
VDDA
0.1u
VDDA
Pinout mapping for output format 2a.
Q1
NPN BCE
SDO
SENB
SDI
SCLK
RESETB
C7
C6
0.1u
VDDLVDS_RX_PLL
VDDLVDS_OUT
R4
VDDA
10u
U1
1
B6
B7
48
TESTO_0
TESTO_1
RxOUT17
2
Vcc
RxOUT16
RxOUT15
RxOUT14
GND
RxOUT13
Vcc
RxOUT12
RxOUT11
RxOUT10
GND
RxOUT9
Vcc
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
RxOUT4
RxOUT3
Vcc
RxOUT2
RxOUT1
GND
B5
B4
B3
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RxOUT18
3
GND
4
B8
B9
Q2
NPN BCE
C8 0.1u
RxOUT19
5
RxOUT20
6
Place 100 Ohm termination resistors as
close to RxIN+/- pins as possible.
B2
N/C
7
R5
LVDS GND
8
B1
B0
G9
RxIN0-
9
C9 1u
U2
LM98620
100 R6
RxIN0+
10
C10
0.1u
RxIN1-
11
C11
0.1u
100 R7
RxIN1+
12
G8
LVDS Vcc
13
Q3
NPN BCE
LVDS GND
14
G7
G6
G5
RxIN2-
15
100 R8
RxIN2+
16
R9
RxCLK IN-
17
61
40
100 R10
VREFBIN2
VREFTIN2
VREFBIN1
VREFTIN1
VSSA
OSR1
VDDA
OSR2
VSSA
OSG1
VDDA
OSG2
VSSA
OSB1
VDDA
OSB2
VSSA
TXOUTA2-
RxCLK IN+
18
G4
G3
G2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
TXOUTA2+
TXOUTB2-
TXOUTB2+
TXOUTC2-
TXOUTC2+
VSSLVDS
VREG2
LVDS GND
19
PLL GND
20
PLL Vcc
21
C12 1u
PLL GND
22
G1
G0
/PWR DWN
23
C14 1u
C17 1u
C13 0.1u
C16 0.1u
C19 0.1u
VCCD
RxCLK OUT
24
RxOUT0
C15 1u
C18 1u
TXCLK2-
DS90CR218A_tssop
TXCLK2+
TXOUTA1-
TXOUTA1+
VSSLVDS
VREG2
TXOUTB1-
TXOUTB1+
TXOUTC1-
TXOUTC1+
TXCLK1-
GPI4
RXCLKOUT2
C20 1u
U3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
68
67
66
65
64
63
62
61
60
59
58
57
56
55
OS3
OS4
ODB
OS2
OS1
ASS
CP
VCLPEXT
VCLPINT
SHP/SAMPLE
ODG
OS5
OS6
ODR
DSS
Phi2B
U4
TXCLK1+
R7
R8
C21
0.1u
C22
10u
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RxOUT17
RxOUT18
GND
RxOUT19
RxOUT20
N/C
LVDS GND
RxIN0-
RxIN0+
RxIN1-
RxIN1+
Vcc
RxOUT16
RxOUT15
RxOUT14
GND
RxOUT13
Vcc
RxOUT12
RxOUT11
RxOUT10
GND
RxOUT9
Vcc
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
RxOUT4
RxOUT3
Vcc
RxOUT2
RxOUT1
GND
R6
R5
R4
R9
GPI5
R14 R15
R16
RS
Phi2A Phi2A
Phi1A Phi1A
R3
VDDD
C25
VDD
NC
NC
NC
NC
VDD
NC
NC
NC
NC
R2
R1
R0
100 R17
100 R19
C23
0.1u
C24
0.1u
GPI1
R20
R23
Q4
NPN BCE
LVDS Vcc
LVDS GND
RxIN2-
C26 C27 VDDD
0.1u 0.1u
C28
0.1u
C29
0.1u
GPI2
GPI3
0
0.1u
15
16
17
18
19
20
21
22
23
24
54
53
52
51
50
49
48
47
46
45
100 R21
100 R22
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RxIN2+
RxCLK IN-
RxCLK IN+
LVDS GND
PLL GND
PLL Vcc
PLL GND
/PWR DWN
RxCLK OUT
RxOUT0
0
0
0
Q5
NPN BCE
R18
11k 1%
R24
0
0
R25
Q6
NPN BCE
R26
DS90CR218A_tssop
0
RXCLKOUT1
MCLK
OVPB
25
26
27
28
29
30
31
32
33
34
44
43
42
41
40
39
38
37
36
35
NC
NC
NC
NC
NC
NC
NC
NC
R27
AGC_ONB
BLKCLP
CLPIN
GPI5
NC NC
Phi1A DSS
Phi2A Phi1A
SH3
NC
SH2
GPI4
GPI3
GPI2
GPI1
Phi2A
NC
SH1
CCD installed on opposite side of
board to other electronics.
HOLD
TCD2703D
SAMPLE
Figure 40. Example Circuit
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8.2.1 Design Requirements
See Figure 40 for an example circuit and the required minimum circuitry around the LM98620.
•
All power supply voltages should be provided from clean linear regulator outputs, NOT switching power
supplies.
•
Place 100 Ω termination resistors as close to RxIN+/- pins as possible.
8.2.2 Detailed Design Procedure
1. 3.3 V Power for Analog, Digital, and LVDS supplies. It is recommended to use a common LDO regulator for
all 3.3V supplies, using EMI filter devices and dedicated decoupling to isolate any noise between buses.
2. Input Timing Signals (Ground referenced logic signal with: 2.0 V < VHigh < 3.3 V)
(a) MCLK: Continuous clock signal at pixel rate or ADC rate of LM98620
(b) CLPIN: Once per scan line signal used to control initial of input clamp for DC restoration of AC coupled
CCD input signals
(c) BLKCLP: Once per scan line signal used to indicate beginning of black pixels for Black (Offset) Level
Calibration
(d) AGC_ONB – Input signal used to initiate start of White (Gain) Calibration
(e) SHP/SAMPLE: Once per pixel signal used to control pixel sample timing
(f) SHD/HOLD: Once per pixel signal used to control pixel sample timing
3. Optional General Purpose logic inputs. Can be used to transfer low speed digital status information from the
imaging board to the data processing module
(a) GPI1-5
4. CCD signals at OS Inputs – These are connected to the outputs from the CCD sensor emitter follower buffer
circuits. The signals are AC coupled to the AFE inputs using 0.1 uF capacitors.
5. Serial control interface from data processing module to LM98620 (Ground referenced logic signal with: 2.0 V
< Vhigh < 3.3 V):
(a) SENB – Serial enable to LM98620
(b) SCLK – Serial clock input to LM98620
(c) SDI – Data input to LM98620
(d) SDO – Data output from LM98620
6. Serialized LVDS data pairs connected to FPGA or LVDS deserializer chip on data processing module
7. Adjust and reconfigure the configuration register settings as needed
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8.2.3 Application Performance Plots
20
15
10
5
0
Gain Setting
8-Bit PGA Gain
Min Gain = 1.0
Max Gain = 10
Remaining Gain of 2x in CDS
Black = Gain in dB
PGA Gain = 283/(283-M)
M = 0 to 255
Max Step = 0.300 dB
Red = Gain by Ratio
Figure 41. PGA Gain Curve
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9 Power Supply Recommendations
9.1 Over Voltage Protection on OS Inputs
The OS inputs are protected from damage caused by transients from the sensor circuitry during power up/down.
When the chip is not powered, or has just been powered up, the OS inputs are clamped to VBSSAB with PMOS
devices. The protective clamp circuits are disabled by applying a high level to the OVPB input pin and setting the
OVP enable bit to its default state of 0.
The maximum voltage and input current specifications for the OS inputs when OVP is enabled are the same as
those listed in Absolute Maximum Ratings(1)
.
Positive input signals will be clamped by the internal switch through a diode to VSSA. Negative input signals will
be clamped by the internal ESD protection diode to one diode drop below VSSD. Typically this will be about 0.7V
below ground.
Table 15. Over Voltage Protection Input Clamping
OVP ENABLE BIT
(REGISTER 0x01, BIT 4)
OVER VOLTAGE PROTECTION
INPUT CLAMPING
OVPB INPUT PIN
0
1
0
1
0
0
1
1
Enabled
Disabled
Enabled
Enabled
(1) Absolute maximum ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
62
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Product Folder Links: LM98620
LM98620
www.ti.com
SNAS426C –FEBRUARY 2008–REVISED MAY 2014
10 Layout
10.1 Layout Guidelines
1. Use Figure 42 configuration for powering the device.
V
IN
V
DDD
Vreg
+
+
V
DDA
+
+
V
DDLVDS
+
Figure 42. Recommended Setup for Powering Device
2. Place decoupling cap(s) next to every supply pin to the ground plane close by.
3. Use a multi-layer boards as shown in Figure 43 to ease routing, and to provide a low inductance ground
plane.
4. Beware of via inductance and when necessary increase the number and / or diameter of vias to reduce
inductance
5. Use ground plane “keep out” areas under sensitive nodes to minimize parasitic capacitance
Copyright © 2008–2014, Texas Instruments Incorporated
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63
Product Folder Links: LM98620
LM98620
SNAS426C –FEBRUARY 2008–REVISED MAY 2014
www.ti.com
10.2 Layout Examples
Figure 43. LM98620 Layout Example
64
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Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM98620
LM98620
www.ti.com
SNAS426C –FEBRUARY 2008–REVISED MAY 2014
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2008–2014, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM98620VHB/NOPB
ACTIVE
TQFP
PFC
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
LM98620VHB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
LM98620VHB/NOPB
PFC
TQFP
80
119
7X17
150
322.6 135.9 7620 17.9
14.3 13.95
Pack Materials-Page 1
PACKAGE OUTLINE
PFC0080A
TQFP - 1.2 mm max height
SCALE 1.250
PLASTIC QUAD FLATPACK
12.2
11.8
B
PIN 1 ID
80
61
A
1
60
12.2
11.8
14.2
TYP
13.8
20
41
40
21
76X 0.5
0.27
80X
0.17
4X 9.5
0.08
C A B
1.2 MAX
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1)
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215165/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PFC0080A
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215165/B 06/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PFC0080A
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4215165/B 06/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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