LMC6022IM/NOPB [TI]
双路、15.5V、350kHz 运算放大器 | D | 8 | -40 to 85;
| 型号： | LMC6022IM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、15.5V、350kHz 运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总25页 (文件大小：1416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMC6022
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SNOS622D –NOVEMBER 1994–REVISED MARCH 2013
LMC6022 Low Power CMOS Dual Operational Amplifier
Check for Samples: LMC6022
1
FEATURES
DESCRIPTION
The LMC6022 is a CMOS dual operational amplifier
which can operate from either a single supply or dual
supplies. Its performance features include an input
common-mode range that reaches V−, low input bias
current, and voltage gain (into 100k and 5 kΩ loads)
that is equal to or better than widely accepted bipolar
equivalents, while the power supply requirement is
less than 0.5 mW.
2
•
•
•
•
•
•
•
•
•
Specified for 100 kΩ and 5 kΩ Loads
High Voltage Gain: 120 dB
Low Offset Voltage Drift: 2.5 μV/°C
Ultra Low Input Bias Current: 40 fA
Input Common-Mode Range Includes V−
Operating Range from +5V to +15V Supply
Low Distortion: 0.01% at 1 kHz
Slew Rate: 0.11 V/μs
This chip is built with National's advanced Double-
Poly Silicon-Gate CMOS process.
Micropower Operation: 0.5 mW
See the LMC6024 datasheet for a CMOS quad
operational amplifier with these same features.
APPLICATIONS
•
•
•
•
•
•
•
High-Impedance Buffer or Preamplifier
Current-to-Voltage Converter
Long-Term Integrator
Sample-and-Hold Circuit
Peak Detector
Medical Instrumentation
Industrial Controls
Connection Diagram
Figure 1. 8-Pin SOIC
Top View
Figure 2. LMC6022 Circuit Topology
(Each Amplifier)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2013, Texas Instruments Incorporated
LMC6022
SNOS622D –NOVEMBER 1994–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
Differential Input Voltage
Supply Voltage (V+ − V−)
Lead Temperature (Soldering, 10 sec.)
Storage Temperature Range
Junction Temperature
±Supply Voltage
16V
260°C
−65°C to +150°C
150°C
ESD Tolerance(2)
1000V
Voltage at Output/Input Pin
Current at Output Pin
(V+) +0.3V, (V−) −0.3V
±18 mA
Current at Power Supply Pin
Power Dissipation
35 mA
See(3)
Current at Input Pin
±5 mA
Output Short Circuit to V−
Output Short Circuit to V+
See(4)
See(5)
(1) Absolute Maximum Ratings indicate limits beyond which damage to component may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
(2) Human body model, 100 pF discharged through a 1.5 kΩ resistor.
(3) The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA
.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
(5) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
OPERATING RATINGS
Temperature Range
Supply Voltage Range
Power Dissipation
−40°C ≤ TJ ≤ +85°C
4.75V to 15.5V
See(1)
(2)
Thermal Resistance (θJA
)
8-Pin SOIC
165°C/W
(1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ−TA)/θJA
.
(2) All numbers apply for packages soldered directly into a PC board.
DC ELECTRICAL CHARACTERISTICS
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
LMC6022I
Limit(2)
Symbol
VOS
Parameter
Conditions
Typical(1)
Units
Input Offset Voltage
1
9
mV
11
max
ΔVOS/ΔT
Input Offset Voltage
Average Drift
2.5
μV/°C
IB
Input Bias Current
Input Offset Current
Input Resistance
0.04
pA
max
pA
200
100
IOS
0.01
>1
max
TeraΩ
RIN
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or correlation.
2
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DC ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
LMC6022I
Limit(2)
Symbol
CMRR
Parameter
Conditions
Typical(1)
Units
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 12V
83
63
dB
min
dB
V+ = 15V
61
+PSRR
−PSRR
VCM
Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V
0V ≤ V− ≤ −10V
83
94
63
61
min
dB
Negative Power Supply
Rejection Ratio
74
73
min
V
Input Common-Mode
Voltage Range
V+ = 5V & 15V
−0.4
−0.1
0
For CMRR ≥ 50 dB
max
V
V+ − 1.9
1000
500
V+ − 2.3
V+ − 2.5
200
100
90
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
V
AV
Large Signal Voltage Gain
RL = 100 kΩ(3)
Sinking
Sourcing
40
RL = 5 kΩ(3)
Sourcing
Sinking
1000
250
100
75
50
20
VO
Output Voltage Swing
V+ = 5V
4.987
0.004
4.940
0.040
14.970
0.007
14.840
0.110
4.40
4.43
0.06
0.09
4.20
4.00
0.25
0.35
14.00
13.90
0.06
0.09
13.70
13.50
0.32
0.40
RL = 100 kΩ to 2.5V
min
V
max
V
V+ = 5V
RL = 5 kΩ to 2.5V
min
V
max
V
V+ = 15V
RL = 100 kΩ to 7.5V
min
V
max
V
V+ = 15V
RL = 5 kΩ to 7.5V
min
V
max
(3) V+ = 15V, VCM = 7.5V, and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
LMC6022I
Limit(2)
Symbol
Parameter
Output Current
Conditions
Typical(1)
Units
IO
V+ = 5V
Sourcing, VO = 0V
22
13
mA
min
mA
min
mA
min
mA
min
μA
9
Sinking, VO = 5V(4)
21
40
39
86
13
9
V+ = 15V
Sourcing, VO = 0V
Sinking, VO = 13V
23
15
(5)
23
15
IS
Supply Current
Both Amplifiers
VO = 1.5V
140
165
max
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
(5) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
AC ELECTRICAL CHARACTERISTICS
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless other otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
LMC6022I
Limit(2)
Symbol
SR
Parameter
Conditions
See(3)
Typical(1)
Units
Slew Rate
0.11
0.05
V/μs
min
0.03
GBW
φM
Gain-Bandwidth Product
Phase Margin
0.35
50
MHz
Deg
GM
Gain Margin
17
dB
Amp-to-Amp Isolation
Input-Referred Voltage Noise
Input-Referred Current Noise
See(4)
130
42
dB
en
in
F = 1 kHz
F = 1 kHz
nV/√Hz
pA/√Hz
0.0002
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or correlation.
(3) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
(4) Input referred. V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 13 VPP
.
4
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TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±7.5V, TA = 25°C unless otherwise specified
Supply Current
vs. Supply Voltage
Input Bias Current
vs. Temperature
Figure 3.
Figure 4.
Input Common-ModeVoltage Range vs.Temperature
Output Characteristics Current Sinking
Figure 5.
Figure 6.
Input Voltage Noise
vs. Frequency
Output Characteristics Current Sourcing
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Crosstalk Rejection
CMRR
vs. Frequency
vs. Frequency
Figure 9.
Figure 10.
CMRR
vs. Temperature
Power Supply Rejection Ratio
vs. Frequency
Figure 11.
Figure 12.
Open-Loop Voltage Gain
vs. Temperature
Open-Loop Frequency Response
Figure 13.
Figure 14.
6
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Gain and Phase Responses
Gain and Phase Responses
vs. Temperature
vs. Load Capacitance
Figure 15.
Figure 16.
Gain Error (VOS
Non-Inverting Slew Rate
vs. Temperature
vs. VOUT
)
Figure 17.
Figure 18.
Inverting Slew Rate
vs. Temperature
Large-Signal Pulse Non-Inverting Response
(AV = +1)
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Non-Inverting Small Signal Pulse Response
(AV = +1)
Inverting Large-Signal Pulse Response
Figure 21.
Figure 22.
Stability
vs. Capacitive Load
Inverting Small-Signal Pulse Response
Note: Avoid resistive loads of less than 500Ω, as they may cause
instability.
Figure 23.
Figure 24.
Stability
vs. Capacitive Load
Figure 25.
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SNOS622D –NOVEMBER 1994–REVISED MARCH 2013
APPLICATION HINTS
AMPLIFIER TOPOLOGY
The topology chosen for the LMC6022 is unconventional (compared to general-purpose op amps) in that the
traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the
integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while
maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the
integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.
Figure 26. LMC6022 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable to traditional bipolar op amps for load resistance of at
least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage;
however, when driving load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical
Characteristics. The op amp can drive load resistance as low as 500Ω without instability.
COMPENSATING INPUT CAPACITANCE
Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary
for compensation and what the value of that capacitor would be.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC6022 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See the TYPICAL PERFORMANCE CHARACTERISTICS.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp's output, and a capacitor (5
pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with
lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note
that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation.
Figure 27. Rx, Cx Improve Capacitive Load Tolerance
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Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 28). Typically a pull up
resistor conducting 50 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 28. Compensating for Large
Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6022, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6022's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs. See Figure 29. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LMC6022's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the
amplifier's performance. See Figure 30a, Figure 30b, Figure 30c for typical connections of guard rings for
standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground
and still provide some protection; see Figure 30d.
Figure 29. Example of Guard Ring in P.C. Board Layout (Using the LMC6024)
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(a) Inverting Amplifier Guard Ring Connections
(b) Non-Inverting Amplifier Guard Ring Connections
(c) Follower Guard Ring Connections
(d) Howland Current Pump Guard Ring Connections
Figure 30. Guard Ring Connections
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 31.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 31. Air Wiring
BIAS CURRENT TESTING
The test method of Figure 32 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then
(1)
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Figure 32. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted)
(2)
where Cx is the stray capacitance at the + input.
Typical Single-Supply Applications
(V+ = 5.0 VDC
)
Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and
lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current).
Figure 33. Photodiode Current-to-Voltage Converter
(Upper limit of output range dictated by input common-mode range;
lower limit dictated by minimum current requirement of LM385.)
Figure 34. Micropower Current Source
Figure 35. Low-Leakage Sample-and-Hold
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(V+ = 5.0 VDC
)
If R1 = R5, R3 = R6, and R4 = R7;
Then
∴AV ≈ 100 for circuit shown
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.
Figure 36. Instrumentation Amplifier
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V.
Figure 37. Sine-Wave Oscillator
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(V+ = 5.0 VDC
)
Figure 38. 1 Hz Square-Wave Oscillator
Figure 39. Power Amplifier
fc = 10 Hz
d = 0.895
Gain = 1
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 40. 10 Hz Bandpass Filter
Figure 41. 10 Hz High-Pass Filter (2 dB Dip)
Figure 42. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only)
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(V+ = 5.0 VDC
)
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV), referred
to VBIAS
.
Figure 43. High Gain Amplifier with Offset Voltage Reduction
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMC6022IM/NOPB
LMC6022IMX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMC60
22IM
ACTIVE
2500 RoHS & Green
SN
LMC60
22IM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC6022IMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMC6022IMX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMC6022IM/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2022, Texas Instruments Incorporated
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