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LMC6442IMX/NOPB [TI]

双路、11V、10kHz 运算放大器 | D | 8 | -40 to 85;
LMC6442IMX/NOPB
型号： LMC6442IMX/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

双路、11V、10kHz 运算放大器 | D | 8 | -40 to 85

放大器 光电二极管 运算放大器
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LMC6442  
www.ti.com  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
LMC6442 Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier  
Check for Samples: LMC6442  
1
FEATURES  
DESCRIPTION  
The LMC6442 is ideal for battery powered systems,  
where very low supply current (less than one  
microamp per amplifier) and Rail-to-Rail output swing  
is required. It is characterized for 2.2V to 10V  
operation, and at 2.2V supply, the LMC6442 is ideal  
for single (Li-Ion) or two cell (NiCad or alkaline)  
battery systems.  
2
•
(Typical, VS = 2.2V)  
•
•
•
•
•
•
•
•
Output Swing to Within 30 mV of Supply Rail  
High Voltage Gain 103 dB  
Gain Bandwidth Product 9.5 KHz  
Ensured for: 2.2V, 5V, 10V  
Low Supply Current 0.95 µA/Amplifier  
Input Voltage Range −0.3V to V+ -0.9V  
2.1 µW/Amplifier Power Consumption  
Stable for AV ≥ +2 or AV ≤ −1  
The LMC6442 is designed for battery powered  
systems that require long service life through low  
supply current, such as smoke and gas detectors,  
and pager or personal communications systems.  
Operation from single supply is enhanced by the wide  
common mode input voltage range which includes the  
ground (or negative supply) for ground sensing  
applications. Very low (5 fA, typical) input bias current  
and near constant supply current over supply voltage  
enhance the LMC6442's performance near the end-  
of-life battery voltage.  
APPLICATIONS  
•
•
•
•
•
•
•
•
Portable Instruments  
Smoke/Gas/CO/Fire Detectors  
Pagers/Cell Phones  
Instrumentation  
Thermostats  
Designed for closed loop gains of greater than plus  
two (or minus one), the amplifier has typically 9.5  
KHz GBWP (Gain Bandwidth Product). Unity gain can  
be used with a simple compensation circuit, which  
also allows capacitive loads of up to 300 pF to be  
driven, as described in the Application Information  
section.  
Occupancy Sensors  
Cameras  
Active Badges  
Connection Diagram  
Top View  
Figure 1. 8-Pin SOIC / PDIP Package  
See Package Numbers D0008A, P0008E  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1997–2013, Texas Instruments Incorporated  
LMC6442  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
www.ti.com  
(1)(2)  
Absolute Maximum Ratings  
ESD Tolerance  
(3)  
2 kV  
±Supply Voltages  
(V+) + 0.3V, (V−) − 0.3V  
16V  
Differential Input Voltage  
Voltage at Input/Output Pin  
Supply Voltage (V+ − V−):  
(4)  
Current at Input Pin  
±5 mA  
Current at Output Pin(5) (6)  
Lead Temp. (soldering 10 sec)  
Storage Temp. Range:  
±30 mA  
260°C  
−65°C to +150°C  
150°C  
(7)  
Junction Temp.  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test  
conditions, see the Electrical Characteristics.  
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.  
(3) Human body model, 1.5 kΩ in series with 100 pF.  
(4) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.  
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in  
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely  
affect reliability.  
(6) Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.  
(7) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient  
temperature is PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly into a PC board.  
(1)  
Operating Ratings  
Supply Voltage  
1.8V ≤ VS ≤ 11V  
−40°C < TJ < +85°C  
193°C/W  
Junction Temperature Range: LMC6442AI, LMC6442I  
Thermal Resistance (θJA  
)
D0008A Package, 8-pin Surface Mount  
P0008E Package, 8-pin Molded DIP  
115°C/W  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test  
conditions, see the Electrical Characteristics.  
2.2V Electrical Characteristics  
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.2V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.  
Boldface limits apply at the temperature extremes.  
LMC6442AI  
Limit  
LMC6442I  
Limit  
(1)  
Parameter  
Test Conditions  
Typ  
Units  
(2)  
(2)  
DC Electrical Characteristics  
VOS  
TCVOS  
IB  
Input Offset Voltage  
±3  
±4  
±7  
±8  
mV  
max  
−0.75  
0.4  
Temp. coefficient of input  
offset voltage  
µV/°C  
(3)  
(3)  
Input Bias Current  
See  
See  
pA  
max  
0.005  
4
2
4
2
Input Offset Current  
pA  
max  
IOS  
0.0025  
92  
CMRR  
Common Mode Rejection  
Ratio  
−0.1V ≤ VCM ≤0.5V  
67  
67  
67  
67  
dB min  
CIN  
Common Mode Input  
Capacitance  
4.7  
95  
pF  
PSRR  
Power Supply Rejection  
Ratio  
VS = 2.5 V to 10V  
75  
75  
75  
75  
dB  
min  
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are specified by testing or statistical analysis unless otherwise specified.  
(3) Limits specified by design.  
2
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LMC6442  
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SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
2.2V Electrical Characteristics (continued)  
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.2V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.  
Boldface limits apply at the temperature extremes.  
LMC6442AI  
Limit  
LMC6442I  
Limit  
(1)  
Parameter  
Test Conditions  
Typ  
Units  
(2)  
(2)  
VCM  
Input Common-Mode  
Voltage Range  
1.05  
0.95  
1.05  
0.95  
V
min  
1.3  
CMRR ≥ 50 dB  
−0.3  
−0.2  
−0.2  
V
0
0
max  
(4)  
AV  
Large Signal Voltage Gain Sourcing  
100  
94  
dB  
(4)  
Sinking  
min  
VO = 0.22V to 2V  
103  
80  
80  
(5)  
VO  
Output Swing  
VID = 100 mV  
2.15  
2.15  
2.15  
2.15  
V
min  
2.18  
22  
(5)  
VID = −100 mV  
60  
60  
mV  
60  
60  
max  
(6) (5)  
(6) (5)  
ISC  
Output Short Circuit  
Current  
Sourcing, VID = 100 mV  
Sinking, VID = −100 mV  
RL = open  
50  
50  
18  
17  
18  
17  
µA  
min  
20  
19  
20  
19  
IS  
Supply Current  
(2 amplifiers)  
1.90  
2.10  
2.4  
3.0  
2.6  
3.2  
µA  
max  
V+ = 1.8V, RL = open  
AC Electrical Characteristics  
(7)  
SR  
Slew Rate  
2.2  
9.5  
63  
V/ms  
KHz  
deg  
GBWP  
φm  
Gain-Bandwidth Product  
Phase Margin  
(8)  
See  
(4) RL connected to V+/2. For Sourcing Test, VO > V+/2. For Sinking tests, VO < V+/2.  
(5) VID is differential input voltage referenced to inverting input.  
(6) Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.  
(7) Slew rate is the slower of the rising and falling slew rates.  
(8) See the Typical Performance Characteristics and Applications Information sections for more details.  
5V Electrical Characteristics  
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.  
Boldface limits apply at the temperature extremes.  
LMC6442AI  
Limit  
LMC6442I  
Limit  
(1)  
Parameter  
Test Conditions  
Typ  
Units  
(2)  
(2)  
DC Electrical Characteristics  
VOS  
TCVOS  
IB  
Input Offset Voltage  
±3  
±4  
±7  
±8  
mV  
max  
−0.75  
Temp. coefficient of input  
offset voltage  
0.4  
µV/°C  
(3)  
(3)  
Input Bias Current  
See  
See  
pA  
max  
0.005  
4
2
4
2
Input Offset Current  
pA  
max  
IOS  
0.0025  
102  
CMRR  
Common Mode Rejection  
Ratio  
−0.1V ≤ VCM ≤3.5V  
70  
70  
70  
70  
dB min  
CIN  
Common Mode Input  
Capacitance  
4.1  
95  
pF  
PSRR  
Power Supply Rejection  
Ratio  
VS = 2.5 V to 10V  
75  
75  
75  
75  
dB  
min  
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are specified by testing or statistical analysis unless otherwise specified.  
(3) Limits specified by design.  
Copyright © 1997–2013, Texas Instruments Incorporated  
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SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
www.ti.com  
5V Electrical Characteristics (continued)  
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.  
Boldface limits apply at the temperature extremes.  
LMC6442AI  
Limit  
LMC6442I  
Limit  
(1)  
Parameter  
Test Conditions  
Typ  
Units  
(2)  
(2)  
VCM  
Input Common-Mode  
Voltage Range  
3.85  
3.75  
3.85  
3.75  
V
min  
4.1  
CMRR ≥ 50 dB  
−0.4  
−0.2  
−0.2  
V
0
0
max  
(4)  
AV  
Large Signal Voltage Gain  
Output Swing  
Sourcing  
100  
94  
dB  
(4)  
Sinking  
min  
VO = 0.5V to 4.5V  
103  
4.99  
80  
80  
(5)  
VO  
VID = 100 mV  
4.95  
4.95  
V
4.95  
4.95  
min  
(5)  
VID = −100 mV  
20  
50  
50  
mV  
50  
50  
max  
(6) (5)  
(6) (5)  
ISC  
Output Short Circuit Current Sourcing, VID = 100 mV  
500  
350  
1.90  
300  
200  
300  
200  
µA  
min  
Sinking, VID = −100 mV  
200  
150  
200  
150  
IS  
Supply Current  
(2 amplifiers)  
RL = open  
2.4  
3.0  
2.6  
3.2  
µA  
max  
AC Electrical Characteristics  
(7)  
SR  
Slew Rate  
4.1  
10  
2.5  
2.5  
V/ms  
KHz  
deg  
%
GBWP  
φm  
Gain-Bandwidth Product  
Phase Margin  
(8)  
See  
64  
THD  
Total Harmonic Distortion  
AV = +2, f = 100 Hz,  
0.08  
RL = 10 MΩ, VOUT = 1 VPP  
(4) RL connected to V+/2. For Sourcing Test, VO > V+/2. For Sinking tests, VO < V+/2.  
(5) VID is differential input voltage referenced to inverting input.  
(6) Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.  
(7) Slew rate is the slower of the rising and falling slew rates.  
(8) See the Typical Performance Characteristics and Applications Information sections for more details.  
10V Electrical Characteristics  
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 10V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.  
Boldface limits apply at the temperature extremes.  
LMC6442AI  
Limit  
LMC6442I  
Limit  
(1)  
Parameter  
Test Conditions  
Typ  
Units  
(2)  
(2)  
DC Electrical Characteristics  
VOS  
TCVOS  
IB  
Input Offset Voltage  
±3  
±4  
±7  
±8  
mV  
max  
−1.5  
Temp. coefficient of input  
offset voltage  
0.4  
µV/°C  
Input Bias Current  
See(3)  
pA  
max  
0.005  
4
2
4
2
(3)  
Input Offset Current  
See  
pA  
max  
IOS  
0.0025  
105  
CMRR  
Common Mode Rejection  
Ratio  
−0.1V ≤ VCM ≤8.5V  
70  
70  
70  
70  
dB min  
CIN  
Common Mode Input  
Capacitance  
3.5  
95  
pF  
PSRR  
Power Supply Rejection  
Ratio  
VS= 2.5 V to 10V  
75  
75  
75  
75  
dB  
min  
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are specified by testing or statistical analysis unless otherwise specified.  
(3) Limits specified by design.  
4
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Product Folder Links: LMC6442  
LMC6442  
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SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
10V Electrical Characteristics (continued)  
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 10V, V− = 0V, VCM = VO = V +/2, and RL = 1 MΩ to V+/2.  
Boldface limits apply at the temperature extremes.  
LMC6442AI  
Limit  
LMC6442I  
Limit  
(1)  
Parameter  
Test Conditions  
Typ  
Units  
(2)  
(2)  
VCM  
Input Common-Mode  
Voltage Range  
8.85  
8.75  
8.85  
8.75  
V
min  
9.1  
CMRR ≥ 50 dB  
−0.4  
−0.2  
−0.2  
V
0
0
max  
(4)  
AV  
Large Signal Voltage Gain Sourcing  
120  
100  
104  
9.99  
dB  
(4)  
Sinking  
min  
VO = 0.5V to 9.5V  
80  
80  
(5)  
VO  
Output Swing  
VID = 100 mV  
9.97  
9.97  
V
9.97  
9.97  
min  
(5)  
VID = −100 mV  
22  
50  
50  
mV  
50  
50  
max  
(6) (5)  
(6) (5)  
ISC  
Output Short Circuit  
Current  
Sourcing, VID = 100 mV  
Sinking, VID = −100 mV  
RL = open  
2100  
900  
1200  
1000  
1200  
1000  
µA  
min  
600  
500  
600  
500  
IS  
Supply Current  
(2 amplifiers)  
1.90  
2.4  
3.0  
2.6  
3.2  
µA  
max  
AC Electrical Characteristics  
SR  
Slew Rate(7)  
4.1  
10.5  
68  
2.5  
2.5  
V/ms  
KHz  
GBWP  
φm  
Gain-Bandwidth Product  
Phase Margin  
(8)  
See  
deg  
en  
Input-Referred Voltage  
Noise  
RL = open  
f = 10 Hz  
170  
nV/√Hz  
in  
Input-Referred Current  
Noise  
RL = open  
f = 10 Hz  
0.0002  
85  
pA/√Hz  
(9)  
Crosstalk Rejection  
See  
dB  
(4) RL connected to V+/2. For Sourcing Test, VO > V+/2. For Sinking tests, VO < V+/2.  
(5) VID is differential input voltage referenced to inverting input.  
(6) Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.  
(7) Slew rate is the slower of the rising and falling slew rates.  
(8) See the Typical Performance Characteristics and Applications Information sections for more details.  
(9) Input referred, V+ = 10V and RL = 10 MΩ connected to 5V. Each amp excited in turn with 1 KHz to produce about 10 VPP output.  
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Typical Performance Characteristics  
VS = 5V, Single Supply, TA = 25°C unless otherwise specified  
Total Supply Current  
Total Supply Current  
vs.  
Supply Voltage (Negative Input Overdrive)  
vs.  
Supply Voltage  
Figure 2.  
Figure 3.  
Total Supply Current  
vs.  
Supply Voltage (Positive Input Overdrive)  
Input Bias Current  
vs.  
Temperature  
Figure 4.  
Figure .  
Offset Voltage  
vs.  
Common Mode Voltage (VS = 2.2V)  
Offset Voltage  
vs.  
Common Mode Voltage (VS = 5V)  
Figure 5.  
Figure 6.  
6
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SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
Typical Performance Characteristics (continued)  
VS = 5V, Single Supply, TA = 25°C unless otherwise specified  
Offset Voltage  
vs.  
Common Mode Voltage (VS = 10V)  
Swing Towards V−  
vs.  
Supply Voltage  
Figure 7.  
Figure 8.  
Swing Towards V+  
vs.  
Supply Voltage  
Swing From Rail(s)  
vs.  
Temperature  
Figure 9.  
Figure 10.  
Output Source Current  
vs.  
Output Sink Current  
vs.  
Output Voltage  
Output Voltage  
Figure 11.  
Figure 12.  
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Typical Performance Characteristics (continued)  
VS = 5V, Single Supply, TA = 25°C unless otherwise specified  
Maximum Output Voltage  
vs.  
Large Signal Voltage Gain  
vs.  
Load Resistance  
Supply Voltage  
Figure 13.  
Figure 14.  
Open Loop Gain/Phase  
Open Loop Gain/Phase  
vs.  
Frequency For Various CL (ZL = 1 MΩ II CL)  
vs.  
Frequency  
Figure 15.  
Figure 16.  
Open Loop Gain/Phase  
Gain Bandwidth Product  
vs.  
vs.  
Frequency For Various CL (ZL = 100 KΩ II CL)  
Supply Voltage  
Figure 17.  
Figure 18.  
8
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Typical Performance Characteristics (continued)  
VS = 5V, Single Supply, TA = 25°C unless otherwise specified  
Phase Margin (Worst Case)  
CMRR  
vs.  
Frequency  
vs.  
Supply Voltage  
Figure 19.  
Figure 20.  
PSRR  
vs.  
Frequency  
Positive Slew Rate  
vs.  
Supply Voltage  
Figure 21.  
Figure 22.  
Negative Slew Rate  
vs.  
Supply Voltage  
Cross-Talk Rejection  
vs.  
Frequency  
Figure 23.  
Figure 24.  
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Typical Performance Characteristics (continued)  
VS = 5V, Single Supply, TA = 25°C unless otherwise specified  
Input Voltage Noise  
vs.  
Output Impedance  
vs.  
Frequency  
Frequency  
Figure 25.  
Figure 26.  
THD+N  
vs.  
Frequency  
THD+N  
vs.  
Amplitude  
Figure 27.  
Figure 28.  
Maximum Output Swing  
vs.  
Small Signal Step Response  
(AV = +2) (CL = 12 pF, 100 pF)  
Frequency  
Figure 29.  
Figure 30.  
10  
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Typical Performance Characteristics (continued)  
VS = 5V, Single Supply, TA = 25°C unless otherwise specified  
Large Signal Step Response  
(AV = +2) (CL = 100 pF)  
Small Signal Step Response  
(AV = −1) (CL= 1MΩ II 100 pF, 200 pF)  
Figure 31.  
Figure 32.  
Small Signal Step Response  
(AV = +1) For Various CL  
Large Signal Step Response  
(AV = +1) (CL = 200 pF)  
Figure 33.  
Figure 34.  
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APPLICATIONS INFORMATION  
USING LMC6442 IN UNITY GAIN APPLICATIONS  
LMC6442 is optimized for maximum bandwidth and minimal external components when operating at a minimum  
closed loop gain of +2 (or −1). However, it is also possible to operate the device in a unity gain configuration by  
adding external compensation as shown in Figure 35:  
Figure 35. AV = +1 Operation by adding CC and RC  
Using this compensation technique it is possible to drive capacitive loads of up to 300 pF without causing  
oscillations (see the Typical Performance Characteristics for step response plots). This compensation can also  
be used with other gain settings in order to improve stability, especially when driving capacitive loads (for  
optimum performance, RC and CC may need to be adjusted).  
USING “T” NETWORK  
Compromises need to be made whenever high gain inverting stages need to achieve a high input impedance as  
well. This is especially important in low current applications which tend to deal with high resistance values. Using  
a traditional inverting amplifier, gain is inversely proportional to the resistor value tied between the inverting  
terminal and input while the input impedance is equal to this value. For example, in order to build an inverting  
amplifier with an input impedance of 10MΩ and a gain of 100, one needs to come up with a feedback resistor of  
1000 MΩ -an expensive task.  
An alternate solution is to use a “T” Network in the feedback path, as shown in Figure 36.  
Closed loop gain, AV is given by:  
(1)  
Figure 36. “T” Network Used to Replace High Value Resistor  
It must be noted, however, that using this scheme, the realizable bandwidth would be less than the theoretical  
maximum. With feedback factor, β, defined as:  
(2)  
BW(−3 dB) ≈ GBWP • β  
(3)  
In this case, assuming a GBWP of about 10 KHz, the expected BW would be around 50 Hz (vs. 100 Hz with the  
conventional inverting amplifier).  
12  
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Copyright © 1997–2013, Texas Instruments Incorporated  
Product Folder Links: LMC6442  
 
 
LMC6442  
www.ti.com  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
Looking at the problem from a different view, with RF defined by AV•Rin, one could select a value for R in the “T”  
Network and then determine R1 based on this selection:  
(4)  
Figure 37. “T” Network Values for Various Values of R  
For convenience, Figure 37 shows R1 vs. RF for different values of R.  
DESIGN CONSIDERATIONS FOR CAPACITIVE LOADS  
As with many other opamps, the LMC6442 is more stable at higher closed loop gains when driving a capacitive  
load. Figure 38 shows minimum closed loop gain versus load capacitance, to achieve less than 10% overshoot in  
the output small signal response. In addition, the LMC6442 is more stable when it provides more output current  
to the load and when its output voltage does not swing close to V−.  
The LMC6442 is more tolerant to capacitive loads when the equivalent output load resistance is lowered or when  
output voltage is 1V or greater from the V− supply. The capacitive load drive capability is also improved by  
adding an isolating resistor in series with the load and the output of the device. Figure 39 shows the value of this  
resistor for various capacitive loads (AV = −1), while limiting the output to less than 10 % overshoot.  
Referring to the Typical Performance Characteristics plot of Phase Margin (Worst Case) vs. Supply Voltage, note  
that Phase Margin increases as the equivalent output load resistance is lowered. This plot shows the expected  
Phase Margin when the device output is very close to V−, which is the least stable condition of operation.  
Comparing this Phase Margin value to the one read off the Open Loop Gain/Phase vs. Frequency plot, one can  
predict the improvement in Phase Margin if the output does not swing close to V−. This dependence of Phase  
Margin on output voltage is minimized as long as the output load, RL, is about 1MΩ or less.  
Output Phase Reversal: The LMC6442 is immune against this behavior even when the input voltages exceed  
the common mode voltage range.  
Output Time Delay: Due to the ultra low power consumption of the device, there could be as long as 2.5 ms of  
time delay from when power is applied to when the device output reaches its final value.  
Copyright © 1997–2013, Texas Instruments Incorporated  
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13  
Product Folder Links: LMC6442  
 
LMC6442  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
www.ti.com  
Figure 38. Minimum Operating Gain vs. Capacitive Load  
Figure 39. Isolating Resistor Value vs Capacitive Load  
14  
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Copyright © 1997–2013, Texas Instruments Incorporated  
Product Folder Links: LMC6442  
LMC6442  
www.ti.com  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
Application Circuits  
V + = 5V: IS < 10 µA, f/VC = 4.3 (Hz/V)  
Figure 40. Micropower Single Supply Voltage to Frequency Converter  
Figure 41. Gain Stage with Current Boosting  
Copyright © 1997–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Links: LMC6442  
LMC6442  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
www.ti.com  
Figure 42. Offset Nulling Schemes  
16  
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Copyright © 1997–2013, Texas Instruments Incorporated  
Product Folder Links: LMC6442  
 
LMC6442  
www.ti.com  
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013  
REVISION HISTORY  
Changes from Revision D (March 2013) to Revision E  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 16  
Copyright © 1997–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Links: LMC6442  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Jun-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LMC6442AIM/NOPB  
LMC6442AIMX/NOPB  
LMC6442IM/NOPB  
LMC6442IMX/NOPB  
LMC6442IN/NOPB  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
D
D
D
D
P
8
8
8
8
8
95  
RoHS & Green  
SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-NA-UNLIM  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
LMC64  
42AIM  
Samples  
Samples  
Samples  
Samples  
Samples  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
2500 RoHS & Green  
95 RoHS & Green  
2500 RoHS & Green  
40 RoHS & Green  
SN  
SN  
LMC64  
42AIM  
LMC64  
42IM  
Call TI | SN  
NIPDAU  
LMC64  
42IM  
LMC6442  
IN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Jun-2023  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Feb-2022  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LMC6442AIMX/NOPB  
LMC6442IMX/NOPB  
SOIC  
SOIC  
D
D
8
8
2500  
2500  
330.0  
330.0  
12.4  
12.4  
6.5  
6.5  
5.4  
5.4  
2.0  
2.0  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Feb-2022  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LMC6442AIMX/NOPB  
LMC6442IMX/NOPB  
SOIC  
SOIC  
D
D
8
8
2500  
2500  
367.0  
367.0  
367.0  
367.0  
35.0  
35.0  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Feb-2022  
TUBE  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
LMC6442AIM/NOPB  
LMC6442IM/NOPB  
LMC6442IN/NOPB  
D
D
P
SOIC  
SOIC  
PDIP  
8
8
8
95  
95  
40  
495  
495  
502  
8
8
4064  
4064  
3.05  
3.05  
4.32  
14  
11938  
Pack Materials-Page 3  
PACKAGE OUTLINE  
D0008A  
SOIC - 1.75 mm max height  
SCALE 2.800  
SMALL OUTLINE INTEGRATED CIRCUIT  
C
SEATING PLANE  
.228-.244 TYP  
[5.80-6.19]  
.004 [0.1] C  
A
PIN 1 ID AREA  
6X .050  
[1.27]  
8
1
2X  
.189-.197  
[4.81-5.00]  
NOTE 3  
.150  
[3.81]  
4X (0 -15 )  
4
5
8X .012-.020  
[0.31-0.51]  
B
.150-.157  
[3.81-3.98]  
NOTE 4  
.069 MAX  
[1.75]  
.010 [0.25]  
C A B  
.005-.010 TYP  
[0.13-0.25]  
4X (0 -15 )  
SEE DETAIL A  
.010  
[0.25]  
.004-.010  
[0.11-0.25]  
0 - 8  
.016-.050  
[0.41-1.27]  
DETAIL A  
TYPICAL  
(.041)  
[1.04]  
4214825/C 02/2019  
NOTES:  
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.  
Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed .006 [0.15] per side.  
4. This dimension does not include interlead flash.  
5. Reference JEDEC registration MS-012, variation AA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
SEE  
DETAILS  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED  
METAL  
EXPOSED  
METAL  
.0028 MAX  
[0.07]  
.0028 MIN  
[0.07]  
ALL AROUND  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4214825/C 02/2019  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
SOLDER PASTE EXAMPLE  
BASED ON .005 INCH [0.125 MM] THICK STENCIL  
SCALE:8X  
4214825/C 02/2019  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023, Texas Instruments Incorporated  

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