LMC6482IN/NOPB [TI]
超低偏置电流、精密 CMOS 轨到轨输入和输出双路运算放大器 | P | 8 | -40 to 85;
| 型号： | LMC6482IN/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低偏置电流、精密 CMOS 轨到轨输入和输出双路运算放大器 | P | 8 | -40 to 85 放大器 光电二极管 运算放大器 放大器电路 |
| 文件： | 总35页 (文件大小：2760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMC6482
www.ti.com
SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
LMC6482 CMOS Dual Rail-To-Rail Input and Output Operational Amplifier
Check for Samples: LMC6482
1
FEATURES
APPLICATIONS
2
•
•
(Typical Unless Otherwise Noted)
•
•
•
•
•
Data Acquisition Systems
Transducer Amplifiers
Rail-to-Rail Input Common-Mode Voltage
Range (Ensured Over Temperature)
Hand-held Analytic Instruments
Medical Instrumentation
•
Rail-to-Rail Output Swing (within 20mV of
Supply Rail, 100kΩ Load)
Active Filter, Peak Detector, Sample and Hold,
pH Meter, Current Source
•
•
•
•
•
•
Ensured 3V, 5V and 15V Performance
Excellent CMRR and PSRR: 82dB
Ultra Low Input Current: 20fA
•
Improved Replacement for TLC272, TLC277
High Voltage Gain (RL = 500kΩ): 130dB
Specified for 2kΩ and 600Ω Loads
Available in VSSOP Package
DESCRIPTION
The LMC6482 provides a common-mode range that extends to both supply rails. This rail-to-rail performance
combined with excellent accuracy, due to a high CMRR, makes it unique among rail-to-rail input amplifiers.
It is ideal for systems, such as data acquisition, that require a large input signal range. The LMC6482 is also an
excellent upgrade for circuits using limited common-mode range amplifiers such as the TLC272 and TLC277.
Maximum dynamic signal range is assured in low voltage and single supply systems by the LMC6482's rail-to-rail
output swing. The LMC6482's rail-to-rail output swing is ensured for loads down to 600Ω.
Ensured low voltage characteristics and low power dissipation make the LMC6482 especially well-suited for
battery-operated systems.
LMC6482 is also available in VSSOP package which is almost half the size of a SOIC-8 device.
See the LMC6484 data sheet for a Quad CMOS operational amplifier with these same features.
3V Single Supply Buffer Circuit
Figure 1. Rail-To-Rail Input
Figure 2.
Figure 3. Rail-To-Rail Output
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2013, Texas Instruments Incorporated
LMC6482
SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
www.ti.com
Connection Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
(3)
ESD Tolerance
1.5kV
±Supply Voltage
(V+) +0.3V, (V−) −0.3V
16V
Differential Input Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
(4)
Current at Input Pin
±5mA
(5) (6)
Current at Output Pin
±30mA
Current at Power Supply Pin
Lead Temperature (Soldering, 10 sec.)
Storage Temperature Range
40mA
260°C
−65°C to +150°C
150°C
(7)
Junction Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human body model, 1.5kΩ in series with 100pF. All pins rated per method 3015.6 of MIL-STD-883. This is a Class 1 device rating.
(4) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
(6) Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
(7) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings
Supply Voltage
3.0V ≤ V+ ≤ 15.5V
Junction Temperature Range
LMC6482AM
−55°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +85°C
LMC6482AI, LMC6482I
Thermal Resistance (θJA
)
P0008E Package, 8-Pin PDIP
D0008A Package, 8-Pin SOIC
DGK0008A Package, 8-Pin VSSOP
90°C/W
155°C/W
194°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
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DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits
apply at the temperature extremes.
LMC6482AI
LMC6482I
LMC6482M
Typ
Parameter
Test Conditions
Limit
Limit
Limit
Units
(1)
(2)
(2)
(2)
VOS
Input Offset Voltage
0.11
0.750
3.0
3.0
mV
1.35
3.7
3.8
max
TCVOS Input Offset Voltage
Average Drift
1.0
μV/°C
(3)
(3)
IB
Input Current
0.02
4.0
2.0
4.0
2.0
10.0
5.0
pA
max
pA
IOS
Input Offset Current
0.01
max
CIN
RIN
Common-Mode Input
Capacitance
3
pF
Input Resistance
>10
82
TeraΩ
CMRR Common Mode Rejection
Ratio
0V ≤ VCM ≤ 15.0V
70
67
65
62
65
60
dB
min
V+ = 15V
0V ≤ VCM ≤ 5.0V
82
82
70
65
65
V+ = 5V
67
62
60
+PSRR Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V, V− = 0V
70
65
65
dB
min
dB
VO = 2.5V
67
62
60
−PSRR Negative Power Supply
−5V ≤ V− ≤ −15V, V+ = 0V
VO = −2.5V
82
70
65
65
Rejection Ratio
67
62
60
min
V
VCM
Input Common-Mode
Voltage Range
V+ = 5V and 15V
For CMRR ≥ 50dB
V− − 0.3
V+ + 0.3V
666
− 0.25
− 0.25
− 0.25
0
0
0
max
V
V+ + 0.25
V+
V+ + 0.25
V+
V+ + 0.25
V+
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
(4) (5)
AV
Large Signal Voltage Gain RL = 2kΩ
Sourcing
Sinking
140
84
120
72
120
60
75
35
35
35
20
20
18
(4) (5)
RL = 600Ω
Sourcing
Sinking
300
80
50
50
48
30
25
35
20
15
15
13
10
8
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
(4) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 3.5V ≤ VO ≤ 7.5V.
(5) Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits
apply at the temperature extremes.
LMC6482AI
LMC6482I
LMC6482M
Typ
Parameter
Test Conditions
Limit
Limit
Limit
Units
(1)
(2)
(2)
(2)
VO
Output Swing
V+ = 5V
4.9
0.1
4.7
0.3
14.7
0.16
14.1
0.5
20
4.8
4.7
0.18
0.24
4.5
4.24
0.5
0.65
14.4
14.2
0.32
0.45
13.4
13.0
1.0
1.3
16
4.8
4.7
0.18
0.24
4.5
4.24
0.5
0.65
14.4
14.2
0.32
0.45
13.4
13.0
1.0
1.3
16
4.8
4.7
0.18
0.24
4.5
4.24
0.5
0.65
14.4
14.2
0.32
0.45
13.4
13.0
1.0
1.3
16
V
RL = 2kΩ to V+/2
min
V
max
V
V+ = 5V
RL = 600Ω to V+/2
min
V
max
V
V+ = 15V
RL = 2kΩ to V+/2
min
V
max
V
V+ = 15V
RL = 600Ω to V+/2
min
V
max
mA
min
mA
min
mA
min
mA
min
mA
max
mA
max
ISC
ISC
IS
Output Short Circuit
Current
Sourcing, VO = 0V
Sinking, VO = 5V
Sourcing, VO = 0V
Sinking, VO = 12V
Both Amplifiers
12
12
10
V+ = 5V
15
11
11
11
9.5
28
9.5
28
8.0
28
Output Short Circuit
Current
30
22
22
20
V+ = 15V
(6)
30
30
30
30
24
24
22
Supply Current
1.0
1.3
1.4
1.8
1.6
1.9
1.4
1.8
1.6
1.9
1.4
1.9
1.6
2.0
V+ = +5V, VO = V+/2
Both Amplifiers
V+ = 15V, VO = V+/2
(6) Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1M. Boldface limits
apply at the temperature extremes.
LMC6482AI
LMC6482I LMC6482M
Typ
Parameter
Test Conditions
Limit
Limit
Limit
Units
(1)
(2)
(2)
(2)
(3)
SR
Slew Rate
1.3
1.0
0.9
0.9
V/μs
min
0.7
0.63
0.54
GBW
Gain-Bandwidth Product
Phase Margin
V+ = 15V
1.5
50
MHz
Deg
φm
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of either the positive or negative slew
rates.
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AC Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1M. Boldface limits
apply at the temperature extremes.
LMC6482AI
LMC6482I LMC6482M
Typ
Parameter
Test Conditions
Limit
Limit
Limit
Units
(1)
(2)
(2)
(2)
Gm
en
Gain Margin
15
150
37
dB
dB
(4)
Amp-to-Amp Isolation
Input-Referred Voltage Noise
F = 1kHz
Vcm = 1V
nV/√Hz
pA/√Hz
%
In
Input-Referred Current Noise
Total Harmonic Distortion
F = 1kHz
0.03
0.01
T.H.D.
F = 10kHz, AV = −2
RL = 10kΩ, VO = 4.1 VPP
F = 10kHz, AV = −2
RL = 10kΩ, VO = 8.5 VPP
V+ = 10V
0.01
%
(4) Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP
.
DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M.
LMC6482AI
LMC6482I
LMC6482M
Typ
Parameter
Test Conditions
Limit
Limit
Limit
Units
(1)
(2)
(2)
(2)
VOS
Input Offset Voltage
0.9
2.0
3.0
3.0
mV
2.7
3.7
3.8
max
TCVOS
Input Offset Voltage
Average Drift
2.0
μV/°C
IB
Input Bias Current
Input Offset Current
0.02
0.01
74
pA
pA
IOS
CMRR
Common Mode Rejection 0V ≤ VCM ≤ 3V
Ratio
Power Supply Rejection 3V ≤ V+ ≤ 15V, V− = 0V
Ratio
64
68
0
60
60
0
60
60
0
dB
min
PSRR
VCM
80
dB
min
Input Common-Mode
Voltage Range
For CMRR ≥ 50dB
V− −0.25
V+ + 0.25
V
max
V+
V+
V+
V
min
VO
Output Swing
RL = 2kΩ to V+/2
RL = 600Ω to V+/2
2.8
0.2
2.7
V
V
2.5
0.6
2.5
0.6
2.5
0.6
V
min
0.37
V
max
IS
Supply Current
Both Amplifiers
0.825
1.2
1.2
1.2
mA
1.5
1.5
1.6
max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
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AC Electrical Characteristics
Unless otherwise specified, V+ = 3V, V− = 0V, VCM = VO = V+/2, and RL > 1M.
LMC6482AI
Limit(2)
LMC6482I LMC6482M
Limit(2) Limit(2)
Parameter
Test Conditions
Typ(1)
Units
(3)
SR
Slew Rate
0.9
1.0
V/μs
GBW
T.H.D.
Gain-Bandwidth Product
Total Harmonic Distortion
MHz
F = 10kHz, AV = −2
RL = 10kΩ, VO = 2 VPP
0.01
%
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Connected as voltage Follower with 2V step input. Number specified is the slower of either the positive or negative slew rates.
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SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Supply Current vs. Supply Voltage
Input Current vs. Temperature
Figure 4.
Figure 5.
Sourcing Current vs. Output Voltage
Sourcing Current vs. Output Voltage
Figure 6.
Figure 7.
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Sinking Current vs. Output Voltage
Sinking Current vs. Output Voltage
Figure 10.
Figure 11.
Output Voltage Swing vs. Supply Voltage
Input Voltage Noise vs. Frequency
Figure 12.
Figure 13.
Input Voltage Noise vs. Input Voltage
Input Voltage Noise vs. Input Voltage
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Input Voltage Noise vs. Input Voltage
Crosstalk Rejection vs. Frequency
Figure 16.
Figure 17.
Crosstalk Rejection vs. Frequency
Positive PSRR vs. Frequency
Figure 18.
Figure 19.
Negative PSRR vs. Frequency
CMRR vs. Frequency
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
CMRR vs. Input Voltage
CMRR vs. Input Voltage
Figure 22.
Figure 23.
CMRR vs. Input Voltage
ΔVOS vs. CMR
Figure 24.
Figure 25.
ΔVOS vs. CMR
Input Voltage vs. Output Voltage
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Input Voltage vs. Output Voltage
Open Loop Frequency Response
Figure 28.
Figure 29.
Open Loop Frequency Response
Open Loop Frequency Response vs. Temperature
Figure 30.
Figure 31.
Maximum Output Swing vs. Frequency
Gain and Phase vs. Capacitive Load
Figure 32.
Figure 33.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Gain and Phase
Open Loop Output Impedance
vs.
vs.
Capacitive Load
Frequency
Figure 34.
Figure 35.
Open Loop Output Impedance
Slew Rate
vs.
Supply Voltage
vs.
Frequency
Figure 36.
Figure 37.
Non-Inverting Large Signal Pulse Response
Non-Inverting Large Signal Pulse Response
Figure 38.
Figure 39.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Non-Inverting Large Signal Pulse Response
Non-Inverting Small Signal Pulse Response
Figure 40.
Figure 41.
Non-Inverting Small Signal Pulse Response
Non-Inverting Small Signal Pulse Response
Figure 42.
Figure 43.
Inverting Large Signal Pulse Response
Inverting Large Signal Pulse Response
Figure 44.
Figure 45.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Inverting Large Signal Pulse Response
Inverting Small Signal Pulse Response
Figure 46.
Figure 47.
Inverting Small Signal Pulse Response
Inverting Small Signal Pulse Response
Figure 48.
Figure 49.
Stability
vs.
Capacitive Load
Stability
vs.
Capacitive Load
Figure 50.
Figure 51.
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Typical Performance Characteristics (continued)
VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Stability
Stability
vs.
Capacitive Load
vs.
Capacitive Load
Figure 52.
Figure 53.
Stability
vs.
Capacitive Load
Stability
vs.
Capacitive Load
Figure 54.
Figure 55.
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APPLICATION INFORMATION
AMPLIFIER TOPOLOGY
The LMC6482 incorporates specially designed wide-compliance range current mirrors and the body effect to
extend input common mode range to each supply rail. Complementary paralleled differential input stages, like the
type used in other CMOS and bipolar rail-to-rail input amplifiers, were not used because of their inherent
accuracy problems due to CMRR, cross-over distortion, and open-loop gain variation.
The LMC6482's input stage design is complemented by an output stage capable of rail-to-rail output swing even
when driving a large load. Rail-to-rail output swing is obtained by taking the output directly from the internal
integrator instead of an output buffer stage.
INPUT COMMON-MODE VOLTAGE RANGE
Unlike Bi-FET amplifier designs, the LMC6482 does not exhibit phase inversion when an input voltage exceeds
the negative supply voltage. Figure 56 shows an input voltage exceeding both supplies with no resulting phase
inversion on the output.
An input voltage signal exceeds the lmc6482 power supply voltages with no output phase inversion.
Figure 56. Input Voltage
The absolute maximum input voltage is 300mV beyond either supply rail at room temperature. Voltages greatly
exceeding this absolute maximum rating, as in Figure 57, can cause excessive current to flow in or out of the
input pins possibly affecting reliability.
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A ±7.5V input signal greatly exceeds the 3V supply in Figure 58 causing no phase inversion due to RI.
Figure 57. Input Signal
Applications that exceed this rating must externally limit the maximum input current to ±5mA with an input
resistor (RI) as shown in Figure 58.
RI input current protection for voltages exceeding the supply voltages.
Figure 58. RI Input Current Protection for
Voltages Exceeding the Supply Voltages
RAIL-TO-RAIL OUTPUT
The approximated output resistance of the LMC6482 is 180Ω sourcing and 130Ω sinking at VS = 3V and 110Ω
sourcing and 80Ω sinking at Vs = 5V. Using the calculated output resistance, maximum output voltage swing can
be estimated as a function of load.
CAPACITIVE LOAD TOLERANCE
The LMC6482 can typically directly drive a 100pF load with VS = 15V at unity gain without oscillating. The unity
gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op-amps.
The combination of the op-amp's output impedance and the capacitive load induces phase lag. This results in
either an under damped pulse response or oscillation.
Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 59. This simple
technique is useful for isolating the capacitive inputs of multiplexers and A/D converters.
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Figure 59. Resistive Isolation of a 330pF Capacitive Load
Figure 60. Pulse Response of the LMC6482 Circuit in Figure 59
Improved frequency response is achieved by indirectly driving capacitive loads, as shown in Figure 61.
Compensated to handle a 330pF capacitive load.
Figure 61. LMC6482 Noninverting Amplifier
R1 and C1 serve to counteract the loss of phase margin by feeding forward the high frequency component of the
output signal back to the amplifiers inverting input, thereby preserving phase margin in the overall feedback loop.
The values of R1 and C1 are experimentally determined for the desired pulse response. The resulting pulse
response can be seen in Figure 62.
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Figure 62. Pulse Response of
LMC6482 Circuit in Figure 61
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance with amplifiers that have ultra-low input current,
like the LMC6482. Large feedback resistors can react with small values of input capacitance due to transducers,
photo diodes, and circuits board parasitics to reduce phase margins.
Figure 63. Canceling the Effect of Input Capacitance
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The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor
(as in Figure 63), Cf, is first estimated by:
(1)
or
R1 CIN ≤ R2 Cf
(2)
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or smaller than that of a bread-board, so the actual
optimum value for Cf may be different. The values of Cf should be checked on the actual circuit. (Refer to the
LMC660 quad CMOS amplifier data sheet for a more detailed discussion.)
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low input current of the
LMC6482, typically less than 20fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even through it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LM6482's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs, as in Figure 64. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5pA if the trace
were a 5V bus adjacent to the pad of the input. This would cause a 250 times degradation from the LMC6482's
actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω
would cause only 0.05pA of leakage current. See Figure 65 through Figure 67 for typical connections of guard
rings for standard op-amp configurations.
Figure 64. Example of Guard Ring in P.C. Board Layout Typical Connections of Guard Rings
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SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
Figure 65. Inverting Amplifier Typical Connections of Guard Rings
Figure 66. Non-Inverting Amplifier Typical Connections of Guard Rings
Figure 67. Follower Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 68.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 68. Air Wiring
OFFSET VOLTAGE ADJUSTMENT
Offset voltage adjustment circuits are illustrated in Figure 69 and Figure 70. Large value resistances and
potentiometers are used to reduce power consumption while providing typically ±2.5mV of adjustment range,
referred to the input, for both configurations with VS = ±5V.
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V+
R4
R3
5V
500 kW
1 kW
V
IN
-
1
LMC6482
-5V
V
OUT
2
1 MW
+
499W
500 kW
V
OUT
R4
R3
= -
V-
V
IN
V-
Figure 69. Inverting Configuration Offset Voltage Adjustment
Figure 70. Non-Inverting Configuration Offset Voltage Adjustment
UPGRADING APPLICATIONS
The LMC6484 quads and LMC6482 duals have industry standard pin outs to retrofit existing applications.
System performance can be greatly increased by the LMC6482's features. The key benefit of designing in the
LMC6482 is increased linear signal range. Most op-amps have limited input common mode ranges. Signals that
exceed this range generate a non-linear output response that persists long after the input signal returns to the
common mode range.
Linear signal range is vital in applications such as filters where signal peaking can exceed input common mode
ranges resulting in output phase inversion or severe distortion.
DATA ACQUISITION SYSTEMS
Low power, single supply data acquisition system solutions are provided by buffering the ADC12038 with the
LMC6482 (Figure 71). Capable of using the full supply range, the LMC6482 does not require input signals to be
scaled down to meet limited common mode voltage ranges. The LMC4282 CMRR of 82dB maintains integral
linearity of a 12-bit data acquisition system to ±0.325 LSB. Other rail-to-rail input amplifiers with only 50dB of
CMRR will degrade the accuracy of the data acquisition system to only 8 bits.
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LMC6482
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SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
Operating from the same supply voltage, the LMC6482 buffers the ADC12038 maintaining excellent accuracy.
Figure 71. Buffering the ADC12038 with the LMC6482
INSTRUMENTATION CIRCUITS
The LMC6482 has the high input impedance, large common-mode range and high CMRR needed for designing
instrumentation circuits. Instrumentation circuits designed with the LMC6482 can reject a larger range of
common-mode signals than most in-amps. This makes instrumentation circuits designed with the LMC6482 an
excellent choice of noisy or industrial environments. Other applications that benefit from these features include
analytic medical instruments, magnetic field detectors, gas detectors, and silicon-based transducers.
A small valued potentiometer is used in series with Rg to set the differential gain of the 3 op-amp instrumentation
circuit in Figure 72. This combination is used instead of one large valued potentiometer to increase gain trim
accuracy and reduce error due to vibration.
Figure 72. Low Power 3 Op-Amp Instrumentation Amplifier
A 2 op-amp instrumentation amplifier designed for a gain of 100 is shown in Figure 73. Low sensitivity trimming
is made for offset voltage, CMRR and gain. Low cost and low power consumption are the main advantages of
this two op-amp circuit.
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Higher frequency and larger common-mode range applications are best facilitated by a three op-amp
instrumentation amplifier.
Figure 73. Low-Power Two-Op-Amp Instrumentation Amplifier
SPICE MACROMODEL
A spice macromodel is available for the LMC6482. This model includes accurate simulation of:
•
•
•
•
•
Input common-mode voltage range
Frequency and transient response
GBW dependence on loading conditions
Quiescent and dynamic supply current
Output swing dependence on loading conditions
and many more characteristics as listed on the macromodel disk.
Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk.
Typical Single-Supply Applications
Figure 74. Half-Wave Rectifier with Input Current Protection (RI)
Figure 75. Half-Wave Rectifier Waveform
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SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
The circuit in Figure 74 uses a single supply to half wave rectify a sinusoid centered about ground. RI limits
current into the amplifier caused by the input voltage exceeding the supply voltage. Full wave rectification is
provided by the circuit in Figure 76.
Figure 76. Full Wave Rectifier with Input Current Protection (RI)
Figure 77. Full Wave Rectifier Waveform
Figure 78. Large Compliance Range Current Source
Figure 79. Positive Supply Current Sense
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Figure 80. Low Voltage Peak Detector with Rail-to-Rail Peak Capture Range
In Figure 80 dielectric absorption and leakage is minimized by using a polystyrene or polyethylene hold
capacitor. The droop rate is primarily determined by the value of CH and diode leakage current. The ultra-low
input current of the LMC6482 has a negligible effect on droop.
Figure 81. Rail-to-Rail Sample and Hold
The LMC6482's high CMRR (82dB) allows excellent accuracy throughout the circuit's rail-to-rail dynamic capture
range.
Figure 82. Rail-to-Rail Single Supply Low Pass Filter
The low pass filter circuit in Figure 82 can be used as an anti-aliasing filter with the same voltage supply as the
A/D converter.
Filter designs can also take advantage of the LMC6482 ultra-low input current. The ultra-low input current yields
negligible offset error even when large value resistors are used. This in turn allows the use of smaller valued
capacitors which take less board space and cost less.
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SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 26
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
LMC6482AIM
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
8
8
8
8
8
8
8
8
95
TBD
Call TI
SN | CU SN
Call TI
Call TI
Level-1-260C-UNLIM
Call TI
LMC64
82AIM
LMC6482AIM/NOPB
LMC6482AIMX
ACTIVE
NRND
D
D
D
P
P
D
D
95
2500
2500
40
Green (RoHS
& no Sb/Br)
LMC64
82AIM
TBD
LMC64
82AIM
LMC6482AIMX/NOPB
LMC6482AIN
ACTIVE
NRND
Green (RoHS
& no Sb/Br)
SN | CU SN
Call TI
Level-1-260C-UNLIM
Call TI
LMC64
82AIM
TBD
LMC64
82AIN
LMC6482AIN/NOPB
LMC6482IM
ACTIVE
NRND
40
Green (RoHS
& no Sb/Br)
SN | CU SN
Call TI
Level-1-NA-UNLIM
Call TI
LMC64
82AIN
95
TBD
LMC64
82IM
LMC6482IM/NOPB
ACTIVE
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
LMC64
82IM
LMC6482IMM
NRND
VSSOP
VSSOP
DGK
DGK
8
8
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
A10
A10
LMC6482IMM/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LMC6482IMMX
NRND
VSSOP
VSSOP
DGK
DGK
8
8
3500
3500
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
A10
A10
LMC6482IMMX/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LMC6482IMX
NRND
SOIC
SOIC
D
D
8
8
2500
2500
TBD
Call TI
Call TI
-40 to 85
-40 to 85
LMC64
82IM
LMC6482IMX/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
LMC64
82IM
LMC6482IN
NRND
PDIP
PDIP
P
P
8
8
40
40
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
LMC6482IN
LMC6482IN
LMC6482IN/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC6482AIMX
LMC6482AIMX/NOPB
LMC6482IMM
SOIC
SOIC
D
D
8
8
8
8
8
8
8
8
2500
2500
1000
1000
3500
3500
2500
2500
330.0
330.0
178.0
178.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.5
6.5
5.3
5.3
5.3
5.3
6.5
6.5
5.4
5.4
3.4
3.4
3.4
3.4
5.4
5.4
2.0
2.0
1.4
1.4
1.4
1.4
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
LMC6482IMM/NOPB
LMC6482IMMX
LMC6482IMMX/NOPB
LMC6482IMX
LMC6482IMX/NOPB
SOIC
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMC6482AIMX
LMC6482AIMX/NOPB
LMC6482IMM
SOIC
SOIC
D
D
8
8
8
8
8
8
8
8
2500
2500
1000
1000
3500
3500
2500
2500
367.0
367.0
210.0
210.0
367.0
367.0
367.0
367.0
367.0
367.0
185.0
185.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
LMC6482IMM/NOPB
LMC6482IMMX
LMC6482IMMX/NOPB
LMC6482IMX
LMC6482IMX/NOPB
SOIC
D
Pack Materials-Page 2
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