LMC6572AIMX [TI]
DUAL OP-AMP, 3500uV OFFSET-MAX, 0.22MHz BAND WIDTH, PDSO8, SO-8;
| 型号： | LMC6572AIMX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL OP-AMP, 3500uV OFFSET-MAX, 0.22MHz BAND WIDTH, PDSO8, SO-8 放大器 光电二极管 |
| 文件： | 总22页 (文件大小：1192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMC6572, LMC6574
www.ti.com
SNOS707D –DECEMBER 1996–REVISED MARCH 2013
LMC6572/LMC6574 Dual and Quad Low Voltage (2.7V and 3V) Operational Amplifier
Check for Samples: LMC6572, LMC6574
1
FEATURES
DESCRIPTION
Low voltage operation and low power dissipation
make the LMC6574/2 ideal for battery-powered
systems.
2
•
(Typical Unless Otherwise Noted)
•
•
Guaranteed 2.7V and 3V Performance
Rail-to-Rail Output Swing (Within 5 mV of
Supply Rail, 100 kΩ Load)
3V amplifier performance is backed by 2.7V
guarantees to ensure operation throughout battery
lifetime. These guarantees also enable analog circuits
to operate from the same 3.3V supply used for digital
logic.
•
•
•
•
Ultra-Low Supply Current: 40 μA/Amplifier
Low Cost
Ultra-Low Input Current: 20 fA
Battery life is maximized because each amplifier
dissipates only micro-watts of power.
High Voltage Gain @ VS=2.7V,
RL=100 kΩ: 120 dB
•
•
Specified for 100 kΩ and 5 kΩ Loads
The LMC6574/2 does not sacrifice functionality for
low voltage operation. The LMC6574/2 generates
120 dB of open-loop gain just like a conventional
amplifier, but the LMC6574/2 can do this from a 2.7V
supply.
Available in VSSOP Package
APPLICATIONS
•
•
•
•
•
•
Transducer Amplifier
These amplifiers are designed with features that
optimize low voltage operation. The output voltage
swings rail-to-rail to maximize signal-to-noise ratio
and dynamic signal range. The common-mode input
voltage range extends from 800 mV below the
positive supply to 100 mV below ground.
Portable or Remote Equipment
Battery-Operated Instruments
Data Acquisition Systems
Medical Instrumentation
Improved Replacement for TLV2322 and
TLV2324
This device is built with Texas Instruments' advanced
Double-Poly Silicon-Gate CMOS process.
LMC6572 is also available in VSSOP package which
is almost half the size of a SOIC-8 device.
Connection Diagram
Figure 1. 8-Pin PDIP/SOIC/VSSOP Package
See Package Number P, D, or DGK
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2013, Texas Instruments Incorporated
LMC6572, LMC6574
SNOS707D –DECEMBER 1996–REVISED MARCH 2013
www.ti.com
Figure 2. 14-Pin PDIP/SOIC Package
See Package Number NFF or D
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3)
2000V
±Supply Voltage
(V+) +0.3V, (V−) −0.3V
12V
Differential Input Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
Current at Input Pin
±5 mA
Current at Output Pin(4)
±10 mA
Current at Power Supply Pin
Lead Temperature (Soldering, 10 Seconds)
Storage Temperature Range
Junction Temperature(5)
35 mA
260°C
−65°C to +150°C
150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5 kΩ in series with 100 pF.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(Max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings(1)
Supply Voltage
2.7V ≤ V+ ≤ 11V
−40°C ≤ TJ ≤ +85°C
−40°C ≤ TJ ≤ +85°C
115°C/W
Junction Temperature Range
LMC6572AI, LMC6572BI
LMC6574AI, LMC6574BI
P Package, 8-Pin PDIP
D Package, 8-Pin SOIC
DGK Package, 8-Pin VSSOP
NFF Package, 14-Pin PDIP
D Package, 14-Pin SOIC
Thermal Resistance (θJA
)
193°C/W
217°C/W
81°C/W
126°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
2
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
2.7V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1MΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ(1)
LMC6574AI LMC6574BI
LMC6572AI LMC6572BI
Units
Limit(2)
Limit(2)
VOS
Input Offset Voltage
V+ = 2.7V and 3V
0.5
3
7
mV
Max
3.5
7.5
TCVOS
IB
Input Offset Voltage Average
Drift
1.5
μV/°C
Input Current
0.02
pA
Max
pA
10
6
10
6
IOS
Input Offset Current
Input Resistance
0.01
Max
Tera Ω
pF
RIN
CIN
>1
3
Common-Mode Input
Capacitance
CMRR
+PSRR
−PSRR
VCM
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 3.5V V+ = 5V
75
75
63
60
60
57
dB
Min
dB
Positive Power Supply
Rejection Ratio
2.7V ≤ V+ ≤ 5V, V− = 0V
67
60
65
58
Min
dB
Negative Power Supply
Rejection Ratio
−2.7V ≤ V− ≤ −5V, V+ = 0V
V+ = 2.7V and 3V for CMRR ≥ 50 dB
83
75
67
73
65
Min
V
Input Common-Mode
Voltage Range
−0.1
V+ − 0.8
−0.05
0
V+ − 1.0
V+ − 1.3
−0.05
0
V+ − 1.0
V+ − 1.3
Max
V
Min
V/mV
V/mV
V
AV
VO
Large Signal Voltage Gain
Output Swing
RL = 100 kΩ(3)
Sourcing
Sinking
1000
500
V+ = 2.7V
2.695
2.68
2.66
0.03
0.05
2.55
2.45
0.15
0.25
2.98
2.96
0.03
0.05
2.85
2.75
0.15
0.25
2.65
2.62
0.06
0.09
2.45
2.35
0.25
0.35
2.95
2.93
0.06
0.09
2.75
2.65
0.25
0.35
RL = 100 kΩ to V+/2
Min
V
0.005
2.66
Max
V
V+ = 2.7V
RL = 5 kΩ to V+/2
Min
V
0.04
Max
V
V+ = 3V
2.995
0.005
2.96
RL = 100 kΩ to V+/2
Min
V
Max
V
V+ = 3V
RL = 5 kΩ to V+/2
Min
V
0.04
Max
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) V+ = 3V, VCM = 1.5V and RL connected to 1.5V. For Sourcing tests, 1.5V ≤ VO ≤ 2.5V. For Sinking tests, 0.5V ≤ VO ≤ 1.5V.
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2.7V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1MΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ(1)
LMC6574AI LMC6574BI
LMC6572AI LMC6572BI
Units
Limit(2)
4.0
Limit(2)
3.0
ISC
Output Short Circuit Current Sourcing, VO = 0V
Sinking, VO = 2.7V
6.0
4.0
160
160
80
mA
Min
mA
Min
μA
3.0
2.0
3.0
2.5
2.0
1.5
IS
Supply Current
Quad Package
240
280
240
280
120
140
120
140
240
280
240
280
120
140
120
140
V+ = +2.7V, VO = V+/2
Max
μA
Quad Package
V+ = +3V, VO = V+/2
Max
μA
Dual Package
V+ = +2.7V, VO = V+/2
Max
μA
Dual Package
80
V+ = +3V, VO = V+/2
Max
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ(1)
LMC6574AI
LMC6572AI
Limit(2)
LMC6574BI
LMC6572BI
Limit(2)
Units
SR
Slew Rate
V+ = 2.7V and 3V(3)
90
30
30
V/ms
Min
MHz
Deg
dB
10
10
GBW
φm
Gain-Bandwidth Product
Phase Margin
V+ = 3V
See(4)
0.22
60
Gm
Gain Margin
12
Amp-to-Amp Isolation
Input-Referred Voltage Noise
120
45
dB
en
F = 1 kHz
VCM = 1V
nV/√Hz
pA/√Hz
%
in
Input-Referred Current Noise
Total Harmonic Distortion
F = 1 kHz
0.002
0.05
T.H.D.
F = 10 kHz, AV = −2
RL = 10 kΩ, VO = 1.0 VPP
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Connected as Voltage Follower with 1.0V step input. Number specified is the slower of the positive and negative slew rates.
(4) Input referred, V+ = 3V and RL = 100 kΩ connected to 1.5V. Each amp excited in turn with 1 KHz to produce VO = 2 VPP
.
4
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Typical Performance Characteristics
VS = +3V, TA = 25°C, Unless otherwise specified
Supply Current vs
Supply Voltage (Dual Package)
Input Current vs
Temperature
Figure 3.
Figure 4.
Sourcing Current vs
Output Voltage
Sinking Current vs
Output Voltage
Figure 5.
Figure 6.
Output Voltage Swing vs
Supply Voltage
Input Voltage Noise vs
Frequency
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VS = +3V, TA = 25°C, Unless otherwise specified
Crosstalk Rejection vs
Positive PSRR vs
Frequency
Frequency
Figure 9.
Figure 10.
CMRR
vs
Frequency
Negative PSRR vs
Frequency
Figure 11.
Figure 12.
Input Voltage vs
Output Voltage (VS = ±1.5)
Open Loop Frequency
Response
Figure 13.
Figure 14.
6
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Typical Performance Characteristics (continued)
VS = +3V, TA = 25°C, Unless otherwise specified
Open Loop Frequency
Response
vs
Maximum Output Swing
vs Frequency
Temperature
Figure 15.
Figure 16.
ZOUT
vs
Frequency
Slew Rate
vs Supply Voltage
Figure 17.
Figure 18.
Non-Inverting Large Signal
Pulse Response
Non-Inverting Small Signal
Pulse Response
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
VS = +3V, TA = 25°C, Unless otherwise specified
Inverting Large Signal
Inverting Small Signal
Pulse Response
Pulse Response
Figure 21.
Figure 22.
Stability
vs Capacitive Load
Stability
vs Capacitive Load
Figure 23.
Figure 24.
Stability
vs Capacitive Load
Stability
vs Capacitive Load
Figure 25.
Figure 26.
8
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Typical Performance Characteristics (continued)
VS = +3V, TA = 25°C, Unless otherwise specified
Bandwidth
vs
Capacitive Load
vs Phase Margin
Capacitive Load
Figure 27.
Figure 28.
Capacitive Load
vs Gain Margin
Figure 29.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
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APPLICATIONS HINTS
LOW VOLTAGE AMPLIFIER TOPOLOGY
The LMC6574/2 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op-amps. These features make the LMC6574/2 both easier to
design with, and provide higher speed than products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6574/2.
Although the LMC6574/2 is highly stable over a wide range of operating conditions, a large feedback resistor will
react even with small values of capacitance at the input of the op-amp to reduce phase margin. The capacitance
at the input of the op-amp comes from transducers, photodiodes and circuit board parasitics.
The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors
(as in Figure 30) such that:
(1)
or
R1 CIN ≤ R2 Cf
(2)
Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating
for input capacitance.
When high input impedances are demanded, guarding of the LMC6574/2 is suggested. Guarding input lines will
not only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
Figure 30. Cancelling the Effect of Input Capacitance
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 31.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Figure 31. LMC6574/2 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 31, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6574/2, typically less than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6574/2's
inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-
amp's inputs, as in Figure 32. To have a significant effect, guard rings should be placed on both the top and
bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the
amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC
board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This would cause a 250 times degradation from the
LMC6574/2's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 35 for typical connections of guard
rings for standard op-amp configurations.
Figure 32. Example of Guard Ring in P.C. Board Layout
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Figure 33. Inverting Amplifier
Figure 34. Non-Inverting Amplifier
Follower
Figure 35. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 36.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board).
Figure 36. Air Wiring
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
SPICE MACROMODEL
A spice macromodel is available for the LMC6574/2. This model includes accurate simulation of:
•
•
•
•
•
input common-mode voltage range
frequency and transient response
GBW dependence on loading conditions
quiescent and dynamic supply current
output swing dependence on loading conditions
and many more characteristics as listed on the macromodel disk.
Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk.
Typical Single-Supply Applications
Figure 37. Low-Power Two-Op-Amp
Instrumentation Amplifier
Figure 38. Sample and Hold
Figure 39. 1 Hz Square Wave Oscillator
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Figure 40. Adder/Subtractor Circuit
Figure 41. Low Pass Filter
14
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
LMC6572AIM/NOPB
LMC6572AIMX/NOPB
LMC6572BIM
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
LMC65
72AIM
ACTIVE
NRND
D
D
D
D
D
D
D
D
D
2500
95
Green (RoHS
& no Sb/Br)
CU SN
LMC65
72AIM
8
TBD
Call TI
LMC65
72BIM
LMC6572BIM/NOPB
LMC6572BIMX/NOPB
LMC6574AIM/NOPB
LMC6574AIMX
ACTIVE
ACTIVE
ACTIVE
NRND
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
LMC65
72BIM
8
2500
55
Green (RoHS
& no Sb/Br)
LMC65
72BIM
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU SN
LMC6574
AIM
2500
2500
55
TBD
Call TI
LMC6574
AIM
LMC6574AIMX/NOPB
LMC6574BIM/NOPB
LMC6574BIMX/NOPB
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LMC6574
AIM
Green (RoHS
& no Sb/Br)
CU SN
LMC6574
BIM
2500
Green (RoHS
& no Sb/Br)
CU SN
LMC6574
BIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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1-Nov-2013
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC6572AIMX/NOPB
LMC6572BIMX/NOPB
LMC6574AIMX
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
16.4
16.4
16.4
6.5
6.5
6.5
6.5
6.5
5.4
5.4
2.0
2.0
2.3
2.3
2.3
8.0
8.0
8.0
8.0
8.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
8
14
14
14
9.35
9.35
9.35
LMC6574AIMX/NOPB
LMC6574BIMX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMC6572AIMX/NOPB
LMC6572BIMX/NOPB
LMC6574AIMX
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
2500
2500
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
8
14
14
14
LMC6574AIMX/NOPB
LMC6574BIMX/NOPB
Pack Materials-Page 2
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相关型号：
LMC6572BIM/NOPB
IC DUAL OP-AMP, 7500 uV OFFSET-MAX, 0.22 MHz BAND WIDTH, PDSO8, SO-8, Operational Amplifier
NSC
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