概述
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替代型号LMC662CMX/NOPB 概述
LMC662 CMOS Dual Operational Amplifier LMC662 CMOS双路运算放大器 运算放大器
LMC662CMX/NOPB 数据手册
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SNOSC51C –APRIL 1998–REVISED MARCH 2013
LMC662 CMOS Dual Operational Amplifier
Check for Samples: LMC662
1
FEATURES
DESCRIPTION
The LMC662 CMOS Dual operational amplifier is
ideal for operation from a single supply. It operates
from +5V to +15V and features rail-to-rail output
swing in addition to an input common-mode range
that includes ground. Performance limitations that
have plagued CMOS amplifiers in the past are not a
problem with this design. Input VOS, drift, and
broadband noise as well as voltage gain into realistic
loads (2 kΩ and 600Ω) are all equal to or better than
widely accepted bipolar equivalents.
2
•
•
•
•
•
•
•
•
•
•
•
Rail-to-Rail Output Swing
Specified for 2 kΩ and 600Ω Loads
High Voltage Gain: 126 dB
Low Input Offset Voltage: 3 mV
Low Offset Voltage Drift: 1.3 μV/°C
Ultra Low Input Bias Current: 2 fA
Input Common-Mode Range Includes V−
Operating Range from +5V to +15V Supply
ISS = 400 μA/amplifier; Independent of V+
Low Distortion: 0.01% at 10 kHz
Slew Rate: 1.1 V/μs
This chip is built with TI's advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC660 datasheet for a Quad CMOS
operational amplifier with these same features.
APPLICATIONS
•
•
•
•
•
•
•
•
High-Impedance Buffer or Preamplifier
Precision Current-to-Voltage Converter
Long-Term Integrator
Sample-and-Hold Circuit
Peak Detector
Medical Instrumentation
Industrial Controls
Automotive Sensors
Connection Diagram
Typical Application
Figure 1. 8-Pin PDIP, SOIC
Figure 2. Low-Leakage Sample-and-Hold
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
LMC662
SNOSC51C –APRIL 1998–REVISED MARCH 2013
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Absolute Maximum Ratings(1)(2)(3)
Differential Input Voltage
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature
±Supply Voltage
16V
See(4)
See(5)
(Soldering, 10 sec.)
260°C
−65°C to +150°C
(V+) +0.3V, (V−) −0.3V
±18 mA
Storage Temp. Range
Voltage at Input/Output Pins
Current at Output Pin
Current at Input Pin
±5 mA
Current at Power Supply Pin
Power Dissipation
35 mA
See(6)
Junction Temperature
150°C
ESD Tolerance(7)
1000V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) A military RETS electrical test specification is available on request.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
(6) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max)–TA)/θJA
.
(7) Human body model, 1.5 kΩ in series with 100 pF.
Operating Ratings(1)
Temperature Range
LMC662AI
−40°C ≤ TJ ≤ +85°C
0°C ≤ TJ ≤ +70°C
4.75V to 15.5V
See(2)
LMC662C
Supply Voltage Range
Power Dissipation
(3)
Thermal Resistance (θJA
)
8-Pin PDIP
101°C/W
165°C/W
8-Pin SOIC
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA
.
(3) All numbers apply for packages soldered directly into a PC board.
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DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC662AI
Limit(1)
LMC662C
Limit(1)
6
Parameter
Input Offset Voltage
Test Conditions
Typ(1)
Units
1
3
mV
3.3
6.3
max
Input Offset Voltage
Average Drift
1.3
μV/°C
Input Bias Current
0.002
pA
max
pA
4
2
2
1
Input Offset Current
0.001
max
TeraΩ
dB
Input Resistance
Common Mode
>1
83
0V ≤ VCM ≤ 12.0V
V+ = 15V
5V ≤ V+ ≤ 15V
70
68
63
62
Rejection Ratio
min
dB
Positive Power Supply
Rejection Ratio
83
94
70
63
VO = 2.5V
0V ≤ V− ≤ −10V
68
62
min
dB
Negative Power Supply
Rejection Ratio
84
74
83
73
min
V
Input Common-Mode
Voltage Range
V+ = 5V & 15V
−0.4
−0.1
0
V+ − 2.3
V+ − 2.5
440
−0.1
0
For CMRR ≥ 50 dB
max
V
V+ − 1.9
2000
500
V+ − 2.3
V+ − 2.4
300
200
90
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
V
Large Signal
Voltage Gain
RL = 2 kΩ(2)
Sourcing
Sinking
400
180
120
80
RL = 600Ω(2)
Sourcing
Sinking
1000
220
150
100
50
200
100
250
60
40
Output Swing
V+ = 5V
4.87
4.82
4.79
0.15
0.17
4.41
4.31
0.50
0.56
14.50
14.44
0.35
0.40
13.35
13.15
1.16
1.32
4.78
4.76
0.19
0.21
4.27
4.21
0.63
0.69
14.37
14.32
0.44
0.48
12.92
12.76
1.45
1.58
RL = 2 kΩ to V+/2
min
V
0.10
4.61
max
V
V+ = 5V
RL = 600Ω to V+/2
min
V
0.30
max
V
V+ = 15V
RL = 2 kΩ to V+/2
14.63
0.26
min
V
max
V
V+ = 15V
RL = 600Ω to V+/2
13.90
0.79
min
V
max
(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
(2) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC662AI
Limit(1)
LMC662C
Limit(1)
Parameter
Test Conditions
Sourcing, VO = 0V
Typ(1)
Units
Output Current
22
16
13
mA
min
mA
min
mA
min
mA
min
mA
max
V+ = 5V
14
11
Sinking, VO = 5V
Sourcing, VO = 0V
21
40
16
13
14
11
Output Current
V+ = 15V
28
23
25
21
Sinking, VO = 13V
See(3)
39
28
23
24
20
Supply Current
Both Amplifiers
VO = 1.5V
0.75
1.3
1.5
1.6
1.8
(3) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC662AI
Limit(1)
0.8
LMC662C
Limit(1)
0.8
Parameter
Test Conditions
Typ(1)
Units
Slew Rate
See(2)
1.1
V/μs
min
0.6
0.7
Gain-Bandwidth Product
Phase Margin
1.4
50
MHz
Deg
Gain Margin
17
dB
Amp-to-Amp Isolation
Input-Referred Voltage Noise
Input-Referred Current Noise
Total Harmonic Distortion
See(3)
130
22
dB
F = 1 kHz
nV√Hz
pA√Hz
F = 1 kHz
0.0002
F = 10 kHz, AV = −10
RL = 2 kΩ, VO = 8 VPP
V+ = 15V
0.01
%
(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
(2) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
(3) Input referred. V+ = 15V and RL = 10 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP
.
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Typical Performance Characteristics
VS = ±7.5V, TA = 25°C unless otherwise specified
Supply Current
vs.
Supply Voltage
Offset Voltage
Figure 3.
Figure 4.
Input Bias Current
Output Characteristics Current Sinking
Figure 5.
Figure 6.
Input Voltage Noise
vs.
Output Characteristics Current Sourcing
Frequency
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
CMRR
vs.
Frequency
Open-Loop Frequency Response
Figure 9.
Figure 10.
Frequency Response
vs.
Capacitive Load
Non-Inverting Large Signal Pulse Response
Figure 11.
Figure 12.
Stability
vs.
Capacitive Load
Stability
vs.
Capacitive Load
Note: Avoid resistive loads < 500Ω, as they may cause instability.
Note: Avoid resistive loads < 500Ω, as they may cause instability.
Figure 13.
Figure 14.
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SNOSC51C –APRIL 1998–REVISED MARCH 2013
APPLICATION HINTS
AMPLIFIER TOPOLOGY
The topology chosen for the LMC662, shown in Figure 15, is unconventional (compared to general-purpose op
amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from
the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to
the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks
now fall to the integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.
Figure 15. LMC662 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ω load.
The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under
heavy load (600Ω) the gain will be reduced as indicated in the Electrical Characteristics.
COMPENSATING INPUT CAPACITANCE
The high input resistance of the LMC662 op amps allows the use of large feedback and source resistor values
without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when
these large-value resistors are used.
Every amplifier has some capacitance between each input and AC ground, and also some differential
capacitance between the inputs. When the feedback network around an amplifier is resistive, this input
capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback
resistors create a pole in the feedback path. In the following General Operational Amplifier Circuit, Figure 16, the
frequency of this pole is
(1)
where: CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray
capacitance from the IC socket (if one is used), circuit board traces, etc., and RP is the parallel combination of RF
and RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op-amp
configurations.
When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high,
since CS is generally less than 10 pF. If the frequency of the feedback pole is much higher than the “ideal”
closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible
effect on stability, as it will add only a small amount of phase shift.
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However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback
capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can
also be stated in terms of the amplifier's low-frequency noise gain: To maintain stability, a feedback capacitor will
probably be needed if:
(2)
where:
(3)
is the amplifier's low-frequency noise gain and GBW is the amplifier's gain bandwidth product. An amplifier's low-
frequency noise gain is represented by the formula:
(4)
regardless of whether the amplifier is being used in an inverting or non-inverting mode. Note that a feedback
capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is
large enough that:
(5)
the following value of feedback capacitor is recommended:
(6)
If
(7)
the feedback capacitor should be:
(8)
Note that these capacitor values are usually significantly smaller than those given by the older, more
conservative formula:
(9)
CS consists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF
compensates for the pole caused by CS and the feedback resistor.
Figure 16. General Operational Amplifier Circuit
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Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may
be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected
stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease
the noise or bandwidth, or simply because the particular circuit implementation needs more feedback
capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or
smaller than the breadboard's, so the actual optimum value for CF may be different from the one estimated using
the breadboard. In most cases, the value of CF should be checked on the actual circuit, starting with the
computed value.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC662 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See the Typical Performance Characteristics.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. As shown in Figure 17, the addition of a small resistor (50Ω to 100Ω) in series with the op amp's
output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe
value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be
tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near
the threshold for oscillation.
Figure 17. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 18. Typically a pull up
resistor conducting 500 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 18. Compensating for Large Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC662,
typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,
the surface leakage will be appreciable.
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To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC662's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LMC662's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance
of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's
performance. See Figure 20, Figure 21, and Figure 22 for typical connections of guard rings for standard op-amp
configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide
some protection; see Figure 23.
Figure 19. Example, using the LMC660,
of Guard Ring in P.C. Board Layout
Figure 20. Guard Ring Connections: Inverting Amplifier
Figure 21. Guard Ring Connections: Non-Inverting Amplifier
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Figure 22. Guard Ring Connections: Follower
Figure 23. Guard Ring Connections: Howland Current Pump
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Do not insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 24.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 24. Air Wiring
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BIAS CURRENT TESTING
The test method of Figure 25 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then
(10)
Figure 25. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of Ib−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted)
(11)
where Cx is the stray capacitance at the + input.
Typical Single-Supply Applications
(V+ = 5.0 VDC
)
Additional single-supply applications ideas can be found in the LM358 datasheet. The LMC662 is pin-for-pin
compatible with the LM358 and offers greater bandwidth and input resistance over the LM358. These features
will improve the performance of many existing single-supply applications. Note, however, that the supply voltage
range of the LM662 is smaller than that of the LM358.
Figure 26. Low-Leakage Sample-and-Hold
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(V+ = 5.0 VDC
)
Figure 27. Instrumentation Amplifier
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
Figure 28. Sine-Wave Oscillator
This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V
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(V+ = 5.0 VDC
)
Figure 29. 1 Hz Square-Wave Oscillator
Figure 30. Power Amplifier
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 31. 10 Hz Bandpass Filter
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(V+ = 5.0 VDC
)
fc = 10 Hz
d = 0.895
Gain = 1
2 dB passband ripple
Figure 32. 10 Hz High-Pass Filter
Figure 33. 1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV).
Figure 34. High Gain Amplifier with
Offset Voltage Reduction
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMC662AIM
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
8
8
8
8
8
8
8
8
8
8
8
8
95
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
SN
Call TI
Level-1-260C-UNLIM
Call TI
LMC66
2AIM
LMC662AIM/NOPB
LMC662AIMX
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
P
P
D
D
D
D
P
P
95
2500
2500
40
Green (RoHS
& no Sb/Br)
LMC66
2AIM
TBD
LMC66
2AIM
LMC662AIMX/NOPB
LMC662AIN
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
LMC66
2AIM
TBD
LMC
662AIN
LMC662AIN/NOPB
LMC662CM
40
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
Call TI
LMC
662AIN
95
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
SN
LMC66
2CM
LMC662CM/NOPB
LMC662CMX
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
0 to 70
LMC66
2CM
2500
2500
40
TBD
0 to 70
LMC66
2CM
LMC662CMX/NOPB
LMC662CN
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
0 to 70
LMC66
2CM
TBD
0 to 70
LMC
662CN
LMC662CN/NOPB
40
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
0 to 70
LMC
662CN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC662AIMX
LMC662AIMX/NOPB
LMC662CMX
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.5
6.5
6.5
6.5
5.4
5.4
5.4
5.4
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
LMC662CMX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMC662AIMX
LMC662AIMX/NOPB
LMC662CMX
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
LMC662CMX/NOPB
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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Copyright © 2013, Texas Instruments Incorporated
LMC662CMX/NOPB CAD模型
引脚图
封装焊盘图
LMC662CMX/NOPB 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| LMC662CM | TI | LMC662 CMOS Dual Operational Amplifier | 完全替代 |
|
| LMC662AIMX/NOPB | TI | LMC662 CMOS Dual Operational Amplifier | 类似代替 |
|
| LMC662CM/NOPB | TI | LMC662 CMOS Dual Operational Amplifier | 类似代替 |
|
LMC662CMX/NOPB 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LMC662CN | NSC | CMOS Dual Operational Amplifier | 获取价格 |
|
| LMC662CN | TI | LMC662 CMOS Dual Operational Amplifier | 获取价格 |
|
| LMC662CN/NOPB | TI | LMC662 CMOS Dual Operational Amplifier | 获取价格 |
|
| LMC662EM | NSC | CMOS Dual Operational Amplifier | 获取价格 |
|
| LMC662EM | TI | DUAL OP-AMP, 6500uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDSO8, SO-8 | 获取价格 |
|
| LMC662EMX | TI | DUAL OP-AMP, 6500uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDSO8, SO-8 | 获取价格 |
|
| LMC662EN | NSC | CMOS Dual Operational Amplifier | 获取价格 |
|
| LMC662EN | TI | DUAL OP-AMP, 6500uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDIP8, DIP-8 | 获取价格 |
|
| LMC6681 | NSC | Low Voltage, Rail-To-Rail Input and Output CMOS | 获取价格 |
|
| LMC6681AIM | NSC | Low Voltage, Rail-To-Rail Input and Output CMOS | 获取价格 |
|
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