LME49880 [TI]
E-Series Dual JFET Input Audio Operational Amplifier;
| 型号： | LME49880 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | E-Series Dual JFET Input Audio Operational Amplifier |
| 文件： | 总16页 (文件大小：953K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LME49880
www.ti.com
SNAS455C –DECEMBER 2009–REVISED APRIL 2013
LME49880 Overture®
E-Series Dual JFET Input Audio Operational Amplifier
Check for Samples: LME49880
1
FEATURES
DESCRIPTION
The LME49880 is part of the ultra-low distortion, low
23
•
Easily Drives 600Ω Loads
noise, high slew rate operational amplifier series
optimized and fully specified for high performance,
high fidelity application. The LME49880 is developed
in JFET technology and reducing the flicker noise as
well as the noise corner frequency significantly. It
combines low voltage noise density (7nV/√Hz) with
very low THD+N (0.00003%). The LME49880 has a
high slew rate of ±17 V/μs and an output current
capability of ±22mA. It drives 600Ω loads to within
1.3V of either power supply voltage.
•
Output Short Circuit Protection
APPLICATIONS
•
•
•
•
•
Ultra High Quality Audio Signal Processing
Preamplifier
Spectrum Analyzers
Ultrasound Preamplifier
Active Filters
The LME49880 has a wide supply range of ±5V to
±17V. Its outstanding GAIN (120dB), and low input
bias current (5pA) give the amplifier excellent
KEY SPECIFICATIONS
•
•
•
Input Bias Current 5 pA (Typ)
operational
amplifier
DC
performance.
The
Power Supply Voltage Range ±5V to ±17 V
THD+N (AV = 1, VOUT = 3VRMS, fIN = 1kHz)
LME49880 is unity gain stable and capable of driving
complex loads with values as high as 100pF. It is
available in an 8-lead narrow body SO PowerPAD.
–
–
RL = 2kΩ 0.00003 % (Typ)
RL = 600Ω, 0.00003 % (Typ)
•
•
•
•
•
•
Slew Rate ±17 V/μs (Typ)
Gain Bandwidth Product 25 MHz (Typ)
Open Loop Gain (RL = 600Ω) 115 dB (Typ)
Input Noise Density 7 nV/√Hz (Typ)
Input Offset Voltage 5 mV (Typ)
CMRR 110 dB (Typ)
TYPICAL APPLICATION
1k
100
Current Noise
10
Voltage Noise
100
1
10
1k
10k
100k
FREQUENCY (Hz)
Figure 1. Current Noise and Voltage Spectral
Density
Figure 2. THD+N vs Frequency
VCC = ±15V, VO = 3VRMS, RL = 600Ω
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Overture is a registered trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LME49880
SNAS455C –DECEMBER 2009–REVISED APRIL 2013
www.ti.com
CONNECTION DIAGRAM
1
2
3
4
8
7
6
5
+
OUTPUT A
V
INVERTING INPUT A
OUTPUT B
A
B
-
+
+
-
NON-INVERTING
INPUT A
INVERTING INPUT B
NON-INVERTING
INPUT B
-
V
Figure 3. Connection Diagram
See Package Number — DDA0008B
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Power Supply Voltage (VS = V+ - V-)
Storage Temperature
Input Voltage
Output Short Circuit(3)
Power Dissipation
ESD Rating(4)
36V
−65°C to 150°C
(V-) - 0.3V to (V+) + 0.3V
Continuous
Internally Limited
2000V
ESD Rating(5)
200V
ESD Rating(6)
1000V
Junction Temperature
Thermal Resistance
Solder Information
150°C
θJA (SO PowerPAD)
55°C/W
Infrared or Convection (20 sec)
260°C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Amplifier output connected to GND, any number of amplifiers within a package.
(4) Human body model, applicable std. JESD22-A114C.
(5) Machine model, applicable std. JESD22-A115-A.
(6) Charge device model, applicable std JESD22-C101-A.
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OPERATING RATINGS
Temperature Range
TMIN ≤ TA ≤ TMAX
–40°C ≤ TA ≤ 85°C
±5V ≤ VS ≤ ±17V
Supply Voltage Range
(1)
ELECTRICAL CHARACTERISTICS
The following specifications apply for VS = ±15V, TA = 25°C, unless otherwise specified.
LME49880
Units
(Limits)
Symbol
Parameter
Conditions
Typical(2)
Limit(3)
AV = 1, VOUT = 3VRMS
RL = 2kΩ
RL = 600Ω
THD+N
Total Harmonic Distortion + Noise
0.00003
0.00003
% (max)
0.00009
19
GBWP
SR
Gain Bandwidth Product
Slew Rate
AV = 1k, RL = 2k
RL = 2k
25
MHz (min)
±17
±12
V/μs (min)
AV = –1, 10V step, CL = 100pF
0.1% error range
ts
Settling time
0.8
0.7
μs
μVRMS
(max)
Equivalent Input Noise Voltage
Equivalent Input Noise Density
fBW = 20Hz to 20kHz
1.6
11
eN
f = 1kHz
f = 10Hz
7
16
nV/√Hz
(max)
iN
Current Noise Density
Offset Voltage
f = 1kHz
6
fA/√Hz
VOS
±5
±10
mV (max)
Average Input Offset Voltage Drift vs
Temperature
ΔVOS/ΔTemp
–40°C ≤ TA ≤ 85°C
3
μV/°C
PSRR
IB
Power Supply Rejection Ratio
Input Bias Current
VCC = ±5V to ±15V
VCM = 0V
110
5
dB
150
100
pA (max)
pA (max)
IOS
Input Offset Current
VCM = 0V
2
+11.5
–11.5
(V+) –5V
(V-) +5V
VIN-CM
CMRR
Common-Mode Input Voltage Range CMRR > 55dB
V (min)
Common-Mode Rejection
Open Loop Voltage Gain
–10V<Vcm<10V
110
115
120
120
±13.2
±13.2
±13.2
±26
90
dB (min)
dB (min)
dB (min)
dB (min)
V (min)
V (min)
V (min)
mA
–10V<Vout<10V, RL = 600Ω
–10V<Vout<10V, RL = 2kΩ
–10V<Vout<10V, RL = 10kΩ
RL = 600Ω
100
AVOL
100
100
±12.0
±12.5
±12.5
VOUTMAX
Maximum Output Voltage Swing
RL = 2kΩ
RL = 10kΩ
IOUT
IOUT-CC
ROUT
IS
Output Current
RL = 600Ω, VS = ±17V
Instantaneous Short Circuit Current
Output Impedance
±48
mA
fIN = 10kHz, Open-Loop
IOUT = 0mA
15
Ω
Total Quiescent Current
14
18
mA (max)
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(3) Datasheet min/max specification limits are specified by test or statistical analysis.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N
vs
Frequency
VCC = 15V, VOUT = 3V
RL = 2kΩ
THD+N
vs
Frequency
VCC = 15V, VOUT = 3V
RL = 600Ω
Figure 4.
Figure 5.
THD+N
vs
Frequency
VCC = 18V, VOUT = 3V
RL = 2kΩ
THD+N
vs
Frequency
VCC = 18V, VOUT = 3V
RL = 600Ω
Figure 6.
Figure 7.
THD+N
vs
Output Voltage
VCC = 15V
RL = 2kΩ
THD+N
vs
Output Voltage
VCC = 15V
RL = 600Ω
Figure 8.
Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N
vs
Output Voltage
VCC = 18V
RL = 2kΩ
THD+N
vs
Output Voltage
VCC = 18V
RL = 600Ω
Figure 10.
Figure 11.
+PSRR
vs
Frequency
−PSRR
vs
Frequency
0
-20
-40
-60
-80
0
-20
-40
-60
-80
-100
-120
-100
-120
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12.
Figure 13.
CMRR
vs
Frequency
0
-20
-40
-60
-80
-100
-120
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Current Noise
vs
Frequency
Voltage Noise
vs
Frequency
1k
100
10
1k
100
10
1
10
1
10
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15.
Figure 16.
6
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SNAS455C –DECEMBER 2009–REVISED APRIL 2013
APPLICATION HINTS
OUTPUT DRIVE AND STABILITY
The LME49880 is unity gain stable within the part’s common-mode range. Some instabilities may occur near the
limit of the common-mode range. It can drive resistive load 600Ω with output circuit with a typical 26mA.
Capacitive loads up to 100pF will cause little change in the phase characteristics of the amplifiers and are
therefore allowable.
Capacitive loads greater than 100pF must be isolated from the output. The most straight forward way to do this is
to put a resistor in series with the output. This resistor will also prevent excess power dissipation if the output is
accidentally shorted. The internal short-circuit protection of LME49880 also prevent the device from damage
when the either outputs are being shorted.
The effective load impedance (including feedback resistance) should be kept above 600Ω for fast settling. Load
capacitance should also be minimized if good settling time is to be optimized. Large feedback resistors will make
the circuit more susceptible to stray capacitance, so in high-speed applications keep the feedback resistors in the
1kΩ to 2kΩ range whenever practical.
OUTPUT COMPENSATION
In most of the audio applications, the device will be operated in a room temperature and compensation networks
are not necessary. However, the consideration of network as shown in Figure 17 may be taken into account for
some of the high performance audio applications such as high speed data conversion or when operating in a
relatively low junction temperature. The compensation network will also provide a small improvement in settling
time for the response time demanding applications.
Figure 17. LME49880 Output Compensation Network
SO PowerPAD EXPOSED PAD PACKAGE
The LME49880 has an exposed pad on the bottom side of the IC package. Connect the exposed pad to pin 4 (V-
) of the IC. The PCB footprint for the exposed pad should be a open polygon of copper to provide a good thermal
path away from the LME49880. Use multiple vias on the exposed pad to create better thermal conductivity. Do
not route traces below the exposed pad as they risk shorting to the exposed pad.
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Figure 18. LME49880 Output Compensation Network
SUPPLY BYPASSING
To achieve a low noise and high-speed audio performance, power supply bypassing is extremely important.
Applying multiple bypass capacitors is highly recommended. From experiment results, a 10μF tantalum, 2.2μF
ceramic, and a 0.47μF ceramic work well. All bypass capacitors leads should be very short. The ground leads of
capacitors should also be separated to reduce the inductance to ground. To obtain the best result, a large
ground plane layout technique is recommended and it was applied in the LME49880 evaluation board.
APPLICATION INFORMATION
SETTLING TIME AND SLEW RATE MEASUREMENTS
The settling time of LME49880 may be verified using the test circuit in Figure 19. The LME49880 is connected
for inverting operation, and the output voltage is summed with the input voltage step. When the LME49880’s
output voltage is equal to the input voltage, the voltage on the PROBE 1 will be zero. Any voltage appearing at
this point will represent an error. And the settling time is equal to the time required for the error signal displayed
on the oscilloscope to decay to less than one-half the necessary accuracy. For a 10V input signal, settling time to
0.01% (1mV) will occur when the displayed error is less than 0.5mV. Since settling time is strongly dependent on
slew rate, settling will be faster for smaller signal swings. The LME49880’s inverting slew rate is faster than its
non-inverting slew rate, so settling will be faster for inverting applications, as well. It is important to note that the
oscilloscope input amplifier may be overdriven during a settling time measurement, so the oscilloscope must be
capable of recovering from overdrive very quickly. The signal generator used for this measurement must be able
to drive 50Ω with a very clean ±10VPP square wave. The Slew Rate of LME49880 tells how fast it responses to a
transient or a step input. It may be measured by the test circuit in Figure 20. The Slew Rate of LME49880 is
specified in close-loop gain = -1 when the output driving a 1kΩ load at 20VPP. The LME49880 behaves very
stable in shape step response and have a minimal ringing in both small and large signal step response (See
TYPICAL PERFORMANCE CHARACTERISTICS). The slew rate typical value reach as high as ±18V/μS was
measured when the output reach -20V refer to the start point when input voltage equals to zero.
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Figure 19. Settling Time Test Circuit
Figure 20. Slew Rate Test Circuit
DISTORTION MEASUREMENTS
The vanishingly low residual distortion produced by LME49880 is below the capabilities of all commercially
available equipment. This makes distortion measurements just slightly more difficult than simply connecting a
distortion meter to the amplifier’s inputs and outputs. The solution, however, is quite simple: an additional
resistor. Adding this resistor extends the resolution of the distortion measurement equipment.
The LME49880’s low residual distortion is an input referred internal error. As shown in Figure 21, adding the 10Ω
resistor connected between the amplifier’s inverting and non-inverting inputs changes the amplifier’s noise gain.
The result is that the error signal (distortion) is amplified by a factor of 101. Although the amplifier’s closed-loop
gain is unaltered, the feedback available to correct distortion errors is reduced by 101, which means that
measurement resolution increases by 101. To ensure minimum effects on distortion measurements, keep the
value of R1 low as shown in Figure 21.
This technique is verified by duplicating the measurements with high closed loop gain and/or making the
measurements at high frequencies. Doing so produces distortion components that are within the measurement
equipment’s capabilities. This datasheet’s THD+N and IMD values were generated using the above described
circuit connected to an Audio Precision System Two Cascade.
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R2
1000W
-
LME49880
R1
10W
Distortion Signal Gain = 1+(R2/R1)
+
Analyzer Input
Generator Output
Audio Precision
System Two
Cascade
Actual Distortion = AP Value/100
Figure 21. THD+N and IMD Distortion Test Circuit
TYPICAL APPLICATIONS
Illustration is:
V0 = 101(V2 − V1)
Figure 22. Balanced Input Mic Amp
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Figure 23. Active Crossover Network for Loudspeaker
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REVISION HISTORY
Rev
1.0
Date
Description
12/16/09
01/08/10
Initial released.
Input text edits.
1.01
Edited the scaling (Y-axis) on the THD+N curves to match the limits described in
the datasheet.
1.02
C
03/22/10
04/04/13
Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2016
PACKAGING INFORMATION
Orderable Device
LME49880MR/NOPB
LME49880MRX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OBSOLETESO PowerPAD
DDA
8
8
TBD
Call TI
Call TI
L49880
MR
OBSOLETESO PowerPAD
DDA
TBD
Call TI
Call TI
-40 to 85
L49880
MR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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1-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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相关型号：
SI9130DB
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