LMF100 [TI]
Dual High-Performance Switched Capacitor Filters;
| 型号： | LMF100 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual High-Performance Switched Capacitor Filters |
| 文件： | 总40页 (文件大小：1829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMF100
SNOSBG9B –JULY 1999–REVISED JUNE 2015
LMF100 Dual High-Performance Switched Capacitor Filters
Not Recommended for New Designs
1 Features
3 Description
The LMF100 device consists of two independent
general-purpose, high-performance switched
1
•
•
•
Wide 4-V to 15-V Power Supply Range
Operation up to 100 kHz
Low Offset Voltage:
capacitor filters. With an external clock and two to
four resistors, each filter block can realize various
second-order and first-order filtering functions. Each
block has three outputs. One output can be
configured to perform either an allpass, highpass, or
notch function. The other two outputs perform
bandpass and lowpass functions. The center
frequency of each filter stage is tuned by using an
external clock or a combination of a clock and resistor
ratio. Up to a fourth-order biquadratic function can be
realized with one LMF100. Higher order filters are
implemented by simply cascading additional
packages, and all the classical filters (such as
Butterworth, Bessel, Elliptic, and Chebyshev) can be
realized.
–
Typically (50:1 or 100:1 mode):
–
–
–
Vos1 = ±5 mV
Vos2 = ±15 mV
Vos3 = ±15 mV
•
•
Low Crosstalk: –60 dB
Clock to Center Frequency Ratio Accuracy ±0.2%
(Typical)
•
•
f0 × Q Range up to 1.8 MHz
Pin-Compatible With MF10
2 Applications
The LMF100 is fabricated on TI’s high-performance
analog silicon gate CMOS process, LMCMOS™. This
allows for the production of a very low-offset, high-
frequency filter building block. The LMF100 is pin-
compatible with the industry standard MF10, but
provides greatly improved performance.
•
Replacing Active RC Filters With Reduced Form
Factors and Higher Accuracy and Tunability
•
An Alternative to Integrated Continuous Time
Filters
Device Information(1)
PART NUMBER
PACKAGE
SOIC (20)
PDIP (20)
BODY SIZE (NOM)
12.60 mm × 10.00 mm
24.33 mm × 6.35 mm
LMF100
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Fourth-Order 100-kHz Butterworth Lowpass Filter
Transfer Curve of Butterworth LP Filter Roll-Off
Magnitude vs Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Not Recommended for New Designs
LMF100
SNOSBG9B –JULY 1999–REVISED JUNE 2015
www.ti.com
Table of Contents
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
9
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
12 Device and Documentation Support ................. 33
12.1 Device Support .................................................... 33
12.2 Community Resources.......................................... 33
12.3 Trademarks........................................................... 33
12.4 Electrostatic Discharge Caution............................ 34
12.5 Glossary................................................................ 34
6.5 Electrical Characteristics for V+ = +5 V and V− = −5
V................................................................................. 5
6.6 Electrical Characteristics for V+ = +2.5 V and V−
=
−2.5 V......................................................................... 6
6.7 Logic Input Characteristics........................................ 8
6.8 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 14
7.1 Definition of Terms Graphics .................................. 14
Detailed Description ............................................ 16
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
Changes from Revision A (July 1999) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
2
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SNOSBG9B –JULY 1999–REVISED JUNE 2015
5 Pin Configuration and Functions
DW and N Package
20-Pin SOIC and PDIP (N20 or M20B)
(Top View)
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
1
LP
20
2
The second order lowpass, bandpass and notch, allpass and highpass outputs. These outputs can typically swing to
within 1 V of each supply when driving a 5-kΩ load. For optimum performance, capacitive loading on these outputs
should be minimized. For signal frequencies above 15 kHz, the capacitance loading should be kept below 30 pF.
BP
I/O
19
3
N/AP/HP
INV
18
4
The inverting input of the summing op-amp of each filter. These are high impedance inputs. The noninverting input is
internally tied to AGND so the opamp can be used only as an inverting amplifier.
I
I
17
5
S1 is a signal input pin used in modes 1b, 4, and 5. The input impedance is 1/fCLK x 1 pF. The pin should be driven with
a source impedance of less than 1 kΩ. If S1 is not driven with a signal it should be tied to AGND (mid-supply).
S1
16
This pin activates a switch that connects one of the inputs of each filter’s second summer either to AGND (SA/B tied to V−)
or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various
modes of operation.
SA/B
6
I
I
I
7(1)
8(1)
This is both the analog and digital positive supply.
+
VA
–
Analog and digital negative supplies. VA– and VD should be derived from the same source. They have been brought out
+
VD
separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and
bypassed with a single capacitor.
–
–
Analog and digital negative supplies. VA– and VD should be derived from the same source. They have been brought out
14
13
VA
I
I
separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and
bypassed with a single capacitor.
–
VD
Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ±5-V
supplies and CMOS (±5 V) or TTL (0 V–5 V) clock levels, LSh should be tied to system ground.
For 0-V to 10-V single-supply operation the AGND pin should be biased at +5 V and the LSh pin should be tied to the
system ground for TTL clock levels. LSh should be biased at +5 V for ±5-V CMOS clock levels.
LSh
CLK
9
The LSh pin is tied to system ground for ±2.5V operation. For single 5V operation the LSh and VD+ pins are tied to
system ground for TTL clock levels.
10
11
Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK
inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50%,
especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to
settle, which yields optimum filter performance.
I
By tying this pin to V+ a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system
ground with dual supplies) or to V– allows the filter to operate at a 100:1 clock to center frequency ratio.
50/100
AGND
12(1)
15
I
I
This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to
mid-supply for single-supply operation. For a further discussion of mid-supply biasing techniques see the Applications
Information (Section 3.2). For optimum filter performance a “clean” ground must be provided.
(1) This device is pin-for-pin compatible with the MF10 except for the following changes:
(a) Unlike the MF10, the LMF100 has a single positive supply pin (VA+).
(b) On the LMF100 VD+ is a control pin and is not the digital positive supply as on the MF10.
(c) Unlike the MF10, the LMF100 does not support the current limiting mode. When the 50/100 pin is tied to V– the LMF100 will remain
in the 100:1 mode.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
16
UNIT
Supply Voltage (V+ – V–)
Voltage at any pin
V
V+ + 0.3
V– – 0.3
5
V
Input current at any pin(2)
Package input current(2)
Power dissipation(3)
mA
mA
mW
20
500
N Package: 10 sec.
250
Soldering information(4)
Vapor Phase (60 sec)
Infrared (15 sec)
215
°C
SOIC Package
220
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V– or the absolute value of current at that pin should be
limited to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed
+
20 mA.VIN
)
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient
temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/RθJA or the number given in the
Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125°C, and the typical junction-to-ambient thermal resistance
of the LMF100CIN when board mounted is 55°C/W. For the LMF100CIWM this number is 66°C/W.
(4) See AN-450Surface Mounting Methods and Their Effect on Product Reliability(Appendix D) for other methods of soldering surface
mount devices.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) A military RETS specification is available upon request.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
70
UNIT
LMF100CCN
Temperature
°C
V
LMF100CIWM
–40
4
85
Supply voltage
≤V+ – V–
≤
15
4
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SNOSBG9B –JULY 1999–REVISED JUNE 2015
6.4 Thermal Information
LMF100
THERMAL METRIC(1)
DW (SOIC)
20 PINS
63.8
N (PDIP)
20 PINS
49.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27.2
41.1
31.8
30.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.7
18.3
ψJB
31.3
30.3
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics for V+ = +5 V and V− = −5 V
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +5 V and V− = −5 V unless otherwise
specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
LMF100CIWM
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
9
9
13
Tested
fCLK = 250 kHz,
No Input Signal
Is
Maximum supply current
Limit(1)
mA
TMIN to TMAX
13
Design
TMIN to TMAX
Limit(2)
13
10000
0
f0
Center frequency
Clock frequency
0.1
5
0.1
5
100000
Hz
Hz
35000
00
fCLK
3500000
±0.2%
±0.2%
±0.8%
±0.8%
±5%
±6%
±0.4
±0.4
±0.2
±0.2
±15
Tested
fCLK/f Clock to center frequency ratio
VPin12 = 5 V or 0
V, fCLK = 1 MHz
Limit(1)
TMIN to TMAX
±0.8%
deviation
0
Design
TMIN to TMAX
Limit(2)
±0.5%
±0.5%
±6%
Q = 10, Mode 1,
VPin12 = 5 V or 0
V,
DQ
Tested
(3)
Q Error (MAX)
Limit(1)
TMIN to TMAX
Q
fCLK = 1 MHz
Design
TMIN to TMAX
Limit(2)
0
0
0
0
Tested
HOBP Bandpass gain at f0
fCLK = 1 MHz
Limit(1)
dB
dB
TMIN to TMAX
±0.4
±0.2
±15
Design
TMIN to TMAX
Limit(2)
Tested
R1 = R2 = 10 k,
fCLK = 250 kHz
HOLP DC Lowpass gain
Limit(1)
TMIN to TMAX
Design
TMIN to TMAX
Limit(2)
±5
±5
Tested
VOS1 DC Offset voltage(4)
fCLK = 250 kHz
Limit(1)
mV
TMIN to TMAX
Design
TMIN to TMAX
Limit(2)
±15
(1) Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
(2) Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
(3) The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading Typical
Characteristics.
(4) Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in Application Information.
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Electrical Characteristics for V+ = +5 V and V− = −5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +5 V and V− = −5 V unless otherwise
specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
LMF100CIWM
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
±80
±80
±70
±70
±40
MIN
TYP
MAX
±30
±30
Tested Limit(1)
mV
SA/B = V+
TMIN to TMAX
±80
Design Limit(2) TMIN to TMAX
VOS2 DC Offset voltage(4)
fCLK = 250 kHz
±15
±15
±15
±15
Tested Limit(1)
TMIN to TMAX
mV
mV
SA/B = V–
±70
±60
Design Limit(2) TMIN to TMAX
Tested
Limit(1)
VOS3 DC Offset voltage(4)
fCLK = 250 kHz
TMIN to TMAX
TMIN to TMAX
Design
Limit(2)
±60
Crosstalk(5)
A Side to B Side or B Side to A Side
fCLK = 250 kHz
20 kHz Bandwidth BP
100:1 Mode LP
fCLK = 250 kHz 100:1 Mode
–60
40
–60
40
dB
µV
N
Output noise(6)
Clock feedthrough(7)
320
300
6
320
300
6
mV
4
4
−4.7
−4.7
±3.8
±3.7
RL = 5 k
(All Outputs)
Tested
Limit(1)
TMIN to TMAX
TMIN to TMAX
±3.7
VOUT Minimum output voltage swing
V
Design
Limit(2)
RL = 3.5 k
3.9
3.9
(All Outputs)
−4.6
−4.6
GB
W
Operational amplifier gain BW
product
5
5
MHz
SR
Operational amplifier slew rate
20
12
45
20
12
45
V/µs
mA
Source
All Outputs
Maximum output,
Isc
Short circuit current(8)
Sink
All Outputs
mA
Tested Limit(1)
Design Limit(2)
10
Input current on Pins: 4, 5, 6, 9,
10, 11, 12, 16, 17
IIN
µA
TMIN to TMAX
10
(5) Crosstalk between the internal filter sections is measured by applying a 1 VRMS 10-kHz signal to one bandpass filter section input and
grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and
the 1 VRMS input signal of the other section.
(6) In 50:1 mode the output noise is 3 dB higher.
(7) In 50:1 mode the clock feed through is 6 dB higher.
(8) The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then
shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its
maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions.
6.6 Electrical Characteristics for V+ = +2.5 V and V− = −2.5 V
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +2.50 V and V− = −2.50 V unless
otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
LMF100CIWM
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
8
8
12
12
Tested
fCLK = 250 kHz,
No Input Signal
Is
Maximum supply current
Center frequency
Limit(1)
mA
Hz
TMIN to TMAX
Design
Limit(2)
12
f0
0.1
50000
0.1
50000
(1) Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
(2) Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
6
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Electrical Characteristics for V+ = +2.5 V and V− = −2.5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +2.50 V and V− = −2.50 V unless
otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
LMF100CIWM
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
15000
00
fCLK
Clock frequency
5
5
1500000
Hz
±0.2%
±0.2%
Tested
fCLK/f Clock to center frequency ratio
VPin12 = 5 V or 0
V, fCLK = 1 MHz
TMIN to TMAX
Limit(1)
±1%
±1%
±1%
deviation
0
Design
Limit(2)
±0.5%
±0.5%
Q = 10, Mode 1,
VPin12 = 5 V or 0
V,
±5%
±8%
±0.4
±0.5
±0.2
±0.2
±15
DQ
Tested
(3)
Q Error (MAX)
Limit(1)
TMIN to TMAX
±8%
±0.5
Q
fCLK = 1 MHz
Design
TMIN to TMAX
Limit(2)
0
0
0
Tested
HOBP Bandpass gain at f0
fCLK = 1 MHz
Limit(1)
dB
dB
TMIN to TMAX
Design
TMIN to TMAX
Limit(2)
0
Tested
R1 = R2 = 10 k,
fCLK = 250 kHz
HOLP DC Lowpass gain
Limit(1)
TMIN to TMAX
±0.2
±15
Design
TMIN to TMAX
Limit(2)
±5
±5
Tested
VOS1 DC Offset voltage(4)
fCLK = 250 kHz
fCLK = 250 kHz
fCLK = 250 kHz
Limit(1)
mV
mV
TMIN to TMAX
Design
TMIN to TMAX
Limit(2)
±15
±20
±10
±20
±60
±60
±50
±60
±25
Tested Limit(1)
SA/B = V+
TMIN to TMAX
±60
mV
Design Limit(2) TMIN to TMAX
VOS2 DC Offset voltage(4)
±10
Tested Limit(1)
TMIN to TMAX
SA/B = V–
±60
Design Limit(2) TMIN to TMAX
±10
±10
Tested
Limit(1)
VOS3 DC Offset voltage(4)
mV
TMIN to TMAX
TMIN to TMAX
±30
Design
Limit(2)
±30
Crosstalk(5)
A Side to B Side or B Side to A Side
fCLK = 250 kHz
20 kHz Bandwidth BP
100:1 Mode LP
fCLK = 250 kHz 100:1 Mode
–65
25
–65
25
dB
µV
N
Output noise(6)
Clock feedthrough(7)
250
220
2
250
220
2
mV
(3) The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading Typical
Characteristics.
(4) Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in the Application Information.
(5) Crosstalk between the internal filter sections is measured by applying a 1 VRMS 10-kHz signal to one bandpass filter section input and
grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and
the 1 VRMS input signal of the other section.
(6) In 50:1 mode the output noise is 3 dB higher.
(7) In 50:1 mode the clock feed through is 6 dB higher.
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Electrical Characteristics for V+ = +2.5 V and V− = −2.5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +2.50 V and V− = −2.50 V unless
otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
LMF100CIWM
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
RL = 5 k
1.6
1.6
All Outputs
−2.2
−2.2
±1.5
±1.4
Tested
V
Limit(1)
RL = 5 k (All
Outputs)
TMIN to TMAX
±1.4
VOUT Minimum output voltage swing
Design
TMIN to TMAX
Limit(2)
1.5
−2.1
1.5
−2.1
RL = 3.5 k
All Outputs
V
GB
W
Operational amplifier gain BW
product
5
5
MHz
SR
Operational amplifier slew rate
18
10
20
18
10
20
V/µs
mA
Source
All Outputs
All Outputs
Maximum output,
Isc
Short circuit current(8)
Sink
mA
(8) The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then
shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its
maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions.
6.7 Logic Input Characteristics
All limits apply to TA = TJ = 25°C unless otherwise specified.
LMF100CCN
MIN TYP
LMF100CIWM
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
MAX
3
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
V+ = +5 V, V− = −5 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
3
V
3
−3
MAX Logical “0” VLSh = 0 V
TMIN to TMAX
TMIN to TMAX
–3
8
V
V
V
V
V
V
V
−3
CMOS Clock
Input Voltage
8
V+ = +10 V, V− = 0 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
8
2
MAX Logical “0” VLSh = +5 V
TMIN to TMAX
TMIN to TMAX
2
2
2
V+ = +5 V, V− = −5 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
2
2
0.8
MAX Logical “0” VLSh = 0 V
TMIN to TMAX
TMIN to TMAX
0.8
2
0.8
2
TTL Clock
Input Voltage
V+ = +10 V, V− = 0 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
2
0.8
MAX Logical “0” VLSh = 0 V
TMIN to TMAX
TMIN to TMAX
0.8
0.8
(1) Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
(2) Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
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Logic Input Characteristics (continued)
All limits apply to TA = TJ = 25°C unless otherwise specified.
LMF100CCN
MIN TYP
LMF100CIWM
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
MAX
1.5
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
Tested Limit(1)
Design Limit(2)
V+ = +2.5 V, V− = −2.5 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
1.5
V
1.5
−1.5
MAX Logical “0” VLSh = 0 V
TMIN to TMAX
TMIN to TMAX
−1.5
4
V
V
V
V
V
−1.5
CMOS Clock
Input Voltage
4
V+ = +5 V, V− = 0 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
4
1
MAX Logical “0” VLSh = +2.5 V
TMIN to TMAX
TMIN to TMAX
1
1
2
+ = +5 V, V− = 0 V,
MIN Logical “1”
TMIN to TMAX
TMIN to TMAX
2
V
2
TTL Clock
Input Voltage
0.8
VLSh = 0 V, VD+ = 0 V
MAX Logical “0”
TMIN to TMAX
TMIN to TMAX
0.8
0.8
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6.8 Typical Characteristics
Figure 1. Power Supply Current vs Power Supply Voltage
Figure 2. Power Supply Current vs Temperature
Figure 4. Positive Output Swing vs Temperature
Figure 3. Output Swing vs Supply Voltage
Figure 5. Negative Output Swing vs Temperature
Figure 6. Positive Output Voltage Swing vs Load Resistance
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Typical Characteristics (continued)
Figure 8. fCLK/f0 Ratio vs Q
Figure 7. Negative Output Voltage Swing vs Load
Resistance
Figure 9. fCLK/f0 Ratio vs Q
Figure 10. fCLK/f0 Ratio vs fCLK
Figure 11. fCLK/f0 Ratio vs fCLK
Figure 12. fCLK/f0 Ratio vs fCLK
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Typical Characteristics (continued)
Figure 14. fCLK/f0 Ratio vs Temperature
Figure 13. fCLK/f0 Ratio vs fCLK
Figure 15. fCLK/f0 Ratio vs Temperature
Figure 17. Q Deviation vs Clock Frequency
Figure 16. Q Deviation vs Clock Frequency
Figure 18. Q Deviation vs Clock Frequency
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Typical Characteristics (continued)
Figure 20. Q Deviation vs Temperature
Figure 19. Q Deviation vs Clock Frequency
Figure 22. Maximum f0 vs Q at Vs = ±7.5 V
Figure 21. Q Deviation vs Temperature
Figure 23. Maximum f0 vs Q at Vs = ±5 V
Figure 24. Maximum f0 vs Q at Vs = ±2.5 V
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7 Parameter Measurement Information
7.1 Definition of Terms Graphics
Figure 25. Second-Order Bandpass Response Gain
Figure 27. Second-Order Lowpass Response Gain
Figure 29. Second-Order Highpass Response Gain
Figure 26. Second-Order Bandpass Response
Phase
Figure 28. Second-Order Lowpass Response
Phase
Figure 30. Second-Order Highpass Response
Phase
Figure 31. Second-Order Notch Response Gain
Figure 32. Second-Order Notch Response Phase
Figure 33. Second-Order Allpass Response Gain
Figure 34. Second-Order Allpass Response Phase
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Definition of Terms Graphics (continued)
Figure 35. Bandpass Response of Various Second-Order
Filters as a Function of Q.
Figure 36. Lowpass Response of Various Second-Order
Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity
Gain
Gains and Center Frequencies are Normalized to Unity
Phase
Figure 37. Highpass Response of Various Second-Order
Filters as a Function of Q.
Figure 38. Notch Response of Various Second-Order
Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity
Gain
Gains and Center Frequencies are Normalized to Unity
Gain
Figure 39. Allpass Response of Various Second-Order Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity Gain
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8 Detailed Description
8.1 Overview
The LMF100 device contains two general-purpose, very high-performance switched capacitor filters that are cost-
effective and space-saving. It enables designers to implement all the classical filters up to fourth-order biquad
with one chip. This switched capacitor filters can be used in a broad range of industrial and consumer application
such as audio, communication, instrumentation, medical, telemetry, etc. It can be directly cascaded to implement
higher order filters,
8.2 Functional Block Diagram
8.3 Feature Description
The LMF100 is an all CMOS switched capacitor filter device that consists of two filters capable of wide supply
range from 4 V to 15 V. It features much higher performance than the pin-compatible MF10 device with operation
frequency to 100 kHz, which is 3X broader, and fo x Q range to 1.8 MHz which is 9X higher. Furthermore, it has
pins that also function to configure filter modes of operation, level shifting, clock to filter center frequency setting,
and power rail selections enabling flexibility and ease of programming.
8.4 Device Functional Modes
8.4.1 Modes of Operation
The LMF100 is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain
analysis is appropriate. Because this is cumbersome, and because the LMF100 closely approximates continuous
filters, the following discussion is based on the well-known frequency domain. Each LMF100 can produce two full
second-order functions. See Table 1 for a summary of the characteristics of the various modes.
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Device Functional Modes (continued)
8.4.1.1 MODE 1: Notch 1, Bandpass, Lowpass Outputs:
fnotch = f0 (See Figure 40)
fCLK
fCLK
50
f0 = center frequency of the complex pole pair =
or
100
(1)
(2)
fnotch = center frequency of the imaginary zero pair = f0
R2
HOLP = Lowpass gain (as f ® 0) = -
(3)
(4)
R3
HOBP = Bandpass gain (at f ® 0) = -
-R2
f ® 0
f ® fCLK / 2
=
HON = Notch output gain as
R1
(5)
f0
R3
Q =
=
= quality factor of the complex pole pair
BW R2
(6)
(7)
BW = the - 3 dB bandwidth of the bandpass output.
Circuit dynamics : HOBP = Q
1
(8)
HOBP
HOLP
=
or HOBP = HOLP ´Q = HON ´Q
Q
(9)
HOLP(peak) @ Q´HOLP (for high Q's)
(10)
8.4.1.2 MODE 1a: Noninverting BP, LP (See Figure 41)
fCLK
fCLK
f0 =
or
100
50
(11)
(12)
(13)
HOLP = -1; HOLP(peak) @ Q´HOLP (for high Q's)
R3
HOBP = -
1
R2
(14)
(15)
(16)
HOBP = 1(noninverting)
2
Circuit dynamics : HOBP = Q
1
Note: VIN should be driven from a low-impedance (<1 kΩ) source.
Figure 40. MODE 1
Figure 41. MODE 1a
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Device Functional Modes (continued)
8.4.1.3 MODE 1b: Notch 1, Bandpass, Lowpass Outputs:
fnotch = f0 (See Figure 42)
fCLK
fCLK
50
f0 = center frequency of the complex pole pair =
´ 2 or
´ 2
100
(17)
(18)
fnotch = center frequency of the imaginary zero pair = f0
R2
HOLP = Lowpass gain (as f ® 0) = -
(19)
(20)
R3
HOBP = Bandpass gain (at f ® 0) = -
-R2
f ® 0
f ® fCLK / 2
=
HON = Notch output gain as
R1
(21)
f0
R3
Q =
=
= quality factor of the complex pole pair
BW R2
(22)
(23)
BW = the - 3 dB bandwidth of the bandpass output.
Circuit dynamics:
HOBP
HOLP =
or HOBP = HOLP ´Q = 2
2Q
(24)
HON ´ Q
HOBP
=
2
(25)
(26)
HOLP(peak) @ Q´HOLP (for high Q's)
8.4.1.4 MODE 2: Notch 2, Bandpass, Lowpass: fnotch < f0 (See Figure 43)
fCLK
100
fCLK
50
R2
R4
R2
R4
f0 = center frequency =
´
+1 or
´
+1
(27)
(28)
fCLK
100
fCLK
50
fnotch
=
or
R2 / R4 +1
R2 / R3
Q = quality factor of the complex pole pair =
(29)
R2 / R1
HOLP = Lowpass output gain (as f ® 0) = -
R2 / R4 +1
(30)
(31)
HOBP = Bandpass gain (at f ® f0 ) = -R3 / R1
R2 / R1
HON = Notch output gain (as f ® 0) = -
1
R2 / R4 +1
(32)
fCLK
æ
ö
HON = Notch output gain as f ®
= - R2 / R1
÷
ç
1
2
è
ø
(33)
(34)
Filter dynamics : HOBP = Q HOLP HON
=
HOLP HON
2
2
1
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Device Functional Modes (continued)
Figure 42. MODE 1b
Figure 43. MODE 2
8.4.1.5 MODE 3: Highpass, Bandpass, Lowpass Outputs (See Figure 44)
fCLK
100
fCLK
50
R2
R4
R2
R4
f0 =
´
+1 or
´
(35)
(36)
R2 R3
´
Q = quality factor of the complex pole pair =
R4 R2
fCLK
æ
ö
R2
R1
HOLP = Highpass gain at f ®
= -
ç
÷
2
è
ø
(37)
(38)
(39)
R3
HOBP = Bandpass gain as f ® f = -
)
(
0
R4
HOLP = Lowpass gain (as f ® 0) = -
H
R2
Circuit dynamics :
=
OHP ; HOBP
R4 HOLP
=
HOHP ´HOLP ´Q
(40)
(41)
(42)
HOLP(peak) @ Q´HOLP (for high Q's)
HOHP(peak) @ Q´HOHP (for high Q's)
8.4.1.6 MODE 3a: HP, BP, LP and Notch With External Op Amp (See Figure 45)
fCLK
100
fCLK
50
R2
R4
R2
R4
f0 =
Q =
´
or
´
(43)
R2 R3
´
R4 R2
(44)
(45)
(46)
(47)
R2
HOHP = -
HOBP = -
HOLP = -
R1
R3
R1
R4
R1
fCLK Rh
100 Rl
fCLK Rh
50 Rl
fn = notch frequency =
or
(48)
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Device Functional Modes (continued)
R
Rg
Rh
æ
ö
HON = gain of notch at f = f = Q g HOLP
-
HOHP
ç
÷
0
ç
÷
Rl
è
ø
(49)
(50)
(51)
Rg
Hn1 = gain of notch as f ® 0 =
)
´HOLP
(
Rl
Rg
fCLK
æ
ç
ö
Hn2 = gain of notch as f ®
=
´HOHP
÷
2
Rh
è
ø
*In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp
causes a slight Q enhancement. If this is a problem, connect a small capacitor (10 pF−100 pF) across R4 to provide
some phase lead.
Figure 44. MODE 3
Figure 45. MODE 3a
8.4.1.7 MODE 4: Allpass, Bandpass, Lowpass Outputs (See Figure 46)
fCLK
100
fCLK
50
f0 = center frequency =
f0
or
;fz * = center frequency of the complex zero » f0
(52)
R3
R3
Q =
´
; Qz = quality factor of the complex zero pair -
BW R2
R1
(53)
(54)
For AP output make R1 = R2
fCLK
æ
ö
R2
R1
HOAP * = Allpass gain at 0 - f =
= -
= -1
ç
÷
2
è
ø
(55)
(56)
R2
R1
æ
ö
HOLP = Lowpass gain as f ® 0 = -
+1 = -2
(
)
ç
÷
è
ø
R3
R2
R2
R1
R3
R2
æ
ö
æ
ö
HOBP = Bandpass gain at f ® f = -
1+
= -2
(
)
0
ç
÷
ç
÷
è
ø
è
ø
(57)
(58)
Circuit dynamics : HOBP = HOLP ´Q = H
(
+1 Q
)
OAP
*Due to the sampled data nature f the filter, as light mismatch for fz and f0 occurs, causing a 0.4-dB peaking
around f0 of the allpass filter amplitude response (which theorectically should be a straight line). If this is
unacceptable, TI recommends Mode 5.
8.4.1.8 MODE 5: Numerator Complex Zeros, BP, LP (See Figure 47)
fCLK
fCLK
50
R2
R2
R4
f0 = 1+
´
or 1+
´
R4 100
fCLK
´
(59)
fCLK
50
R1
R1
R4
fz = 1-
or 1-
´
R4 100
(60)
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Device Functional Modes (continued)
R3
Q = 1+ R2 / R4 ´
R2
(61)
(62)
R3
Qz = 1- R1/ R4 ´
R1
-R2 R4 -R1
(
R1 R2 + R4
)
)
H0z1 = gain at C.Z. output as f ® 0 Hz
(
)
(
(63)
(64)
(65)
(66)
fCLK
æ
ö -R2
H2 = gain at C.Z. output as f ®
ç
÷
2
R1
ø
è
R2
R1
R3
R2
æ
ö
HOBP = -
+1 ´
ç
÷
è
ø
R2 + R1 R4
æ
ö
÷
HOLP = -
´
ç
R2 + R4
R1
è
ø
Figure 46. MODE 4
8.4.1.9 MODE 6a: Single-Pole, HP, LP Filter (See Figure 48)
Figure 47. MODE 5
f
f
CLK
R2
R2
CLK
f0 = cutoff frequency of LP or HP output =
or
R3 100
R3 50
(67)
(68)
(69)
R3
HOLP = -
R1
R2
HOHP = -
R1
Figure 48. MODE 6a
8.4.1.10 MODE 6b: Single-Pole LP Filter (Inverting and Noninverting) (See Figure 49)
f
f
CLK
R2
R2
CLK
fc = cutoff frequency of LP outputs =
or
R3 100 R3 50
(70)
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Device Functional Modes (continued)
HOLP = 1 noninverting
(
)
1
(71)
(72)
R3
R2
HOHP
=
2
8.4.1.11 MODE 6c: Single-Pole, AP, LP Filter (See Figure 50)
fCLK
fCLK
fc =
or
100
50
(73)
(74)
(75)
(76)
(77)
HOAP =1(as f ®0)
HOAP = -1(as f ® fCLK / 2)
HOLP = -2
R1 = R2 = R3
Figure 49. MODE 6b
Figure 50. MODE 6c
8.4.1.12 Summing Integrator (See Figure 52)
16
8
t
= integrator time constant @
or
fCLK
fCLK
Figure 51. Equivalent Circuit
Figure 52. MODE 7
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Device Functional Modes (continued)
Table 1. Summary of Modes(1)
NUMBER
ADJUSTABLE
fCLK/f0
OF
RESISTOR
S
MODE
BP
LP
HP
N
AP
NOTES
1
1a
1b
2
*
*
*
3
2
3
3
No
No
No
HOBP1 = −Q
HOBP2 = + 1
HOLP = + 1
May need input buffer. Poor dynamics for high Q.
Useful for high-frequency applications.
*
*
*
*
*
Yes (above fCLK/50 or
fCLK/100)
*
Universal State-Variable Filter. Best general-purpose
mode.
3
3a
4
*
*
*
*
*
*
*
*
4
7
3
Yes
Yes
No
*
As above, but also includes resistor-tuneable notch.
Gives Allpass response with HOAP = − 1 and HOLP
−2.
=
*
*
Gives flatter allpass response than above
if R1 = R2 = 0.02R4.
5
*
*
4
3
Yes
Yes
6a
*
*
Single pole.
HOLP1 = +1
6b
-R3
2
Yes
Single pole.
HOLP2
=
R2
6c
7
*
*
3
2
No
Single pole.
Yes
Summing integrator with adjustable time constant.
(1) Realizable filter types (that is, lowpass) denoted by asterisks (*). Unless otherwise noted, gains of various filter outputs are inverting and
adjustable by resistor ratios.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMF100 is a general purpose dual second-order state variable filter whose center frequency is proportional
to the frequency of the square wave applied to the clock input (fCLK). The various clocking options are
summarized in Table 2.
Table 2. Clocking Options
+
POWER SUPPLY
−5 V and +5 V
−5 V and +5 V
0 V and 10 V
0 V and 10 V
−2.5 V and +2.5 V
0 V and 5 V
CLOCK LEVELS
TTL (0 V to 5 V)
LSh
0 V
VD
+5 V
+5 V
+10 V
+10 V
+2.5 V
0 V
CMOS (−5 V to +5 V)
TTL (0 V to 5 V)
0 V
0 V
CMOS (0 V to 10 V)
CMOS
+5 V
0 V
(−2.5 V to +2.5 V) TTL (0 V to 5 V)
CMOS (0 V to 5 V)
0 V
0 V and 5 V
+2.5 V
+5 V
By connecting pin 12 to the appropriate DC voltage, the filter center frequency, f0, can be made equal to either
fCLK/100 or fCLK/50. f0 can be very accurately set (within ±0.6%) by using a crystal clock oscillator, or can be
easily varied over a wide frequency range by adjusting the clock frequency. If desired, the fCLK/f0 ratio can be
altered by external resistors as in Figure 43 through Figure 49. This is useful when high-order filters (greater than
two) are to be realized by cascading the second-order sections. This allows each stage to be stagger tuned while
using only one clock. The filter Q and gain are set by external resistor ratios.
All of the five second-order filter types can be built using either section of the LMF100. These are illustrated in
Figure 25 through Figure 33 along with their transfer functions and some related equations. Figure 35 shows the
effect of Q on the shapes of these curves.
9.2 Typical Application
When designing a LP filter that has similar pass band characteristic as a Butterworth topology but requiring a
much steeper roll off then a fourth-order Chebyshev topology can implement the need with one LMF100.
Figure 53. Implement a Fourth-Order Chebyshev LP Filter Having a 1-kHz Cutoff Frequency and 1-dB PB
Ripple With an LMF100
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Typical Application (continued)
9.2.1 Design Requirements
In order to design a filter using the LMF100, we must define the necessary values of three parameters for each
second-order section: f0, the filter section’s center frequency; H0, the passband gain; and the filter’s Q. These are
determined by the characteristics required of the filter being designed.
As an example, assume that a system requires a fourth-order Chebyshev lowpass filter with 1-dB ripple, unity
gain at DC, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both second-order
sections of an LMF100. Many filter design texts (and TI Switched Capacitor Filter Handbook) include tables that
list the characteristics (f0 and Q) of each of the second-order filter sections needed to synthesize a given higher-
order filter. For the Chebyshev filter defined above, such a table yields the following characteristics:
f0A = 529 Hz — — QA = 0.785
f0B = 993 Hz — — QB = 3.559
For unity gain at DC, we also specify:
H0A = 1
H0B = 1
The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100, and a 100-kHz clock signal
is available. The required center frequencies for the two second-order sections will not be obtainable with clock-
fCLK
f0
to-center-frequency ratios of 50 or 100. It will be necessary to adjust
externally. From Table 1, we see that
Mode 3 can be used to produce a lowpass filter with resistor-adjustable center frequency.
In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values
ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher
relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage
will provide some attenuation at the center frequency and thus help avoid clipping of signals near this frequency.
For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage.
For the first section, we begin the design by choosing a convenient value for the input resistance: R1A = 20 k.
The absolute value of the passband gain HOLPA is made equal to 1 by choosing R4A such that: R4A = −HOLPAR1A
=
R1A = 20 k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we
find R2A by:
2
(529)2
(1000)2
f0A
R2A = R4A
= 2´104 ´
= 5.6k and
2
)
f
(
/ 100
CLK
R3A = QA R2AR4A = 0.785 5.6´103 ´ 2´104 = 8.3k
The resistors for the second section are found in a similar fashion:
R1B = 20k
R4B = R1B = 20k
2
(993)2
(1000)2
f0B
R2B = R4B
= 20k
= 19.7k
2
)
f
(
/ 100
CLK
R3B = QB R2BR4B = 3.559 1.97´104 ´ 2´104 = 70.6k
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Typical Application (continued)
The complete circuit is shown in Figure 54 for split ±5-V power supplies. TI highly recommends Supply bypass
capacitors.
±5-V power supply. 0-V to 5-V TTL or ±5-V CMOS logic levels.
Figure 54. Fourth-Order Chebyshev Lowpass Filter from Example in 3.1.
9.2.2 Detailed Design Procedure
9.2.2.1 Single-Supply Operation
The LMF100 can also operate with a single-ended power supply. Figure 55 shows the example filter with a
+
+
single-ended power supply. VA and VD are again connected to the positive power supply (4 to 15 volts), and
−
−
VA and VD are connected to ground. The AGND pin must be tied to V+/2 for single-supply operation. This half-
supply point should be very “clean”, as any noise appearing on it will be treated as an input to the filter. It can be
derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure 56), or a low-impedance
half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (Figure 57
and Figure 58). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided
that the time constant is long enough to reject any power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or
operational amplifier approaches may be preferable because they will require smaller capacitors to filter the clock
frequency. The main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 μF
26
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Typical Application (continued)
Single 10-V power supply. 0-V to 5-V TTL logic levels. Input signals should be referred to half-supply or applied
through a coupling capacitor.
Figure 55. Fourth-Order Chebyshev Lowpass Filter from Example in 3.1.
Figure 56. Three Ways of Generating V+/2 for
Single-Supply Operation Option A
Figure 57. Three Ways of Generating V+/2 for
Single-Supply Operation Option B
Figure 58. Three Ways of Generating V+/2 for Single-Supply Operation Option C
9.2.2.2 Dynamic Considerations
The maximum signal handling capability of the LMF100, like that of any active filter, is limited by the power
supply voltages used. The amplifiers in the LMF100 can swing to within about 1 volt of the supplies, so the input
signals must be kept small enough that none of the outputs will exceed these limits. If the LMF100 is operating
on ±5 volts, for example, the outputs will clip at about 8 Vp-p. The maximum input voltage multiplied by the filter
gain should therefore be less than 8 Vp-p
.
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Typical Application (continued)
If the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain
(Figure 35). As an example, a lowpass filter with a Q of 10 will have a 20-dB peak in its amplitude response at f0.
If the nominal gain of the filter (HOLP) is equal to 1, the gain at f0 will be 10. The maximum input signal at f0 must
therefore be less than 800 mVp-p when the circuit is operated on ±5 volt supplies.
Also, one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 40). The notch output will be very small at f0, so it might appear safe
to apply a large signal to the input. However, the bandpass will have its maximum gain at f0 and can clip if
overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any
filter section, even ones whose outputs are not being directly used. Accompanying Figure 40 through Figure 50
are equations labeled circuit dynamics, which relate the Q and the gains at the various outputs. These should be
consulted to determine peak circuit gains and maximum allowable signals for a given application.
9.2.2.3 Offset Voltage
The switched capacitor integrators of the LMF100 have a slightly higher input offset voltage than found in a
typical continuous time active filter integrator. Because of TI's new LMCMOS process and new design techniques
the internal offsets have been minimized, compared to the industry standard MF10. Figure 59 shows an
equivalent circuit of the LMF100 from which the output DC offsets can be calculated. Typical values for these
offsets with SA/B tied to V+ are:
VOS1 = opamp offset = ±5 mV
VOS2 = ±30 mV at 50:1 or 100:1
VOS3 = ±15 mV at 50:1 or 100:1
When SA/B is tied to V−, VOS2 will approximately halve. The DC offset at the BP output is equal to the input offset
of the lowpass integrator (VOS3). The offsets at the other outputs depend on the mode of operation and the
resistor ratios, as described in the following expressions.
Mode 1 and Mode 4
VOS3
Q
1
æ
ö
VOS(N)
= VOS1
+1+ HOLP
-
ç
÷
Q
è
ø
VOS(BP)
VOS(LP)
= VOS3
= VOS(N) - VOS2
Mode 1a
VOS3
Q
1
æ
ö
VOS(N.INV.BP)
= 1+
VOS1
-
ç
÷
Q
è
ø
VOS(INV.BP)
VOS(LP)
= VOS3
= VOS(N.INV.BP) - VOS2
Mode 1b
R2 R2
+
R3 R1
R2
R3
æ
ö
VOS(N)
= VOS1 1+
-
VOS3
ç
÷
è
ø
VOS(BP)
= VOS3
VOS(N)
VOS2
VOS(LP)
=
-
Mode 2 and Mode 5
æ
ç
è
ö
VOS3
R2
Rp
1
1
VOS(N)
=
+1 V
´
+ VOS2
-
: Rp = R1|| R3 || R4
÷
OS3
1+ R2 / R4
1+ R4 / R2
Q 1+ R2 / R4
ø
VOS(BP)
VOS(LP)
= VOS3
= VOS(N) - VOS2
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Typical Application (continued)
Mode 3
VOS(HP)
= VOS2
VOS(BP)
= VOS3
é
ù
R4
R
R4
R2
R4
R3
æ
ö
æ
ö
VOS(LP)
= V
1+
- V
- VOS3
OS1 ê
ú
OS2
ç
÷
ç
÷
è
ø
è
ø
ê
ë
ú
p û
Rp = R1|| R2 || R3
Mode 6a and 6c
VOS(HP)
= VOS2
æ
ö
÷
ø
R3 R3
+
R2 R1
R3
R2
VOS(LP)
= V
OS1 ç
1+
-
VOS2
è
Mode 6b
VOS(LP(N.INV))
= VOS2
æ
ö
R3
R2
R3
R2
VOS(LP(INV))
= V
OS1 ç
1+
-
VOS2
÷
è
ø
Figure 59. Offset Voltage Sources
In many applications, the outputs are AC-coupled and DC offsets are not bothersome unless large signals are
applied to the filter input. However, larger offset voltages will cause clipping to occur at lower AC signal levels,
and clipping at any of the outputs will cause gain nonlinearities and will change f0 and Q. When operating in
Mode 3, offsets can become excessively large if R2 and R4 are used to make fCLK/f0 significantly higher than the
nominal value, especially if Q is also high.
For example, Figure 60 shows a second-order 60-Hz notch filter. This circuit yields a notch with about 40 dB of
attenuation at 60 Hz. A notch is formed by subtracting the bandpass output of a mode 3 configuration from the
input using the unused side B operational amplifier. The Q is 10 and the gain is 1 V/V in the passband. However,
fCLK/f0 = 1000 to allow for a wide input spectrum. This means that for pin 12 tied to ground (100:1 mode),
R4/R2 = 100. The offset voltage at the lowpass output (LP) will be about 3 V. However, this is an extreme case
and the resistor ratio is usually much smaller. Where necessary, the offset voltage can be adjusted by using the
circuit of Figure 61. This allows adjustment of VOS1, which will have varying effects on the different outputs as
described in the above equations. Some outputs cannot be adjusted this way in some modes, however (VOS(BP)
in modes 1a and 3, for example).
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Typical Application (continued)
Figure 60. Second-Order Notch Filter
Figure 61. Method for Trimming VOS
9.2.2.4 Sampled Data System Considerations
The LMF100 is a sampled data filter, and as such, differs in many ways from conventional continuous-time filters.
An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-
half the sampling frequency. (The sampling frequency of the LMF100 is the same as its clock frequency.) If a
signal with a frequency greater than one-half the sampling frequency is applied to the input of a sampled data
system, it will be reflected to a frequency less than one-half the sampling frequency. Thus, an input signal whose
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Typical Application (continued)
frequency is fs/2 + 100 Hz will cause the system to respond as though the input frequency was fs/2 − 100 Hz.
This phenomenon is known as aliasing, and can be reduced or eliminated by limiting the input signal spectrum to
less than fs/2. This may in some cases require the use of a bandwidth-limiting filter ahead of the LMF100 to limit
the input spectrum. However, because the clock frequency is much higher than the center frequency, this will
often not be necessary.
Another characteristic of sampled-data circuits is that the output signal changes amplitude once every sampling
period, resulting in “steps” in the output voltage which occur at the clock rate (Figure 62). If necessary, these can
be “smoothed” with a simple R-C lowpass filter at the LMF100 output.
The ratio of fCLK to fc (normally either 50:1 or 100:1) will also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise-sensitive applications, a ratio
of 100:1 will result in 3 dB lower output noise for the same filter configuration.
The accuracy of the fCLK/f0 ratio is dependent on the value of Q. This is shown in the curves under the heading
Figure 54. As Q is changed, the true value of the ratio changes as well. Unless the Q is low, the error in fCLK/f0
will be small. If the error is too large for a specific application, use a mode that allows adjustment of the ratio with
external resistors.
Figure 62. The Sampled-Data Output Waveform
9.2.3 Application Curve
Figure 63. The Wide BW of a Fourth-Order Butterworth LP Implemented With One LMF100
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10 Power Supply Recommendations
The LMF100 can operate with a single-ended power supply as well as bipolar supplies. Refer to Figure 56
through Figure 58 for methods of generating V+/2 for single-supply operation. In this circumstance, pins VA+ and
VD+ are connected to the positive power supply (4 to 15 V), and VA− and VD− are connected to ground. The
AGND pin must be tied to V+/2. Furthermore, the half-supply node should be very “clean”, as any noise
appearing on it will be treated as an input to the filter. Ensure liberal bypassing is employed to reject any supply
noise and present a low impedance to the clock frequency. Bypass caps should always be located as close to
the supply pins a practical. Moreover, the regulator or op-amp approaches of generating V+/e is preferred for
very low clock frequency applications. The main power supply voltage should also be clean (preferably
regulated) and bypassed with 0.1-µF nonpolar ceramic capacitor. If there is no bulk cap nearby, a 10-uF
electrolytic tantalum in parallel with the 0.1-µF supply bypass cap should achieve cleaner and optimal transient
response. Select capacitors with low ESR and ESL rating and test them to ensure no ringing occurs. The power
source is preferably a linear supply or regulator. If a switching supply is used ensure it is a clean switcher and
deploy proper bypassing or post regulate with an LDO as necessary.
11 Layout
11.1 Layout Guidelines
The most critical part to the success of a switched capacitor filter design is a properly layout PCB. Because of
the mixed signal circuitry involved, take extra care in the board design for noise abatement, star-grounding, and
shielding techniques. A ground plane must separate digital and analog ground planes if possible, or have
separate paths and join together only at the common return node at the supply source. All component leads and
PCB tracks are kept as short as possible. The filter clock input should be a shielded cable.
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SNOSBG9B –JULY 1999–REVISED JUNE 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Definitions of Terms
fCLK: the frequency of the external clock signal applied to pin 10 or 11.
f0: center frequency of the second order function complex pole pair. f0 is measured at the bandpass outputs of
the LMF100, and is the frequency of maximum bandpass gain. (Figure 25).
fnotch: the frequency of minimum (ideally zero) gain at the notch outputs.
fz: the center frequency of the second order complex zero pair, if any. If is different from and if Qz is high, it
fz
f0
can be observed as the frequency of a notch at the allpass output. (Figure 46).
Q: “quality factor” of the 2nd order filter. Q is measured at the bandpass outputs of the LMF100 and is equal to f0
divided by the −3 dB bandwidth of the 2nd order bandpass filter (Figure 25). The value of Q determines the shape
of the 2nd order filter responses as shown in Figure 35.
Qz: the quality factor of the second order complex zero pair, if any. QZ is related to the allpass characteristic,
which is written:
2
æ
ö
÷
÷
ø
swo + wo
H
s2 -
ç
OAP ç
Qz
è
HAP(s) =
swo
2
s2 -
+ wo
Q
where QZ = Q for an allpass response.
HOLP: the gain (in V/V) of the lowpass output as f → 0 Hz (Figure 27).
HOHP: the gain (in V/V) of the highpass output as f → fCLK/2 (Figure 29).
HON: the gain (in V/V) of the notch output as f → 0 Hz and as f → fCLK/2, when the notch filter has equal gain
above and below the center frequency (Figure 31 ). When the low-frequency gain differs from the high-frequency
gain, as in modes 2 and 3a (Figure 43 and Figure 45), the two quantities below are used in place of HON
.
HON1: the gain (in V/V) of the notch output as f → 0 Hz.
HON2: the gain (in V/V) of the notch output as f → fCLK/2.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
LMCMOS, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2016
PACKAGING INFORMATION
Orderable Device
LMF100CIWM
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OBSOLETE
SOIC
SOIC
SOIC
SOIC
DW
20
20
20
20
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
LMF100
CIWM
LMF100CIWM/NOPB
LMF100CIWMX
OBSOLETE
OBSOLETE
OBSOLETE
DW
DW
DW
-40 to 85
LMF100
CIWM
-40 to 85
LMF100
CIWM
LMF100CIWMX/NOPB
-40 to 85
LMF100
CIWM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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