LMG1205 [TI]

适用于 GaNFET 和 MOSFET、具有 5V UVLO 的 1.2A/5A 90V 半桥栅极驱动器;


型号：	LMG1205
厂家：	TEXAS INSTRUMENTS
描述：	适用于 GaNFET 和 MOSFET、具有 5V UVLO 的 1.2A/5A 90V 半桥栅极驱动器栅极驱动驱动器
文件：	总27页 (文件大小：1631K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMG1205

ZHCSG61B –MARCH 2017 –REVISED APRIL 2023

LMG1205 具有集成自举二极管的100V、1.2A 至5A 半桥GaN 驱动器

1 特性

3 说明

• 独立的高边和低边

TTL 逻辑输入

LMG1205 设计用于驱动采用同步降压、升压或半桥配

置的高边和低边增强模式氮化镓 (GaN) FET。此器件

具有一个集成于内部的100V 自举二极管，还为高边和

低边输出分别提供了独立的输入，可实现最大程度的灵

活控制。高边偏置电压采用自举技术生成，内部钳位为

5V，可防止栅极电压超过增强模式GaN FET 的最大栅

源电压额定值。LMG1205 的输入与TTL 逻辑兼容，并

且无论VDD 电压如何，都能够承受高达14V 的输入电

压。LMG1205 具有分离栅输出，可独立灵活地调节导

通和关断强度。

• 1.2A 峰值拉电流，5A 灌电流

• 高边浮动偏置电压轨

工作电压高达100VDC

• 内部自举电源电压钳位

• 分离输出实现可调的

导通/关断强度

• 0.6Ω 下拉电阻，2.1Ω 上拉电阻

• 快速传播时间（典型值为35ns）

• 出色的传播延迟匹配

（典型值为1.5ns）

此外，LMG1205 具有强劲的灌电流能力，可使栅极保

持低电平状态，从而防止开关操作期间发生意外导通。

LMG1205 的工作频率可高达数 MHz。LMG1205 采用

12 引脚 DSBGA 封装，具有紧凑的外形尺寸和超小的

封装电感。

• 电源轨欠压锁定

• 低功耗

2 应用

• 电流馈入型推挽式转换器

• 半桥和全桥转换器

• 同步降压转换器

• 双开关正激式转换器

• 有源钳位正激式转换器

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

LMG1205

封装

DSBGA (12)

2.00mm x 2.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

0.1 ꢀF

VIN

HOH

VDD

1 ꢀF

Load

LMG1205

LOH

LOL

VSS

简化版应用示意图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNOSD37

LMG1205

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ZHCSG61B –MARCH 2017 –REVISED APRIL 2023

Table of Contents

7.4 Device Functional Modes..........................................12

8 Application and Implementation..................................13

8.1 Application Information............................................. 13

8.2 Typical Application.................................................... 13

9 Power Supply Recommendations................................17

10 Layout...........................................................................18

10.1 Layout Guidelines................................................... 18

10.2 Layout Examples.................................................... 18

11 Device and Documentation Support..........................19

11.1 Device Support........................................................19

11.2 Documentation Support.......................................... 19

11.3 接收文档更新通知................................................... 19

11.4 支持资源..................................................................19

11.5 Trademarks............................................................. 19

11.6 静电放电警告...........................................................19

11.7 术语表..................................................................... 19

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics............................................7

6.7 Typical Characteristics................................................8

7 Detailed Description......................................................11

7.1 Overview................................................................... 11

7.2 Functional Block Diagram......................................... 11

7.3 Feature Description...................................................11

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (February 2018) to Revision B (April 2023)

Page

• 将数据表标题从 80V 更改为 100V......................................................................................................................1

• Added clamping circuit delay time and functional explanation to 节7.3.3 .......................................................12

• Changed equation in 节8.2.2.2 .......................................................................................................................14

Changes from Revision * (March 2017) to Revision A (February 2018)

Page

• 更改了数据表标题...............................................................................................................................................1

English Data Sheet: SNOSD37

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5 Pin Configuration and Functions

LOL

LOH

VSS

VDD

HOL

HOH

图5-1. YFX Package 12-Pin DSBGA Top View

表5-1. Pin Functions

TYPE ⁽²⁾

DESCRIPTION

NUMBER

NAME

LOL

Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with

a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.

VSS

VDD

Ground return: all signals are referenced to this ground.

5-V positive gate drive supply: locally decouple to VSS using low ESR/ESL capacitor

located as close as possible to the IC.

A3, C4⁽¹⁾

Low-side driver control input. The LMG1205 inputs have TTL type thresholds. Unused

inputs must be tied to ground and not left open.

Low-side gate driver source-current output: connect to the gate of low-side GaN FET with a

short, low inductance path. A gate resistor can be used to adjust the turnon speed.

LOH

High-side driver control input. The LMG1205 inputs have TTL type thresholds. Unused

inputs must be tied to ground and not left open.

High-side GaN FET source connection: connect to the bootstrap capacitor negative

terminal and the source of the high-side GaN FET.

C1, D4⁽¹⁾

High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short,

low inductance path. A gate resistor can be used to adjust the turnoff speed.

HOL

HOH

High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short,

low inductance path. A gate resistor can be used to adjust the turnon speed.

High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor

to HB and the negative terminal to HS. The bootstrap capacitor must be placed as close as

possible to the IC.

(1) A3 and C4, C1 and D4 are internally connected

(2) I = Input, O = Output, G = Ground, P = Power

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English Data Sheet: SNOSD37

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

V_HS–0.3

–5

MAX

UNIT

VDD to VSS

HB to HS

LI or HI input

LOH, LOL output

VDD +0.3

HOH, HOL output

HS to VSS

V_HB+0.3

HS to VSS ⁽²⁾

100

–5

HB to VSS

100

HB to VSS⁽²⁾

107

Operating junction temperature

Storage temperature, T_stg

150

°C

150

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Device can withstand 1000 pulses up to the value indicated in the table of 100-ms duration and less than 1% duty cycle over its

lifetime.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

5.5

UNIT

VDD

LI or HI input

–5

V_HS+ 4

V_HS+ 5.5

HS slew rate

V/ns

°C

Operating junction temperature

125

–40

6.4 Thermal Information

LMG1205

THERMAL METRIC⁽¹⁾

YFX (DSBGA)

12 PINS

76.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

R_θJC(top)

R_θJB

0.6

12.0

1.6

ψ_JT

English Data Sheet: SNOSD37

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6.4 Thermal Information (continued)

LMG1205

THERMAL METRIC⁽¹⁾

YFX (DSBGA)

12 PINS

12.0

UNIT

Junction-to-board characterization parameter

°C/W

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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English Data Sheet: SNOSD37

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6.5 Electrical Characteristics

Specifications are T_J= 25°C. Unless otherwise specified: V_DD= V_HB= 5 V, V_SS= V_HS= 0 V.

No load on LOL and HOL or HOH and HOL⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

0.09

MAX

UNIT

SUPPLY CURRENTS

T_J= 25°C

LI = HI = 0 V, V_DD= V_HB

4 V

I_DD

VDD quiescent current

µA

0.12

T_J= –40°C to 125°C

T_J= 25°C

I_DDO

VDD operating current

f = 500 kHz

T_J= –40°C to 125°C

T_J= 25°C

0.10

1.5

0.1

0.4

LI = HI = 0 V, V_DD= V_HB

4 V

I_HB

Total HB quiescent current

Total HB operating current

HB to VSS quiescent current

HB to VSS operating current

0.12

2.5

T_J= –40°C to 125°C

T_J= 25°C

I_HBO

I_HBS

I_HBSO

f = 500 kHz

T_J= –40°C to 125°C

T_J= 25°C

HS = HB = 80 V

f = 500 kHz

T_J= –40°C to 125°C

T_J= 25°C

T_J= –40°C to 125°C

INPUT PINS

T_J= 25°C

2.06

1.66

V_IR

Input voltage threshold

Rising edge

Falling edge

1.89

1.48

2.18

1.76

T_J= –40°C to 125°C

T_J= 25°C

V_IF

Input voltage threshold

Input voltage hysteresis

Input pulldown resistance

T_J= –40°C to 125°C

V_IHYS

R_I

400

200

kΩ

T_J= 25°C

100

3.2

2.5

300

4.5

3.9

T_J= –40°C to 125°C

UNDERVOLTAGE PROTECTION

T_J= 25°C

3.8

V_DDR

V_DDH

V_HBR

V_HBH

VDD rising threshold

VDD threshold hysteresis

HB rising threshold

T_J= –40°C to 125°C

0.2

3.2

T_J= 25°C

T_J= –40°C to 125°C

HB threshold hysteresis

0.2

0.45

0.9

BOOTSTRAP DIODE AND CLAMP

T_J= 25°C

V_DL

V_DH

R_D

Low-current forward voltage

High-current forward voltage

Dynamic resistance

I_VDD-HB= 100 µA

I_VDD-HB= 100 mA

0.65

T_J= –40°C to 125°C

T_J= 25°C

T_J= –40°C to 125°C

T_J= 25°C

1.85

Ω

3.6

5.25

T_J= –40°C to 125°C

T_J= 25°C

HB-HS clamp regulation voltage

4.5

T_J= –40°C to 125°C

English Data Sheet: SNOSD37

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6.5 Electrical Characteristics (continued)

Specifications are T_J= 25°C. Unless otherwise specified: V_DD= V_HB= 5 V, V_SS= V_HS= 0 V.

No load on LOL and HOL or HOH and HOL⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

0.06

0.21

MAX

UNIT

LOW- and HIGH-SIDE GATE DRIVER

T_J= 25°C

V_OL

Low-level output voltage

I_HOL= I_LOL= 100 mA

I_HOH= I_LOH= 100 mA

0.1

T_J= –40°C to 125°C

High-level output voltage

V_OH= VDD –LOH

or V_OH= HB –HOH

T_J= 25°C

V_OH

0.31

T_J= –40°C to 125°C

I_OHL

I_OLL

Peak source current

Peak sink current

HOH, LOH = 0 V

HOL, LOL = 5 V

1.2

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_LPHL

t_LPLH

t_HPHL

t_HPLH

LO turnoff propagation delay

LI falling to LOL falling

LI rising to LOH rising

HI falling to HOL falling

HI rising to HOH rising

T_J= 25°C

33.5

T_J= –40°C to

125°C

LO turnon propagation delay

HO turnoff propagation delay

HO turnon propagation delay

T_J= 25°C

33.5

T_J= –40°C to

125°C

T_J= 25°C

T_J= –40°C to

125°C

T_J= 25°C

T_J= –40°C to

125°C

t_MON

Delay matching

LO on and HO off

T_J= 25°C

1.5

T_J= –40°C to 125°C

T_J= 25°C

t_MOFF

Delay matching

LO off and HO on

T_J= –40°C to 125°C

C_L= 1000 pF

t_HRC

t_LRC

t_HFC

t_LFC

t_PW

HO rise time (0.5 V –4.5 V)

LO rise time (0.5 V –4.5 V)

HO fall time (0.5 V –4.5 V)

LO fall time (0.5 V –4.5 V)

3.5

Minimum input pulse width

that changes the output

t_BS

Bootstrap diode

reverse recovery time

I_F= 100 mA, I_R= 100 mA

(1) Parameters that show only a typical value are ensured by design and may not be tested in production.

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HPLH

LPLH

HPHL

LPHL

MON

MOFF

图6-1. Timing Diagram

6.7 Typical Characteristics

图6-2. Peak Source Current vs Output Voltage

图6-3. Peak Sink Current vs Output Voltage

图6-4. I_DDOvs Frequency

图6-5. I_HBOvs Frequency

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6.7 Typical Characteristics (continued)

100

-50 -25

25 50 75 100 125 150

-50 -25

25 50 75 100 125 150

TEMPERATURE (ºC)

D005

D006

图6-6. I_DDvs Temperature

图6-7. I_HBvs Temperature

图6-8. UVLO Rising Thresholds vs Temperature

图6-9. UVLO Falling Thresholds vs Temperature

图6-10. Input Thresholds vs Temperature

图6-11. Input Threshold Hysteresis vs Temperature

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6.7 Typical Characteristics (continued)

T_PLH

T_PHL

-50 -25

25 50 75 100 125 150

TEMPERATURE (ºC)

图6-13. Propagation Delay vs Temperature

5.2

D012

图6-12. Bootstrap Diode Forward Voltage

5.1

4.9

4.8

4.7

-50 -25

25 50 75 100 125 150

TEMPERATURE (ºC)

D014

图6-14. LO & HO Gate Drive –High/Low Level Output Voltage

vs Temperature

图6-15. HB Regulation Voltage vs Temperature

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7 Detailed Description

7.1 Overview

The LMG1205 is a high frequency high- and low- side gate driver for enhancement mode Gallium Nitride (GaN)

FETs in a synchronous buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a

bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the

maximum gate-source voltage rating of enhancement mode GaN FETs. The LMG1205 has split-gate outputs

with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.

The LMG1205 can operate up to several MHz, and is available in a 12-pin DSBGA package that offers a

compact footprint and minimized package inductance.

7.2 Functional Block Diagram

UVLO

& CLAMP

HOH

LEVEL

SHIFT

HOL

VDD

UVLO

LOH

LOL

VSS

7.3 Feature Description

7.3.1 Input and Output

The input pins of the LMG1205 are independently controlled with TTL input thresholds and can withstand

voltages up to 12 V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs

of an analog PWM controller with up to 12-V power supply, eliminating the need for a buffer stage.

The output pulldown and pullup resistance of LMG1205 is optimized for enhancement mode GaN FETs to

achieve high frequency and efficient operation. The 0.6-Ωpulldown resistance provides a robust low impedance

turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup

resistance helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LMG1205

offers flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the

turnon path and/or the turnoff path.

If the input signal for either of the the two channels, HI or LI, is not used, the control pin must be tied to either

VDD or VSS. These inputs must not be left floating.

7.3.2 Start-up and UVLO

The LMG1205 has an undervoltage lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD

voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs

from being partially turned on. Also, if there is insufficient VDD voltage, the UVLO actively pulls the LOL and

HOL low. When the VDD voltage is above its UVLO threshold, but the HB to HS bootstrap voltage is below the

UVLO threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to

avoid chattering.

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表7-1. VDD UVLO Feature Logic Operation

CONDITION (V_HB-HS> V_HBRfor all cases below)

V_DD- V_SS< V_DDRduring device start-up

V_DD- V_SS< V_DDR- V_DDHafter device start-up

表7-2. V_HB-HSUVLO Feature Logic Operation

CONDITION (V_DD> V_DDRfor all cases below)

V_HB-HS< V_HBRduring device start-up

V_HB-HS< V_HBR- V_HBHafter device start-up

7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping

Due to the intrinsic nature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch is

usually higher than a diode forward voltage drop when the gate is pulled low. This causes negative voltage on

HS pin. Moreover, this negative voltage transient may become even more pronounced due to the effects of

board layout and device drain/source parasitic inductances. With high-side driver using the floating bootstrap

configuration, negative HS voltage can lead to an excessive bootstrap voltage, which can damage the high-side

GaN FET. The LMG1205 solves this problem with an internal clamping circuit that prevents the bootstrap voltage

from exceeding 5 V typical. The clamping circuit works by opening an internal switch in series with the internal

bootstrap diode when the bootstrap voltage exceeds the threshold, preventing further charging. The clamping

circuit has a delay of about 270 ns between the threshold being exceeded and charging being stopped. In

addition, the clamping circuit is bypassed if an external bootstrap diode is used.

7.3.4 Level Shift

The level-shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to

the switch node (HS). The level shift allows control of the HO output, which is referenced to the HS pin and

provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around

1.5 ns.

7.4 Device Functional Modes

表7-3 shows the device truth table.

表7-3. Truth Table

HOH

Open

HOL

LOH

Open

LOL

Open

English Data Sheet: SNOSD37

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a

powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.

Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current

levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation

is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which

cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3 V signal to the gate-drive

voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses.

Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove

inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both

the level-shifting and buffer-drive functions. Gate drivers also address other needs such as minimizing the effect

of high-frequency switching noise (by placing the high-current driver IC physically close to the power switch),

driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and

thermal stress in controllers by moving gate charge power losses from the controller into the driver.

The LMG1205 is a MHz high- and low-side gate driver for enhancement mode GaN FETs in a synchronous

buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a bootstrap technique

and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source

voltage rating of enhancement mode GaN FETs. The LMG1205 has split-gate outputs with strong sink capability,

providing flexibility to adjust the turnon and turnoff strength independently.

8.2 Typical Application

The circuit in 图 8-1 shows a synchronous buck converter to evaluate LMG1205. Detailed synchronous buck

converter specifications are listed in 节8.2.1. Optimization of he power loop (loop impedance from VIN capacitor

to PGND) is critical to the performance of the design. Having a high power loop inductance causes significant

ringing in the SW node and also causes an associated power loss. For more information, please refer to 节

11.2.1.

0.1 ꢀF

VIN

Rgh

HOH

VDD

HOL

V_OUT

1 ꢀF

LMG1205

C_OUT

Rgl

LOH

LOL

VSS

图8-1. Application Circuit

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English Data Sheet: SNOSD37

LMG1205

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ZHCSG61B –MARCH 2017 –REVISED APRIL 2023

8.2.1 Design Requirements

When designing a synchronous buck converter application that incorporates the LMG1205 gate driver and GaN

power FETs, some design considerations must be evaluated first to make the most appropriate selection. Among

these considerations are the input voltages, passive components, operating frequency, and controller selection.

表 8-1 shows some sample values for a typical application. See 节 9, 节 10, and 节 8.2.2.3 for other key design

considerations for the LMG1205.

表8-1. Design Parameters

PARAMETER

SAMPLE VALUE

Half-bridge input supply voltage,

V_IN

48 V

Output voltage, V_OUT

Output current

Dead time

12 V

8 A

8 ns

Inductor

4.7 µH

1 MHz

Switching frequency

8.2.2 Detailed Design Procedure

This procedure outlines the design considerations of LMG1205 in a synchronous buck converter with

enhancement mode GaN FET. For additional design help, see 节11.2.1.

8.2.2.1 VDD Bypass Capacitor

The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the

reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with 方程式

Q_gH+ Q_gL+ Q_rr

C_VDD

(1)

where

• Q_gHand Q_gLare gate charge of the high-side and low-side transistors, respectively

• Q_rris the reverse recovery charge of the bootstrap diode, which is typically around 4nC

• ΔV is the maximum allowable voltage drop across the bypass capacitor

TI recommends a 0.1–µF or larger value, good-quality ceramic capacitor. The bypass capacitor must be placed

as close as possible to the device pins to minimize the parasitic inductance.

8.2.2.2 Bootstrap Capacitor

The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB undervoltage

lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be

calculated with 方程式2.

+ I

× T + Q

ON rr

GSS

∆ V

(2)

BST

where

• I_HBis the quiescent current of the high-side driver

• T_onis the maximum on-time period of the high-side transistor

• I_GSSis the gate leakage current of the high-side transistor

A good-quality ceramic capacitor must be used for the bootstrap capacitor. TI recommends placing the bootstrap

capacitor as close as possible to the HB and HS pins.

English Data Sheet: SNOSD37

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8.2.2.3 Power Dissipation

The power consumption of the driver is an important measure that determines the maximum achievable

operating frequency of the driver. It must be kept below the maximum power dissipation limit of the package at

the operating temperature. The total power dissipation of the LMG1205 is the sum of the gate driver losses and

the bootstrap diode power loss.

The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as

P = C_LoadH+ C_LoadLì V_D²_Dì f_SW

(

)

(3)

where

• C_LoadHand C_LoadLare the high-side and the low-side capacitive loads, respectively

It can also be calculated with the total input gate charge of the high-side and the low-side transistors as

P = Q_gH+ Q_gLì V_DDì f_SW

(

)

(4)

There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and

HO outputs. 图 8-2 shows the measured gate driver power dissipation versus frequency and load capacitance.

At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses

driving the output loads and agrees well with the above equations. 图 8-2 can be used to approximate the power

losses due to the gate drivers.

Gate driver power dissipation (LO+HO), VDD = 5 V

图8-2. Neglecting Bootstrap Diode Losses

The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the

bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these

events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger

capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input

voltages (V_IN) to the half bridge also result in higher reverse recovery losses.

图 8-3 and 图 8-4 show the forward bias power loss and the reverse bias power loss of the bootstrap diode

respectively. The plots are generated based on calculations and lab measurements of the diode reverse time

and current under several operating conditions. 图 8-3 and 图 8-4 can be used to predict the bootstrap diode

power loss under different operating conditions.

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The load of high-side driver is a GaN FET with total gate

charge of 10 nC.

图8-4. Reverse Recovery Power Loss of Bootstrap

图8-3. Forward Bias Power Loss of Bootstrap

Diode V_IN= 50 V

The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient

temperature, the maximum allowable power loss of the IC can be defined as 方程式5.

(T_J- T_A)

P =

q_JA

(5)

English Data Sheet: SNOSD37

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8.2.3 Application Curves

Conditions: Input Voltage = 48 V DC, Load Current = 5

ATraces: Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2

V Bottom Trace: LI of LMG1205, Volt/div = 5 V Bandwidth Limit

= 600 MHz Horizontal Resolution = 0.2 µs/div

Conditions: Input Voltage = 48 V DC, Load Current = 10

ATraces: Trace: Switch-Node Voltage, Volts/div = 20 V

Bandwidth Limit = 600 MHz Horizontal Resolution = 50 ns/div

图8-6. Switch-Node Voltage

图8-5. Low-Side Driver Input and Output

9 Power Supply Recommendations

The recommended bias supply voltage range for LMG1205 is from 4.5 V to 5.5 V. The lower end of this range is

governed by the internal UVLO protection feature of the VDD supply circuit. TI recommends keeping proper

margin to allow for transient voltage spikes while not violating the LMG1205 absolute maximum VDD voltage

rating and the GaN transistor gate breakdown voltage limit.

The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in

normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage

drop does not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis

specification, the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on

the VDD power supply output must be smaller than the hysteresis specification of LMG1205 UVLO to avoid

triggering device shutdown.

A local bypass capacitor must be placed between the VDD and VSS pins. This capacitor must be located as

close as possible to the device. TI recommends a low-ESR, ceramic, surface-mount capacitor. TI also

recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high

frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10

μF, for IC bias requirements.

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10 Layout

10.1 Layout Guidelines

Small gate capacitance and Miller capacitance enable enhancement mode GaN FETs to operate with fast

switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited

headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum

performance. Following are some recommendations:

1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and

discharge the GaN FETs gate into a minimal physical area. This decreases the loop inductance and

minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs must be placed close to the

driver.

2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass

capacitor and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the

bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval

and involves high peak current. Minimizing this loop length and area on the circuit board is important to

ensure reliable operation.

3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose

excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to

the respective source of the high-side and low-side transistors with a short and low-inductance path.

4. The parasitic source inductance, along with the gate capacitor and the driver pull-down path, can form an

LCR resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to

damp the ringing.

5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the

HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping

bullet #1 (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to place the VDD

decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the PC board as the driver.

The inductance of vias can impose excessive ringing on the IC pins.

6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing low-

ESR ceramic capacitors adjacent to the GaN FETs.

图 10-1 and 图 10-2 show recommended layout patterns for the LMG1205. Two cases are considered: (1)

without any gate resistors, and (2) with an optional turnon gate resistor. Note that 0402 surface mount package

is assumed for the passive components in the drawings. For information on DSBGA package assembly, refer to

节11.2.1.

spacer

10.2 Layout Examples

Bootstrap

Capacitor

Bootstrap

Capacitor

To Hi-Side FET

HOH

HOL

HOH

VDD

HOL

VDD

LOH

LOL

LOH

LOL

VDD

VSS

VDD

VSS

Bypass

Capacitor

GND

To Low-Side FET

Bypass

Capacitor

GND

To Low-Side FET

图10-2. Layout Example with HOH and LOH Gate

图10-1. Layout Example Without Gate Resistors

Resistors

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• AN-1112 DSBGA Wafer Level Chip Scale Package

• Using the LMG1205HBEVM GaN Half-Bridge EVM

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this datasheet, refer to the left-hand navigation.

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Product Folder Links: LMG1205

English Data Sheet: SNOSD37

PACKAGE OPTION ADDENDUM

www.ti.com

15-Apr-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMG1205YFXR

LMG1205YFXT

ACTIVE

DSBGA

YFX

3000 RoHS & Green

250 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

1205

Samples

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

15-Apr-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMG1205YFXR

LMG1205YFXT

DSBGA

YFX

3000

250

178.0

8.4

1.85

2.01

0.76

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMG1205YFXR

LMG1205YFXT

DSBGA

YFX

3000

250

208.0

191.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

YFX0012

DSBGA - 0.675 mm max height

SCALE 8.000

DIE SIZE BALL GRID ARRAY

BALL A1

CORNER

0.675 MAX

SEATING PLANE

0.05 C

0.205

0.165

1.2 TYP

SYMM

1.2 TYP

0.4 TYP

D: Max = 1.905 mm, Min =1.845 mm

E: Max = 1.756 mm, Min =1.695 mm

0.28

12X

0.25

0.4 TYP

0.015

C A B

4215094/B 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFX0012

DSBGA - 0.675 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

12X ( 0.225)

(0.4) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 40X

0.05 MIN

0.05 MAX

METAL UNDER

SOLDER MASK

(

0.225)

METAL

(

0.225)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4215094/B 08/2022

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFX0012

DSBGA - 0.675 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

(R0.05) TYP

12X ( 0.25)

(0.4) TYP

SYMM

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 40X

4215094/B 08/2022

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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LMG1205 [TI]

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SI9130_11

SI9137

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SI9137LG

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