LMG1210RVRR [TI]
适用于 GaNFET 和 MOSFET、具有 5V UVLO 和可编程死区时间的 1.5A、3A 200V 半桥栅极驱动器 | RVR | 19 | -40 to 125;
| 型号： | LMG1210RVRR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 GaNFET 和 MOSFET、具有 5V UVLO 和可编程死区时间的 1.5A、3A 200V 半桥栅极驱动器 | RVR | 19 | -40 to 125 栅极驱动 驱动器 |
| 文件： | 总31页 (文件大小：1896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMG1210
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
具有可调节死区时间的 LMG1210 200V、1.5A、3A 半桥 MOSFET 和
GaN FET 驱动器 （适合 工作频率高达 50MHz 的应用）
1 特性
3 说明
1
•
工作频率高达 50MHz
10ns 典型传播延迟
3.4ns 高侧至低侧匹配
4ns 最小脉宽
LMG1210 是一款 200V 半桥 MOSFET 和氮化镓场效
应晶体管 (GaN FET) 驱动器，专为要求超高频率、高
效率的 应用 而开发， 具有 可调节死区时间功能、极
短的传播延迟以及 3.4ns 高侧/低侧匹配，以优化系统
效率。此部件还 具备 一个内部 LDO，可确保 5V 的栅
极驱动器电压（而与电源电压无关）。
•
•
•
•
两个控制输入选项
–
–
具有可调死区时间的单个 PWM 输入
独立输入模式
为了在各种应用中获得 最佳性能，LMG1210 允许设计
人员选择最佳的自举二极管对高侧自举电容器充电。当
低侧不导通时，内部开关会关闭自举二极管，以有效防
止高侧自举过度充电，并将反向恢复电荷降至最低。
GaN FET 上额外的寄生电容被最小化至小于 1pF，以
减少额外的开关损耗。
•
•
•
•
•
•
•
1.5A 峰值拉电流和 3A 峰值灌电流
外部自举二极管可实现灵活性
内部 LDO 可实现对电压轨的适应能力
高 300V/ns CMTI
HO 到 LO 的电容小于 1pF
UVLO 和过热保护
该 LMG1210 具有 两种控制输入模式：独立输入模式
(IIM) 和 PWM 模式。在 IIM 中，每个输出都由专用输
入独立控制。在 PWM 模式下，两个补偿输出信号由
单个输入产生，用户可将每个沿的死区时间从 0ns 调
节为 20ns。LMG1210 可在 –40°C 至 125°C 的宽温度
范围内运行，并采用低电感 WQFN 封装。
低电感 WQFN 封装
2 应用
•
•
•
•
•
高速直流/直流转换器
射频封装跟踪
D 类音频放大器
E 类无线充电
高精度电机控制
器件信息(1)
器件型号
LMG1210
封装
WQFN (19)
封装尺寸（标称值）
4.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化的典型应用
BST
200 V
HB
HO
HS
6 œ 18 V
VIN
EN
LDO
UVLO
OTP
5 V
VDD
LO
EN
PWM
Dead
Time
PWM
Delay
Match
VSS
DHL
DLH
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSD12
LMG1210
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
8.3 Do's and Don'ts ...................................................... 20
Power Supply Recommendations...................... 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
6.8 Timing Diagrams..................................................... 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 文档支持 ............................................................... 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 术语表 ................................................................... 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
Changes from Revision C (December 2018) to Revision D
Page
•
Changed Maximum High-side dynamic current from 0.61mA/MHz to 0.7mA/MHz .............................................................. 5
Changes from Revision B (November 2018) to Revision C
Page
•
•
•
•
•
•
•
已更改 将差错从 2.5ns 更改为 3.4ns...................................................................................................................................... 1
已更改 将最小脉宽从 3ns 更改为 4ns..................................................................................................................................... 1
Changed Reordered Pin Functions table in alphabetical order.............................................................................................. 3
已添加 Figure 14 IIM Timing Diagram ................................................................................................................................. 10
已添加 CMTI performance reference app note .................................................................................................................... 13
已添加 charge per cycle removed from the bootstrap due to dynamic high side current ................................................... 17
已添加 Power Consumption Calculation reference app note .............................................................................................. 19
Changes from Revision A (May 2018) to Revision B
Page
•
已更改 将销售状态从“产品预览”更改为“最终信息”。初始发行版。......................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
LMG1210
www.ti.com.cn
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
5 Pin Configuration and Functions
RVR Package
19-Pin WQFN
Top View
15
16
14
13
12
11
10
(HS)
HS
HO
HS
Thermal Pad
9
8
7
6
BST
EN/HI
17
18
LO
(VSS)
VSS
DLH
Thermal Pad
PWM/LI
19
1
2
3
4
5
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BST
DHL
17
O
I
Bootstrap diode anode connection point.
Sets the dead time for a high-to-low transition in PWM mode by connecting a resistor to VSS. If
using IIM this pin can be left floating, tied to GND, tied to VDD.
5
6
DLH
Sets the dead time for a low-to-high transition in PWM mode by connecting a resistor to VSS. Tie
to VDD to select IIM.
I
I
I
EN/HI
Enable input or high-side driver control. In PWM mode this is the EN pin. In IIM mode this is the
HI pin.
18
19
PWM/LI
PWM input or low-side driver control. In PWM mode this is the PWM pin. In IIM mode this is the
LI pin.
HB
HO
HS
LO
12
10
I
O
I
High-side driver supply. Bootstrap diode cathode connection point.
High-side driver output.
9,13,16
8
Switch node and high-side driver ground. These pins are internally connected.
Low-side driver output.
O
—
I
NC
NC1
1,11,15
14
Not internally connected.
For proper operation, this pin should be either unconnected or tied to HS.
Connected to HS.
Thermal Pad
(HS)
21
20
I
I
Thermal Pad
(VSS)
Connected to VSS.
VDD
VIN
4
2
O
I
Low-side driver supply and LDO output. 5 V
6 V to 18 V input to LDO. If LDO is not required, connect to VDD.
Low-side ground return: all low-side signals are referenced to this ground.
VSS
3,7
—
Copyright © 2018–2019, Texas Instruments Incorporated
3
LMG1210
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.5
MAX
20
UNIT
V
VIN
Input Supply Voltage
VDD
5V Supply Voltage
-0.5
5.5
V
VHS
High Side Voltage Without Bootstrap Diode
Bootstrap supply voltage, continuous
Input Pin Voltage on LI or HI
Voltage on DLH and DHL pins
Low-side gate driver output
High-side gate driver output
Bootstrap pin voltage
-300
-0.5
300
V
VHB-VHS
VLI/PWM, VHI/EN
VDHL, VDHL
VLO
5.5
V
-0.5
10
V
-0.5
VDD + 0.5
VDD + 0.5
VHB+ 0.5
VDD + 0.5
150
V
-0.5
V
VHO
VHS-0.5
-0.5
V
VBST
V
TJ
Operating Junction Temperature Range
Storage Temperature
-40
°C
°C
TSTG
-55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±YYY V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
NOM
MAX
18
UNIT
V
VIN
Input Supply Voltage (if using internal LDO)
5V Supply Voltage (if bypassing internal LDO)
VDD
4.75
-200
3.80
-0.3
-40
5.00
5.25
200
5.25
10
V
(1)
VHS-VSS
VHB-VHS
VLI,VHI
TJ
High-Side Voltage Without Bootstrap diode
V
Bootstrap Supply Voltage
V
Input Pin Voltage
V
Operating Junction Temperature Range
High Side Slew Rate
125
300
1800
1.8
°C
V/ns
kΩ
V
CMTI
RDHL, RDLH
VDT
Dead Time Adjustment External Resistance
Dead Time Voltage Range
20
0.8
(1) If using a bootstrap diode, actual negative HS pin voltage may be more limited, see Section 7.3.6 for details.
4
Copyright © 2018–2019, Texas Instruments Incorporated
LMG1210
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ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
6.4 Thermal Information
LMG1210
THERMAL METRIC(1)
RVR (QFN)
19 PINS
40.5
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
40
16.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.9
ψJB
16.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VDD=5V, HB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LI, HI=0V, Independent Mode
300
380
475
550
850
μA
μA
Quiescent Current for Low-Side
Circuits Only, Vin=6V, powered
through LDO
IDD
EN=0V, PWM=X, PWM Input Mode,
RDHL and RDLH = 1.78MΩ
IHB
HB Quiescent Current
HI=0V, Independent Mode
VHS=100V
520
1
μA
nA
nA
IHBS
HB to VSS Quiescent Current
HB to VSS Operating Current
Low-side dynamic current
High-side dynamic current
IHBSO
ILSDyn
IHSDyn
VHS=100V, FSW=1MHz
Unloaded, PWM Mode
Unloaded
1
1
1.25 mA/MHz
0.7 mA/MHz
0.5
LOW-SIDE TO HIGH-SIDE CAPACITANCE
Low Side Pins Shorted Together,
High Side Pins Shorted Together
CISO
Capacitance from High to Low Side
0.25
pF
5V LDO
V5V
LDO Output
VIN=10V
IO=100mA
VIN=12V
VIN=12V
4.75
5.00
400
5.25
750
V
VDO
Dropout Voltage
Maximum Current
Short Circuit Current
mV
mA
mA
ILDOM
ISC
100
105
250
0.3
Minimum Required Output
Capacitance(1)
Effective Capacitance at Bias
Voltage
COUT
µF
DIGITAL INPUT PINS (LI/PWM & HI/EN)
VIR
Input Rising Edge Threshold
Input Falling Edge Threshold
Input Hysteresis
1.70
0.70
2.45
1.30
V
V
VIF
VIHYS
RIPD
1
V
Input Pull-Down Resistance
VLI, VHI=1V
100
200
300
kΩ
UNDERVOLTAGE LOCKOUT
VDDR
VDDF
VDDH
VHBR
VHBF
VHBH
VDD Rising Threshold
VDD Falling Threshold
VDD Hysteresis
4.00
3.8
4.25
4.05
200
4.50
4.3
V
V
mV
V
HB-HS Rising Threshold
HB-HS Falling Threshold
HB-HS Hysteresis
3.40
3.30
3.55
3.45
130
3.8
3.65
V
mV
BOOTSTRAP DIODE SWITCH
RSW
Diode Switch On Resistance
ID=100mA
0.4
Ω
GATE DRIVER
VOL
Low-Level Output Voltage
IOL=100mA
0.16
V
(1) Ensured by design
Copyright © 2018–2019, Texas Instruments Incorporated
5
LMG1210
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
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Electrical Characteristics (continued)
VDD=5V, HB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH= -100mA
MIN
TYP
MAX
UNIT
VDD-VOH
IOL
High-Level Output Voltage
Peak Sink Current
0.30
4.3
V
A
A
VLO,VHO=5V
VLO,VHO=0V
2.0
3.1
IOH
Peak Source Current
0.85
1.58
2.4
VDD, VHB Floating, 1 mA pull-up
applied to LO/HO
VCLAMP
Unpowered Gate Clamp Voltage
0.55
0.8
V
THERMAL SHUTDOWN
Thermal Shutdown Switching, Rising
TSD
150
160
3
°C
°C
°C
°C
Edge(2)
Thermal Shut Down LDO, Rising
Edge(2)
TSD_LDO
THYS_SD
TSD_HS
Thermal Hysteresis, LDO &
Switching(2)
10
25
Thermal Shutdown for High-Side,
Rising Edge(2)
160
DEADTIME CONTROL RESISTORS
RPU Internal Pullup Resistor
(2) Ensured by design
23.5
27
kΩ
6
Copyright © 2018–2019, Texas Instruments Incorporated
LMG1210
www.ti.com.cn
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
6.6 Switching Characteristics
VDD=5V, VHB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INDEPENDENT INPUT MODE
tPHL
tPLH
Turn-Off Delay
Turn-On Delay
10
10
18
18
ns
ns
High-Off to Low-On and Low-Off to
High-On Delay Mismatch
tMTCH
Over temperature, TjHI=TjLO
1
3.4
ns
PWM INPUT MODE
PWM rising to LO falling and PWM
falling to HO falling
tPHL
Turn-Off Delay
Minimum Dead Time
11
21
ns
tDEAD_MIN
Rext=1.78 MΩ
Rext=20 kΩ
-0.55
16
0.8
20
11
3.1
26
20
ns
ns
ns
tDEAD_MAX Maximum Dead Time
tEN Enable Propagation Time
OTHER CHARACTERISTICS
tOR
Output Rise Time, Unloaded
10%-90%
0.5
0.5
3.5
2.3
ns
ns
ns
ns
tOF
Output Fall Time, Unloaded
Output Rise Time, Loaded
Output Fall Time, Loaded
90%-10%
tORL
tOFL
CO=1nF, 10%-90%
CO=1nF, 90%-10%
5.6
3.3
Minimum input pulse width which
changes the output
Unloaded(2)
(1)
(1)
tPW
Minimum Input Pulse Width
H-L-H Pulse extender width
1.8
4.0
ns
tPW,ext
4.5
25
10
60
ns
µs
µs
Independent Control Mode
PWM Control Mode
Start-Up Time of low side after VDD-
GND goes over UVLO threshold.
tSTLS
100
150
Start-Up Time of High-Side After
VHB-VHS Goes Above UVLO
tSTHS
tPWD
16
1
28
3
µs
ns
Pulse-Width Distortion
|tPLH-tPHL|, Independent Input Mode
(1) Ensured by design
(2) Pulses longer than tPW, but shorter than tPW,ext get extended to tPW,ext
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LMG1210
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
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6.7 Typical Characteristics
1.75
1.5
1.25
1
4
3.5
3
2.5
2
0.75
0.5
0.25
0
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LO, HO (V)
LO, HO (V)
D001
D002
图 1. Peak Source Current vs Output Voltage
图 2. Peak Sink Current vs Output Voltage
30
24
18
12
6
50
40
30
20
10
0
-40 èC
25 èC
125 èC
-40 èC
25 èC
125 èC
0
0.05 0.1 0.2 0.3 0.5
1
2
3 4 567 10
20 30 50
0.05 0.1 0.2 0.3 0.5
1
2
3 4 567 10
20 30 50
Frequency (MHz)
Frequency (MHz)
D003
D004
图 3. IDD vs Frequency, Unloaded
图 4. IHBO vs Frequency, Unloaded
315
310
305
300
295
290
285
280
275
270
265
700
650
600
550
500
450
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D005
D006
图 5. IDD vs Temperature
图 6. IHB vs Temperature
8
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LMG1210
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ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
Typical Characteristics (接下页)
13
1.1
1
DHL
DLH
12
11
10
9
0.9
0.8
0.7
0.6
0.5
0.4
Low Side TPLH
Low Side TPHL
High Side TPLH
High Side TPHL
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D007
D008
图 7. Propagation Delay vs Temperature
图 8. Minimum Dead Time vs Temperature
12
0.8
50 V/ns
100 V/ns
300 V/ns
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
11.6
11.2
10.8
10.4
10
9.6
-0.1
-0.2
9.2
-20
-15
-10
-5
0
5
10
15
20
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
Phase of CMTI Relative to Signal (ns)
Bootstrap Voltage (V)
D010
D009
图 10. Propagation Delay vs relative phase of CMTI Phase
图 9. Propagation Delay Change vs Bootstrap voltage
4.5
4.5
LO Sink
LO Source
HO Sink
HO Rise Time
LO Rise Time
LO Fall Time
4
3.5
3
4
HO Source
HO Fall Time
3.5
2.5
2
3
2.5
2
1.5
1
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D011
D012
图 11. LO and HO Output Current vs Temperature
图 12. 1 nF Loaded Rise and Fall Time vs Temperature
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LMG1210
ZHCSHO1D –NOVEMBER 2018–REVISED JANUARY 2019
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6.8 Timing Diagrams
TPLH
TPHL
TOR
TOF
50%
50%
PWM
TON
90%
10%
HO
LO
TDHL
TDLH
图 13. Timing diagram of LMG1210 in PWM mode under no load condition
HI
LI
tPHL
tPLH
t
PHL
HO
LO
tMTCH
tMTCH
tPHL
tPWD = |tPLH t tPHL|
图 14. Timing diagram of LMG1210 in IIM mode under no load condition
10
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7 Detailed Description
7.1 Overview
The LMG1210 is a high-speed half-bridge driver specifically designed to work with enhancement mode GaN
FETs. Designed to operate up to 50 MHz, the LMG1210 is optimized for maximum performance and highly
efficient operation. This includes reducing additional capacitance at the switch node (HS) to less than 1 pF and
increased dV/dt noise immunity up to 300 V/ns on the HS pin to minimize additional switching losses. By having
a 21 ns maximum propagation delay with 3.4 ns maximum mismatch, excessive dead times can be greatly
reduced.
Auxiliary input voltages applied above 5 V enables an internal LDO to precisely regulate the output voltage at 5-
V, preventing damage on the gate. An external bootstrap diode allows the designer to select an optimal diode.
An integrated switch in series with the bootstrap diode stops overcharging of the bootstrap capacitor and
decreases Qrr losses in the diode.
The LMG1210 comes in a low-inductance WQFN package designed for small gate drive loops with minimal
voltage overshoot.
7.2 Functional Block Diagram
BST
HB
VIN
LDO
HO
HS
EN
VDD
Dead Time
Delay
Match
PWM
LO
VSS
1.8 V
1.8 V
UVLO
OTP
DHL DLH
7.3 Feature Description
The LMG1210 provides numerous features optimized for driving external GaN FETs.
7.3.1 Bootstrap Diode Operation
An internal low impedance switch enables the bootstrap only when the low-side GaN FET is on. If used in a
converter where the low-side FET operates in third quadrant conduction during the dead times, this provides two
main benefits. First, it stops the bootstrap diode from overcharging the high-side bootstrap rail. Second, if using a
p-n junction diode with Qrr as the bootstrap diode, it decreases the Qrr losses of the diode. There is a 1 kΩ
resistor connected between the drain and source of this internal bootstrap switch to allow the bootstrap capacitor
to slowly charge at start-up before the low-side FET is turned on.
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Feature Description (接下页)
The part does not have an actual clamp on the high-side bootstrap supply. The bootstrap switch disables
conduction during the dead times, and the actual bootstrap capacitor voltage is set by the operating conditions of
the circuit during the low-side on-time. The bootstrap voltage can be approximately calculated in 公式 1 through
公式 3.
The bootstrap voltage is given by 公式 1:
VBST = VDD – VF – VHS
where
•
VF is the forward voltage drop of the bootstrap diode and series bootstrap switch.
(1)
VHS is calculated in 公式 2:
VHS = –IL × RDSON
where
•
•
IL is the inductor current defined as flowing out of the half-bridge
and RDSON is the FET on resistance.
(2)
(3)
Substituting (2) into (1) gives the expression for the bootstrap voltage as 公式 3:
VBST = VDD – VF + IL × RDSON
From (3) one can determine that in an application where the current flows out of the half-bridge (IL is positive) the
bootstrap voltage can be charged up to a voltage higher than VDD if IL × RDSON is greater than VF. Take care not
to overcharge the bootstrap too much in this application by choosing a diode with a larger VF or limiting the IL ×
RDSON product.
In an application where IL is negative, the IL × RDSON product subtracts from the available bootstrap cap voltage.
In this case using a smaller VF diode is recommended if IL × RDSON is large.
7.3.2 LDO Operation
An internal LDO allows the driver to run off higher voltages from 6 V to 18 V and regulates the supply to 5 V, so
the LMG1210 can run off of higher input voltages with wide tolerances. To maintain stability of the internal LDO,
care must be taken to make sure a capacitor of at least 0.3 µF from VDD to VSS with an ESR below 500 mΩ is
used. A high-quality ceramic capacitor with an X7R dielectric is recommended. There is no maximum limit on the
capacitance allowed on the output of the LDO.
If the input supply is already 5 V ±5%, then the LDO can be bypassed. This is achieved by connecting the 5 V
supply directly to the VDD pin. The VIN pin should be tied to the VDD pin, and the capacitor on the VIN pin can be
removed. Do not ground the VIN pin.
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Feature Description (接下页)
7.3.3 Dead Time Selection
In PWM mode the dead time can be set with a resistor placed between DHL/DLH and VSS. For a desired dead
time (tdt), the corresponding required resistance can be calculated in 公式 4 with tdt in ns and Rext in kΩ.
Rext = (900/tdt ) – 25
(4)
The maximum dead time is 20 ns, which gives a minimum resistor value of 20 kΩ. The minimum dead time is
0.5ns, which gives a maximum resistor value of 1.8 MΩ. There is an internal pull-up resistor at DHL/DLH pin,
which forms a voltage divider with the external resistor. This voltage decides the final dead time. The calculation
between dead time tDT in ns and VDT is shown in 公式 5.
tdt = (1.8-VDT ) x20
(5)
Before being used to generate the dead times, the voltages on the DHL and DLH pins are first filtered through an
internal RC filter with a nominal corner frequency of 10 kHz to attenuate switching noise.
The pulse widths of the HO and LO outputs are decreased from the PWM input by the chosen dead-times. The
timing diagram under no load condition is shown in 图 13 and 图 14. PWM mode and Independent mode
configurations can be found in 图 16 .
7.3.4 Overtemperature Protection
The LMG1210 has three separate overtemperature thresholds: two on the low-side and one on the high-side.
The lowest overtemperature threshold is the low-side switching threshold at 150 degrees minimum. When
exceeded, this disables switching on both the low and high sides. However, the 5 V LDO continues to operate.
If the low-side temperature continues to rise, due to a short or external load on the 5 V LDO, then at 10 degrees
higher, the low-side shuts down the 5 V LDO.
The high-side has an independent overtemperature threshold at 160 minimum. When triggered, it only shuts off
the high-side while the low-side may continue to operate.
If it is undesirable in an application to have only the high side shut off and not the low side, TI recommends
designing the thermal cooling of the board in a way to make the low-side die hotter. This can be achieved by
controlling the size of the thermal planes connected to each thermal pad.
7.3.5 High-Performance Level Shifter
The LMG1210 uses a high-performance level shifter to translate the signal from the low side to the high side.
The level shifter is built using TI's proprietary high-voltage capacitor technology, which showcases best-in-class
CMTI (common-mode transient immunity), or dV/dt on the HS pin. The level shifter can handle very high CMT
(common-mode transient) rates while simultaneously providing low propagation time which does not vary
depending on CMT rate. For more information on LMG1210 CMTI performance refer to section 2.4 from Design
Considerations for LMG1205 Advanced GaN FET Driver During High-Frequency Operation.
7.3.6 Negative HS Voltage Handling
The LMG1210 by itself can operate with -200V on the HS pin as stated in the recommended operating conditions
table. However, if using a bootstrap diode, the system will be more limited based on the potential of high-currents
flowing through the bootstrap diode.
HS goes most negative during the dead times when the low-side FET is off. This also means the bootstrap
switch is off so the BST pin is relatively high impedance. Therefore as HS goes negative, the bootstrap diode
becomes forward biased and pulls the voltage at BST down with it. Because the bootstrap switch is off, very little
current will flow until the bootstrap diode attempts to pull the BST pin below ground at which point the ESD diode
on the BST pin will clamp the voltage at a diode drop below ground. The point where significant current begins to
flow through the bootstrap diode is given in 公式 6
VHS = – VBST – VESD – (VHB – VHS
)
(6)
Where VBST is the forward voltage drop of the selected bootstrap diode and VESD is the forward voltage drop of
the ESD diode of the BST pin which is typically 0.7V at room temp. 图 15 shows a schematic of this current path.
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Feature Description (接下页)
VDD
Bootstrap
Switch (open)
Bootstrap
Diode
BST
HB
HS
CBST
ESD Diode
Current Path
图 15. Current Path Across Bootstrap Diode
Once this negative voltage is exceeded, large currents will begin to flow out of the BST pin and through the
bootstrap diode. The currents may be limited by the following: resistance of the BST ESD diode, resistance of
the bootstrap diode, inductance of the bootstrap loop, or additional resistance purposely added in series with the
bootstrap diode. If this current is too high, damage to the bootstrap diode or the LMG1210 can result. If this
current delivers significant enough total charge, this can over-charge the bootstrap rail as well.
The BST pin ESD diode has been specifically designed to be robust to carry up to a couple amps surge current
without damage.
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7.4 Device Functional Modes
The mode of operation is determined by the state of DHL and DLH pins during power up. The state of the pins is
sampled at power up and cannot be changed during operation. There are two different modes: independent
operation where separate HI and LI signals are required, and PWM mode where one PWM input signal is
required and the LMG1210 generates the complementary HI and LI signals. For PWM input, the dead time for
the low-to-high and high-to-low switch-node transition is independently set by an external resistor at DHL and
DLH. For independent input mode, DLH is tied to VDD and DHL is internally set to high-impedance and can be
tied to VDD, tied to ground or left floating.
Operating
Mode
DLH
DHL
PWM
Leave
Floating or
Tie to VSS
Independent
Input Mode
VDD
图 16. Operation Mode Selection
表 1 lists the functional modes for the LMG1210.
表 1. LMG1210 Truth Table
INPUTS
PWM MODE
INDEPENDENT MODE
EN/HI
PWM/LI
HO
0
LO
0
HO
LO
0
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMG1210 is designed to optimally drive GaN FETs in half-bridge configurations, such as synchronous buck
and boost converters, as well as more complex topologies. By integrating the level shifting and bootstrap
operation the complexities of driving the high-side device are solved for the designer.
The list below shows some sample values for a typical 48 V to 12 V application synchronous buck.
•
•
•
•
•
•
•
Input Voltage: 48 V
Output Voltage: 12 V
Output Current: 10 A
Bias Voltage: 6 V
Duty Cycle: 25 %
Switching Frequency: 1 MHz
Inductor: 4.7 µH
8.2 Typical Application
0 œ 200 V
BST
HB
HO
HS
6 œ 18 V
VIN
LDO
5 V
VDD
LO
EN
Dead
PWM
Time
VSS
LMG1210
DHL
DLH
Controller
图 17. Simplified LMG1210 Configured as Synchronous Buck Converter
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Typical Application (接下页)
8.2.1 Design Requirements
When designing a multi-MHz application that incorporates the LMG1210 gate driver and GaN power FETs, some
design considerations must be evaluated first to make the most appropriate selection. Among these
considerations are layout optimization, circuit voltages, passive components, operating frequency, and controller
selection.
8.2.2 Detailed Design Procedure
8.2.2.1 Bypass Capacitor
To properly drive the GaN FETs, TI recommends placing high-quality ceramic bypass capacitors as close as
possible between the HB to HS and VDD to VSS. If using the LDO, the VDD-VSS capacitor is required to be at least
0.3 µF at bias for stability. However, a larger capacitor may be required for many applications.
The bootstrap capacitor must be large enough to support charging the high-side FET and supplying the high-side
quiescent current when the high-side FET is on. The required capacitance can be calculated as 公式 7:
(0.5 nC + Qrr + QgH + IHB × ton)/ΔV = CBST,min
where
•
•
•
•
•
•
QgH is the gate charge of the high-side GaN FET,
IHB is the quiescent current of the high-side driver,
tON is the maximum on time period of the high side,
Qrr is the reverse recovery of the bootstrap diode,
0.5 nC is the additional charge per cycle removed from the bootstrap due to high side dynamic current,
and ΔV is the acceptable droop on the bootstrap capacitor voltage.
(7)
When using larger bootstrap capacitors, TI recommends that the VDD-VSS capacitor also be increased to keep
the ratio at least 5 to 1. If this is not maintained, the charging of the bootstrap capacitor can pull the VDD-VSS rail
down sufficiently to cause UVLO conditions and potentially unwanted behavior.
8.2.2.2 Bootstrap Diode Selection
The bootstrap diode blocks the high voltage from the gate drive circuitry when the switch node swings high, with
the rated blocking voltage equal to the maximum Vds of the GaN FET. For low or moderate frequency operation
ultra-fast recovery diodes (<50 ns) are recommended. The internal low voltage switch in the LMG1210 acts to
reduce the reverse recovery. For high-frequency operation a Schottky diode is recommended. To minimize
switching losses and improve performance, it is important to select a diode with low capacitance.
For extreme cases, where the low-side FET on time is less than 20 ns, TI recommends using a small GaN FET
as synchronous bootstrap instead of a diode. In this case, TI recommends leaving the BST pin floating or
connected to VDD, and to connect the source of the synchronous bootstrap directly to VDD
.
8.2.2.3 Handling Ground Bounce
For the best switching performance, it is important to connect the VSS gate return to the source of the low-side
FET with a very low-inductance path.
However, doing so can cause the ground of the LMG1210 to bounce relative to the system or controller ground
and cause erroneous switching transitions on the inputs. Multiple strategies can be employed to eliminate these
undesired transitions.
The LMG1210 has input hysteresis built into the input buffers to help counteract this effect, but this alone may
not be sufficient in all applications. The simplest option is to tie the system ground together and the power
ground only at the LMG1210 (single-point connection). This gives the cleanest solution but may not always be
possible depending on system grounding requirements.
For moderate ground-bounce cases, a simple R-C filter can be built with a simple resistor in series with the
inputs. The resistor should be close to the inputs of the LMG1210. The input capacitance of the LMG1210
produces an RC filter which can help decrease ringing at the inputs. The addition of a small C on the inputs to
supplement the LMG1210 input capacitance can also be helpful. This solution is acceptable for moderate cases
in applications where the extra delay is acceptable.
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Typical Application (接下页)
For more extreme cases or where no delay is tolerable, using a common-mode choke provides the best results.
One example application where the ground bounce is particularly challenging is when using a current sense
resistor. In this application, the LMG1210 ground is connected to the GaN source, while the controller ground is
connected to the other side of the current sense resistor as shown in 图 18.
BST
0 œ 200 V
HB
HO
HS
6 œ 18 V
VIN
LDO
RC filter
5 V
VDD
LO
EN/HI
Dead
Time
PWM/LI
VSS
Vsense
Rsense
LMG1210
DHL
DLH
CM choke
Controller
图 18. LMG1210 Configured With Current Sense Resistor Using a CMC as Filter
The combination of high dI/dt experienced through the sense resistor inductance will cause severe ground noise
that could cause false triggering or even damage the part. To prevent this, a common-mode choke (CMC) can be
used. Each signal requires its own CMC. Also, to provide additional RC filtering, a 100 Ω resistor should be
added to the signal output line before the LMG1210.
8.2.2.4 Independent Input Mode
In independent input mode, the signals LI and HI will propagate to the outputs LO and HO maintaining the same
phase shift, varied only by the timing mismatch.
In this mode, the dead time-generating circuit will be inoperative, and the correct dead time value would have to
be generated by the controller.
LI and HI cannot be high at the same time. The controller is responsible for assuring that the LI and HI on-times
do not overlap and cause shoot-through.
8.2.2.5 Computing Power Dissipation
The power dissipation of the LMG1210 can be divided up into three parts. One is the quiescent current which is
defined in the Electrical Characteristics table. This is the current consumed when no switching is taking place.
The second is the dynamic power consumed in the internal circuits of the driver at each switching transition
regardless of the load on the output. This can be measured by switching the driver with no output load.
The third component is the power used to switch the load capacitance presented by the external FET.
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Typical Application (接下页)
If operating in PWM mode, there is an additional quiescent current consumed in the dead time resistors. The
additional current consumed in each dead time pin can be calculated as 公式 8.
Iqdxx = 1.8/(25k + Rext
)
(8)
The first component, the quiescent power, is given in the Electrical Characteristics table. The second component,
the dynamic power dissipation can be calculated as 公式 9.
IINT = IDYN × Fsw
where
•
•
IDYN is the dynamic current consumption found in the Electrical Characteristics table
and Fsw is the switching frequency in MHz.
(9)
The third component of the power dissipation is the gate driver power. The current associated to this loss can be
calculated given the Qg of the FET as 公式 10:
I FET,g= Qg × Fsw
(10)
or alternatively in terms of Ciss as 公式 11:
IFET,g = Ciss × Vsup × Fsw
(11)
These current consumption numbers should be calculated for both the high side and low side separately and
added together. When a total current consumption is computed, multiplying it by the input supply voltage gives a
worst-case approximation for the total power dissipation of the LMG1210. If using a non-zero external gate
resistor of value Rg,ext, some of this power will be dissipated in this external resistor, and can be subtracted from
the power consumed inside the IC. For further details when calculating total driver power loss see section 2 from
Design Considerations for LMG1205 Advanced GaN FET Driver During High-Frequency Operation.
The WQFN package has two thermal pads: one for the low-side die and another for the high-side die. Though
there is good thermal coupling between the die and the associated thermal pad, there is very limited thermal
coupling between a die and the opposite thermal pad. This means that if power dissipation calculations indicate a
die needs improved cooling, the cooling must be focused on cooling the correct thermal pad.
8.2.3 Application Curves
图 19. 1-MHz, 80-V Operation
图 20. 10-MHz Operation, No Bus Voltage
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8.3 Do's and Don'ts
When using the LMG1210, DO:
1. Read and fully understand the data sheet, including the application notes and layout recommendations.
2. Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance.
3. Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance.
4. Use the proper size decoupling capacitors and place them close to the IC as described in the Layout
Guidelines section.
5. Use common-mode chokes for the input signals to reduce ground bounce noise. If not, ensure the signal
source is connected to the signal VSS plane which is tied to the power source only at the LMG1210 IC.
To avoid issues in your system when using the LMG1210, DON'T:
1. Use a single-layer or two-layer PCB for the LMG1210 as the power-loop and bypass capacitor inductances
will be excessive and prevent proper operation of the IC.
2. Reduce the bypass capacitor values below the recommended values.
3. Allow the device to experience pin transients above 200 V as they may damage the device.
4. Drive the IC from a controller with a separate ground connection than the VSS pin of the IC, unless
connecting though a CMC.
9 Power Supply Recommendations
The power to the LMG1210 can be supplied either through the LDO or the LDO can be bypassed and 5 V can
be supplied directly. The maximum input voltage to the LDO of the LMG1210 is specified in the electrical
characteristics table. The minimum input voltage of the LDO is set by the minimum drop-out of the LDO at the
operational current. The dropout at max current is specified in the electrical characteristics table, but a lower
dropout can be used in a lower-current application. A local bypass capacitor must be placed between the VIN and
VSS pins, and the VDD and VSS pins. This capacitor must be placed as close as possible to the device. TI
recommends a low-ESR, ceramic, surface-mount capacitor. TI also recommends using 2 capacitors across VDD
and VSS pin: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and
VSS pin, and another surface-mount capacitor, 220 nF to 10 μF, for IC bias requirement. The VIN and VSS
capacitor can be removed if the LDO is bypassed.
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10 Layout
10.1 Layout Guidelines
The layout of the LMG1210 is critical for performance and functionality. The low inductance WQFN package
helps mitigate many of the problems associated with board level parasitics, but take care with layout and
placement with components to ensure proper operation. The following design rules are recommended.
•
•
•
•
•
Place LMG1210 as close to the GaN FETs as possible to minimize the length of high-current traces between
the HO/LO and the Gate of the GaN FETs
Place bootstrap diode as close as possible to the LMG1210 to minimize the inductance of the BST to HB
loop.
Place the bypass capacitors across VIN to VSS, VDD to VSS, and HB to HS as close to the LMG1210 pins as
possible. The VDD to VSS cap is a higher priority than the VIN to VSS cap.
Separate power traces and signal traces, such as output and input signals, and minimize any overlaps
between layers
Minimize capacitance from the high-side pins to the input pins to minimize noise injection.
10.2 Layout Example
图 21. LMG1210 Layout Example
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
《LMG1210 半桥 GaN 驱动器的死区时间优化》(SNVA815)
LMG1205 高级 GaN FET 驱动器在高频运行期间的设计注意事项 (SNVA723)
《LMG1210 TINA-TI 参考设计》(SNOM617)
《LMG1210 TINA-TI 瞬态 Spice 模型》(SNOM616)
《LMG1210 PSpice 瞬态模型》(SNOM615)
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
LMG1210 作为 MSL3 发布。超过其车间寿命的产品可以通过烘烤进行再加工，以排除残留的湿气。IPC/JEDEC J-
STD-033C 提供有关烘烤规程的指导，以及为了确保塑料外壳（托盘、卷带封装或管）能够承受所考虑温度，您应
留意哪些方面。
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25
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMG1210RVRR
LMG1210RVRT
ACTIVE
ACTIVE
WQFN
WQFN
RVR
RVR
19
19
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LMG1210
LMG1210
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMG1210RVRR
LMG1210RVRT
WQFN
WQFN
RVR
RVR
19
19
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
4.3
4.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMG1210RVRR
LMG1210RVRT
WQFN
WQFN
RVR
RVR
19
19
3000
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
相关型号：
LMG1210RVRT
适用于 GaNFET 和 MOSFET、具有 5V UVLO 和可编程死区时间的 1.5A、3A 200V 半桥栅极驱动器 | RVR | 19 | -40 to 125
TI
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