LMG3410R070RWHT [TI]
具有集成驱动器和保护功能的 600V 70mΩ GaN | RWH | 32 | -40 to 150;
| 型号： | LMG3410R070RWHT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成驱动器和保护功能的 600V 70mΩ GaN | RWH | 32 | -40 to 150 驱动 驱动器 |
| 文件： | 总33页 (文件大小：1737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
具有集成驱动器和保护功能的 LMG341xR070 600V 70mΩ GaN
1 特性
2 应用
1
•
TI GaN 工艺通过了实际应用硬开关任务剖面可靠
性加速测试
•
•
•
•
•
•
高密度工业电源和消费类电源
多电平转换器
光伏逆变器
•
支持高密度电源转换设计
–
与共源共栅或独立 GaN FET 相比具有卓越的系
统性能
工业电机驱动器
不间断电源
–
低电感 8mm x 8mm QFN 封装简化了设计和布
局
高电压电池充电器
–
–
–
可调节驱动强度确保开关性能和 EMI 控制
数字故障状态输出信号
3 说明
LMG341xR070 GaN 功率级具有集成型驱动器和保护
功能，可让设计人员在电力电子系统中实现更高水平的
功率密度和效率。LMG341x 的固有优势超越硅
MOSFET，包括超低输入和输出电容值、可将开关损
耗降低 80% 的零反向恢复以及可降低 EMI 的低开关节
点振铃。这些优势支持诸如图腾柱 PFC 之类的密集高
效拓扑。
仅需 +12V 非稳压电源
•
•
集成栅极驱动器
–
–
–
–
零共源电感
20ns 传播延迟确保 MHz 级工作频率
工艺经过调整的栅极偏置电压确保可靠性
25 到 100V/ns 的用户可调节压摆率
强大的保护
LMG341xR070 通过集成一系列独一无二的特性提供
传统共源共栅 GaN 和独立 GaN FET 的 替代产品 ，
以简化设计，最大限度地提高可靠性并优化任何电源的
性能。集成式栅极驱动器支持 100V/ns 开关（Vds 振
铃几乎为零），低于 100ns 的限流可自行防止意外击
穿事件，过热关断可防止热逃逸，而且系统接口信号可
提供自监控功能。
–
–
–
–
–
–
无需外部保护组件
过流保护，响应时间低于 100ns
压摆率抗扰性高于 150V/ns
瞬态过压抗扰度
过热保护
针对所有电源轨的 UVLO 保护
•
器件选项：
器件信息(1)
–
–
LMG3410R070：锁存过流保护
器件型号
封装
封装尺寸（标称值）
LMG3411R070：逐周期过流保护
LMG341xR070
QFN (32)
8.00mm x 8.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化方框图
高于 100V/ns 时的开关性能
D
Direct-Drive
Slew Rate
600 V
GaN
S
RDRV
IN
VDD
VNEG
Current
LDO, OCP, OTP,
BB UVLO
5 V
FAULT
S
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSD10
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
7.1 Switching Parameters ............................................... 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 16
9.3 Paralleling GaN Devices ......................................... 19
9.4 Do's and Don'ts ...................................................... 19
10 Power Supply Recommendations ..................... 20
10.1 Using an Isolated Power Supply........................... 20
10.2 Using a Bootstrap Diode ...................................... 20
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 25
12.1 器件支持................................................................ 25
12.2 文档支持 ............................................................... 25
12.3 接收文档更新通知 ................................................. 25
12.4 社区资源................................................................ 25
12.5 商标....................................................................... 25
12.6 静电放电警告......................................................... 25
12.7 术语表 ................................................................... 25
13 机械、封装和可订购信息....................................... 25
7
8
4 修订历史记录
Changes from Revision D (August 2018) to Revision E
Page
•
•
已添加 向 LMG3410R070 数据表添加了 LMG3411R070....................................................................................................... 1
已添加 additional information in the overcurrent protection section. .................................................................................... 13
Changes from Revision C (November 2017) to Revision D
Page
•
•
将数据表状态从“预告信息”更改成了“生产数据”....................................................................................................................... 1
将通用器件型号从 LMG3S10 更改成了 LMG3410R070......................................................................................................... 1
Changes from Revision B (March 2017) to Revision C
Page
•
已更改 更改了首页.................................................................................................................................................................. 1
Changes from Revision A (June 2016) to Revision B
Page
•
已更改 将 Gan 技术预览更改成了预告信息 ............................................................................................................................ 1
Changes from Original (April 2016) to Revision A
Page
•
•
•
•
阐明了首页中的器件 特性 列表............................................................................................................................................... 1
Clarified definition of turn-on and turn-off energy ................................................................................................................ 11
Corrected wording in Do's and Don'ts section ..................................................................................................................... 19
Removed non-suitable isolated supply recommendation..................................................................................................... 20
2
Copyright © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
5 Pin Configuration and Functions
RWH (QFN) PACKAGE
32 PINS
(Top View)
DRAIN
12
32
31
FAULT
IN
13
14
15
PAD
30 RDRV
29
28
LPM
BBSW
16
SOURCE
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
BBSW
DRAIN
FAULT
IN
NO.
28
P
P
O
I
Internal buck-boost converter switch pin. Connect an inductor from this point to source
Power transistor drain
1-11
32
Fault output, push-pull, active low
31
CMOS-compatible non-inverting gate drive input
5-V LDO output for external digital isolator.
LDO5V
LPM
25
29
P
I
Enables low-power-mode by connecting the pin to source
Power transistor source, die-attach pad, thermal sink, signal ground reference
SOURCE
12-16, 18-24
P
Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive
strength to control slew rate,
RDRV
30
I
VDD
VNEG
NC
27
26
17
—
P
P
12-V power input, relative to source. Supplies 5-V rail and gate drive supply.
Negative supply output, bypass to source with 2.2-µF capacitor
Not connected, connect to source or leave floating.
—
P
PAD
Thermal Pad, tie to source with multiple vias.
(1) I = Input, O = Output, P = Power
Copyright © 2016–2018, Texas Instruments Incorporated
3
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
V DS
VDS,tr
V DD
Drain-Source Voltage
600
800
20
V
V
V
A
(2)
Transient Drain-Source Voltage
Supply Voltage
–0.3
(3)
I DS,pul
Drain-Source Current, Pulsed
Continous drain current @Tj=25℃
Continous drain current @Tj=100℃
IN, LPM Pin Voltage
100
40
(4)
IDS
30
A
V
V IN
-0.3
–0.3
–55
–40
5.5
5.5
150
150
V FAULT
T STG
T J
FAULT Pin Voltage
V
Storage Temperature
°C
°C
Operating Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) <1% duty cycle, <1us, for 1M pulses
(3) Pulse current <100ns
(4) The current is the drain current of GaN transistor only. Power stage current is clamped by integrated OCP. Please refer to the OCP
thresholds in Electrical Characteristics section.
6.2 ESD Ratings
VALUE
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins
±250
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
480
18
UNIT
V
VDS
VDD
IDS
Drain-Source Voltage
Supply Voltage
9.5
12
V
DC Drain-Source Current (Tj=125℃)
IN, LPM Pin Voltage
12
A
VIN
5
V
I+5V
LDO External Load Current
Slew rate control resistor
5
mA
kΩ
µH
µF
°C
RDRV
LDCDC
CDCDC
TJ
15
150
DC-DC buck-boost converter output inductor
DC-DC buck/boost converter output capacitor
Operating Temperature
22
2.2
-40
125
4
Copyright © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
6.4 Thermal Information
LMG3410R070
(1)
THERMAL METRIC
RWH (QFN)
UNIT
32 PINS
57
R θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
R θJC(top)
R θJC(bot)
5.3
0.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range, 9.5 V < VDD < 18 V, LPM = 5 V, VNEG = -14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GaN POWER
TRANSISTOR
TJ = 25°C
70
110
5
RDS,ON
On-state Resistance
mΩ
V
TJ = 125°C
IN = 0 V, ISD = 0.1 A
Third-quadrant mode source-drain
voltage
VSD
IN = 0 V, ISD = 10 A
7.8
1
VDS = 600 V, TJ = 25°C
VDS = 600 V, TJ = 125°C
IN = 0 V, VDS = 400 V, fSW = 250 kHz
5
IDSS
Drain Leakage Current
GaN output capacitance
µA
10
71
Coss
pF
pF
Effective output capacitance, energy
related
Coss,er
IN = 0 V, VDS =0-400 V
95
Effective output capacitance, time
related
Coss,tr
Qrr
ID = 5 A, IN = 0 V, VDS = 0-400 V
145
0
pF
nC
Reverse recovery charge
VR = 400 V, ISD = 5 A, dISD/dt = 1 A/ns
DRIVER SUPPLY
Quiescent current, ultra-low-power
IVDD,LPM
VLPM = 0 V, VDD = 12 V
80
95
µA
mA
mA
mode
Transistor held off
transistor held on
0.5
0.5
IVDD,Q
Quiescent current (average)
VDD = 12 V, fSW = 1 MHz, RDRV=40
kΩ, 50% duty cycle
IVDD,op
Operating current
43
V+5V
5V LDO output voltage
Negative Supply
VDD = 12 V
4.7
5.3
V
V
VNEG
30-mA load current
-13.9
BUCK BOOST
CONVERTER
fSW,GAN
FET switching frequency
Peak inductor current
1
250
50
MHz
mA
IOUT = 20 mA, VIN = 12 V, VOUT = -14
V
IDCDC,PK
350
2.5
ΔVNEG
DC-DC output ripple voltage, pk-pk
CNEG = 2.2 µF, IOUT = 20 mA
mV
DRIVER INPUT
Input pin, LPM pin, logic high
threshold
VIH
V
VIL
Input pin, LPM pin, low threshold
Input pin, LPM pin, hysteresis
Input pull-down resistance
0.8
V
V
VHYST
RIN,L
RLPM
0.8
150
150
kΩ
kΩ
LPM pin pull-down resistance
Copyright © 2016–2018, Texas Instruments Incorporated
5
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range, 9.5 V < VDD < 18 V, LPM = 5 V, VNEG = -14 V (unless otherwise noted)
PARAMETER
UNDERVOLTAGE LOCKOUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD,(ON)
VDD,(OFF)
ΔVDD,UVLO
FAULT
Itrip
VDD turnon threshold
VDD turnoff threshold
UVLO Hysteresis
Turn-on voltage
9.1
8.5
V
V
Turn-off voltage
trip point
550
mV
Current Fault Trip Point
Temperature Trip Point
Temperature Trip Hysteresis
22
36
165
20
50
A
Ttrip
°C
°C
TtripHys
6.6 Switching Characteristics
over operating free-air temperature range, 9.5 V < VDD < 18 V, VNEG = -14 V, VBUS = 400 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GaN FET
RDRV = 15 kΩ
100
50
dv/dt
Turn-on Drain Slew Rate
RDRV = 40 kΩ
V/ns
RDRV = 100 kΩ
25
Δdv/dt
dv/dt
Slew Rate Variation
Edge Rate Immunity
turn on, IL = 5 A, RDRV = 40 kΩ
25
%
Drain dv/dt, device remains off
inductor-fed, max di/dt = 10 A/ns
150
1
V/ns
STARTUP
tSTART
Time until gate responds to IN CNEG
= 2.2 µF, CLDO = 1 µF
Startup Time, VIN rising above UVLO
ms
DRIVER
tpd,on
IN rising to IDS > 1 A, VDS = 400 V
RDRV = 40 kΩ, VNEG = -14 V
Propagation delay, turn on
Turn on delay time
20
12
ns
ns
IDS > 1 A to VDS < 320 V, RDRV = 40
kΩ
tdelay,on
tVDS,ft
tpd,off
VDS fall time
VDS = 320 V to VDS = 80 V, ID = 5 A
IN falling to VDS > 10 V; ID = 5 A
VDS = 10 V to VDS = 80 V, ID = 5 A
VDS = 80 V to VDS = 320 V, ID = 5 A
4.2
36
10
15
ns
ns
ns
ns
Propagation delay, turn off
Turn off delay time
VDS rise time
tdelay,off
tVDS,rt
FAULT
tcurr
Current Fault Delay
Current Fault Blanking Time
Fault reset time
IDS > ITH to FAULT low
50
55
ns
ns
µs
VIN>VIH to end of blanking,
RDRV=15kΩ
tblank
treset
IN held low
250
350
500
6
版权 © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
6.7 Typical Characteristics
100
90
80
70
60
50
40
30
20
10
50
Propagation delay (turn on)
Turn on delay
45
Rise time
40
35
ID = 5 A
30
25
20
15
10
5
0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
RDRV (kW)
Drive Strength Resistor (kW)
D010
D001
图 1. Turn-on Delays vs Drive-Strength Resistor
图 2. Drain Slew Rate vs Drive-Strength Resistor
8
7.8
7.6
7.4
7.2
7
180
160
140
120
100
80
25 èC
125 èC
OCP limit
60
40
6.8
6.6
20
IN = 0 V
0
0
3
6
9
12
15
18
21
24
27
30
0
1
2
3
4
5
6
7
8
9
10
VDS (V)
Source-Drain Current (A)
IV
D004
图 4. Source-Drain Voltage in 3rd Quadrant Operation
图 3. IDS - VDS curve
2
1.8
1.6
1.4
1.2
1
50
30
20
10
7
5
3
2
VDS = 400 V
VDS = 50 V
VDS = 0 V
1
0.7
0.5
0.8
0.6
-40 -20
0
20
40
60
80 100 120 140 160
10
20 30 40 50 70 100
200 300 500 7001000
Temperature (èC)
Switching Frequency (kHz)
D011
D001
图 5. Normalized On Resistance vs Temperature
图 6. VDD Supply Current vs Switching Frequency
版权 © 2016–2018, Texas Instruments Incorporated
7
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
1000
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Turn-on Energy
Turn-off Energy
700
500
400
RDRV = 40 kW
300
200
100
70
50
0
50 100 150 200 250 300 350 400 450 500 550 600
0
1
2
3
4
5
6
7
8
9
10
Drain-Source Voltage (V)
Drain Current (A)
D001
D008
图 7. Output Capacitance
图 8. Hard-switched Half-Bridge Turn-on and Turn-off
Switching Energy vs Drain Current
115
110
105
100
95
90
85
80
75
180
160
140
120
100
80
70
65
60
55
50
60
45
40
ID = 5 A
140 160
40
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
RDRV (kW)
RDRV Value (k
W
)
D009
RDRV
图 9. Hard-switched Half-Bridge Turn-On Switching Energy
图 10. RDRV vs Blanking Time
vs Slew Rate Resistor
8
版权 © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
7 Parameter Measurement Information
7.1 Switching Parameters
The circuit used to measure most switching parameters is shown in 图 11. The top LMG341xR070 in this circuit
is used to re-circulate the inductor current and functions in third-quadrant mode only. The bottom device is the
active device; it is turned on to increase the inductor current to the desired test current. The bottom device is
then turned off and on to create switching waveforms at a specific inductor current. Both the drain current (at the
source) and the drain-source voltage is measured. The specific timing measurement is shown in 图 12. It is
recommended to use the half-bridge as double pulse tester. Excessive 3rd quadrant operation may over heat the
top LMG341xR070.
D
Slew
Rate
Direct-Drive
S
600 V
GaN
RDRV
IN
500 uH
VDD
VNEG
LDO, OCP, OTP, Current
5 V
BB
UVLO
FAULT
S
VBUS
480 V
DC
CPCB
D
Slew
Rate
Direct-Drive
S
600 V
GaN
RDRV
IN
+
VDD
VDS
_
VNEG
LDO, OCP, OTP, Current
BB UVLO
5 V
FAULT
PWM input
S
图 11. Circuit Used to Determine Switching Parameters
版权 © 2016–2018, Texas Instruments Incorporated
9
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
Switching Parameters (接下页)
IN
50%
50%
tpd,off
tpd,on
ID
1A
tdelay,on
tdelay,off
tVDS,ft
tVDS,rt
80%
80%
VDS
20%
20%
图 12. Measurement to Determine Propagation Delays and Slew Rates
7.1.1 Turn-on Delays
The timing of the turn-on transition has three components: propagation delay, turn-on delay and rise time. The
first component is the propagation delay of the driver from when the input goes high to when the GaN FET starts
turning on (represented by 1 A drain current). The turn-on delay is the delay from when the FET starts turning on
to when the drain voltage swings down by 20 percent. Finally, the VDS fall time is the time it takes the drain
voltage to slew between 80 percent and 20 percent of the bus voltage. The drive-strength resistor value has a
large effect on turn-on delay and VDS fall time but does not affect the propagation delay significantly.
7.1.2 Turn-off Delays
The timing of the turn-off transition has three components: propagation delay, turn-off delay and fall time. The
first component is the propagation delay of the driver from when the input goes low to when the GaN FET starts
turning off. The turn-off delay is the delay from when the FET starts turning of (represented by the drain rising
above 10 V) to when the drain voltage swings up by 20 percent. Finally, the VDS rise time is the time it takes the
drain voltage to slew between 20 percent and 80 percent of the bus voltage. The turn-off delays of the
LMG341xR070 are independent of the drive-strength resistor but the turn-off delay and the VDS rise time are
heavily dependent on the load current.
7.1.3 Drain Slew Rate
The slew rate, measured in volts per nanosecond, is measured on the turn-on edge of the LMG341xR070. The
slew rate is considered over the VDS fall time, where the drain falls from 80 percent to 20 percent of the bus
voltage. The drain slew rate is thus given by 60 percent of the bus voltage divided by the VDS fall time. This drain
slew rate is dependent on the RDRV value and is only slightly affected by drain current. Please refer to 图 2 for
the RDRV that is matched with the needed slew rate.
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Switching Parameters (接下页)
7.1.4 Turn-on and Turn-off Energy
The turn-on and turn-off energy, shown in 图 8, represent the energy absorbed by the low-side device during the
turn-on and turn-off transients of the circuit in 图 11, respectively. As this circuit represents a synchronous buck
converter, with input shorted to output, the switching energy is dissipated in the low-side device. The turn-on
transition is lossy, while the turn-off transition is essentially lossless; the output capacitance of the devices is
charged by the inductor current. The turn-on and turn-off losses have been calculated from experimental
waveforms by integrating the product of the drain current with the drain-source voltage over the turn-on and turn-
off times, respectively. The skew of probes for voltage and current are very important for accurate measurement
of turn-on and turn-off energy.
The switching loss of the converter can be determined by adding the turn-on and turn-off energy in 图 8,
adjusting for the RDRV value (shown in 图 9). To obtain the switching loss, multiply this value by the switching
frequency. The obtained loss is a sum of the V-I overlap loss (due to hard switching) and the loss caused by
charging and discharging the COSS of both devices. Additional test-fixture capacitance, including PCB and
inductor intra-winding capacitance, has not been removed from these measurements.
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8 Detailed Description
8.1 Overview
LMG341xR070 is a high-performance 600-V GaN transistor with integrated gate driver. The GaN transistor
provides ultra-low input and output capacitance and zero reverse recovery. The lack of reverse recovery enables
efficient operation in half-bridge and bridge-based topologies.
TI utilizes a Direct Drive architecture to control the GaN FET within the LMG341xR070. When the driver is
powered up, the GaN FET is controlled directly with the integrated gate driver. This architecture provides
superior switching performance compared with the traditional cascode approach.
The integrated driver solves a number of challenges using GaN devices. The LMG341xR070 contains a driver
specifically tuned to the GaN device for fast driving without ringing on the gate. The driver ensures the device
stays off for high drain slew rates up to 150 V/ns. In addition, the integrated driver protects against faults by
providing over-current and over-temperature protection. This feature can protect the system in case of a device
failure, or prevent a device failure in the case of a controller error or malfunction. LMG3410R070 and
LMG3411R070 have the same design and features, except the handling of OCP events. LMG3410R070 adopts
a latch-off strategy at OCP events, while LMG3411R070 can realize cycle-by-cycle current limit function. Please
refer to Fault Detection for more details.
Unlike silicon MOSFETs, there is no p-n junction from source to drain in GaN devices. That is why GaN devices
have no reverse recovery losses. However, the GaN device can still conduct from source to drain in 3rd quadrant
of operation similar to a body diode but with higher voltage drop and higher conduction loss. 3rd quadrant
operation can be defined as follows; when the GaN device is turned off and negative current pulls the drain node
voltage to be lower than its source. The voltage drop across GaN device during 3rd quadrant operation is high;
therefore, it is recommended to operate with synchronous switching and keep the duration of 3rd quadrant
operation at minimum.
8.2 Functional Block Diagram
DRAIN
VDD
GaN
LDO
UVLO
(+5 V, VDD, VNEG)
LDO5V
FAULT
IN
OCP
OTP
Level Shift
BBSW
LPM
Buck-Boost
Controller
VNEG
RDRV
SOURCE
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8.3 Feature Description
The LMG341xR070 includes numerous features to provide increased switching performance and efficiency in
customers' applications while providing an easy-to-use solution.
8.3.1 Direct-Drive GaN Architecture
The LMG341xR070 utilizes a series FET to ensure the GaN module stays off when VDD is not applied. When this
FET is off, the gate of the GaN transistor is held within a volt of the FET's source. As the silicon FET blocks the
drain voltage, the VGS of the GaN transistor decreases until it passes its threshold voltage. Then, the GaN
transistor turns off and blocks the remaining drain voltage.
When the LMG341xR070 is powered up, the internal buck-boost converter generates a negative voltage (VNEG
)
that is sufficient to directly turn off the GaN transistor. In this case, the silicon FET is held on and the GaN
transistor is gated directly with the negative voltage. During operation, this removes the switching loss of silicon
FET.
8.3.2 Internal Buck-Boost DC-DC Converter
An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the GaN
device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation,
the converter remains in discontinuous-conduction mode, but may enter continuous-conduction mode during
startup and overload conditions. The converter is controlled internally and requires only a single surface-mount
inductor and output bypass capacitor. For recommendations on the required passives, see Buck-Boost Converter
Design.
8.3.3 Internal Auxiliary LDO
An internal low-dropout regulator is provided to supply external loads, such as digital isolators for the high-side
drive signal. It is capable of delivering up to 5 mA to an external load. A bypass capacitor with 1 µF typical is
required for stability.
8.3.4 Fault Detection
The GaN driver includes built-in over-current protection (OCP), over-temperature protection (OTP) and under
voltage lockout (UVLO).
8.3.4.1 Over-current Protection
The OCP circuit monitors the LMG341xR070's drain current and compares that current signal with an internally-
set limit. Upon detection of the over-current, the family of GaN FETs has two optional protection actions: 1)
latched overcurrent protection; and 2) cycle-by-cycle overcurrent protection.
LMG3410R070 provides 1) latched OCP option, by which the FET is shut off and held off until the fault is reset
by either holding the IN pin low for more than 350 microseconds or removing power from VDD.
LMG3411R070 provides 2) cycle-by-cycle cycle-by-cycle OCP option. In this mode, the FET is also shut off when
overcurrent happens, but the output fault signal will clear after the input PWM goes low. In the next cycle, the
FET can turn on as normal. The cycle-by-cycle function can be used in cases where steady state operation
current is below the OCP level but transient response can still reach high current, while the circuit operation
cannot be paused. It also prevents the power stage from overheating by having overcurrent induced conduction
loss.
During cycle-by-cycle operation, after the current reaches the upper limit but the PWM input is still high, the load
current can flow through the third quadrant of the other FET of a half-bridge with no synchronous rectification.
The extra high negative voltage drop (–6V to –8V) from drain to source could lead to high third quadrant loss,
similar to dead time loss but with much longer time. An operation scheme of cycle-by-cycle current limitation is
shown as 图 13. Therefore, it is critical to design the control scheme to make sure the number of switching
cycles in cycle-by-cycle mode is limited, or to change PWM input based on the fault signal to shorten the time in
third quadrant conduction mode of the power stage.
OCP circuit has a 20ns typical blanking time at slew rate of 100V/ns to prevent false triggering during switch
node transitions. The blanking time increases with respect to lower slew rates accordingly since lower slew rates
results in longer switching transition time. This fast response OCP circuit protects the GaN device even under a
hard short-circuit condition.
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Feature Description (接下页)
Current limit
Inductor
current
VSW
Input PWM
FAULT
图 13. Cycle-by-cycle OCP Operation
8.3.4.2 Over-Temperature Protection and UVLO
The over-temperature protection circuit measures the temperature of the driver die and trips if the temperature
exceeds the over-temperature threshold (typically 165 °C). Upon an over-temperature condition, the GaN device
is held off until temperature falls below the hysteresis limit, typically 15 degrees below the turn-off threshold.
The FAULT output is a push-pull output indicating the readiness and fault status of the driver. It is held low when
starting up until the safety FET is turned on. In an OCP or OTP fault condition, it is held low until the fault latches
are reset or fault is cleared. If the power supplies go below the UVLO thresholds, power transistor switching is
disabled and FAULT is held low until the power supplies recover.
8.3.5 Drive Strength Adjustment
To allow for an adjustable slew rate to control stability and ringing in the circuit, as well as an adjustment to pass
electro-magnetic compliance (EMC) standards, LMG341xR070 allows the user to adjust its drive strength. A
resistor is connected the RDRV pin and ground. The value of the resistor determines the slew rate of the device
during turn-on between 30V/ns and 100V/ns; see 图 2 for the relationship between RDRV and the drain slew
rate. The propagation delays vary with RDRV; consult 图 1 for more details. The turn-off slew rate is dependent
on the load current; therefore, it is not controlled.
14
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8.4 Device Functional Modes
8.4.1 Low-Power Mode
In some applications, it is important to reduce quiescent current during low power mode such as start up or burst.
The LMP pins reduces the quiescent current to support low power modes. When LPM is pulled low, the supply
current in the low-power mode is typically 80 µA. Once this pin is pulled high, the buck-boost converter will start
up and LMG341xR070 will be ready to operate within 1 ms.
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMG341xR070 is a single-channel GaN power stage targeting high-voltage applications. It targets hard-
switched and soft-switched applications running from a 350 V to 480 V bus such as power-factor correction
(PFC) applications. As GaN devices such as the LMG341xR070 have zero reverse-recovery charge, they are
well-suited for hard-switched half-bridge applications, such as the totem-pole bridgeless PFC circuit. It is also
well-suited for resonant DC-DC converters, such as the LLC and phase-shifted full-bridge. As both of these
converters utilize the half-bridge building block, this section will describe how to use the LMG341xR070 in a half-
bridge configuration.
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9.2 Typical Application
ISO_12V_L
5V
VHV
i
D1
UFM15PL-TP
HVBUS
C1
1µF
ISO_12V_H
Q1
VDD
R2
U1
VCC1
0
R1
20
5V_H
27
25
1
C3
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
5V_H
1
3
4
5
6
7
16
14
2
VCC2
OUTA
OUTB
INC
C4
22pF
AGND
ISO_RET_H
3
R3
LDO5V
R4
0.1µF
C8
47µF
4
PWM_H
FauLT_H
INA
C5
0.22µF
49.9
5
49.9
13ISONC2
6
68pF
C2
INB
7
12
ISO_RET_H
8
OUTC
NC
ISO_RET_H
IN_H
FAULT_H
9
ISONC1
ISONC3
11
10
10
11
NC
31
32
29
30
28
26
IN
C6
68pF
EN1
EN2
AGND
5V_H
12
13
14
15
16
18
19
20
21
22
23
33
FAULT
LPM
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
PAD
R7
2
8
15
9
GND1
GND1
GND2
GND2
10.0k
ISO7831FDWR
L1
RDRV
BBSW
VNEG
AGND
ISO_RET_H
SW_H
BRC2518T220K
15k 100V/ns
40.2k 50V/ns
C10
C29
R5
15k
VM12V_H
0.01µF
1206
0.01µF
C12
0.01µF
1206
C13
C14
0.1µF
C15
0.1µF
0.01µF
1206
C9
2.2uF
1206
5V
17
24
NC
GND
C16
1µF
LMG3410R070
ISO_RET_H
ISO_RET_H
VSWNET
i
U2
12V
ISO_12V_L
Q2
R18
0
AGND
5V_L
C18
1
3
4
5
6
7
16
14
13
12
11
10
27
25
1
VCC1
INA
VCC2
OUTA
OUTB
INC
VDD
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
C23
10µF
5V_L
2
0.1µF
3
LDO5V
ISO_RET_L
4
R11
C19
22pF
C7
0.22µF
5
PWM_L
FAULT_L
INB
ISO_RET_L
6
R12
7
OUTC
NC
8
C17
68pF
49.9
ISO_RET_L
IN_L
9
NC
10
11
31
32
29
30
28
26
EN1
EN2
IN
AGND
C11
68pF
FAULT_L
R8
2
8
15
9
12
13
14
15
16
18
19
20
21
22
23
33
GND1
GND1
GND2
GND2
FAULT
LPM
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
PAD
5V_L
15k 100v/ns
ISO7831FDWR
10.0k
R6
17.8k
R9
100k
L2
RDRV
BBSW
VNEG
AGND
17.8k 100V/ns
68.1k 50V/ns
ISO_RET_L
SW_L
BRC2518T220K
VM12V_L
ISO_RET_L
Q3
MGSF1N02LT1G
C26
2.2uF
1
17
24
NC
GND
ISO_RET_L
LMG3410R070
ISO_RET_L
ISO_RET_L
ISO_RET_L
图 14. Typical Half-Bridge Application
16
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9.2.1 Design Requirements
This design example is for a hard-switched boost converter which is representative of PFC applications. The
system parameters considered are as follows.
表 1. Design Parameters
DESIGN PARAMETER
Input Voltage
EXAMPLE VALUE
200 VDC
400 VDC
5 A
Output Voltage
Input (Inductor) Current
Switching Frequency
100 kHz
9.2.2 Detailed Design Procedure
In high-voltage power converters, correct circuit design and PCB layout is essential to obtaining a high-
performance and even functional power converter. While the general procedure for designing a power converter
is out of the scope of this document, this datasheet describes how to utilize the LMG341xR070 to build efficient,
well-behaved power converters.
9.2.2.1 Slew Rate Selection
The LMG341xR070 supports slew rate adjustment through connecting a resistor from RDRV to source. The
choice of RDRV will control the slew rate of the drain voltage of the device between approximately 25 V/ns and
100 V/ns. The slew rate adjustment is used to control the following aspects of the power stage:
•
•
•
•
Switching loss in a hard-switched converter
Radiated and conducted EMI generated by the switching stage
Interference elsewhere in the circuit coupled from the switch node
Voltage overshoot and ringing on the switch node due to power loop inductance and other parasitics
When increasing the slew rate, the switching power loss will decrease, as the portion of the switching period
where the switch simultaneous conducts high current while blocking high voltage is decreased. However, by
increasing the slew rate of the device, the other three aspects of the power stage get worse. Following the
design recommendations in this datasheet will help mitigate the system-related challenges related to high slew
rate. Ultimately, it is up to the power designer to ensure the chosen slew rate provides the best performance in
his or her end application.
9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
Using a bootstrap supply for the high-side LMG341xR070 places additional constraints on the startup of the
circuit. Before the high-side LMG341xR070 functions correctly, its VDD, LDO5V and VNEG power supplies must
start up and be functional. Prior to the device powering up, the GaN device operates in cascode mode with
reduced performance. In particular, under high drain slew rate (dv/dt), the transistor can conduct to a small extent
and cause additional power dissipation. The correct startup procedure for a bootstrap-supplied half-bridge
depends on the circuit used.
In a buck converter without pre-bias, where the initial output voltage is zero, the startup procedure is
straightforward. In this case, before switching begins, turn on the low-side device to allow the high-side bootstrap
transistor to charge up. When the FAULT signal goes high, the high-side device has powered up completely, and
normal switching can begin.
In a boost converter or a buck converter with a pre-biased output, it is necessary to operate the circuit in
switching PWM mode while the high-side LMG341xR070 is powering up. With a boost converter, if the low-side
device is held on, the power inductor current will likely run away and the inductor will saturate. To start up a
boost converter, the duty cycle has to be very low and gradually increase to charge the output to the desired
value without the inductor current reaching saturation. This pulse sequence can be performed open-loop or using
a current-mode controller. This startup mode is standard for boost-type converters.
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However, with the LMG341xR070, during the boost converter startup, significant shoot-through current can occur
for high drain slew rates while starting up. This shoot-through current is approximately 1.25 µC per switching
event at 50 V/ns, and is comparable to a reverse-recovery event. If this shoot-through current is undesirable, the
drain slew rate of the low-side device must be reduced during startup. In 图 14, the FAULT output from the high-
side device is used to gate MOSFET Q1. When FAULT from the high-side is high, once the device is powered
up, Q1 turns on and reduces the effective resistance connected to RDRV on the low-side LMG341xR070. With
this circuit, the dv/dt of the low-side device can be held low to reduce power dissipation and reduce ringing
during high-side startup, but then increase to reduce switching loss during normal operation.
9.2.2.2 Signal Level-Shifting
As the LMG341xR070 is a single-channel power stage, two devices are used to construct a half-bridge
converter, such as the one shown in 图 14. A high-voltage level shifter or digital isolator must be used to provide
signals to the high-side device. Using an isolator for the low-side device is optional but will equalize propagation
delays between the high-side and low-side signal path, as well as providing the ability to use different grounds for
the power stage and the controller. If an isolator is not used on the low-side device, the control ground and the
power ground must be connected at the LMG341xR070, as described in Layout Guidelines, and nowhere else on
the board. With the high current slew rate of the fast-switching GaN device, any ground-plane inductance
common with the power path may cause oscillation or instability in the power stage without the use of an isolator.
Choosing a digital isolator for level-shifting is an important consideration for fault-free operation. Because GaN
switches very quickly, exceeding 50 V/ns in hard-switching applications, isolators with high common-mode
transient immunity (CMTI) are required. If an isolator suffers from a CMTI issue, it can output a false pulse or
signal which can cause shoot-through. In addition, choosing an isolator that is not edge-triggered can improve
circuit robustness. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states and cause
circuit malfunctioning.
On/off keyed isolators are preferred, such as the TI ISO78xxF series, as a high CMTI event would only cause a
short (few nanosecond) false pulse, which can be filtered out. To allow for filtering of these false pulses, an R-C
filter at the driver input is recommended to ensure these false pulses can be filtered. If issues are observed,
values of 1 kΩ and 22 pF can be used to filter out any false pulses.
9.2.2.3 Buck-Boost Converter Design
The Buck-boost converter generates the negative voltage necessary to turn off the direct-drive GaN FET. While it
is controlled internally, it requires an external power inductor and output capacitor. The converter is designed to
use a 22 µH inductor and a 2.2 µF output capacitor. As the peak current of the buck-boost is limited to less than
350 mA, the inductor chosen must have a saturation current above 350 mA. A Taiyo-Yuden BRC2518T220K 22
µH SMT inductor in a 0806 package is recommended. This inductor is connected between the BBSW pin and
ground. A 2.2 µF, 25V 0805 bypass capacitor is required between VNEG and ground. Due to the voltage
coefficient of X7R capacitors, a 2.2 µF capacitor will provide the required minimum 1.0 µF capacitance when
operating.
9.2.3 Application Curves
VDS (50 V/div)
ID (2.5 A/div)
VDS (50 V/div)
ID (1.25 A/div)
VOUT = 400V
IL = 5 A
RDRV = 40 kW
VBUS = 400 V
IL = 5 A
RDRV = 40 kW
Time (5 ns/div)
Time (5 ns/div)
D006
D007
图 15. Turn-on Waveform in Application Example
图 16. Turn-off Waveform in Application Example
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9.3 Paralleling GaN Devices
LMG341xR070s can be paralleled directly in soft-switching applications. As for hard-switching applications, small
decoupling inductors should be utilized to parallel the two half-bridge LMG341xR070s. This type of setup
prevents current and thermal unbalances among the parallel devices due to any propagation delay and gate-
source threshold voltage mismatches, and other factors.
9.4 Do's and Don'ts
The successful use of GaN devices in general and the LMG341xR070 in particular depends on proper use of the
device. When using the LMG341xR070, DO:
•
•
•
•
Read and fully understand the datasheet, including the application notes and layout recommendations
Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance
Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance
Use the proper size decoupling capacitors and locate them close to the IC as described in the Layout
Guidelines section
•
•
Use a signal isolator to supply the input signal for the low side device. If not, ensure the signal source is
connected to the signal GND plane which is tied to the power source only at the LMG341xR070 IC
Use the FAULT pin to determine power-up state and to detect over-current and over-temperature events and
safely shut off the converter.
To avoid issues in your system when using the LMG341xR070, DON'T:
•
Use a single-layer or two-layer PCB for the LMG341xR070 as the power-loop and bypass capacitor
inductances will be excessive and prevent proper operation of the IC
•
•
•
Reduce the bypass capacitor values below the recommended values
Allow the device to experience drain transients above 600 V as they may damage the device
Allow significant third-quadrant conduction when the device is OFF or unpowered, which may cause
overheating. Self-protection feature cannot protect the device in this mode of operation
•
Ignore the FAULT pin output.
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10 Power Supply Recommendations
The LMG341xR070 requires an unregulated 12-V supply to power its internal driver and fault protection circuitry.
The low-side supply can be supplied from the local controller supply. The high-side device's supply must come
from an isolated supply or bootstrap supply.
10.1 Using an Isolated Power Supply
Using an isolated power supply to power the high-side device has the advantage that it will work regardless of
continued power-stage switching or duty cycle. It can also power the high-side device before power-stage
switching begins, eliminating the power-loss concern of switching with an unpowered LMG341xR070 (see
Startup and Slew Rate with Bootstrap High-Side Supply for details). Finally, a properly-selected isolated supply
will contribute fewer parasitics to the switching power stage, increasing power-stage efficiency. However, the
isolated power supply solution is larger and more expensive than the bootstrap solution.
The isolated supply can be constructed from an output of a flyback or FlyBuck™ converter, or using an isolated
power module. When using an unregulated supply, ensure that the input to the LMG341xR070 does not exceed
the maximum supply voltage. If necessary, a 18 V zener to clamp the VDD voltage supplied by the isolated
power converter. Minimizing the inter-winding capacitance of the isolated power supply or transformer is
necessary to reduce switching loss in hard-switched applications.
10.2 Using a Bootstrap Diode
When used in a half-bridge configuration, a floating supply is necessary for the top-side switch. Due to the
switching performance of LMG341xR070, a transformer-isolated power supply is recommended. With caution, a
bootstrap supply can be used with the recommendations in this section.
10.2.1 Diode Selection
LMG341xR070 has no reverse-recovery charge and little output charge. Hard-switched circuits using
LMG341xR070 also exhibit high voltage slew rates. A compatible bootstrap diode must exhibit low output charge
and, if used in a hard-switching circuit, very low reverse-recovery charge.
For soft-switching applications, the MCC UFM15PL ultra-fast silicon diode can be used. The output charge of 2.7
nC is small in comparison with the switching transistors, so it will have little influence on switching performance.
In a hard-switching application, the reverse recovery charge of the silicon diode may contribute an additional loss
to the circuit.
For hard-switched applications, a silicon carbide diode can be used to avoid reverse-recovery effects. The Cree
C3D1P7060Q SiC diode has an output charge of 4.5 nC and a reverse recovery charge of about 5 nC. There will
be some losses using this diode due to the output charge, but these will not dominate the switching stage’s
losses.
10.2.2 Managing the Bootstrap Voltage
In a synchronous buck, totem-pole PFC, or other converter where the low-side switch occasionally operates in
third-quadrant mode, it is important to consider the bootstrap supply. During the dead time, the bootstrap supply
charges through a path that includes the third-quadrant voltage drop of the low-side LMG341xR070. This third-
quadrant drop can be large, which may over-charge the bootstrap supply in certain conditions. The VDD supply of
LMG341xR070 must not exceed 18 V in bootstrap operation.
20
版权 © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
Using a Bootstrap Diode (接下页)
DRAIN
VDD
VF
SOURCE
+
œ
DRAIN
VDD
VF
SOURCE
Copyright © 2017, Texas Instruments Incorporated
图 17. Charging Path for Bootstrap Diode
The recommended bootstrap supply connection includes a bootstrap diode and a series resistor with an optional
zener as shown in 图 18. The series resistor limits the charging current at startup and when the low-side device
is operating in third-quadrant mode. This resistor must be chosen to allow sufficient current to power the
LMG341xR070 at the desired operating frequency. At 100 kHz operation, a value of approximately 5.1 ohms is
recommended. At higher frequencies, this resistor value should be reduced or the resistor omitted entirely to
ensure sufficient supply current.
DRAIN
+12 V
VDD
VF
SOURCE
Copyright © 2017, Texas Instruments Incorporated
图 18. Suggested Bootstrap Regulation Circuit
Using a series resistor with the bootstrap supply will create a charging time constant in conjunction with the
bypass capacitance on the order of a microsecond. When the dead time, or third-quadrant conduction time, is
much lower than this time constant, the bootstrap voltage will be well-controlled and the optional zener clamp in
图 18 will not be necessary. If a large deadtime is needed, a 14-V zener diode can be used in parallel with the
VDD bypass capacitor to prevent damaging the high-side LMG341xR070.
10.2.3 Reliable Bootstrap Start-up
In some applications such as boost converter, the low side LMG341xR070 may need to start switching at high
frequency while high side LMG341xR070 is not fully biased. If low side GaN device turn-on speed is adjusted to
achieve high slew rate, the high side GaN device can turn-on unintentionally as high dv/dt can charge high side
GaN device drain to source capacitance. For reliable operation, the slew rate should be slowed down to 30 V/ns
by changing the resistance of RDRV pin of the low side LMG341xR070 until high side LMG341xR070's bias is
fully settled. This can be monitored through the FAULT output of high side LMG341xR070 as given in 图 14.
版权 © 2016–2018, Texas Instruments Incorporated
21
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The layout of the LMG341xR070 is critical to its performance and functionality. Because the half-bridge
configuration is typically used with these GaN devices, layout recommendations will be considered with this
configuration. A four-layer or higher layer count board is required to reduce the parasitic inductances of the
layout to achieve suitable performance.
11.1.1 Power Loop Inductance
The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes
large di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic
interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
This loop inductance is minimized by locating the power devices as close together as possible. The bus
capacitance is positioned in line with the two devices, either below the low-side device or above the high-side
device, on the same side of the PCB. The return path (PGND in this case) is located on the second layer on the
PCB in close proximity to the top layer. By using an inner layer and not the bottom layer, the vertical dimension
of the loop is reduced, thus minimizing inductance. A large number of vias near both the device terminal and bus
capacitance carries the high-frequency switching current to the inner layer while minimizing impedance.
11.1.2 Signal Ground Connection
The LMG341xR070's SOURCE pin is also signal ground reference. The signal GND plane should be connected
to SOURCE with low impedance kelvin connection. In addition, the return path for the passives associated to the
driver (e.g. bypass capacitance) must be connected to the GND plane. In 图 19, local signal GND planes are
located on the second copper layer to act as the return for the local circuitry. The local signal GND planes are
isolated from the high-current SOURCE plane except the kelvin connection at the source pin through enough low
impedance vias.
11.1.3 Bypass Capacitors
The gate drive loop impedance must also be minimized to yield strong performance. Although the gate driver is
integrated on package, the bypass capacitance for the driver is placed externally on the PCB board. As the GaN
device is turned off to a negative voltage, the impedance of the negative source is included in the crucial turn-off
path. As the critical hold-off path passes through this external bypass capacitor attached to VNEG, this capacitor
must be located close to the LMG341xR070. In the 图 19, VNEG bypass capacitors C9 and C26 are located
immediately adjacent to the pins on the IC with a direct connection to the SOURCE pin.
The bypass capacitors for the input supply (C8 and C23) and the 5V regulator (C5 and C7) must also be located
immediately next to the IC with a close connection to the ground plane.
11.1.4 Switch-Node Capacitance
GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching
loss. To preserve this low switching loss, additional capacitance added to the output node must be minimized.
The PCB capacitance at the switch node can be minimized by following these guidelines:
•
•
•
•
•
•
Minimize overlap between the switch-node plane and other power and ground planes
Thin the GND return path under the high-side device somewhat while still maintaining a low-inductance path
Choose high-side isolator ICs and bootstrap diodes with low capacitance
Locate the power inductor as close to the power stage as possible
Power inductors should be constructed with a single-layer winding to minimize intra-winding capacitance
If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and
the power stage to effectively shield the power stage from the additional capacitance
•
If a back-side heat-sink is used, restrict the switch-node copper coverage on the bottom copper layer to the
minimum area necessary to extract the needed heat
22
版权 © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
Layout Guidelines (接下页)
11.1.5 Signal Integrity
The control signals to the LMG341xR070 must be protected from the high dv/dt that the GaN power stage
produces. Coupling between the control signals and the drain may cause circuit instability and potential
destruction. Route the control signals (IN, FAULT and LPM) over a ground plane located on an adjacent layer.
For example, in the layout in 图 19, all the signals are routed on the top layer directly over the signal GND plane
on the first inner copper layer.
The signals for the high-side device are often particularly vulnerable. Coupling between these signals and system
ground planes could cause issues in the circuit. Keep the traces associated with the control signals away from
drain copper. For the high-side level shifter, ensure no copper from either the input or output side extends
beneath the isolator or the device's CMTI may be compromised.
11.1.6 High-Voltage Spacing
Circuits using the LMG341xR070 involve high voltage, potentially up to 600V. When laying out circuits using the
LMG341xR070, understand the creepage and clearance requirements in your application and how they apply to
the power stage. Functional (or working) isolation is required between the source and drain of each transistor,
and between the high-voltage power supply and ground. Functional isolation or perhaps stronger isolation (such
as reinforced isolation) may be required between the input circuitry to the LMG341xR070 and the power
controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet your
isolation requirements.
If a heatsink is used to manage thermal dissipation of the LMG341xR070, ensure necessary electrical isolation
and mechanical spacing is maintained between the heatsink and the PCB.
11.1.7 Thermal Recommendations
The LMG341xR070 is a lateral transistor grown on a Si substrate. The thermal pad is connected to the Source
node. The LMG341xR070 may be used in applications with significant power dissipation, for example, hard-
switched power converters. In these converters, cooling using just the PCB may not be sufficient to keep the part
at a reasonable temperature. To improve the thermal dissipation of the part, TI recommends a heatsink is
connected to the back of the PCB to extract additional heat. Using power planes and numerous thermal vias, the
heat dissipated in the LMG341xR070(s) can be spread out in the PCB and effectively passed to the other side of
the PCB. A heat sink can be applied to bare areas on the back of the PCB using an adhesive thermal interface
material (TIM). The soldermask from the back of the board underneath the heatsink can be removed for more
effective heat removal.
Please refer to the High Voltage Half Bridge Design Guide for LMG341x Smart GaN FET application note for
more recommendations and performance data on thermal layouts.
11.2 Layout Example
Correct layout of the LMG341xR070 and its surrounding components is essential for correct operation. The
layout shown here reflects the power stage schematic in 图 14. It may be possible to obtain acceptable
performance with alternate layout schemes, however this layout has been shown to produce good results and is
intended as a guideline.
版权 © 2016–2018, Texas Instruments Incorporated
23
LMG3410R070, LMG3411R070
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
www.ti.com.cn
Layout Example (接下页)
图 19. Example Half-Bridge Layout
24
版权 © 2016–2018, Texas Instruments Incorporated
LMG3410R070, LMG3411R070
www.ti.com.cn
ZHCSIP2E –APRIL 2016–REVISED OCTOBER 2018
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
《LMG3410 智能 GaN FET 的高压半桥设计指南》应用手册。
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
FlyBuck, E2E are trademarks of Texas Instruments.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2000
250
(1)
(2)
(3)
(4/5)
(6)
LMG3410R070RWHR
LMG3410R070RWHT
LMG3411R070RWHR
LMG3411R070RWHT
ACTIVE
VQFN
VQFN
VQFN
VQFN
RWH
32
32
32
32
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168HRS
Level-3-260C-168HRS
Level-3-260C-168HRS
Level-3-260C-168HRS
-40 to 150
-40 to 150
-40 to 150
-40 to 150
LMG3410
Samples
Samples
Samples
Samples
R070
ACTIVE
ACTIVE
ACTIVE
RWH
RoHS-Exempt
& Green
NIPDAU
NIPDAU
NIPDAU
LMG3410
R070
RWH
2000
250
RoHS-Exempt
& Green
LMG3411
R070
RWH
RoHS-Exempt
& Green
LMG3411
R070
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMG3410R070RWHR
LMG3411R070RWHR
VQFN
VQFN
RWH
RWH
32
32
2000
2000
330.0
330.0
16.4
16.4
8.3
8.3
8.3
8.3
2.25
2.25
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMG3410R070RWHR
LMG3411R070RWHR
VQFN
VQFN
RWH
RWH
32
32
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
RWH0032A
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
8.1
7.9
A
B
PIN 1 INDEX AREA
8.1
7.9
1.0
0.8
(0.2) TYP
C
SEATING PLANE
3.75 0.1
PKG
0.05
0.00
0.08 C
(2.75)
(0.65)
0.65
0.55
32X
4X 0.85
12
16
11
17
0.85
0.75
4X
2X
0.1
C A B
C
6.2 0.1
0.05
5.2
33
PKG SYMM
16X 0.65
PIN 1 ID
0.45
0.35
24X
0.1
C A B
C
27
4X
0.05
1
32
28
0.65
0.55
0.1
4X 0.65
2X 1.3
C A B
C
0.05
4X 0.75
2X 2.85
4221569/D 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RWH0032A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.75)
(0.8) TYP
(1.875)
28
32
27
1
4X (0.8)
2X (1.05)
24X (0.4)
22X ( 0.2)
VIA
(7.6)
33
PKG SYMM
(6.2)
(0.595)
(1.19)
TYP
20X (0.65)
(0.4)
4X (0.85)
(0.8) TYP
17
11
(R0.05) TYP
16
12
(1.225)
4X (0.6)
PKG
PAD
2X (2.85)
4X (0.75)
(7.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221569/D 08/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
RWH0032A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
PKG
32
5X
(1.8)
(0.314)
SEE DETAIL A
28
27
1
24X (0.4)
(0.2)
TYP
4X (1.19)
(7.6)
PKG SYMM
(R0.05) TYP
20X (0.65)
33
10X (0.99)
4X (0.85)
17
11
16
12
10X (1.6)
4X (0.6)
4X (0.75)
2X (2.85)
(0.76)
(7.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:10X
METAL
PASTE
DETAIL A
4X, SCALE: 30X
4221569/D 08/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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