LMG3422R030_V01_技术文档

LMG3422R030, LMG3425R030

SNOSDA7C – AUGUST 2020 – REVISED DECEMBER 2021

LMG342xR030 600-V 30-mΩ GaN FET With Integrated Driver, Protection, and

Temperature Reporting

1 Features

3 Description

•

Qualified for JEDEC JEP180 for hard-switching

topologies

600-V GaN-on-Si FET with Integrated gate driver

– Integrated high precision gate bias voltage

– 200-V/ns CMTI

The LMG342xR030 GaN FET with integrated driver

and protection enables designers to achieve new

levels of power density and efficiency in power

electronics systems.

•

The LMG342xR030 integrates a silicon driver that

enables switching speed up to 150 V/ns. TI’s

integrated precision gate bias results in higher

switching SOA compared to discrete silicon gate

drivers. This integration, combined with TI's low-

inductance package, delivers clean switching and

minimal ringing in hard-switching power supply

topologies. Adjustable gate drive strength allows

control of the slew rate from 20 V/ns to 150 V/ns,

which can be used to actively control EMI and

optimize switching performance. The LMG3425R030

includes ideal diode mode, which reduces third-

quadrant losses by enabling adaptive dead-time

control.

– 2.2-MHz switching frequency

– 30-V/ns to 150-V/ns slew rate for optimization

of switching performance and EMI mitigation

– Operates from 7.5-V to 18-V supply

Robust protection

– Cycle-by-cycle overcurrent and latched short-

circuit protection with < 100-ns response

– Withstands 720-V surge while hard-switching

– Self-protection from internal overtemperature

and UVLO monitoring

•

Advanced power management

– Digital temperature PWM output

– Ideal diode mode reduces third-quadrant losses

in LMG3425R030

Advanced power management features include digital

temperature reporting and fault detection. The

temperature of the GaN FET is reported through

a variable duty cycle PWM output, which simplifies

managing device loading. Faults reported include

overtemperature, overcurrent, and UVLO monitoring.

2 Applications

•

High density industrial power supplies

Solar inverters and industrial motor drives

Uninterruptable power supplies

Merchant network and server PSU

Merchant telecom rectifiers

Device Information

PART NUMBER

LMG3422R030

PACKAGE ⁽¹⁾

BODY SIZE (NOM)

VQFN (54)

12.00 mm × 12.00 mm

LMG3425R030 ⁽²⁾

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) Device is ADVANCE INFORMATION.

DRAIN

Direct-Drive

Slew

GaN

Rate

SOURCE

RDRV

IN

VDD

VNEG

LDO,

BB

OCP, SCP,

OTP, UVLO

Current

LDO5V

TEMP

FAULT

OC

SOURCE

Simplified Block Diagram

Switching Performance at > 100 V/ns

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

LMG3422R030, LMG3425R030

SNOSDA7C – AUGUST 2020 – REVISED DECEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................6

7.6 Switching Characteristics............................................8

7.7 Typical Characteristics..............................................10

8 Parameter Measurement Information..........................12

8.1 Switching Parameters...............................................12

9 Detailed Description......................................................15

9.1 Overview...................................................................15

9.2 Functional Block Diagram.........................................16

9.3 Feature Description...................................................17

9.4 Device Functional Modes..........................................26

10 Application and Implementation................................27

10.1 Application Information........................................... 27

10.2 Typical Application.................................................. 28

10.3 Do's and Don'ts.......................................................32

11 Power Supply Recommendations..............................33

11.1 Using an Isolated Power Supply............................. 33

11.2 Using a Bootstrap Diode......................................... 33

12 Layout...........................................................................35

12.1 Layout Guidelines................................................... 35

12.2 Layout Examples.................................................... 37

13 Device and Documentation Support..........................39

13.1 Documentation Support.......................................... 39

13.2 Receiving Notification of Documentation Updates..39

13.3 Support Resources................................................. 39

13.4 Trademarks.............................................................39

13.5 Electrostatic Discharge Caution..............................39

13.6 Export Control Notice..............................................39

13.7 Glossary..................................................................39

14 Mechanical, Packaging, and Orderable

Information.................................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2021) to Revision C (December 2021)

Page

•

Changed the data sheet status from Advance Information to Production Data..................................................1

2

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5 Device Comparison

DUAL OVERCURRENT /

SHORT-CIRCUIT PROTECTION

OPERATIONAL IDEAL-DIODE

DEVICE NAME

TEMPERATURE REPORTING

MODE

LMG3422R030

Yes

No

LMG3425R030 ⁽¹⁾

Yes

(1) Device is ADVANCE INFORMATION.

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6 Pin Configuration and Functions

DRAIN

15 14

13 12 11 10

9

8

7

6

5

4

3

2

1

16

17

54

NC2

18

19

20

21

22

23

24

25

26

53

52

51

50

49

48

47

46

45

LDO5V

RDRV

TEMP

OC

THERMAL PAD

GND

FAULT

IN

VDD

GND

27

44

GND

28

29 30

31 32 33 34 35 36 37 38

39 40 41 42

43

VNEG

SOURCE

Figure 6-1. RQZ Package 54-Pin VQFN (Top View)

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NC1

NO.

1, 16

2-15

Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads

are non-solder mask defined pads and must not be physically connected to any other metal on the PCB.

Internally connected to DRAIN.

—

P

DRAIN

NC2

GaN FET drain. Internally connected to NC1.

Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads

are non-solder mask defined pads and must not be physically connected to any other metal on the PCB.

Internally connected to SOURCE, GND, and THERMAL PAD.

17, 54

—

SOURCE

VNEG

18-40

41-42

P

GaN FET source. Internally connected to GND, NC2, and THERMAL PAD.

Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode

GaN FET. Bypass to ground with a 2.2-µF capacitor.

BBSW

GND

VDD

IN

43

44, 45, 49

46

P

G

P

I

Internal buck-boost converter switch pin. Connect an inductor from this point to ground.

Signal ground. Internally connected to SOURCE, NC2, and THERMAL PAD.

Device input supply.

47

CMOS-compatible non-inverting input used to turn the FET on and off.

Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.

FAULT

48

O

Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault

Detection for details.

OC

50

51

O

Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed

waveform. The device temperature is encoded as the duty cycle of the waveform.

TEMP

Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive strength to

control slew rate. Tie the pin to GND to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.

RDRV

52

53

—

I

LDO5V

P

5-V LDO output for external digital isolator

THERMAL

PAD

Thermal pad. Internally connected to SOURCE, GND, and NC2. The thermal pad can be used to conduct

rated device current.

—

(1) I = input, O = output, P = power, G = ground

4

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7 Specifications

7.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are respect to GND⁽¹⁾

MIN

MAX

600

UNIT

V

V_DS

Drain-source voltage, FET off

V_DS(surge)Drain-source surge voltage, FET switching, surge condition⁽²⁾

720

V

V_DS(tr)

Drain-source surge transient ringing peak voltage, FET off, surge condition^{(2) (3)}

800

V

(surge)

VDD

–0.3

–16

20

5.5

0.3

V

LDO5V

VNEG

BBSW

V_VNEG–1 V_VDD+0.5

Pin voltage

IN

–0.3

20

V_LDO5V+0.

3

FAULT, OC, TEMP

RDRV

V

5.5

55

V

A

I_D(RMS)

I_D(pulse)

Drain RMS current, FET on

Internally

Limited

Drain pulsed current, FET on, tp < 10 µs⁽⁴⁾

–120

A

I_S(pulse)

T_J

Source pulsed current, FET off, tp < 1 µs

Operating junction temperature⁽⁵⁾

Storage temperature

80

150

A

–40

–55

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) See Section 9.3.3 for an explanation of the switching cycle drain-source voltage ratings.

(3) t1 < 200 ns in Figure 9-1.

(4) The positive pulsed current must remain below the overcurrent threshold to avoid the FET being automatically shut off. The FET drain

intrinsic positive pulsed current rating for t_p< 10 µs is 120 A.

(5) Refer to the Electrical and Switching Characteristics Tables for junction temperature test conditions.

7.2 ESD Ratings

PARAMETER

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Unless otherwise noted: voltages are respect to GND, SOURCE connected to GND

MIN

7.5

0

NOM

12

MAX

UNIT

VDD

Supply voltage

(Maximum switching frequency derated

for V_VDD< 9 V)

18

V

Input voltage

IN

5

18

40

V

A

I_D(RMS)

Drain RMS current

Positive source current

LDO5V

25

mA

kΩ

uF

R_RDRV

C_VNEG

RDRV to GND resistance from external slew-rate control resistor

VNEG to GND capacitance from external bypass capacitor

0

1

500

10

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7.3 Recommended Operating Conditions (continued)

Unless otherwise noted: voltages are respect to GND, SOURCE connected to GND

MIN

NOM

MAX

10

UNIT

L_BBSW

BBSW to GND inductance from external buck-boost inductor

3

4.7

uH

7.4 Thermal Information

LMG342xR030

THERMAL METRIC⁽¹⁾

RQZ (VQFN)

UNIT

54 PINS

16.6

4.2

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

3.1

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.12

3

Ψ_JB

R_θJC(bot)

0.33

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ T_J≤ 125℃;

V_DS= 480 V; 9 V ≤ V_VDD≤ 18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GAN POWER TRANSISTOR

V_IN= 5 V, T_J= 25°C

26

45

3.8

5

35

mΩ

V

R_DS(on)

Drain-source on resistance

V_IN= 5 V, T_J= 125°C

I_S= 0.1 A

Third-quadrant mode source-drain

voltage

V_SD

I_S= 20 A

3

V

V_DS= 600 V, T_J= 25°C

V_DS= 600 V, T_J= 125°C

V_DS= 400 V

1

uA

pF

I_DSS

Drain leakage current

Output capacitance

10

170

C_OSS

C_O(er)

130

230

Energy related effective output

capacitance

276

430

335

pF

Time related effective output

capacitance

V_DS= 0 V to 400 V

C_O(tr)

Q_OSS

Q_RR

Output charge

160

175

0

nC

Reverse recovery charge

VDD – SUPPLY CURRENTS

VDD quiescent current (LMG3422)

V_VDD= 12 V, V_IN= 0 V or 5V

700

780

13

1200

1300

18

uA

VDD quiescent current (LMG3425)

VDD operating current

V_VDD= 12 V, V_IN= 0 V or 5V

V_VDD= 12 V, f_IN= 140 kHz, soft-switching

mA

BUCK BOOST CONVERTER

VNEG output voltage

VNEG sinking 50 mA

–14

0.4

V

A

Peak BBSW sourcing current at low

peak current mode setting

(Peak external buck-boost inductor

current)

0.3

0.5

6

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7.5 Electrical Characteristics (continued)

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ T_J≤ 125℃;

V_DS= 480 V; 9 V ≤ V_VDD≤ 18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Peak BBSW sourcing current at high

peak current mode setting

(Peak external buck-boost inductor

current)

0.8

1

1.2

A

High peak current mode setting

enable – IN positive-going threshold

frequency

280

420

515

kHz

LDO5V

Output voltage

LDO5V sourcing 25 mA

4.75

25

5

5.25

100

V

Short-circuit current

50

mA

IN

V_IN,IT+

V_IN,IT–

Positive-going input threshold voltage

Negative-going input threshold voltage

Input threshold hysteresis

1.7

0.7

100

1.9

1

2.45

1.3

V

0.9

150

1.3

V

Input pulldown resistance

V_IN= 2 V

200

kΩ

FAULT, OC, TEMP – OUPUT DRIVE

Low-level output voltage

Output sinking 8 mA

0.16

0.2

0.4

V

Output sourcing 8 mA, Measured as

V_LDO5V– V_O

High-level output voltage

0.45

VDD, VNEG – UNDER VOLTAGE LOCKOUT

V_VDD,T+

VDD UVLO – positive-going threshold

voltage

6.5

6.1

7

6.5

7.5

7

V

(UVLO)

VDD UVLO – negative-going threshold

voltage

VDD UVLO – Input threshold voltage

hysteresis

510

mV

V

VNEG UVLO – negative-going

threshold voltage

–13.6

–13.2

–13.0

–12.75

–12.3

–12.1

VNEG UVLO – positive-going threshold

voltage

V

GATE DRIVER

From V_DS< 320 V to V_DS< 80 V, RDRV

disconnected from LDO5V, R_RDRV= 300

kΩ, T_J= 25℃, V_BUS= 400 V, L_HBcurrent

= 10 A, see Figure 8-1

20

100

150

V/ns

MHz

From V_DS< 320 V to V_DS< 80 V, T_J=

25℃, V_BUS= 400 V, L_HBcurrent = 10 A,

see Figure 8-1

Turn-on slew rate

From V_DS< 320 V to V_DS< 80 V, RDRV

disconnected from LDO5V, V_RDRV= 0 V,

T_J= 25℃, V_BUS= 400 V, L_HBcurrent = 10

A, see Figure 8-1

V_NEGrising to > –13.25 V, soft-switched,

maximum switching frequency derated for

V_VDD< 9 V

Maximum GaN FET switching

frequency.

2.2

FAULTS

DRAIN overcurrent fault – threshold

current

I_T(OC)

60

80

70

95

80

A

DRAIN short-circuit fault – threshold

current

I_T(SC)

110

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7.5 Electrical Characteristics (continued)

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ T_J≤ 125℃;

V_DS= 480 V; 9 V ≤ V_VDD≤ 18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

di/dt threshold between overcurrent and

short-circuit faults

150

A/µs

Short-circuit current to overcurrent fault

trip difference

25

175

30

A

GaN temperature fault – postive-going

threshold temperature

°C

GaN Temperature fault – threshold

temperature hysteresis

Driver temperature fault – positive-

going threshold temperature

185

20

Driver Temperature fault – threshold

temperature hysteresis

TEMP

Output Frequency

4.5

9

82

14

kHz

%

GaN T_J= 150℃

GaN T_J= 125℃

GaN T_J= 85℃

GaN T_J= 25℃

58.5

36.2

0.3

64.6

40

70

43.7

6

%

Output PWM Duty Cycle

%

3

%

IDEAL-DIODE MODE CONTROL

Drain-source third-quadrant detection –

V_T(3rd)

–0.15

0

0.15

V

threshold voltage

0℃ ≤ T_J≤ 125℃

–40℃ ≤ T_J≤ 0℃

–0.2

0

0.2

A

Drain zero-current detection – threshold

current

I_T(ZC)

–0.35

0.35

7.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ T_J≤ 125℃;

V_DS= 480 V; 9 V ≤ V_VDD≤ 18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SWITCHING TIMES

From V_IN> V_IN,IT+to I_D> 1 A, V_BUS

400 V, L_HBcurrent = 10 A, see Figure 8-1

and Figure 8-2

=

t_d(on)

Drain-current turn-on delay time

Turn-on delay time

28

32

42

52

4

ns

(Idrain)

From V_IN> V_IN,IT+to V_DS< 320 V, V_BUS

400 V, L_HBcurrent = 10 A, see Figure 8-1

and Figure 8-2

=

t_d(on)

t_r(on)

t_d(off)

t_f(off)

From V_DS< 320 V to V_DS< 80 V, V_BUS

400 V, L_HBcurrent = 10 A, see Figure 8-1

and Figure 8-2

=

Turn-on rise time

2.5

44

From V_IN< V_{IN ,IT–}to V_DS> 80 V, V_BUS

400 V, L_HBcurrent = 10 A, see Figure 8-1

and Figure 8-2

=

Turn-off delay time

65

21

24

From V_DS> 80 V to V_DS> 320 V, V_BUS

400 V, L_HBcurrent = 10 A, see Figure 8-1

and Figure 8-2

=

Turn-off fall time⁽¹⁾

V_INrise/fall times < 1 ns, V_DSfalls to <

200 V, V_BUS= 400 V, L_HBcurrent = 10 A,

see Figure 8-1

Minimum IN high pulse-width for FET

turn-on

STARTUP TIMES

8

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7.6 Switching Characteristics (continued)

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ T_J≤ 125℃;

V_DS= 480 V; 9 V ≤ V_VDD≤ 18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

From V_VDD> V_VDD,T+

_(UVLO)to FAULT high, C_LDO5V= 100

nF, C_VNEG= 2.2 µF at 0-V bias linearly

decreasing to 1.5 µF at 15-V bias

Driver start-up time

310

470

us

FAULT TIMES

Overcurrent fault FET turn-off time, FET

on before overcurrent

V_IN= 5 V, From I_D> I_T(OC)to I_D< 50 A, I_D

di/dt = 100 A/µs

t_off(OC)

t_off(SC)

110

65

145

100

250

ns

Short-circuit current fault FET turn-off

time, FET on before short circuit

V_IN= 5 V, From I_D> I_T(SC)to I_D< 50 A, I_D

di/dt = 700 A/µs

Overcurrent fault FET turn-off time, FET

turning on into overcurrent

From I_D> I_T(OC)to I_D< 50 A

200

Short-circuit fault FET turn-off time, FET

turning on into short circuit

From I_D> I_T(SC)to I_D< 50 A

80

180

580

ns

us

IN reset time to clear FAULT latch

From V_IN< V_IN,IT–to FAULT high

250

380

IDEAL-DIODE MODE CONTROL TIMES

V_DS< V_T(3rd)to FET turn-on, V_DSbeing

discharged by half-bridge configuration

inductor at 5 A

Ideal-diode mode FET turn-on time

50

65

ns

I_D> I_T(ZC)to FET turn-off, I_Ddi/dt =

100 A/µs created with a half-bridge

configuration

Ideal-diode mode FET turn-off time

50

76

ns

Overtemperature-shutdown ideal-diode

mode IN falling blanking time

150

230

360

(1) During turn-off, V_DSrise time is the result of the resonance of C_OSSand loop inductance as well as load current.

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7.7 Typical Characteristics

85

140

120

100

80

−40°C

0°C

25°C

85°C

−40°C

0°C

25°C

85°C

125°C

80

75

70

65

60

55

50

45

40

35

30

25

20

125°C

60

40

20

0

50 100 150 200 250 300 350 400 450 500

0

50 100 150 200 250 300 350 400 450 500

RDRV Resistance (k)

Figure 7-1. Drain-Current Turn-On Delay Time vs Drive Strength

Resistance

Figure 7-2. Turn-On Delay Time vs Drive Strength Resistance

25

120

−40°C

0°C

25°C

85°C

125°C

−40°C

0°C

25°C

85°C

125°C

100

80

60

40

20

0

20

15

10

5

0

50 100 150 200 250 300 350 400 450 500

0

50 100 150 200 250 300 350 400 450 500

RDRV Resistance (k)

Figure 7-4. Turn-On Slew Rate vs Drive Strength Resistance

Figure 7-3. Turn-On Rise Time vs Drive Strength Resistance

6.5

2.2

2

−40°C

0°C

25°C

85°C

125°C

6

1.8

1.6

1.4

1.2

1

5.5

5

4.5

4

3.5

3

0.8

0.6

0

5

10

15

20

25

30

35

-40 -20

0

20

40

60

80 100 120 140 160

Source Current (A)

Junction Temperature (°C)

Figure 7-6. Normalized On-Resistance vs Junction Temperatue

IN = 0 V

Figure 7-5. Off-State Source-Drain Voltage vs Source Current

10

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7.7 Typical Characteristics (continued)

250

200

150

100

50

V_DS= 0 V

V_DS= 50 V

V_DS= 400 V

V_DS= 0 V

V_DS= 50 V

V_DS= 400 V

200

150

100

50

V_DS= 50 V

V_DS= 0 V

0

400

800

1200

1600

2000

0

400

800

1200

1600

2000

IN Switching Frequency (kHz)

T_J= 25°C

T_J= 125°C

Figure 7-7. VDD Supply Current vs IN Switching Frequency

Figure 7-8. VDD Supply Current vs IN Switching Frequency

1750

120

−40°C

0°C

25°C

85°C

1500

100

80

1250

1000

750

500

250

0

125°C

60

Turn-On Switching Energy (J)

Turn-Off Switching Energy (J)

40

20

0

3

6

9

12

15

18

21

24

27

30

0

50 100 150 200 250 300 350 400 450 500

Drain-Source Voltage (V)

Inductive Load Current (A)

Figure 7-10. Half-Bridge Switching Energy vs Inductive Load

Current

Figure 7-9. Output Capacitance vs Drain-Source Voltage

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8 Parameter Measurement Information

8.1 Switching Parameters

Figure 8-1 shows the circuit used to measure most switching parameters. The top device in this circuit is used

to re-circulate the inductor current and functions in third-quadrant mode only. Only the LMG3422R030 must be

used as the top device as it does not have the ideal-diode mode feature. Do not use the LMG3425R030 for the

top device. If the top device has the ideal-diode mode feature, it will automatically turn on the GaN FET when

the inductor current is re-circulating and cause a shoot-through current event when the bottom device turns on.

The bottom device is the active device that turns on to increase the inductor current to the desired test current.

The bottom device is then turned off and on to create switching waveforms at a specific inductor current. Both

the drain current (at the source) and the drain-source voltage is measured. Figure 8-2 shows the specific timing

measurement. TI recommends to use the half-bridge as double pulse tester. Excessive third-quadrant operation

can overheat the top device.

DRAIN

Slew

Rate

Direct- Drive

SOURCE

GaN

RDRV

IN

VDD

VNEG

OCP, OTP, Current

UVLO,

TEMP

LDO,

BB

LDO5V

L_HB

TEMP

FAULT

OC

V_BUS

+

œ

SOURCE

C_PCB

DRAIN

Slew

Rate

Direct- Drive

SOURCE

GaN

RDRV

IN

+

VDD

VNEG

VDS

_

OCP, OTP,

UVLO,

TEMP

Current

LDO,

BB

LDO5V

TEMP

PWM input

FAULT

OC

SOURCE

Figure 8-1. Circuit Used to Determine Switching Parameters

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50%

IN

I_D

t_{d(on)(Idrain)}

1A

t_d(on)

t_d(off)

t_r(on)

t_f(off)

V_DS

80%

20%

Figure 8-2. Measurement to Determine Propagation Delays and Slew Rates

8.1.1 Turn-On Times

The turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and

turn-on rise time . The drain-current turn-on delay time is from when IN goes high to when the GaN FET

drain-current reaches 1 A. The turn-on delay time is from when IN goes high to when the drain-source voltage

falls 20% below the bus voltage. Finally, the turn-on rise time is from when drain-source voltage falls 20% below

the bus voltage to when the drain-source voltage falls 80% below the bus voltage. Note that the turn-on rise time

is the same as the V_DS80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin

setting.

8.1.2 Turn-Off Times

The turn-off transition has two timing components: turn-off delay time, and turn-off fall time. The turn-off delay

time is from when IN goes low to when the drain-source voltage rises to 20% of the bus voltage. The turn-off

fall time is from when the drain-source voltage rises to 20% of the bus voltage to when the drain-source voltage

rises to 80% of the bus voltage. Note that the turn-off fall time is the same as the V_DS20% to 80% rise time.

The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the L_HBload

current.

8.1.3 Drain-Source Turn-On Slew Rate

The drain-source turn-on slew rate, measured in volts per nanosecond, is the inverse of the turn-on rise time or

equivalently the inverse of the V_DS80% to 20% fall time. The RDRV pin is used to program the slew rate.

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8.1.4 Turn-On and Turn-Off Switching Energy

The turn-on and turn-off switching energy shown in Figure 7-10 represent the energy absorbed by the low-side

device during the turn-on and turn-off transients of the circuit. As the circuit in Figure 8-1 represents a boost

converter with input shorted to output, the switching energy is dissipated in the low-side device. The turn-on

transition is lossy while the turn-off transition is essentially lossless with the output capacitance energy charged

by the inductor current. The turn-on and turn-off losses have been calculated from experimental waveforms by

integrating the product of the drain current with the drain-source voltage over the turn-on and turn-off times,

respectively. The skew of probes for voltage and current are very important for accurate measurement of turn-on

and turn-off energy.

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9 Detailed Description

9.1 Overview

The LMG342xR030 is a high-performance power GaN device with integrated gate driver. The GaN device

offers zero reverse recovery and ultra-low output capacitance, which enables high efficiency in bridge-based

topologies. Direct Drive architecture is applied to control the GaN device directly by the integrated gate driver.

This architecture provides superior switching performance compared to the traditional cascode approach and

helps solve a number of challenges in GaN applications.

The integrated driver ensures the device stays off for high drain slew rates. The integrated driver also protects

the GaN device from overcurrent, short-circuit, undervoltage, and overtemperature. Regarding fault signal

reporting, LMG342xR030 provides different reporting method which is shown in Table 9-1. Refer to Fault

Detection for more details. The integrated driver is also able to sense the die temperature and send out the

temperature signal through a modulated PWM signal.

Unlike Si MOSFETs, GaN devices do not have a p-n junction from source to drain and thus have no reverse

recovery charge. However, GaN devices still conduct from source to drain similar to a p-n junction body diode,

but with higher voltage drop and higher conduction loss. Therefore, source-to-drain conduction time must be

minimized while the LMG342xR030 GaN FET is turned off. The ideal-diode mode feature in the LMG3425R030

automatically minimizes the source-to-drain conduction loss that occur on the GaN FET soft-switched turn-on

edge, similar to optimum dead-time control.

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9.2 Functional Block Diagram

TEMP

DRAIN

VDD

Third-Quadrant

Detection

GaN

LDO

LDO5V

UVLO

(+5V, VDD, VNEG)

FAULT

Series

Si FET

Die

Temp

Sensing

Thermal

Shutdown

Short Circuit Protection

Overcurrent Protection

OC

IN

Gating logic control

& level shifting

Buck-Boost

Controller

BBSW

VNEG

SOURCE

RDRV

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9.3 Feature Description

The LMG342xR030 includes advanced features to provide superior switching performance and converter

efficiency.

9.3.1 GaN FET Operation Definitions

For the purposes of this data sheet, the following terms are defined below. The SOURCE pin is assumed to be at

0 V for these definitions.

First-Quadrant Current = Positive current flowing internally from the DRAIN pin to the SOURCE pin.

Third-Quadrant Current = Positive current flowing internally from the SOURCE pin to the DRAIN pin.

First-Quadrant Voltage = Drain pin voltage – Source pin voltage = Drain pin voltage

Third-Quadrant Voltage = SOURCE pin voltage – DRAIN pin voltage = –DRAIN pin voltage

FET On-State = FET channel is at rated R_DS(on). Both first-quadrant current and third-quadrant current can flow

at rated R_DS(on)

.

FET Off-State = FET channel is fully off for positive first-quadrant voltage. No first-quadrant current can flow.

While first-quadrant current cannot flow in the FET Off-State, third-quadrant current still flows if the DRAIN

voltage is taken sufficiently negative (positive third-quadrant voltage). For devices with an intrinsic p-n junction

body diode, current flow begins when the DRAIN voltage drops enough to forward bias the p-n junction.

GaN FETS do not have an intrinsic p-n junction body diode. Instead, current flows because the GaN FET

channel turns back on. In this case, the DRAIN pin becomes the electrical source and the SOURCE pin

becomes the electrical drain. To enhance the channel in third-quadrant, the DRAIN (electrical source) voltage

must be taken sufficiently low to establish a V_GSvoltage greater than the GaN FET threshold voltage. The GaN

FET channel is operating in saturation and only turns on enough to support the third-quadrant current as its

saturated current.

LMG342xR030 GaN FET On-State = GaN FET internal gate voltage is held at the SOURCE pin voltage to

achieve rated R_DS(on). The GaN FET channel is at rated R_DS(on)with V_GS= 0 V because the LMG342xR030 GaN

FET is a depletion mode FET.

LMG342xR030 GaN FET Off-State = GaN FET internal gate voltage is held at the VNEG pin voltage to block

all first-quadrant current. The VNEG voltage is lower than the GaN FET negative threshold voltage to cut off the

channel.

To enhance the channel in off-state third quadrant, the LMG342xR030 DRAIN (electrical source) voltage must be

taken sufficiently close to VNEG to establish a V_GSvoltage greater than the GaN FET threshold voltage. Again,

because the LMG342xR030 GaN FET is a depletion mode FET with a negative threshold voltage, this means

the GaN FET turns on with DRAIN (electrical source) voltage between 0 V and VNEG. The typical off-state

third-quadrant voltage is 4.5 V for third-quadrant current at 20 A. Thus, the off-state third-quadrant losses for

the LMG342xR030 are significantly higher than a comparable power device with an intrinsic p-n junction body

diode. The ideal-diode mode function described in Ideal-Diode Mode Operation can help mitigate these losses in

specific situations.

9.3.2 Direct-Drive GaN Architecture

The LMG342xR030 uses a series Si FET to ensure the power IC stays off when VDD bias power is not applied.

When the VDD bias power is off, the series Si FET is interconnected with the GaN device in a cascode mode,

which is shown in the Functional Block Diagram. The gate of the GaN device is held within a volt of the series

Si FET's source. When a high voltage is applied on the module and the silicon FET blocks the drain voltage, the

V_GSof the GaN device decreases until the GaN device passes the threshold voltage. Then, the GaN device is

turned off and blocks the remaining major part of drain voltage. There is an internal clamp to make sure that the

V_DSdoes not exceed its maximum rating. This feature avoids the avalanche of the series Si FET when there is

no bias power.

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When LMG342xR030 is powered up with VDD bias power, the internal buck-boost converter generates a

negative voltage (V_VNEG) that is sufficient to directly turn off the GaN device. In this case, the series Si FET is

held on and the GaN device is gated directly with the negative voltage. During operation, this action removes the

switching loss of the series Si FET.

9.3.3 Drain-Source Voltage Capability

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware

that the headline drain-source voltage cannot be used as an equivalent point to compare devices across

technologies. The headline drain-source voltage of a silicon FET is set by the avalanche breakdown voltage.

The headline drain-source voltage of a GaN FET is set by the long term reliability with respect to data sheet

specifications.

Exceeding the headline drain-source voltage of a silicon FET can lead to immediate and permanent damage.

Meanwhile, the breakdown voltage of a GaN FET is much higher than the headline drain-source voltage. For

example, the breakdown voltage of the LMG342xR030 is more than 800 V.

A silicon FET is usually the weakest link in a power application during an input voltage surge. Surge protection

circuits must be carefully designed to ensure the silicon FET avalanche capability is not exceeded because it

is not feasible to clamp the surge below the silicon FET breakdown voltage. Meanwhile, it is easy to clamp the

surge voltage below a GaN FET breakdown voltage. In fact, a GaN FET can continue switching during the surge

event which means output power is safe from interruption.

The LMG342xR030 drain-source capability is explained with the assistance of Figure 9-1. The figure shows the

drain-source voltage versus time for a GaN FET for a single switch cycle in a switching application. No claim is

made about the switching frequency or duty cycle.

V_DS(tr)

V_DS(off)

V_{DS(switching)}

t₀t₁

t₂

Figure 9-1. Drain-Source Voltage Switching Cycle

The waveform starts before t₀with the FET in the on state. At t₀the GaN FET turns off and parasitic elements

cause the drain-source voltage to ring at a high frequency. The peak ring voltage is designated V_DS(tr). The

high frequency ringing has damped out by t₁. Between t₁and t₂the FET drain-source voltage is set by

the characteristic response of the switching application. The characteristic is shown as a flat line, but other

responses are possible. The voltage between t₁and t₂is designated V_DS(off). At t₂the GaN FET is turned on at

a non-zero drain-source voltage. The drain-source voltage at t₂is designated V_{DS(switching)}. Unique V_DS(tr), V_DS(off)

and V_{DS(switching)}parameters are shown because each can contribute to stress over the lifetime of the GaN FET.

The LMG342xR030 drain-source surge voltage capability is seen with the absolute maximum ratings V_{DS(tr)(surge)}

and V_DS(surge)in Absolute Maximum Ratings where V_{DS(tr)(surge)}maps to V_DS(tr)in Figure 9-1 and V_DS(surge)maps

to both V_DS(off)and V_{DS(switching)}in Figure 9-1. More information about the surge capability of TI GaN FETs is

found in A New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-conditions.

9.3.4 Internal Buck-Boost DC-DC Converter

An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the

GaN device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal

operation, the converter remains in discontinuous-conduction mode, but can enter continuous-conduction mode

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during start-up and overload the conditions. The converter is controlled internally and requires only a single

surface-mount inductor and output bypass capacitor.

The LMG342xR030 supports the GaN operation up to 2.2 MHz. As power consumption is very different in a

wide switching frequency range enabled by the GaN device, two peak current limits are used to control the

buck-boost converter. The two ranges are separated by IN positive-going threshold frequency. When switching

frequency is in the lower range, the peak current is set to the lower value (around 0.4 A) so a smaller inductor

can be selected. When switching frequency is in the higher range, the peak current is raised to the higher value

(around 1 A) and requires a larger inductor. There is a filter on this frequency detection logic, therefore the

LMG342xR030 requires five consecutive cycles at the higher frequency before it is set to the higher buck-boost

peak current limit. The current limit does not go down again until power off after the higher limit is set. Even if the

switching frequency returns to the lower range, the current limit does not decrease to the lower limit.

9.3.5 VDD Bias Supply

Wide VDD voltage ranges from 7.5 V to 18 V are supported by an internal LDO which regulates supplies

the internal low voltage and buck-boost converter circuits. If the VDD input voltage is less than 9 V, then the

maximum switching frequency is de-rated. TI recommends to use a 12-V unregulated power supply to supply

VDD, otherwise no external LDO is needed.

9.3.6 Auxiliary LDO

There is a 5-V voltage regulator inside the part used to supply external loads, such as digital isolators for the

high-side drive signal. The digital outputs of the part use this rail as their supply. No capacitor is required for

stability, but transient response is poor if no external capacitor is provided. If the application uses this rail to

supply external circuits, TI recommends to have a capacitor of at least 0.1 μF for improved transient response.

A larger capacitor can be used for further transient response improvement. The decoupling capacitor used

here must be a low-ESR ceramic type. Capacitances above 0.47 μF will slow down the start-up time of the

LMG342xR030 due to the ramp-up time of the 5-V rail.

9.3.7 Fault Detection

The GaN power IC integrates overcurrent protection (OCP), short-circuit protection (SCP), overtemperature

protection (OTP) and undervoltage lockout (UVLO).

9.3.7.1 Overcurrent Protection and Short-Circuit Protection

There are two types of current faults which can be detected by the driver: overcurrent fault and short-circuit fault.

The overcurrent protection (OCP) circuit monitors drain current and compares that current signal with an

internally set limit. Upon detection of the overcurrent, the LMG342xR030 conducts cycle-by-cycle overcurrent

protection as shown in Figure 9-2. In this mode, the GaN device is shut off when overcurrent happens, but

the overcurrent signal clears after the input PWM goes low. In the next cycle, the GaN device can turn on as

normal. The cycle-by-cycle function can be used in cases where steady-state operation current is below the

OCP level but transient response can still reach current limit, while the circuit operation cannot be paused.

The cycle-by-cycle function also prevents the GaN device from overheating by overcurrent induced conduction

losses.

The short-circuit protection (SCP) monitors drain current and compares that current signal with a internally set

limit higher than that of OCP as shown in Figure 9-3. The short-circuit protection is designed to protect the GaN

device from high-current short-circuit fault. If a short-circuit fault is detected, the driver turn-off is intentionally

slowed down to obtain lower di/dt so that a lower overshoot voltage and ringing can be achieved during the

turn-off event. On detection of an overcurrent fault, LMG342xR030 latches off. This fast response circuit helps

protect the GaN device even under a hard short-circuit condition. In this protection, the GaN device is shut

off and held off until the fault is reset by either holding the IN pin low for a period of time defined in the

Specifications or removing power from VDD.

During OCP or SCP in a half bridge, after the current reaches the upper limit and the device is turned off by

protection, the PWM input of the device could still be high and the PWM input of the complementary device

could still be low. In this case, the load current can flow through the third quadrant of the complementary device

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with no synchronous rectification. The extra high negative voltage drop (–6 V to –8 V) from drain to source could

lead to high third-quadrant loss, similar to dead-time loss but for a longer time.

For safety considerations, OCP allows cycle-by-cycle operation while SCP latches the device until reset. By

reading the FAULT and OC pins, the exact current fault type can be determined. Refer to Fault Reporting for

detailed information.

I_T(OC)

Inductor current

V_SW

Input PWM

Figure 9-2. Cycle-by-Cycle OCP Operation

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t_off(SC)

t_off(OC)

I_T(SC)

I_T(OC)

I_D

IN

OC

Cycle by cycle OCP

Latched SCP

Figure 9-3. Overcurrent Detection vs Short-Circuit Detection

9.3.7.2 Overtemperature Shutdown

The LMG342xR030 implements two overtemperature-shutdown (OTSD) functions, the GaN OTSD and the

Driver OTSD. Two OTSD functions are needed to maximize device protection by sensing different locations in

the device and protecting against different thermal-fault scenarios.

The GaN OTSD senses the GaN FET temperature. The GaN FET can overheat from both first-quadrant current

and third-quadrant current. As explained in GaN FET Operation Definitions, a FET can prevent first-quadrant

current by going into the off-state but is unable to prevent third-quadrant current. FET third-quadrant losses are

a function of the FET technology, current magnitude, and if the FET is operating in the on-state or off-state.

As explained in GaN FET Operation Definitions, the LMG342xR030 has much higher GaN FET third-quadrant

losses in the off-state.

When the GaN FET is too hot, the best protection is to turn off the GaN FET when first-quadrant current tries

to flow and turn on the GaN FET when third-quadrant current is flowing. This type of FET control is known

as ideal-diode mode (IDM). When the GaN OTSD trip point is exceeded, the GaN OTSD puts the GaN FET

into overtemperature-shutdown ideal-diode mode (OTSD-IDM) operation to achieve this optimum protection.

OTSD-IDM is explained in Ideal-Diode Mode Operation.

The Driver OTSD senses the integrated driver temperature and trips at a higher temperature compared to the

GaN OTSD. This second OTSD function exists to protect the LMG342xR030 from driver thermal-fault events

while allowing sufficient temperature difference for OTSD-IDM to operate. These driver thermal events include

shorts on the LD05V, BBSW, and VNEG device pins. When the Driver OTSD trip point is exceeded, the Driver

OTSD shuts off the LDO5V regulator, the VNEG buck-boost converter, and the GaN FET. Note that OTSD-IDM

does not function in Driver OTSD. This is why the Driver OTSD must trip higher than the GaN OTSD function.

Otherwise, GaN FET third-quadrant overheating cannot be addressed.

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Besides the temperature difference in the GaN OTSD and Driver OTSD trip points, further temperature

separation is obtained due to the thermal gradient difference between the GaN OTSD and Driver OTSD sense

points. The GaN OTSD sensor is typically at least 20°C hotter than the driver OTSD sensor when the device is in

GaN OTSD due to GaN FET power dissipation.

The FAULT pin is asserted for either or both the GaN OTSD state and the Driver OTSD state. FAULT de-asserts

and the device automatically returns to normal operation after both the GaN OTSD and Driver OTSD fall below

their negative-going trip points. During cool down, when the device exits the Driver OTSD state but is still in the

GaN OTSD state, the device automatically resumes OTSD-IDM operation.

9.3.7.3 UVLO Protection

The LMG342xR030 supports a wide range of VDD voltages. However, when the device is below UVLO

threshold, the GaN device stops switching and is held off. The FAULT pin is pulled low as an indication of

UVLO. The LDO is turned on by the rising-edge of the VIN UVLO and shuts off around 5 V to 6 V.

9.3.7.4 Fault Reporting

The FAULT and OC outputs form a fault reporting scheme together. The FAULT and OC outputs are both

push-pull outputs indicating the readiness and fault status of the driver. These two pins are logic high in normal

operation, and change logic according to Table 9-1.

Table 9-1. Fault Types and Reporting

NORMAL

UVLO, OT, and RDRV-OPEN

OVERCURRENT

SHORT-CIRCUIT

FAULT

OC

1

0

1

0

FAULT is held low when starting up until the series Si FET is turned on. During operation, if the power supplies

go below the UVLO thresholds or the device temperature go above the OT thresholds, power device is disabled

and FAULT is held low until a fault condition is no longer detected. If RDRV is open, FAULT is also held low.

In a short-circuit or overtemperature fault condition, FAULT is held low until the fault latches are reset or fault is

cleared. The OC pin is held low if there is a short-circuit or overcurrent fault. The signals help notify the controller

the exact type of faults by reading the truth table. If a combined reporting of the faults on a single pin is desired,

one can short the OC pin to ground during power up. All faults assert the FAULT pin then and the OC pin is not

used. Please note: internal protection happens regardless of the connection of the pin outputs, which means that

the protection features continue to operate even if fault reporting is ignored..

9.3.8 Drive Strength Adjustment

The LMG342xR030 allows users to adjust the drive strength of the device and obtain a desired slew rate, which

provides flexibility when optimizing switching losses and noise coupling.

To adjust drive strength, a resistor can be placed between the RDRV pin and GND pin. The resistance

determines the slew rate of the device, from 30 V/ns to 150 V/ns, during turn-on. On the other hand, there

are two dv/dt values that can be selected without the resistor: shorting the RDRV pin to ground sets the slew rate

to 150 V/ns, and shorting the RDRV pin to LDO5V sets the slew rate to 100 V/ns. The device detects the short

to LDO5V one time at power up. Once the short to LDO5V condition is detected, the device no longer monitors

the RDRV pin. Otherwise, the RDRV pin is continuously monitored and the dv/dt setting can be changed by

modulating the resistance during device operation. The modulation must be fairly slow since there is there is

significant internal filtering to reject switching noise.

9.3.9 Temperature-Sensing Output

The integrated driver senses the GaN die temperature and outputs the information through a modulated PWM

signal on the TEMP pin. The typical PWM frequency is 9 kHz with the same refresh rate. The minimum PWM

duty cycle is around 1%, which can be observed at temperature below 25°C. The target temperature range is

from 25°C to 150°C, and the corresponding PWM duty cycle is typically from 3% to 82%. At temperatures above

150°C, the duty cycle continues to increase linearly until overtemperature fault happens. When overtemperature

happens, the TEMP pin is pulled high to indicate this fault until the temperature is reduced to the normal range.

There is a hysteresis to clear overtemperature fault.

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9.3.10 Ideal-Diode Mode Operation

Off-state FETs act like diodes by blocking current in one direction (first quadrant) and allowing current in the

other direction (third quadrant) with a corresponding diode like voltage drop. FETs, though, can also conduct

third-quadrant current in the on-state at a significantly lower voltage drop. Ideal-diode mode (IDM) is when an

FET is controlled to block first-quadrant current by going to the off-state and conduct third-quadrant current by

going to the on-state, thus achieving an ideal lower voltage drop.

FET off-state third-quadrant current flow is commonly seen in power converters, both in normal and fault

situations. As explained in GaN FET Operation Definitions, GaN FETs do not have an intrinsic p-n junction

body diode to conduct off-state third-quadrant current. Instead, the off-state third-quadrant voltage drop for the

LMG342xR030 is several times higher than a p-n junction voltage drop, which can impact efficiency in normal

operation and device ruggedness in fault conditions.

To mitigate efficiency degradation, the LMG3425R030 implements an operational ideal-diode mode (OP-IDM)

function. Meanwhile, to improve device ruggedness in a GaN FET overtemperature fault situation, all devices

in the LMG342xR030 family implement a GaN FET overtemperature-shutdown ideal-diode mode (OTSD-IDM)

function as referenced in Overtemperature Shutdown. Both OP-IDM and OTSD-IDM are described in more detail

below.

Operational Ideal-Diode Mode (LMG3425R030)

Operational ideal-diode mode (OP-IDM) is implemented in the LMG3425R030 but not in the LMG3422R030.

Understand that the OP-IDM function is not a general-purpose ideal-diode mode function which allows the

LMG342xR030 to autonomously operate as a diode, including as an autonomous synchronous rectifier.

Furthermore, the OP-IDM function is not intended to support an ideal-diode mode transition from the on-state to

the off-state in a high-voltage, hard-switched application. Exposing the LMG342xR030 to this situation is akin to

operating a half-bridge power stage with negative dead time with corresponding high shoot-through current.

Instead, as described below, the LMG342xR030 OP-IDM function is narrowly implemented to address a specific

off-state third-quadrant current flow situation while minimizing situations where the ideal-diode mode can create

a dangerous shoot-through current event.

OP-IDM is intended to minimize GaN FET off-state third-quadrant losses that occur in a zero-voltage switched

(ZVS) event. ZVS events are seen in applications such as synchronous rectifiers and LLC converters. The ZVS

event occurs at the FET off-state to on-state transition when an inductive element discharges the FET drain

voltage before the FET is turned-on. The discharge ends with the inductive element pulling the FET drain-source

voltage negative and the FET conducting off-state third-quadrant current.

Power supply controllers use dead-time control to set the time for the ZVS event to complete before turning

on the FET. Both the ZVS time and resulting FET off-state third-quadrant current are a function of the power

converter operation. Long ZVS time and low third-quadrant current occur when the inductive element is slewing

the FET with low current and short ZVS time and high third-quadrant current occur when the inductive element

is slewing at the FET with high current. Sophisticated controllers optimally adjust the dead time to minimize

third-quadrant losses. Simpler controllers use a fixed dead time to handle the longest possible ZVS time.

Thus, in a fixed dead-time application, the highest possible off-state third-quadrant losses occur for the longest

possible time.

OP-IDM mitigates the losses in a fixed dead-time application by automatically turning on the GaN FET as soon

as third-quadrant current is detected. In this sense, OP-IDM can be described as providing a turn-on assist

function with optimum dead-time control. Meanwhile, OP-IDM is not intended to be used to turn-off the GaN

FET in normal operation. OP-IDM turnoff capability is only provided as a protection mechanism to guard against

shoot-through current.

OP-IDM works within the confines of normal LMG342xR030 switching operation as controlled by the IN pin.

The key consideration for the OP-IDM operation is to ensure the turn-on assist function is only activated on

the ZVS edge. For example, third-quadrant current is seen in a LMG342xR030 used as a synchronous rectifier

both before the IN pin goes high to turn on the GaN FET and after the IN pin goes low to turn off the GaN

FET. OP-IDM turns on the GaN FET before the IN pin goes high when OP-IDM detects third-quadrant current.

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But it would be a mistake for OP-IDM to turn the GaN FET back on right after IN has turned it off because

OP-IDM detects third-quadrant current. If OP-IDM were to turn on the GaN FET in this situation, it would create

a shoot-through current event when the opposite-side power switch turns on. OP-IDM avoids this shoot-through

current problem on the turn-off edge by requiring the drain voltage to first go positive before looking for the ZVS

event.

The OP-IDM state machine is shown in Figure 9-4. Each state is assigned a state number in the upper right side

of the state box.

IN low

1

5

FET OFF

FET ON

OP-IDM looking for

positive V_DS

OP-IDM idle

IN high

Positive V_DS

IN high

4

2

3

FET OFF

FET ON

FET Off

OP-IDM looking for

negative V_DS

OP-IDM looking for first-

quadrant drain current

First-quadrant drain

current

Negative V_DSdue to

third-quadrant drain

current

OP-IDM locks FET off

Power

Up

Exit OTSD

Figure 9-4. Operational Ideal-Diode Mode (OP-IDM) State Machine

1. A new OP-IDM cycle begins in OP-IDM state #1 after the IN pin goes low in OP-IDM state #5. OP-IDM turns

off the GaN FET in OP-IDM state #1. OP-IDM monitors the GaN FET drain voltage, looking for a positive

drain voltage to know it can now start looking for a ZVS event. After a positive GaN FET drain voltage is

detected, the device moves to OP-IDM state #2.

2. OP-IDM keeps the GaN FET off in OP-IDM state #2. OP-IDM continues monitoring the GaN FET drain

voltage. But this time it is looking for a negative drain voltage which means third-quadrant current is flowing

after a ZVS event. This is also the starting state when the device powers up or exits OTSD. After a negative

GaN FET drain voltage is detected, the device moves to OP-IDM state #3.

3. OP-IDM turns on the GaN FET in OP-IDM state #3. OP-IDM monitors the drain current in this state. Ideally,

the device simply stays in this state until IN goes high. The drain current is monitored to protect against

an unexpected shoot-through current event. If first-quadrant drain current is detected, the device moves to

OP-IDM state #4.

4. OP-IDM locks the GaN FET off in OP-IDM state #4. The GaN FET only turns back on when the IN pin goes

high.

5. The device moves to OP-IDM state #5 from any other state when the IN pin goes high. The GaN FET is

commanded on in OP-IDM state #5. OP-IDM is idle in this state. A new OP-IDM switching cycle begins when

IN goes low moving the device into OP-IDM state #1.

OP-IDM can only turn on the GaN FET after per IN cycle. If an unexpected shoot-through current is detected

between OP-IDM turning in the GaN FET and the IN pin going high, OP-IDM locks the GaN FET off for the

remainder of the IN cycle.

Understand that the OP-IDM function turns on the GaN FET, after IN goes low, if it sees a positive drain voltage

followed by a negative drain voltage. A design using the LMG3425R030 must be analyzed for any situations

where this sequence of events creates a shoot-through current event. The analysis must include all power

system corner cases including start-up, shutdown, no load, overload, and fault events. Note that discontinuous

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mode conduction (DCM) operation can easily create an OP-IDM shoot-through current event when the ringing at

the end of a DCM cycle triggers OP-IDM to turn on the GaN FET.

Overtemperature-Shutdown Ideal-Diode Mode

Overtemperature-shutdown ideal-diode mode (OTSD-IDM) is implemented in all devices in the LMG342xR030

family. As explained in Overtemperature Shutdown, ideal-diode mode provides the best GaN FET protection

when the GaN FET is overheating.

OTSD-IDM accounts for all, some, or none of the power system operating when OTSD-IDM is protecting the

GaN FET. The power system may not have the capability to shut itself down, in response to the LMG342xR030

asserting the FAULT pin in a GaN OTSD event, and just continue to try to operate. Parts of the power system

can stop operating due to any reason such as a controller software bug or a solder joint breaking or a device

shutting off to protect itself. At the moment of power system shutdown, the power system stops providing gate

drive signals but the inductive elements continue to force current flow while they discharge.

The OTSD-IDM state machine is shown in Figure 9-5. Each state is assigned a state number in the upper right

side of the state box. The OTSD-IDM state machine has a similar structure to the OP-IDM state machine. Similar

states use the same state number.

1

IN falling edge from

any OTSD-IDM State

FET OFF

OTSD-IDM waiting for IN

falling-edge blank time to

expire

IN falling-edge blank

time expired

First-quadrant drain

current

2

3

FET OFF

FET ON

OTSD-IDM looking for negative

V_DS

OTSD-IDM looking for first-

quadrant drain current

Negative V_DSdue to

third-quadrant drain

current

Enter OTSD

Figure 9-5. Overtemperature-Shutdown Ideal-Diode Mode (OTSD-IDM) State Machine

1. The LMG342xR030 GaN FET always goes to state #1 if a falling edge is detected on the IN pin. OTSD-IDM

turns off the GaN FET in OTSD-IDM state #1. OTSD-IDM is waiting for the IN falling edge blank time to

expire. This time gives the opposite-side FET time to switch to create a positive drain voltage. After the blank

time expires, the device moves to OTSD-IDM state #2.

2. OTSD-IDM keeps the GaN FET off it is coming from OTSD-IDM state #2 and turns the GaN FET off if it is

coming from OTSD-IDM state #3. OTSD-IDM is monitoring the GaN FET drain voltage in OP-IDM state #2. It

is looking for a negative drain voltage which means third-quadrant current is flowing. This is also the starting

state when the device enters OTSD. After a negative GaN FET drain voltage is detected, the device moves

to OTSD-IDM state #3

3. OP-IDM turns on the GaN FET in OTSD-IDM state #3. OP-IDM monitors the drain current in this state. If

first-quadrant drain current is detected, the device moves to OP-IDM state #3.

State #1 is only used if the IN signal continues to switch. State #1 is used to protect against shoot-through

current in a similar manner to OP-IDM state #1. The difference is that state #1 in the OTSD-IDM state machine

simply waits for a fixed time period before proceeding to state #2. The fixed time period is to give the opposite-

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side switch time to switch and create a positive drain voltage. A fixed time is used to avoid a stuck condition for

cases where a positive drain voltage is not created.

If there is no IN signal, the state machine only moves between states #2 and #3 as a classic ideal-diode

mode state machine. This allows all the inductive elements to discharge, when the power system shuts off, with

minimum discharge stress created in the GaN FET.

Note that the OTSD-IDM state machine has no protection against repetitive shoot-through current event. There

are degenerate cases, such as the LMG342xR030 losing its IN signal during converter operation, which can

expose the OTSD-IDM to repetitive shoot-through current events. There is no good solution in this scenario. If

OTSD-IDM did not allow repeated shoot-thru current events, the GaN FET is instead be exposed to excessive

off-state third-quadrant losses.

9.4 Device Functional Modes

The device has one mode of operation that applies when operated within the Recommended Operating

Conditions.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The LMG342xR030 is a power IC targeting hard-switching and soft-switching applications operating up to

480V bus voltages. GaN devices offer zero reverse-recovery charge enabling high-frequency, hard-switching in

applications like the totem-pole PFC. Low Q_ossof GaN devices also benefits soft-switching converters, such as

the LLC and phase-shifted full-bridge configurations. As half-bridge configurations are the foundation of the two

mentioned applications and many others, this section describes how to use the LMG342xR030 in a half-bridge

configuration.

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10.2.1 Design Requirements

This design example is for a hard-switched boost converter which is representative of PFC applications. Table

10-1 shows the system parameters for this design.

Table 10-1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

200 VDC

400 VDC

20 A

Output voltage

Input (inductor) current

Switching frequency

100 kHz

10.2.2 Detailed Design Procedure

In high-voltage power converters, circuit design and PCB layout are essential for high-performance power

converters. As designing a power converter is out of the scope of this document, this data sheet describes how

to build well-behaved half-bridge configurations with the LMG342xR030.

10.2.2.1 Slew Rate Selection

The slew rate of LMG342xR030 can be adjusted between approximately 20 V/ns and 150 V/ns by connecting a

resistor, R_DRV, from the RDRV pin to GND. The slew rate affects GaN device performance in terms of:

•

Switching loss

Voltage overshoot

Noise coupling

EMI emission

Generally, high slew rates provide low switching loss, but high slew rates can also create higher voltage

overshoot, noise coupling, and EMI emissions. Following the design recommendations in this data sheet helps

mitigate the challenges caused by a high slew rate. The LMG342xR030 offers circuit designers the flexibility to

select the proper slew rate for the best performance of their applications.

10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply

Using a bootstrap supply introduces additional constraints on the start-up of the high-side LMG342xR030. Prior

to powering up, the GaN device operates in cascode mode with reduced performance. In some circuits, a proper

slew rate can be required for the start-up of a bootstrap-supplied half-bridge configuration.

10.2.2.2 Signal Level-Shifting

In half-bridges, high-voltage level shifters or digital isolators must be used to provide isolation for signal paths

between the high-side device and control circuit. Using an isolator is optional for the low-side device. However,

using and isolator equalizes the propagation delays between the high-side and low-side signal paths, and

provides the ability to use different grounds for the GaN device and the controller. If an isolator is not used on

the low-side device, the control ground and the power ground must be connected at the device and nowhere

else on the board. For more information, see Layout Guidelines. With fast-switching devices, common ground

inductance can easily cause noise issues without the use of an isolator.

Choosing a digital isolator for level-shifting is important for improvement of noise immunity. As GaN device

can easily create high dv/dt, > 50 V/ns, in hard-switching applications, TI highly recommends to use isolators

with high common-mode transient immunity (CMTI). Isolators with low CMTI can easily generate false signals,

which could cause shoot-through. Additionally, TI strongly encourages to select isolators which are not edge-

triggered. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states and cause circuit

malfunction.

Generally, ON/OFF keyed isolators are preferred, such as the TI ISO77xxF series, as a high CMTI event would

only cause a very short false pulse, a few nanoseconds, which can be filtered out. To filter these false pulses, TI

recommends a low pass filter, like 1 kΩ and 22 pF R-C filter, to be placed at the driver input.

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10.2.2.3 Buck-Boost Converter Design

The buck-boost converter generates the negative voltage to turn off the direct-drive GaN device. While the

buck-boost converter is controlled internally, it requires an external power inductor and output capacitor. The

converter is designed to use a 4.7-µH inductor and a 2.2-µF output capacitor.

As the peak current of the buck-boost is subject to two different peak current limits which are 0.4 A and 1 A

for low and high frequency operation (see Internal Buck-Boost DC-DC Converter), so the inductor must have a

saturation current well above the rated peak current limit. After the higher limit is established by switching at a

higher frequency, the current limit does not go back to the lower level even when GaN device is then switched

at a lower frequency. Therefore, select an inductor according to the higher 1-A limit if higher frequency GaN

operation is anticipated.

The buck-boost converter uses a peak current hysteretic control. As shown in Figure 10-2, the inductor current

increases at the beginning of a switching cycle until the inductor reaches the peak current limit. The inductor

current goes down to zero. The idle time between each current pulse is determined automatically by the output

current, and can be reduced to zero. Therefore, the maximum output current happens when the idle time is zero,

and is decided by the peak current but independent of the inductor value.

A minimum inductance value of 3 µH is preferred for the buck-boost converter so that the di/dt across the

inductor is not too high. This leaves enough margin for the control loop to respond. As a result, the maximum

di/dt of the inductor is limited to 6 A/µs. On the other hand, large inductance also limits the transient response for

stable output voltage, and it is preferred to have inductors less than 10 µH.

V_{NEG_avg}

ûV_NEG

V_NEG

I_DCDC,PK

Smaller

inductor

Larger

inductor

Idle time

Buck-boost

inductor current

1/(buck-boost frequency)

Figure 10-2. Buck-Boost Converter Inductor Current

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10.2.3 Application Curves

V_DS(50 V/div)

I_D(2.5 A/div)

V_DS(50 V/div)

I_D(1.25 A/div)

V_OUT= 400V

I_L= 5 A

R_DRV= 40 kW

V_BUS= 400 V

I_L= 5 A

R_DRV= 40 kW

Time (5 ns/div)

D006

D007

Figure 10-3. Turn-On Waveform in Application

Example

Figure 10-4. Turn-Off Waveform in Application

Example

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10.3 Do's and Don'ts

The successful use of GaN devices in general, and LMG342xR030 in particular, depends on proper use of the

device. When using the LMG342xR030, DO:

•

Read and fully understand the data sheet, including the application notes and layout recommendations.

Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance.

Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance.

Use the proper size decoupling capacitors and locate them close to the IC as described in Layout Guidelines.

Use a signal isolator to supply the input signal for the low-side device. If not, ensure the signal source is

connected to the signal GND plane which is tied to the power source only at the LMG342xR030 IC.

Use the FAULT pin to determine power-up state and to detect overcurrent and overtemperature events and

safely shut off the converter.

•

To avoid issues in your system when using the LMG342xR030, DON'T:

•

Use a single-layer or two-layer PCB for the LMG342xR030 as the power-loop and bypass capacitor

inductances is excessive and prevent proper operation of the IC.

•

Reduce the bypass capacitor values below the recommended values.

Allow the device to experience drain transients above 600 V as they can damage the device.

Allow significant third-quadrant conduction when the device is OFF or unpowered, which can cause

overheating. Self-protection features cannot protect the device in this mode of operation.

Ignore the FAULT pin output.

•

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11 Power Supply Recommendations

The LMG342xR030 only requires an unregulated 12-V supply. The low-side supply can be obtained from the

local controller supply. The supply of the high-side device must come from an isolated supply or a bootstrap

supply.

11.1 Using an Isolated Power Supply

Using an isolated power supply to power the high-side device has the advantage that it works regardless of

continued power-stage switching or duty cycle. Using an isolated power supply can also power the high-side

device before power-stage switching begins, eliminating the power-loss concern of switching with an unpowered

LMG342xR030 (see Start-Up and Slew Rate With Bootstrap High-Side Supply for details). Finally, a properly-

selected isolated supply introduces less parasitics and reduces noise coupling.

The isolated supply can be obtained with a push-pull converter, a flyback converter, a FlyBuck^™converter, or

an isolated power module. When using an unregulated supply, the input of LMG342xR030 must not exceed

the maximum supply voltage. A 16-V TVS diode can be used to clamp the VDD voltage of LMG342xR030 for

additional protection. Minimizing the inter-winding capacitance of the isolated power supply or transformer is

necessary to reduce switching loss in hard-switched applications. Furthermore, capacitance across the isolated

bias supply inject high currents into the signal-ground of the LMG342xR030 and can cause problematic ground-

bounce transients. A common-mode choke can alleviate most of these issues.

11.2 Using a Bootstrap Diode

In half-bridge configuration, a floating supply is necessary for the high-side device. To obtain the best

performance of LMG342xR030, Ti highly recommends Using an Isolated Power Supply. A bootstrap supply

can be used with the recommendations of this section.

In applications like a boost converter, the low side LMG342xR030 always start switching while high side

LMG342xR030 is unpowered. If the low side is adjusted to achieve very high slew rate before the high side

bias is fully settled, there can be unintentional turn-on at the high side due to parasitic coupling at high slew rate.

The start-up slew rate must be slowed down to 30 V/ns by changing the resistance of RDRV pin of the low side.

This slow down can be achieved by controlling the low side RDRV resistance with the high side FAULT as given

in Figure 10-1.

11.2.1 Diode Selection

The LMG342xR030 offers no reverse-recovery charge and very limited output charge. Hard-switching circuits

using the LMG342xR030 also exhibit high voltage slew rates. A compatible bootstrap diode must not introduce

high output charge and reverse-recovery charge.

A silicon carbide diode, like the GB01SLT06-214, can be used to avoid reverse-recovery effects. The SiC diode

has an output charge of 3 nC. Althought there is additional loss from its output charge, it does not dominate the

losses of the switching stage.

11.2.2 Managing the Bootstrap Voltage

In a synchronous buck or other converter where the low-side switch occasionally operates in third-quadrant,

the bootstrap supply charges through a path that includes the third-quadrant voltage drop of the low-side

LMG342xR030 during the dead time as shown in Figure 11-1. This third-quadrant drop can be large, which can

over-charge the bootstrap supply in certain conditions. The V_DDsupply of LMG342xR030 must be kept below 18

V.

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DRAIN

V_DD

V_F

SOURCE

+

œ

DRAIN

V_DD

V_F

SOURCE

Figure 11-1. Charging Path for Bootstrap Diode

As shown in Figure 11-2, the recommended bootstrap supply includes a bootstrap diode, a series resistor,

and a 16-V TVS or zener diode in parallel with the V_DDbypass capacitor to prevent damaging the high-side

LMG342xR030. The series resistor limits the charging current at start-up and when the low-side device

is operating in third-quadrant mode. This resistor must be selected to allow sufficient current to power

the LMG342xR030 at the desired operating frequency. At 100-kHz operation, TI recommends a value of

approximately 2 Ω . At higher frequencies, this resistor value must be reduced or the resistor omitted entirely to

ensure sufficient supply current.

DRAIN

+12 V

V_DD

V_F

SOURCE

Figure 11-2. Suggested Bootstrap Regulation Circuit

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12 Layout

12.1 Layout Guidelines

The layout of the LMG342xR030 is critical to its performance and functionality. Because the half-bridge

configuration is typically used with these GaN devices, layout recommendations are considered with this

configuration. A four-layer or higher layer count board is required to reduce the parasitic inductances of the

layout to achieve suitable performance.

12.1.1 Solder-Joint Reliability

Large QFN packages can experience high solder-joint stress. TI recommends several best practices to ensure

solder-joint reliability. First, the instructions for the NC1 and NC2 anchor pins found in Table 6-1 must be

followed. Second, all the LMG342xR030 board solder pads must be non-solder-mask defined (NSMD) as shown

in the land pattern example in Mechanical, Packaging, and Orderable Information. Finally, any board trace

connected to an NSMD pad must be less than 2/3 the width of the pad on the pad side where it is connected.

The trace must maintain this 2/3 width limit for as long as it is not covered by solder mask. After the trace is

under solder mask, there are no limits on the trace dimensions. All these recommendations are followed in the

Layout Example.

12.1.2 Power-Loop Inductance

The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes

high di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic

interference (EMI) can be reduced, as well as reducing voltage stress on the devices.

Place the power devices as close as possible to minimize the power-loop inductance. The decoupling capacitors

are positioned in line with the two devices. They can be placed close to either device. In Layout Examples,

the decoupling capacitors are placed on the same layer as the devices. The return path (PGND in this case)

is located on second layer in close proximity to the top layer. By using inner layer and not bottom layer, the

vertical dimension of the loop is reduced, thus minimizing inductance. A large number of vias near both the

device terminal and bus capacitance carries the high-frequency switching current to inner layer while minimizing

impedance.

12.1.3 Signal-Ground Connection

The LMG342xR030's SOURCE pin is internally connected to GND pins of the power IC, the signal-ground

reference. Local signal-ground planes must be connected to GND pins with low impedance star connection. In

addition, the return path for the passives associated to the driver (for example, bypass capacitance) must be

connected to the GND pins. In Layout Example, local signal-ground planes are located on second layer to act

as the return path for the local circuitry. The local signal-ground planes are not connected to the high-current

SOURCE pins except the star connection at GND pins.

12.1.4 Bypass Capacitors

The gate drive loop impedance must be minimized to obtain good performance. Although the gate driver is

integrated on package, the bypass capacitance for the driver is placed externally. As the GaN device is turned

off to a negative voltage, the impedance of the path to the external VNEG capacitor is included in the gate drive

loop. The VNEG capacitor must be placed close to VNEG and GND pins.

The VDD pin bypass capacitors, C1 and C11, must also be placed close to the VDD pin with low impedance

connections.

12.1.5 Switch-Node Capacitance

GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching

losses. To preserve this low switching losses, additional capacitance added to the output node must be

minimized. The PCB capacitance at the switch node can be minimized by following these guidelines:

•

Minimize overlap between the switch-node plane and other power and ground planes.

Make the GND return path under the high-side device thinner while still maintaining a low-inductance path.

Choose high-side isolator ICs and bootstrap diodes with low capacitance.

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•

Place the power inductor as close to the GaN device as possible.

Power inductors must be constructed with a single-layer winding to minimize intra-winding capacitance.

If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and

the GaN device to effectively shield the GaN device from the additional capacitance.

If a back-side heat-sink is used, use the least amount of area of the switch-node copper coverage on the

bottom copper layer to improve the thermal dissipation.

•

12.1.6 Signal Integrity

The control signals to the LMG342xR030 must be protected from the high dv/dt caused by fast switching.

Coupling between the control signals and the drain can cause circuit instability and potential destruction. Route

the control signals (IN, FAULT and OC) over a ground plane placed on an adjacent layer. In Layout Example, for

example, all the signals are routed on layers close to the local signal ground plane.

Capacitive coupling between the traces for the high-side device and the static planes, such as PGND and

HVBUS, could cause common mode current and ground bounce. The coupling can be mitigated by reducing

overlap between the high-side traces and the static planes. For the high-side level shifter, ensure no copper from

either the input or output side extends beneath the isolator or the CMTI of the device can be compromised.

12.1.7 High-Voltage Spacing

Circuits using the LMG342xR030 involve high voltage, potentially up to 600 V. When laying out circuits using

the LMG342xR030, understand the creepage and clearance requirements for the application and how they

apply to the GaN device. Functional (or working) isolation is required between the source and drain of each

transistor, and between the high-voltage power supply and ground. Functional isolation or perhaps stronger

isolation (such as reinforced isolation) can be required between the input circuitry to the LMG342xR030 and the

power controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet your

isolation requirements.

If a heat sink is used to manage thermal dissipation of the LMG342xR030, ensure necessary electrical isolation

and mechanical spacing is maintained between the heat sink and the PCB.

12.1.8 Thermal Recommendations

The LMG342xR030 is a lateral device grown on a Si substrate. The thermal pad is connected to the source

of device. The LMG342xR030 can be used in applications with significant power dissipation, for example,

hard-switched power converters. In these converters, cooling using just the PCB can not be sufficient to keep the

part at a reasonable temperature. To improve the thermal dissipation of the part, TI recommends a heat sink is

connected to the back of the PCB to extract additional heat. Using power planes and numerous thermal vias, the

heat dissipated in the LMG342xR030 can be spread out in the PCB and effectively passed to the other side of

the PCB. A heat sink can be applied to bare areas on the back of the PCB using an thermal interface material

(TIM). The solder mask from the back of the board underneath the heat sink can be removed for more effective

heat removal.

Refer to the High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note for more

recommendations and performance data on thermal layouts.

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12.2 Layout Examples

Correct layout of the LMG342xR030 and its surrounding components is essential for correct operation. The

layouts shown here reflect the GaN device schematic in Figure 10-1 . These layouts are shown to produce

good results and is intended as a guideline. However, it can be possible to obtain acceptable performance with

alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and

Orderable Information for the latest recommended PCB footprint of the device.

The the top-layer layout and mid-layer layout are shown. The layouts are zoomed in to the LMG342xR030 U1

and U2 component placements. The mid-layer layout includes the outlines of the top level components to assist

the reader in lining up the top-layer and mid-layer layouts.

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Figure 12-1. Half-Bridge Top-Layer Layout

Figure 12-2. Half-Bridge Mid-Layer Layout

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

•

Texas Instruments, High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note.

Texas Instruments, A New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-

conditions.

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

FlyBuck^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

13.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RQZ0054A-C01

VQFN - 1 mm max height

S

C

A

L

E

1

.

1

0

PLASTIC QUAD FLATPACK - NO LEAD

12.1

11.9

A

B

PIN 1 ID

INDEX AREA

12.1

11.9

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

7.8 0.1

PKG

(2.75)

0.65

0.55

54X

(2.65)

(0.1) TYP

27

17

4X 0.975

16

28

1.1

4X

1.0

0.1

C A B

C

10.2 0.1

2X 8.45

0.05

55

PKG SYMM

26X 0.65

PIN 1 ID

(45 X 0.3)

0.45

0.35

46X

0.1

C A B

C

0.05

43

1

54

44

4X (0.25)

0.65

0.55

4X

2X 1.285

4X (0.2)

0.1

C A B

16X 0.65

2X 5.2

0.05

C

4X 0.75

4228230/A 11/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RQZ0054A-C01

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(7.8)

(4.906)

(2.65)

(4.449) TYP

(0.914) TYP

54X (0.8)

54

44

(0.508) TYP

43

4X (1.05)

1

(

0.2) TYP

VIA

(4.572)

(4.826)

46X (0.4)

(10.2)

55

PKG SYMM

(11.6)

(R0.05) TYP

42X (0.65)

4X (0.975)

28

16

17

27

4X (0.75)

2X (2.035)

(1.25)

PAD

4X (0.6)

PKG

(11.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.07 MAX

ALL AROUND

METAL EDGE

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4228230/A 11/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. All pads must be NSMD for mechanical performance, refer to the device datasheet for trace connection recommendations to the pads.

6. Filling the thermal pad with thermal vias is recommended for thermal performance, refer to the device datasheet. Vias must be ﬁlled and

planarized.

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EXAMPLE STENCIL DESIGN

RQZ0054A-C01

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(4.225)

(1.19) TYP

50X (0.8)

54

4X (0.76)

44

1

43

4X (1)

48X ( 0.99)

(1.19) TYP

(4.165)

46X (0.4)

55

PKG SYMM

(11.6)

(R0.05) TYP

42X (0.65)

4X (0.975)

28

16

17

27

PKG

4X (0.6)

4X (0.75)

2X (2.035)

(11.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 1, 16, 28 & 43: 90%

PAD 55: 60%

SCALE:8X

4228230/A 11/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMG3422R030_V01
厂家：	TEXAS INSTRUMENTS
描述：	LMG342xR030 600-V 30-mÎ© GaN FET With Integrated Driver, Protection, and Temperature Reporting
文件：	总45页 (文件大小：1835K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMG3422R030_V01 [TI]

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