LMG3522R030RQSR_技术文档

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

LMG3522R030 650V 30mΩ 具有集成驱动器、保护和温度报告功能的GaN FET

1 特性

3 说明

• 具有集成栅极驱动器的650V GaN-on-Si FET

LMG3522R030 GaN FET 具有集成式驱动器和保护功

能，适用于开关模式电源转换器，可让设计人员实现更

高水平的功率密度和效率。

– 集成高精度栅极偏置电压

– 200V/ns FET 释抑

– 23.6MHz 开关频率

– 20V/ns 至150V/ns 压摆率，用于优化开关性能

和缓解EMI

LMG3522R030 集成了一个硅驱动器，可实现高达

150V/ns 的开关速度。与分立式硅栅极驱动器相比，TI

的集成式精密栅极偏置可实现更高的开关 SOA。这种

集成特性与 TI 的低电感封装技术相结合，可在硬开关

电源拓扑中提供干净的开关和超小的振铃。可调栅极驱

动强度允许将压摆率控制在20V/ns 至150V/ns 之间，

这可用于主动控制EMI 并优化开关性能。

– 在7.5V 至18V 电源下工作

• 强大的保护

– 响应时间少于100ns 的逐周期过流和锁存短路

保护

– 硬开关时可承受720V 浪涌

– 针对内部过热和UVLO 监控的自我保护

• 高级电源管理

高级电源管理功能包括数字温度报告和故障检测。

GaN FET 的温度通过可变占空比 PWM 输出进行报

告，这可简化器件加载管理。报告的故障包括过热、过

流和UVLO 监控。

– 数字温度PWM 输出

• 顶部冷却12mm × 12mm VQFN 封装将电气路径和

散热路径分开，可实现更低的电源环路电感

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

2 应用

LMG3522R030

VQFN (52)

12.00mm × 12.00mm

• 开关模式电源转换器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 商用网络和服务器PSU

• 商用通信电源整流器

• 光伏逆变器和工业电机驱动器

• 不间断电源

DRAIN

Direct-Drive

Slew

GaN

Rate

SOURCE

RDRV

IN

VDD

VNEG

LDO,

BB

OCP, SCP,

OTP, UVLO

Current

LDO5V

TEMP

FAULT

OC

SOURCE

高于100V/ns 时的开关性能

简化版方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNOSDF3

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

Table of Contents

8.4 Start Up Sequence....................................................24

8.5 Safe Operation Area (SOA)...................................... 25

8.6 Device Functional Modes..........................................25

9 Application and Implementation..................................26

9.1 Application Information............................................. 26

9.2 Typical Application.................................................... 27

9.3 Do's and Don'ts.........................................................31

9.4 Power Supply Recommendations.............................31

9.5 Layout....................................................................... 32

10 Device and Documentation Support..........................37

10.1 Documentation Support.......................................... 37

10.2 接收文档更新通知................................................... 37

10.3 支持资源..................................................................37

10.4 Trademarks.............................................................37

10.5 Electrostatic Discharge Caution..............................37

10.6 Export Control Notice..............................................37

10.7 术语表..................................................................... 37

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics............................................9

6.7 Typical Characteristics..............................................10

7 Parameter Measurement Information..........................12

7.1 Switching Parameters...............................................12

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................15

Information.................................................................... 37

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

November 2022

*

Initial release.

2

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

5 Pin Configuration and Functions

DRAIN

16

15 14

13 12 11 10

9

8

7

6

5

4

3

2

1

NC2

17

52

NC2

18

19

20

21

22

23

24

25

26

51

50

49

48

47

46

45

44

43

LDO5V

RDRV

TEMP

OC

THERMAL PAD

NC2

FAULT

IN

VDD

NC2

27

28 29

30 31 32 33 34 35 36 37

38 39 40 41

42

SOURCE

VNEG

图5-1. RQS Package 52-Pin VQFN (Top View)

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NC1

NO.

1, 16

2-15

Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are

non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally

connected to DRAIN.

—

DRAIN

NC2

P

GaN FET drain. Internally connected to NC1.

Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are

non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally

connected to SOURCE, and THERMAL PAD.

17, 27, 43, 47,

52

—

SOURCE

VNEG

18-26, 28-39

40, 41

P

GaN FET source. Internally connected to NC2, and THERMAL PAD.

Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN

FET. Bypass to SOURCE with a 2.2-µF capacitor.

BBSW

VDD

IN

42

44

45

46

P

I

Internal buck-boost converter switch pin. Connect an inductor from this point to SOURCE.

Device input supply.

CMOS-compatible non-inverting input used to turn the FET on and off.

Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.

FAULT

O

Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault

Detection for details.

OC

48

49

50

51

—

O

I

Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed

waveform. The device temperature is encoded as the duty cycle of the waveform.

TEMP

RDRV

LDO5V

Drive strength selection pin. Connect a resistor from this pin to SOURCE to set the turn-on drive strength to

control slew rate. Tie the pin to SOURCE to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.

5-V LDO output for external digital isolator. If using this externally, connect a 0.1-µF or greater capacitor to

SOURCE.

P

—

THERMAL

PAD

Thermal pad. Internally connected to SOURCE, and NC2.

(1) I = input, O = output, P = power

Submit Document Feedback

3

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are in respect to SOURCE connected to reference ground⁽¹⁾

MIN

MAX UNIT

V_DS

Drain-source voltage, FET off

650

720

800

20

V

V_DS(surge)

V_DS,tr

Drain-source voltage, FET switching, surge condition⁽²⁾

Drain-source transient ringing peak voltage, FET off, surge condition^{(2) (3)}

V_DD

-0.3

-16

LDO5V

VNEG

5.5

0.5

V_VNEG

–1

Pin voltage

BBSW

V_VDD+0.5

V

IN

-0.3

20

V

FAULT, OC, TEMP

RDRV

V_LDO5V+0.3

5.5

V

I_D(RMS)

I_D(pulse)

I_S(pulse)

T_J

Drain RMS current, FET on

55

A

Drain pulsed current, FET on, tp < 10 µs⁽⁴⁾

Source pulsed current, FET off, tp < 1 µs

Operating junction temperature⁽⁵⁾

Storage temperature

-125

Internally Limited

A

80

150

A

-40

-55

°C

T_STG

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) See 节8.3.3 for an explanation of the switching cycle drain-source voltage ratings.

(3) t1 < 200 ns in 图8-1.

(4) The positive pulsed current must remain below the overcurrent threshold to avoid the FET being automatically shut off. The FET drain

intrinsic positive pulsed current rating for t_p< 10 µs is 120 A.

(5) Refer to the Electrical and Switching Characteristics Tables for junction temperature test conditions.

4

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.2 ESD Ratings

PARAMETER

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

Electrostatic

V_(ESD)

V

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Unless otherwise noted: voltages are in respect to SOURCE connected to reference ground.

MIN NOM MAX UNIT

VDD

Supply voltage

(Maximum switching frequency derated for V_VDD< 9

V)

7.5

0

12

5

18

V

Input voltage

IN

18

38

V

A

I_D(RMS

Drain RMS current

Positive source current

)

LDO5V

25 mA

R_RDRVRDRV to SOURCE resistance from external slew-rate control resistor

C_VNEGVNEG to SOURCE capacitance from external bypass capacitor

L_BBSWBBSW to SOURCE inductance from external buck-boost inductor ⁽¹⁾

0

1

3

500

kΩ

10 uF

10 uH

4.7

(1) > 1 A current rating is recommended.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾

LMG3522R030

RQS (VQFN)

52 PINS

UNIT

R_θJC(top)

Junction-to-case (top) thermal resistance

0.28

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

Submit Document Feedback

5

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.5 Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are in respect to SOURCE connected with

reference ground; –40 ℃≤T_J≤125 ℃;

V_DS= 520 V; 9 V ≤V_VDD≤18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GAN POWER TRANSISTOR

V_IN= 5 V, T_J= 25°C

26

45

3.6

5

35

mΩ

V

R_DS(on)

Drain-source on resistance

V_IN= 5 V, T_J= 125°C

I_S= 0.1 A

Third-quadrant mode source-drain

voltage

V_SD

I_S= 20 A

3

V

V_DS= 650 V, T_J= 25°C

V_DS= 650 V, T_J= 125°C

V_DS= 400 V

1

uA

pF

I_DSS

Drain leakage current

Output capacitance

10

235

C_OSS

C_O(er)

Energy related effective output

capacitance

320

pF

V_DS= 0 V to 400 V

C_O(tr)

Q_OSS

Q_RR

Time related effective output capacitance

Output charge

460

190

0

pF

nC

Reverse recovery charge

VDD - SUPPLY CURRENTS

V_DDquiescent current

V_VDD= 12 V, V_IN= 0 V or 5V

700

1200

20

uA

V_VDD= 12 V, f_IN= 140 kHz, soft-

switching

V_DDoperating current

15.5

mA

BUCK BOOST CONVERTER

VNEG output voltage

VNEG sinking 50 mA

-14

0.4

V

A

Peak BBSW sourcing current at low peak

I_BBSW,PK(lcurrent mode setting

(Peak external buck-boost inductor

0.3

0.5

ow)

current)

Peak BBSW sourcing current at low peak

I_BBSW,PK(current mode setting

0.8

1

1.2

A

(Peak external buck-boost inductor

high)

current)

High peak current mode setting enable –

IN positive-going threshold frequency

280

420

515

kHz

LDO5V

Output voltage

LDO5V sourcing 25 mA

4.75

25

5

5.25

100

V

Short-circuit current

50

mA

IN

V_IN,IT+

V_IN,IT-

Positive-going input threshold voltage

Negative-going input threshold voltage

Input threshold hysteresis

1.7

0.7

100

1.9

1.0

0.9

150

2.45

1.3

V

1.3

V

Input pulldown resistance

V_IN= 2 V

200

kΩ

FAULT, OC, TEMP –OUPUT DRIVE

Low-level output voltage

Output sinking 8 mA

0.16

0.2

0.4

V

Output sourcing 8 mA, Measured as

High-level output voltage

0.45

V

_LDO5V–V_O

VDD, VNEG –UNDER VOLTAGE LOCKOUT

V_VDD,T+

VDD UVLO –positive-going threshold

voltage

6.4

7

7.6

V

(UVLO)

6

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.5 Electrical Characteristics (continued)

Unless otherwise noted: voltage, resistance, capacitance, and inductance are in respect to SOURCE connected with

reference ground; –40 ℃≤T_J≤125 ℃;

V_DS= 520 V; 9 V ≤V_VDD≤18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD UVLO –negative-going threshold

voltage

6

6.5

7.1

V

VDD UVLO –Input threshold voltage

hysteresis

510

-13.0

mV

V

VNEG UVLO –negative-going threshold

voltage

-13.6

-13.3

-12.3

-12.1

VNEG UVLO –positive-going threshold

voltage

-12.75

V

GATE DRIVER

From V_DS< 320 V to V_DS< 80 V, RDRV

disconnected from LDO5V, R_RDRV= 300

kΩ, T_J= 25℃, V_BUS= 400 V, L_HBcurrent

= 10 A, see 图7-1

20

90

V/ns

MHz

From V_DS< 320 V to V_DS< 80 V, RDRV

tied to LDO5V, T_J= 25℃, V_BUS= 400 V,

L_HBcurrent = 10 A, see 图7-1

Turn-on slew rate

From V_DS< 320 V to V_DS< 80 V, RDRV

disconnected from LDO5V, R_RDRV= 0 Ω,

T_J= 25℃, V_BUS= 400 V, L_HBcurrent = 10

A, see 图7-1

150

V_NEGrising to > –13.25 V, soft-switched,

maximum switching frequency derated for

V_VDD< 9 V

Maximum GaN FET switching frequency.

2

FAULTS

DRAIN overcurrent fault –threshold

current

I_T(OC)

60

75

70

90

80

A

DRAIN short-circuit fault –threshold

current

I_T(SC)

105

di/dt threshold between overcurrent and

short-circuit faults

di/dt_T(SC)

150

A/µs

°C

GaN temperature fault –postive-going

threshold temperature

175

30

GaN temperature fault –threshold

temperature hysteresis

Driver temperature fault –positive-going

threshold temperature

185

20

Driver Temperature fault –threshold

temperature hysteresis

TEMP

Output Frequency

4.3

9

82

14

kHz

%

GaN T_J= 150℃

GaN T_J= 125℃

GaN T_J= 85℃

GaN T_J= 25℃

58.5

36.2

0.3

64.6

40

70

43.7

6

%

Output PWM Duty Cycle

%

3

%

IDEAL-DIODE MODE CONTROL

Drain-source third-quadrant detection –

V_T(3rd)

-0.15

0

0.15

V

threshold voltage

Submit Document Feedback

7

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.5 Electrical Characteristics (continued)

Unless otherwise noted: voltage, resistance, capacitance, and inductance are in respect to SOURCE connected with

reference ground; –40 ℃≤T_J≤125 ℃;

V_DS= 520 V; 9 V ≤V_VDD≤18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

-0.2

TYP

0

MAX

0.2

UNIT

A

0℃≤T_J≤125℃

Drain zero-current detection –threshold

I_T(ZC)

current

-0.35

0

0.35

A

–40°C ≤T_J≤0°C

8

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE connected with reference

ground; –40 ℃≤T_J≤125 ℃; 9 V ≤V_VDD≤18 V; V_IN= 0 V; RDRV connected to LDO5V; L_BBSW= 4.7 µH

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SWITCHING TIMES

From V_IN> V_IN,IT+to I_D> 1 A, V_BUS= 400

V, L_HBcurrent = 10 A, see 图7-1 and 图

7-2

t_d(on)

Drain-current turn-on delay time

Turn-on delay time

28

33

42

54

4.3

69

22

24

ns

(Idrain)

From V_IN> V_IN,IT+to V_DS< 320 V, V_BUS

400 V, L_HBcurrent = 10 A, see 图7-1

and 图7-2

=

t_d(on)

t_r(on)

t_d(off)

t_f(off)

From V_DS< 320 V to V_DS< 80 V, V_BUS

400 V, L_HBcurrent = 10 A, see 图7-1

and 图7-2

=

Turn-on rise time

2.8

48

From V_IN< V_{IN ,IT–}to V_DS> 80 V, V_BUS

400 V, L_HBcurrent = 10 A, see 图7-1

and 图7-2

=

Turn-off delay time

From V_DS> 80 V to V_DS> 320 V, V_BUS

400 V, L_HBcurrent = 10 A, see 图7-1

and 图7-2

=

Turn-off fall time⁽¹⁾

V_INrise/fall times < 1 ns, V_DSfalls to <

200 V, V_BUS= 400 V, L_HBcurrent = 10 A,

see 图7-1

Minimum IN high pulse-width for FET

turn-on

STARTUP TIMES

From V_VDD> V_VDD,T+

_(UVLO)to FAULT high, C_LDO5V= 100

nF, C_VNEG= 2.2 µF at 0-V bias linearly

decreasing to 1.5 µF at 15-V bias

t_(start)

Driver start-up time

310

470

us

FAULT TIMES

Overcurrent fault FET turn-off time, FET

on before overcurrent

V_IN= 5 V, From I_D> I_T(OC)to I_D< 50 A, I_D

di/dt = 100 A/µs

t_off(OC)

t_off(SC)

115

65

170

100

250

ns

Short-circuit current fault FET turn-off

time, FET on before short circuit

V_IN= 5 V, From I_D> I_T(SC)to I_D< 50 A, I_D

di/dt = 700 A/µs

Overcurrent fault FET turn-off time, FET

turning on into overcurrent

From I_D> I_T(OC)to I_D< 50 A

200

Short-circuit fault FET turn-off time, FET

turning on into short circuit

From I_D> I_T(SC)to I_D< 50 A

80

380

50

180

580

ns

us

ns

IN reset time to clear FAULT latch

From V_IN< V_IN,IT–to FAULT high

250

t_(window)

Overcurrent fault to short-circuit fault

window time

(OC)

IDEAL-DIODE MODE CONTROL TIMES

V_DS< V_T(3rd)to FET turn-on, V_DSbeing

discharged by half-bridge configuration

inductor at 5 A

Ideal-diode mode FET turn-on time

50

65

ns

I_D> I_T(ZC)to FET turn-off, I_Ddi/dt = 100

A/µs created with a half-bridge

configuration

Ideal-diode mode FET turn-off time

55

76

ns

Overtemperature-shutdown ideal-diode

mode IN falling blanking time

150

230

360

(1) During turn-off, V_DSrise time is the result of the resonance of C_OSSand loop inductance as well as load current.

Submit Document Feedback

9

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.7 Typical Characteristics

95

160

140

120

100

80

-40C

0C

25C

85C

125C

-40C

0C

25C

85C

125C

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

60

40

20

0

50 100 150 200 250 300 350 400 450 500

0

50 100 150 200 250 300 350 400 450 500

RDRV Resistance (k)

图6-2. Turn-On Delay Time vs Drive Strength Resistance

图6-1. Drain-Current Turn-On Delay Time vs Drive Strength

Resistance

140

-40C

0C

120

25C

85C

100

125C

80

60

40

20

0

50 100 150 200 250 300 350 400 450 500

RDRV Resistance (k)

图6-4. Turn-On Slew Rate vs Drive Strength Resistance

图6-3. Turn-On Rise Time vs Drive Strength Resistance

600

6.5

-40C

0C

6

500

25C

85C

5.5

125C

400

5

4.5

4

-40C

300

25C

125C

OC limit

200

100

0

3.5

3

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

Drain-Source Voltage (V)

Source Current (A)

图6-5. Drain Current vs Drain-Source Voltage

IN = 0 V

图6-6. Off-State Source-Drain Voltage vs Source Current

10

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

6.7 Typical Characteristics (continued)

2

1.8

1.6

1.4

1.2

1

1750

1500

1250

1000

750

500

250

0

-40C

0C

25C

85C

125C

0.8

0.6

0

50 100 150 200 250 300 350 400 450 500

Drain-Source Voltage (V)

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

图6-8. Output Capacitance vs Drain-Source Voltage

图6-7. Normalized On-Resistance vs Junction Temperatue

250

V_ds= 0 V

V_ds= 50 V

V_ds= 400 V

V_ds= 0 V

V_ds= 50 V

V_ds= 400 V

200

150

100

50

150

V_ds= 50 V

100

V_ds= 0 V

50

0

400

800

1200

1600

2000

0

400

800

1200

1600

2000

IN Switching Frequency (kHz)

VDD = 12 V; T_J= 25 °C.

VDD = 12 V; T_J= 125 °C.

图6-10. VDD Supply Current vs IN Switching Frequency

图6-9. VDD Supply Current vs IN Switching Frequency

80

70

60

50

40

30

20

10

0

50 100 150 200 250 300 350 400 450 500 550

Drain-Source Voltage (V)

图6-11. Repetitive Safe Operation Area

Submit Document Feedback

11

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

7 Parameter Measurement Information

7.1 Switching Parameters

图 7-1 shows the circuit used to measure most switching parameters. The top device in this circuit is used to re-

circulate the inductor current and functions in third-quadrant mode only. The bottom device is the active device

that turns on to increase the inductor current to the desired test current. The bottom device is then turned off and

on to create switching waveforms at a specific inductor current. Both the drain current (at the source) and the

drain-source voltage is measured. 图 7-2 shows the specific timing measurement. TI recommends to use the

half-bridge as a double pulse tester. Excessive third-quadrant operation can overheat the top device.

DRAIN

Slew

Rate

Direct-Drive

SOURCE

GaN

RDRV

IN

VDD

LDO5V

TEMP

VNEG

OCP, OTP,

UVLO,

TEMP

Current

LDO,

BB

L_HB

FAULT

OC

V_BUS

+

–

C_VDC

SOURCE

DRAIN

Slew

Rate

Direct-Drive

SOURCE

GaN

RDRV

IN

+

V_DS

VDD

LDO5V

TEMP

VNEG

OCP, OTP,

UVLO,

TEMP

Current

LDO,

BB

_

PWM input

FAULT

OC

I_D

SOURCE

图7-1. Circuit Used to Determine Switching Parameters

12

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

50%

IN

I_D

t_{d(on)(Idrain)}

1A

t_d(on)

t_d(off)

t_r(on)

t_f(off)

80%

V_DS

80%

20%

图7-2. Measurement to Determine Propagation Delays and Slew Rates

7.1.1 Turn-On Times

The turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and

turn-on rise time. The drain-current turn-on delay time is from when IN goes high to when the GaN FET drain-

current reaches 1 A. The turn-on delay time is from when IN goes high to when the drain-source voltage falls

20% below the bus voltage. Finally, the turn-on rise time is from when drain-source voltage falls 20% below the

bus voltage to when the drain-source voltage falls 80% below the bus voltage. Note that the turn-on rise time is

the same as the V_DS80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin

setting.

7.1.2 Turn-Off Times

The turn-off transition has two timing components: turn-off delay time, and turn-off fall time. The turn-off delay

time is from when IN goes low to when the drain-source voltage rises to 20% of the bus voltage. The turn-off fall

time is from when the drain-source voltage rises to 20% of the bus voltage to when the drain-source voltage

rises to 80% of the bus voltage. Note that the turn-off fall time is the same as the V_DS20% to 80% rise time. The

turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the L_HBload

current.

7.1.3 Drain-Source Turn-On Slew Rate

The drain-source turn-on slew rate, measured in volts per nanosecond, is the inverse of the turn-on rise time or

equivalently the inverse of the V_DS80% to 20% fall time. The RDRV pin is used to program the slew rate.

Submit Document Feedback

13

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

8 Detailed Description

8.1 Overview

The LMG3522R030 is a high-performance power GaN device with integrated gate driver. The GaN device offers

zero reverse recovery and ultra-low output capacitance, which enables high efficiency in bridge-based

topologies. Direct Drive architecture is applied to control the GaN device directly by the integrated gate driver.

This architecture provides superior switching performance compared to the traditional cascode approach and

helps solve a number of challenges in GaN applications.

The integrated driver ensures the device stays off for high drain slew rates. The integrated driver also protects

the GaN device from overcurrent, short-circuit, undervoltage, and overtemperature. Regarding fault signal

reporting, LMG3522R030 provides different reporting method which is shown in 表 8-1. Refer to Fault Detection

for more details. The integrated driver is also able to sense the die temperature and send out the temperature

signal through a modulated PWM signal.

Unlike Si MOSFETs, GaN devices do not have a p-n junction from source to drain and thus have no reverse

recovery charge. However, GaN devices still conduct from source to drain similar to a p-n junction body diode,

but with higher voltage drop and higher conduction loss. Therefore, source-to-drain conduction time must be

minimized while the LMG3522R030 GaN FET is turned off.

8.2 Functional Block Diagram

TEMP

DRAIN

VDD

Third-Quadrant

Detection

GaN

LDO

LDO5V

UVLO

(+5V, VDD, VNEG)

FAULT

Series

Si FET

Die

Temp

Sensing

Thermal

Shutdown

Short Circuit Protection

Overcurrent Protection

OC

IN

Gating logic control

& level shifting

Buck-Boost

Controller

BBSW

VNEG

SOURCE

RDRV

14

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

8.3 Feature Description

The LMG3522R030 includes advanced features to provide superior switching performance and converter

efficiency.

8.3.1 GaN FET Operation Definitions

For the purposes of this data sheet, the following terms are defined below. The SOURCE pin is assumed to be at

0 V for these definitions.

First-Quadrant Current = Positive current flowing internally from the DRAIN pin to the SOURCE pin.

Third-Quadrant Current = Positive current flowing internally from the SOURCE pin to the DRAIN pin.

First-Quadrant Voltage = Drain pin voltage –Source pin voltage = Drain pin voltage

Third-Quadrant Voltage = SOURCE pin voltage –DRAIN pin voltage = –DRAIN pin voltage

FET On-State = FET channel is at rated R_DS(on). Both first-quadrant current and third-quadrant current can flow

at rated R_DS(on)

.

For LMG3522R030 in On-State, GaN FET internal gate voltage is held at the SOURCE pin voltage to achieve

rated R_DS(on). The GaN FET channel is at rated R_DS(on)with V_GS= 0 V because the LMG3522R030 GaN FET is

a depletion mode FET.

FET Off-State = FET channel is fully off for positive first-quadrant voltage. No first-quadrant current can flow.

While first-quadrant current cannot flow in the FET Off-State, third-quadrant current still flows if the DRAIN

voltage is taken sufficiently negative (positive third-quadrant voltage). For devices with an intrinsic p-n junction

body diode, current flow begins when the DRAIN voltage drops enough to forward bias the p-n junction.

GaN FETS do not have an intrinsic p-n junction body diode. Instead, current flows because the GaN FET

channel turns back on. In this case, the DRAIN pin becomes the electrical source and the SOURCE pin

becomes the electrical drain. To enhance the channel in third-quadrant, the DRAIN (electrical source) voltage

must be taken sufficiently low to establish a V_GSvoltage greater than the GaN FET threshold voltage. The GaN

FET channel is operating in saturation and only turns on enough to support the third-quadrant current as its

saturated current.

For LMG3522R030 in Off-State, GaN FET internal gate voltage is held at the VNEG pin voltage to block all first-

quadrant current. The VNEG voltage is lower than the GaN FET negative threshold voltage to cut off the

channel.

To enhance the channel in off-state third quadrant, the LMG3522R030 DRAIN (electrical source) voltage must

be taken sufficiently close to VNEG to establish a V_GSvoltage greater than the GaN FET threshold voltage.

Again, because the LMG3522R030 GaN FET is a depletion mode FET with a negative threshold voltage, this

means the GaN FET turns on with DRAIN (electrical source) voltage between 0 V and VNEG. The typical off-

state third-quadrant voltage is 5 V for third-quadrant current at 20 A. Thus, the off-state third-quadrant losses for

the LMG3522R030 are significantly higher than a comparable power device with an intrinsic p-n junction body

diode.

8.3.2 Direct-Drive GaN Architecture

The LMG3522R030 uses a series Si FET to ensure the power IC stays off when VDD bias power is not applied.

When the VDD bias power is off, the series Si FET is interconnected with the GaN device in a cascode mode,

which is shown in the Functional Block Diagram. The gate of the GaN device is held within a volt of the series Si

FET's source. When a high voltage is applied on the drain and the silicon FET blocks the drain voltage, the V_GS

of the GaN device decreases until the GaN device passes the threshold voltage. Then, the GaN device is turned

off and blocks the remaining major part of drain voltage. There is an internal clamp to make sure that the V_DSof

the Si FET does not exceed its maximum rating. This feature avoids the avalanche of the series Si FET when

there is no bias power.

Submit Document Feedback

15

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

When LMG3522R030 is powered up with VDD bias power, the internal buck-boost converter generates a

negative voltage (V_VNEG) that is sufficient to directly turn off the GaN device. In this case, the series Si FET is

held on and the GaN device is gated directly with the negative voltage.

Comparing with traditional cascode drive GaN architecture, where the GaN gate is grounded and the Si

MOSFET gate is being driven to control the GaN device, direct-drive configuration has multiple advantages.

First, as the Si MOSFET does need to switch in every switching cycle, GaN gate-to-source charge (Q_GS) is lower

and there’s no Si MOSFET reverse-recovery related losses. Second, the voltage distribution between the GaN

and Si MOSFET in off-mode in a cascode configuration can cause the MOSFET to avalanche due to high GaN

drain-to-source capacitance (C_DS). Finally, the switching slew rate in direct-drive configuration can be controlled

while cascode drive cannot. More information about the direct-drive GaN architecture can be found in Direct-

drive configuration for GaN devices.

8.3.3 Drain-Source Voltage Capability

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware

that the headline drain-source voltage cannot be used as an equivalent point to compare devices across

technologies. The headline drain-source voltage of a silicon FET is set by the avalanche breakdown voltage.

The headline drain-source voltage of a GaN FET is set by the long term reliability with respect to data sheet

specifications.

Exceeding the headline drain-source voltage of a silicon FET can lead to immediate and permanent damage.

Meanwhile, the breakdown voltage of a GaN FET is much higher than the headline drain-source voltage. For

example, the breakdown voltage of the LMG3522R030 is more than 800 V.

A silicon FET is usually the weakest link in a power application during an input voltage surge. Surge protection

circuits must be carefully designed to ensure the silicon FET avalanche capability is not exceeded because it is

not feasible to clamp the surge below the silicon FET breakdown voltage. Meanwhile, it is easy to clamp the

surge voltage below a GaN FET breakdown voltage. In fact, a GaN FET can continue switching during the surge

event which means output power is safe from interruption.

The LMG3522R030 drain-source capability is explained with the assistance of 图 8-1. The figure shows the

drain-source voltage versus time for a GaN FET for a single switch cycle in a switching application. No claim is

made about the switching frequency or duty cycle.

V_DS(tr)

V_DS(off)

V_{DS(switching)}

t₀t₁

t₂

图8-1. Drain-Source Voltage Switching Cycle

The waveform starts before t₀with the FET in the on state. At t₀the GaN FET turns off and parasitic elements

cause the drain-source voltage to ring at a high frequency. The peak ring voltage is designated V_DS(tr). The high

frequency ringing has damped out by t₁. Between t₁and t₂the FET drain-source voltage is set by the

characteristic response of the switching application. The characteristic is shown as a flat line, but other

responses are possible. The voltage between t₁and t₂is designated V_DS(off). At t₂the GaN FET is turned on at a

non-zero drain-source voltage. The drain-source voltage at t₂is designated V_{DS(switching)}. Unique V_DS(tr), V_DS(off)

and V_{DS(switching)}parameters are shown because each can contribute to stress over the lifetime of the GaN FET.

16

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

The LMG3522R030 drain-source surge voltage capability is seen with the absolute maximum ratings V_{DS(tr)(surge)}

and V_DS(surge)in the Specifications where V_{DS(tr)(surge)}maps to V_DS(tr)in 图 8-1 and V_DS(surge)maps to both

V_DS(off)and V_{DS(switching)}in 图8-1. More information about the surge capability of TI GaN FETs is found in A New

Approach to Validate GaN FET Reliability to Power-line Surges Under Use-conditions.

8.3.4 Internal Buck-Boost DC-DC Converter

An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the GaN

device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation,

the converter remains in discontinuous-conduction mode, but can enter continuous-conduction mode during

start-up. The converter is controlled internally and requires only a single surface-mount inductor and output

bypass capacitor. Typically, the converter is designed to use a 4.7 μH inductor and a 2.2 μF output capacitor.

The buck-boost converter uses a peak current hysteretic control. As shown in 图 8-2, the inductor current

increases at the beginning of a switching cycle until the inductor reaches the peak current limit. Then the

inductor current goes down to zero. The idle time between each current pulse is determined automatically by the

buck-boost controller, and can be reduced to zero. Therefore, the maximum output current happens when the

idle time is zero, and is decided by the peak current but to a first order is independent of the inductor value.

However, the peak output current the buck-boost can deliver to the -14V rail is proportional to the VDD input

voltage. Therefore, the maximum switching frequency of the GaN that the buck-boost can support varies with

VDD voltage and is only specified for operation up to 2 MHz for VDD voltages above 9V.

V_{NEG_avg}

ûV_NEG

V_NEG

I_DCDC,PK

Smaller

inductor

Larger

inductor

Idle time

Buck-boost

inductor current

1/(buck-boost frequency)

图8-2. Buck-Boost Converter Inductor Current

The LMG3522R030 supports the GaN operation up to 2 MHz. As power consumption is very different in a wide

switching frequency range enabled by the GaN device, two peak current limits are used to control the buck-boost

converter. The two ranges are separated by IN positive-going threshold frequency. As shown in 图 8-3, when

switching frequency is in the lower range, the peak current is initially set to the lower value I_BBSW,M(low)(typically

0.4 A) . When switching frequency is in the higher range, the peak current is raised to the higher value

I_BBSW,M(high)(typically 1 A) and requires a larger inductor. There is a filter on this frequency detection logic,

therefore the LMG3522R030 requires five consecutive cycles at the higher frequency before it is set to the

higher buck-boost peak current limit. The current limit does not go down again until power off after the higher

limit is set. Even if the switching frequency returns to the lower range, the current limit does not decrease to the

lower limit.

Submit Document Feedback

17

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

I_{BBSW,PK(high)}

I_BBSW,PK(low)

I_BBSW,PK

IN

图8-3. Buck-Boost Converter Peak Current

As the peak current of the buck-boost is subject to two different peak current limits which are 0.4 A and 1 A for

low and high frequency operation (see Internal Buck-Boost DC-DC Converter), so the inductor must have a

saturation current well above the rated peak current limit. After the higher limit is established by switching at a

higher frequency, the current limit does not go back to the lower level even when GaN device is then switched at

a lower frequency. Therefore, selecting an inductor according to the higher 1-A limit is recommended.

8.3.5 VDD Bias Supply

Wide VDD voltage ranges from 7.5 V to 18 V are supported by internal regulators which supply the bias supplies

needed for the internal circuits to function. TI recommends to use a 12-V unregulated power supply to supply

VDD.

8.3.6 Auxiliary LDO

There is a 5-V voltage regulator inside the part used to supply external loads, such as digital isolators for the

high-side drive signal. The digital outputs of the part use this rail as their supply. No capacitor is required for

stability, but transient response is poor if no external capacitor is provided. If the application uses this rail to

supply external circuits, TI recommends to have a capacitor of at least 0.1 μF for improved transient response.

A larger capacitor can be used for further transient response improvement. The decoupling capacitor used here

must be a low-ESR ceramic type. Capacitances above 0.47 μF will slow down the start-up time of the

LMG3522R030 due to the ramp-up time of the 5-V rail.

8.3.7 Fault Detection

The GaN power IC integrates overcurrent protection (OCP), short-circuit protection (SCP), overtemperature

protection (OTP) and undervoltage lockout (UVLO).

8.3.7.1 Overcurrent Protection and Short-Circuit Protection

There are two types of current faults which can be detected by the driver: overcurrent fault and short-circuit fault.

The overcurrent protection (OCP) circuit monitors drain current and compares that current signal with an

internally set limit I_T(OC). Upon detection of the overcurrent, the LMG3522R030 conducts cycle-by-cycle

overcurrent protection as shown in 图 8-4. In this mode, the GaN device is shut off and the OC pin is pulled low

when the drain current crosses the I_T(OC)plus a delay t_off(OC), but the overcurrent signal clears after the IN pin

signal goes low. In the next cycle, the GaN device can turn on as normal. The cycle-by-cycle function can be

used in cases where steady-state operation current is below the OCP level but transient response can still reach

current limit, while the circuit operation cannot be paused. The cycle-by-cycle function also prevents the GaN

device from overheating by overcurrent induced conduction losses.

18

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

The short-circuit protection (SCP) monitors the drain current and triggers if the di/dt of the current exceeds a

threshold di/dt _T(SC)as the current crosses between the OC and SC thresholds. It performs this di/dt detection by

delaying the OC detection signal by an amount t_OC,windowand using a higher current SC detection threshold. If

the delayed OC occurs before the non-delayed SC, the di/dt is below the threshold and an OC is triggered. If the

SC is detected first, the di/dt is fast enough and the SC is detected as shown in 图 8-5. This extremely high di/dt

current would typically be caused by a short of the output of the half-bridge and can be damaging for the GaN to

continue to operate in that condition. Therefore, if a short-circuit fault is detected, the GaN device is turned off

with an intentionally slowed driver so that a lower overshoot voltage and ringing can be achieved during the turn-

off event. This fast response circuit helps protect the GaN device even under a hard short-circuit condition. In

this protection, the GaN device is shut off and held off until the fault is reset by either holding the IN pin low for a

period of time defined in the Specifications or removing power from VDD.

During OCP or SCP in a half bridge, after the current reaches the upper limit and the device is turned off by

protection, the PWM input of the device could still be high and the PWM input of the complementary device

could still be low. In this case, the load current can flow through the third quadrant of the complementary device

with no synchronous rectification. The high negative V_DSof the GaN device (–3 V to –5 V) from drain to source

could lead to high third-quadrant loss, similar to dead-time loss but for a longer time.

For safety considerations, OCP allows cycle-by-cycle operation while SCP latches the device until reset. By

reading the FAULT and OC pins, the exact current fault type can be determined. Refer to Fault Reporting for

detailed information.

I_T(OC)

Inductor current

V_SW

Input PWM

图8-4. Cycle-by-Cycle OCP Operation

Submit Document Feedback

19

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

t_off(SC)

t_off(OC)

I_T(SC)

< t_(window)(OC)

I_T(OC)

I_D

IN

OC

Cycle by cycle OCP

Latched SCP

图8-5. Overcurrent Detection vs Short-Circuit Detection

8.3.7.2 Overtemperature Shutdown

The LMG3522R030 implements two overtemperature-shutdown (OTSD) functions, the GaN OTSD and the

Driver OTSD. Two OTSD functions are needed to maximize device protection by sensing different locations in

the device and protecting against different thermal-fault scenarios.

The GaN OTSD senses the GaN FET temperature. The GaN FET can overheat from both first-quadrant current

and third-quadrant current. As explained in GaN FET Operation Definitions, a FET can prevent first-quadrant

current by going into the off-state but is unable to prevent third-quadrant current. FET third-quadrant losses are a

function of the FET technology, current magnitude, and if the FET is operating in the on-state or off-state. As

explained in GaN FET Operation Definitions, the LMG3522R030 has much higher GaN FET third-quadrant

losses in the off-state.

When the GaN FET is too hot, the best protection is to turn off the GaN FET when first-quadrant current tries to

flow and turn on the GaN FET when third-quadrant current is flowing. This type of FET control is known as ideal-

diode mode (IDM). When the GaN OTSD trip point is exceeded, the GaN OTSD puts the GaN FET into

overtemperature-shutdown ideal-diode mode (OTSD-IDM) operation to achieve this optimum protection. OTSD-

IDM is explained in 节8.3.10 .

The Driver OTSD senses the integrated driver temperature and trips at a higher temperature compared to the

GaN OTSD. This second OTSD function exists to protect the LMG3522R030 from driver thermal-fault events

while allowing sufficient temperature difference for OTSD-IDM to operate. These driver thermal events include

shorts on the LDO5V, BBSW, and VNEG device pins. When the Driver OTSD trip point is exceeded, the Driver

OTSD shuts off the LDO5V regulator, the VNEG buck-boost converter, and the GaN FET. Note that OTSD-IDM

does not function in Driver OTSD. This is why the Driver OTSD must trip higher than the GaN OTSD function.

Otherwise, GaN FET third-quadrant overheating cannot be addressed.

20

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

Besides the temperature difference in the GaN OTSD and Driver OTSD trip points, further temperature

separation is obtained due to the thermal gradient difference between the GaN OTSD and Driver OTSD sense

points. The GaN OTSD sensor is typically at least 20°C hotter than the driver OTSD sensor when the device is

in GaN OTSD due to GaN FET power dissipation.

The FAULT pin is asserted for either or both the GaN OTSD state and the Driver OTSD state. FAULT de-asserts

and the device automatically returns to normal operation after both the GaN OTSD and Driver OTSD fall below

their negative-going trip points. During cool down, when the device exits the Driver OTSD state but is still in the

GaN OTSD state, the device automatically resumes OTSD-IDM operation.

8.3.7.3 UVLO Protection

The LMG3522R030 supports a wide range of VDD voltages. However, when the device is below UVLO

threshold, the GaN device stops switching and is held off. The FAULT pin is pulled low as an indication of UVLO.

The LDO and buck-boost are turned on by the rising-edge of the VIN UVLO and shuts off around 5 V to 6 V.

8.3.7.4 Fault Reporting

The FAULT and OC outputs form a fault reporting scheme together. The FAULT and OC outputs are both push-

pull outputs indicating the readiness and fault status of the driver. These two pins are logic high in normal

operation, and change logic according to 表8-1.

表8-1. Fault Types and Reporting

NORMAL

UVLO, OT, and RDRV-OPEN

OVERCURRENT

SHORT-CIRCUIT

FAULT

OC

1

0

1

0

FAULT is held low when starting up until the series Si FET is turned on. During operation, if the power supplies

go below the UVLO thresholds or the device temperature go above the OT thresholds, power device is disabled

and FAULT is held low until a fault condition is no longer detected. If RDRV is open, FAULT is also held low. In a

short-circuit or overtemperature fault condition, FAULT is held low until the fault latches are reset or fault is

cleared. The OC pin is held low if there is a short-circuit or overcurrent fault. The signals help notify the controller

the exact type of faults by reading the truth table. If a combined reporting of the faults on a single pin is desired,

one can short the OC pin to ground during power up. All faults assert the FAULT pin then and the OC pin is not

used. Please note: internal protection happens regardless of the connection of the pin outputs, which means that

the protection features continue to operate even if fault reporting is ignored.

8.3.8 Drive Strength Adjustment

The LMG3522R030 allows users to adjust the drive strength of the device and obtain a desired slew rate, which

provides flexibility when optimizing switching losses and noise coupling.

To adjust drive strength, a resistor can be placed between the RDRV pin and SOURCE pin. The resistance

determines the slew rate of the device, from 20 V/ns to 150 V/ns, during turn-on. On the other hand, there are

two dv/dt values that can be selected without the resistor: shorting the RDRV pin to ground sets the slew rate to

150 V/ns, and shorting the RDRV pin to LDO5V sets the slew rate to 100 V/ns. The device detects the short to

LDO5V one time at power up. Once the short to LDO5V condition is detected, the device no longer monitors the

RDRV pin. Otherwise, the RDRV pin is continuously monitored and the dv/dt setting can be changed by

modulating the resistance during device operation. The modulation must be fairly slow since there is significant

internal filtering to reject switching noise.

Please note: parasitic power loop inductance can influence the voltage slew rate reading from the V_DSswitching

waveform.The inductance induces a drop on V_DSin the current rising phase before voltage falling phase, if this

drop is more than 20% of the V_DC, the voltage slew rate reading can be influenced. Refer to 节 9.5.1.2 for the

power loop design guideline and how to estimate the parasitic power loop inductance.

8.3.9 Temperature-Sensing Output

The integrated driver senses the GaN die temperature and outputs the information through a modulated PWM

signal on the TEMP pin. The typical PWM frequency is 9 kHz with the same refresh rate. The minimum PWM

Submit Document Feedback

21

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

duty cycle is around 1%, which can be observed at temperature below 25°C. The target temperature range is

from 25°C to 150°C, and the corresponding PWM duty cycle is typically from 3% to 82%. Following equation can

be used to calculate the typical junction temperature T_J,typin °C from the duty cycle D_TEMP

:

T_J,typ(°C) = 162.3 * D_TEMP+ 20.1

The tolerances of typical measurement are listed in 表8-2.

表8-2. Typical Junction Temperature Measurement based on TEMP Signal and Tolerance

Typical T_JMeasurement based on TEMP Signal (°C)

25

85

125

Tolerance (°C)

± 5

± 6

± 10

At temperatures above 150°C, the duty cycle continues to increase linearly until overtemperature fault happens.

When overtemperature happens, the TEMP pin is pulled high to indicate this fault until the temperature is

reduced to the normal range. There is a hysteresis to clear overtemperature fault.

8.3.10 Ideal-Diode Mode Operation

Off-state FETs act like diodes by blocking current in one direction (first quadrant) and allowing current in the

other direction (third quadrant) with a corresponding diode like voltage drop. FETs, though, can also conduct

third-quadrant current in the on-state at a significantly lower voltage drop. Ideal-diode mode (IDM) is when an

FET is controlled to block first-quadrant current by going to the off-state and conduct third-quadrant current by

going to the on-state, thus achieving an ideal lower voltage drop.

FET off-state third-quadrant current flow is commonly seen in power converters, both in normal and fault

situations. As explained in GaN FET Operation Definitions, GaN FETs do not have an intrinsic p-n junction body

diode to conduct off-state third-quadrant current. Instead, the off-state third-quadrant voltage drop for the

LMG3522R030 is several times higher than a p-n junction voltage drop, which can impact efficiency in normal

operation and device ruggedness in fault conditions.

To improve device ruggedness in a GaN FET overtemperature fault situation, LMG3522R030 devices implement

a

GaN FET overtemperature-shutdown ideal-diode mode (OTSD-IDM) function as referenced in

Overtemperature Shutdown. The OTSD-IDM function is described in more detail below.

8.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode

Overtemperature-shutdown ideal-diode mode (OTSD-IDM) is implemented in LMG3522R030. As explained in

Overtemperature Shutdown, ideal-diode mode provides the best GaN FET protection when the GaN FET is

overheating.

OTSD-IDM accounts for all, some, or none of the power system operating when OTSD-IDM is protecting the

GaN FET. The power system may not have the capability to shut itself down, in response to the LMG3522R030

asserting the FAULT pin in a GaN OTSD event, and just continue to try to operate. Parts of the power system

can stop operating due to any reason such as a controller software bug or a solder joint breaking or a device

shutting off to protect itself. At the moment of power system shutdown, the power system stops providing gate

drive signals but the inductive elements continue to force current flow while they discharge.

The OTSD-IDM state machine is shown in 图 8-6. Each state is assigned a state number in the upper right side

of the state box. The OTSD-IDM state machine has a similar structure to the OP-IDM state machine. Similar

states use the same state number.

22

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

1

FET OFF

OTSD-IDM waiting for IN

falling-edge blank time to

expire

IN falling-edge blank

time expired

IN falling edge

First-quadrant drain

current

2

3

FET OFF

FET ON

OTSD-IDM looking for negative

V_DS

OTSD-IDM looking for first-

quadrant drain current

Negative V_DSdue to

third-quadrant drain

current

Enter OTSD

图8-6. Overtemperature-Shutdown Ideal-Diode Mode (OTSD-IDM) State Machine

1. The LMG3522R030 GaN FET always goes to state #1 if a falling edge is detected on the IN pin. OTSD-IDM

turns off the GaN FET in OTSD-IDM state #1. OTSD-IDM is waiting for the IN falling edge blank time to

expire. This time gives the opposite-side FET time to switch to create a positive drain voltage. After the blank

time expires, the device moves to OTSD-IDM state #2.

2. For OTSD-IDM state #2, OTSD-IDM keeps the GaN FET off if it is coming from OTSD-IDM state #1 and

turns the GaN FET off if it is coming from OTSD-IDM state #3. OTSD-IDM is monitoring the GaN FET drain

voltage in OP-IDM state #2. It is looking for a negative drain voltage which means third-quadrant current is

flowing. This is also the starting state when the device enters OTSD. After a negative GaN FET drain voltage

is detected, the device moves to OTSD-IDM state #3

3. OP-IDM turns on the GaN FET in OTSD-IDM state #3. OP-IDM monitors the drain current in this state. If

first-quadrant drain current is detected, the device moves to OP-IDM state #2.

State #1 is used to protect against shoot-through current. The state #1 in the OTSD-IDM state machine waits for

a fixed time period before proceeding to state #2. The fixed time period is to give the opposite-side switch time to

switch and create a positive drain voltage. A fixed time is used to avoid a stuck condition for cases where a

positive drain voltage is not created.

State #1 will help protect against shoot-through currents if the converter continues switching when the

LMG3522R030 enters OTSD. Meanwhile, if the converter initiates switching with the LMG3522R030 already in

OTSD, shoot-through current protection can be obtained by switching the OTSD device first to force it to

progress though state #1. For example, the synchronous rectifier in a boost PFC can go into OTSD during initial

input power application as the inrush current charges the PFC output cap. A shoot-through current event can be

avoided if converter switching begins by switching the synchronous rectifier FET before switching the boost PFC

FET.

If there is no IN signal, the state machine only moves between states #2 and #3 as a classic ideal-diode mode

state machine. This allows all the inductive elements to discharge, when the power system shuts off, with

minimum discharge stress created in the GaN FET.

Note that the OTSD-IDM state machine has no protection against repetitive shoot-through current events. There

are degenerate cases, such as the LMG3522R030 losing its IN signal during converter operation, which can

expose the OTSD-IDM to repetitive shoot-through current events. There is no good solution in this scenario. If

OTSD-IDM did not allow repeated shoot-thru current events, the GaN FET would instead be exposed to

excessive off-state third-quadrant losses.

Submit Document Feedback

23

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

8.4 Start Up Sequence

图8-7 shows the start up sequence of LMG3522R030.

Time interval A: V_DDstarts to build up. FAULT signal is initially pulled low.

Time interval B: After V_DDpasses the UVLO threshold V_VDD,T+(UVLO), both LDO5V and V_NEGstart to built up. In a

typical case where C_LDO5V= 100 nF and C_VNEG= 2.2 μF, LDO5V reaches its UVLO thresold earlier than V_NEG

.

The start-up time may vary if different capacitors are utilized. If V_DDhas some glitches and falls below UVLO

threshold V_VDD,T-(UVLO)in this time interval, LDO5V and V_NEGwill stop building up and only resume when V_DD

goes above V_VDD,T+(UVLO)again. A longer start-up time is expected in this case.

Time interval C: After LDO5V and V_NEGboth reach their thresholds, the FAULT signal is cleared (pulled high)

and the device is able to switch following the IN pin signal.

V_VDD,T+(UVLO)

V_DD

V_NEG

V_LDO5V

t_(start)

FAULT

(A)

(B)

(C)

图8-7. Start Up Timing Diagram

24

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

8.5 Safe Operation Area (SOA)

8.5.1 Safe Operation Area (SOA) - Repetitive SOA

The allowed repetitive SOA for the LMG3522R030 (图 6-11) is defined by the peak drain current (I_DS) and the

drain to source voltage (V_DS) of the device during turn on. The peak drain current during switching is the sum of

several currents going into drain terminal: the inductor current (I_ind); the current required to charge the C_OSSof

the other GaN device in the totem pole; and the current required to charge the parasitic capacitance (C_par) on

the switching node. 310 pF is used as an average C_OSSof the device during switching. The parasitic

capacitance on the switch node may be estimated by using the overlap capacitance of the PCB. A boost

topology is used for the SOA testing. The circuit shown in 图 8-8 is used to generate the SOA curve in 图 6-11.

For reliable operation, the junction temperature of the device must also be limited to 125 °C. The I_DSof 图 6-11

can be calculated by:

I_DS= I_ind+ (310 pF + C_par) * Drain slew rate at peak current

where drain slew rate at the peak current is estimated between 70 percent and 30 percent of the bus voltage,

and C_paris the parasitic board capacitance at the switched node.

Q1,Q2:

LMG3522R030

D

Q1

GaN

FAULT

IN

RDRV

V_bus

520 V

L

Temp, Current

L

O

A

D

C_out

S

D

Q2

I_ind

C_par

V_in

GaN

FAULT

50 pF

IN

RDRV

Temp, Current

S

图8-8. Circuit Used for SOA Curve

Refer to Achieving GaN Products With Lifetime Reliability for more details.

8.6 Device Functional Modes

The device has one mode of operation that applies when operated within the Recommended Operating

Conditions.

Submit Document Feedback

25

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The LMG3522R030 is a power IC targeting hard-switching and soft-switching applications operating up to 520-V

bus voltages. GaN devices offer zero reverse-recovery charge enabling high-frequency, hard-switching in

applications like the totem-pole PFC. Low Q_ossof GaN devices also benefits soft-switching converters, such as

the LLC and phase-shifted full-bridge configurations. As half-bridge configurations are the foundation of the two

mentioned applications and many others, this section describes how to use the LMG3522R030 in a half-bridge

configuration.

26

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

9.2.1 Design Requirements

This design example is for a hard-switched boost converter which is representative of PFC applications. 表 9-1

shows the system parameters for this design.

表9-1. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

200 VDC

400 VDC

20 A

Output voltage

Input (inductor) current

Switching frequency

100 kHz

9.2.2 Detailed Design Procedure

In high-voltage power converters, circuit design and PCB layout are essential for high-performance power

converters. As designing a power converter is out of the scope of this document, this data sheet describes how

to build well-behaved half-bridge configurations with the LMG3522R030.

9.2.2.1 Slew Rate Selection

The slew rate of LMG3522R030 can be adjusted between approximately 20 V/ns and 150 V/ns by connecting a

resistor, R_RDRV, from the RDRV pin to GND. The RDRV pin is a high-impedance node if a large R_RDRVresistor is

used. Therefore it can be susceptible to coupling from the drain or other fast-slewing high-voltage nodes if it

isn’t well-shielded. This will manifest itself as an unstable switching dv/dt and in extreme cases transient faults

due to the RDRV being detected as open. Shielding the pin in the layout should be a priority, however if this

coupling is still a problem, a cap of up to 1nF from RDRV to GND can be added to stabilize the pin voltage.

The slew rate affects GaN device performance in terms of:

• Switching loss

• Voltage overshoot

• Noise coupling

• EMI emission

Generally, high slew rates provide low switching loss, but high slew rates can also create higher voltage

overshoot, noise coupling, and EMI emissions. Following the design recommendations in this data sheet helps

mitigate the challenges caused by a high slew rate. The LMG3522R030 offers circuit designers the flexibility to

select the proper slew rate for the best performance of their applications.

9.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply

Using a bootstrap supply introduces additional constraints on the start-up of the high-side LMG3522R030. Prior

to powering up, the GaN device operates in cascode mode with reduced performance. In some circuits, a slower

slew rate can be required for the start-up of a bootstrap-supplied half-bridge configuration. More information can

be found in 节9.4.2.

9.2.2.2 Signal Level-Shifting

In half-bridges, high-voltage level shifters or digital isolators must be used to provide isolation for signal paths

between the high-side device and control circuit. Using an isolator is optional for the low-side device. However,

using and isolator equalizes the propagation delays between the high-side and low-side signal paths, and

provides the ability to use different grounds for the GaN device and the controller. If an isolator is not used on the

low-side device, the control ground and the power ground must be connected at the device and nowhere else on

the board. For more information, see Layout Guidelines. With fast-switching devices, common ground

inductance can easily cause noise issues without the use of an isolator.

Choosing a digital isolator for level-shifting is important for improvement of noise immunity. As GaN device can

easily create high dv/dt, > 50 V/ns, in hard-switching applications, TI highly recommends to use isolators with

high common-mode transient immunity (CMTI) and low barrier capacitance. Isolators with low CMTI can easily

Submit Document Feedback

29

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

generate false signals, which could cause shoot-through. The barrier capacitance is part of the isolation

capacitance between the signal ground and power ground, which is in direct proportion to the common mode

current and EMI emission generated during the switching. Additionally, TI strongly encourages to select isolators

which are not edge-triggered. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states

and cause circuit malfunction.

Generally, ON/OFF keyed isolators with default output low are preferred, such as the TI ISO77xxF or ISO67xxF

series. Default low state ensures the system will not shoot-through when starting up or recovering from fault

events. As a high CMTI event would only cause a very short (a few nanoseconds) false pulse, TI recommends a

low pass filter, like 300 Ωand 22 pF R-C filter, to be placed at the driver input to filter out these false pulses.

9.2.2.3 Buck-Boost Converter Design

图 9-3 and 图 9-4 show the buck-boost converter efficiency versus load current with different inductors and peak

current modes. A minimum inductance value of 3 µH is preferred for the buck-boost converter so that the di/dt

across the inductor is not too high. This leaves enough margin for the control loop to respond. As a result, the

maximum di/dt of the inductor is limited to 6 A/µs. On the other hand, large inductance also limits the transient

response for stable output voltage, and it is preferred to have inductors less than 10 µH.

85

80

75

70

L_BBSW= 3.3 H

L_BBSW= 4.7 H

65

60

55

50

L_BBSW= 10 H

0

10

20

30

40

50

60

70

80

90

Buck-Boost Load Current (mA)

VDD = 12 V;

T_J= 25 °C.

VDD = 12 V; T_J= 25 °C.

图9-4. Buck-Boost Efficiency vs Load when

图9-3. Buck-Boost Efficiency vs Load when

I_BBSW,PK= I_{BBSW,PK(high)}

I_BBSW,PK= I_BBSW,PK(low)

9.2.3 Application Curves

V_DS(50 V/div)

I_D(2.5 A/div)

V_DS(50 V/div)

I_D(1.25 A/div)

V_OUT= 400V

I_L= 5 A

R_DRV= 40 kW

V_BUS= 400 V

I_L= 5 A

R_DRV= 40 kW

Time (5 ns/div)

D006

D007

图9-5. Turn-On Waveform in Application Example 图9-6. Turn-Off Waveform in Application Example

30

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

9.3 Do's and Don'ts

The successful use of GaN devices in general, and LMG3522R030 in particular, depends on proper use of the

device. When using the LMG3522R030, DO:

• Read and fully understand the data sheet, including the application notes and layout recommendations.

• Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance.

• Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance.

• Use the proper size decoupling capacitors and locate them close to the IC as described in Layout Guidelines.

• Use a signal isolator to supply the input signal for the low-side device. If not, ensure the signal source is

connected to the signal GND plane which is tied to the power source only at the LMG3522R030 IC.

• Use the FAULT pin to determine power-up state and to detect overcurrent and overtemperature events and

safely shut off the converter.

To avoid issues in your system when using the LMG3522R030, DON'T:

• Use a single-layer or two-layer PCB for the LMG3522R030 as the power-loop and bypass capacitor

inductances is excessive and prevent proper operation of the IC.

• Reduce the bypass capacitor values below the recommended values.

• Allow the device to experience drain transients above 600 V as they can damage the device.

• Allow significant third-quadrant conduction when the device is OFF or unpowered, which can cause

overheating. Self-protection features cannot protect the device in this mode of operation.

• Ignore the FAULT pin output.

9.4 Power Supply Recommendations

The LMG3522R030 only requires an unregulated VDD power supply from 7.5 V to 18 V. The low-side supply can

be obtained from the local controller supply. The supply of the high-side device must come from an isolated

supply or a bootstrap supply.

9.4.1 Using an Isolated Power Supply

Using an isolated power supply to power the high-side device has the advantage that it works regardless of

continued power-stage switching or duty cycle. Using an isolated power supply can also power the high-side

device before power-stage switching begins, eliminating the power-loss concern of switching with an unpowered

LMG3522R030 (see Start-Up and Slew Rate With Bootstrap High-Side Supply for details). Finally, a properly-

selected isolated supply introduces less parasitics and reduces noise coupling.

The isolated supply can be obtained with a push-pull converter, a flyback converter, a FlyBuck^™converter, or an

isolated power module. When using an unregulated supply, the input of LMG3522R030 must not exceed the

maximum supply voltage. A 16-V TVS diode can be used to clamp the VDD voltage of LMG3522R030 for

additional protection. Minimizing the inter-winding capacitance of the isolated power supply or transformer is

necessary to reduce switching loss in hard-switched applications. Furthermore, capacitance across the isolated

bias supply inject high currents into the signal-ground of the LMG3522R030 and can cause problematic ground-

bounce transients. A common-mode choke can alleviate most of these issues.

9.4.2 Using a Bootstrap Diode

In half-bridge configuration, a floating supply is necessary for the high-side device. To obtain the best

performance of LMG3522R030, TI highly recommends Using an Isolated Power Supply. A bootstrap supply can

be used with the recommendations of this section.

In applications like a boost converter, the low side LMG3522R030 always start switching while high side

LMG3522R030 is unpowered. If the low side is adjusted to achieve very high slew rate before the high side bias

is fully settled, there can be unintentional turn-on at the high side due to parasitic coupling at high slew rate. The

start-up slew rate must be slowed down to 100 V/ns by changing the resistance of RDRV pin of the low side.

This slow down can be achieved by controlling the low side RDRV resistance with the high side FAULT as given

in 图9-1.

Submit Document Feedback

31

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

9.4.2.1 Diode Selection

The LMG3522R030 offers no reverse-recovery charge and very limited output charge. Hard-switching circuits

using the LMG3522R030 also exhibit high voltage slew rates. A compatible bootstrap diode must not introduce

high output charge and reverse-recovery charge.

A silicon carbide diode, like the GB01SLT06-214, can be used to avoid reverse-recovery effects. The SiC diode

has an output charge of 3 nC. Althought there is additional loss from its output charge, it does not dominate the

losses of the switching stage.

9.4.2.2 Managing the Bootstrap Voltage

In a synchronous buck or other converter where the low-side switch occasionally operates in third-quadrant, the

bootstrap supply charges through a path that includes the third-quadrant voltage drop of the low-side

LMG3522R030 during the dead time as shown in 图 9-7. This third-quadrant drop can be large, which can over-

charge the bootstrap supply in certain conditions. The V_DDsupply of LMG3522R030 must be kept below 18 V.

DRAIN

V_DD

V_F

SOURCE

+

œ

DRAIN

V_DD

V_F

SOURCE

图9-7. Charging Path for Bootstrap Diode

As shown in 图9-8, the recommended bootstrap supply includes a bootstrap diode, a series resistor, and a 16-V

TVS or zener diode in parallel with the V_DDbypass capacitor to prevent damaging the high-side LMG3522R030.

The series resistor limits the charging current at start-up and when the low-side device is operating in third-

quadrant mode. This resistor must be selected to allow sufficient current to power the LMG3522R030 at the

desired operating frequency. At 100-kHz operation, TI recommends a value of approximately 2 Ω . At higher

frequencies, this resistor value must be reduced or the resistor omitted entirely to ensure sufficient supply

current.

DRAIN

+12 V

V_DD

V_F

SOURCE

图9-8. Suggested Bootstrap Regulation Circuit

9.5 Layout

9.5.1 Layout Guidelines

The layout of the LMG3522R030 is critical to its performance and functionality. Because the half-bridge

configuration is typically used with these GaN devices, layout recommendations are considered with this

32

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

configuration. A four-layer or higher layer count board is required to reduce the parasitic inductances of the

layout to achieve suitable performance. 图 9-9 summarizes the critical layout guidelines, and more details are

further elaborated in the descriptions below.

V_dc

Use RC circuits if

SGND is floating to

FET signal ground

for CMTI

Use high-side signal

ground plane

(connected to SW)

to shield traces

D

LMG352x

C_DRVL

R_DRVH

Minimize power

loop to mitigate

transient

RDRV

IN

overvoltage

Isolator

ISO77X1F

R_INH

PWM_H

TEMP_H

C_NEGH

VNEG

BBSW

TEMP

C_INH

R_OCH

L_BBSWH

/OC_H

R_FTH

/FAULT_H

C_FTHC_OCH

/OC

/FAULT

LDO5V

C_LDOH

SGND

VDD

PWR

Transformer

driver

SN6505

C_VDDH

GND

SGND

S

D

Recommend to parallel a

cap to reduce the noise

Minimize the loops of

these caps to mitigate

switching noises

Use Kelvin connection

between high side signal

ground and SW

SW

C_decoupling

Use low-side signal

ground plane

(connected to GND)

to shield traces

LMG352x

C_DRVL

RDRV

IN

R_DRVL

Isolator

ISO77X1F

R_INL

C_INL

PWM_L

C_NEGL

TEMP_L

/OC_L

VNEG

BBSW

TEMP

L_BBSWL

/FAULT_L

/OC

/FAULT

LDO5V

C_LDOL

VDD

PWR

Transformer

driver

SN6505

C_VDDL

GND

SGND

S

Minimize the loops of

these caps to mitigate

switching noises

Use Kelvin connection

between low side signal

ground and GND

PGND

图9-9. Typical Schematic with Layout Considerations

9.5.1.1 Solder-Joint Reliability

Large QFN packages can experience high solder-joint stress. TI recommends several best practices to ensure

solder-joint reliability. First, the instructions for the NC1 and NC2 anchor pins found in 表 5-1 must be followed.

Second, all the LMG3522R030 board solder pads must be non-solder-mask defined (NSMD) as shown in the

land pattern example in Mechanical, Packaging, and Orderable Information. Finally, any board trace connected

to an NSMD pad must be less than 2/3 the width of the pad on the pad side where it is connected. The trace

must maintain this 2/3 width limit for as long as it is not covered by solder mask. After the trace is under solder

mask, there are no limits on the trace dimensions. All these recommendations are followed in the Layout

Example.

9.5.1.2 Power-Loop Inductance

The power loop, comprising of the two devices in the half bridge and the high-voltage bus capacitance,

undergoes high di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-

magnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.

Place the power devices as close as possible to minimize the power loop inductance. The decoupling capacitors

are positioned in line with the two devices. They can be placed close to either device. In Layout Examples, the

devices are placed on the bottom layer and the decoupling capacitors are placed on the top layer. The PGND is

Submit Document Feedback

33

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

placed on the top layer, the HVBUS is located on top and third layer, and the switching node is on the top layer.

They are connected to the power devices on bottom layer with vias. Area of traces close to the devices are

minimized by bottom layer in order to keep clearance between heatsink and conductors.

The power loop inductance can be estimated based on the ringing frequency f_ringof the drain-source voltage

switching waveform based on the following equation

1

L

=

(1)

pl

2

4π f

C

ring ring

where C_ringis equal to C_OSSat the bus voltage (refer to 图 6-8 for the typical value) plus the drain-source

parasitic capacitance from the board and load inductor or transformer.

As the parasitic capacitance of load components is hard to character, it's recommended to capture the V_DS

switching waveform without load components to estimate the power loop inductance. Typically, the power loop

inductance of the Layout Example is around 2.5 nH.

9.5.1.3 Signal-Ground Connection

The LMG3522R030's SOURCE pins are internally connected to the power IC signal ground. The return path for

the passives associated to the driver (for example, bypass capacitance) must be connected to the SOURCE

pins. Local signal ground planes must be connected to SOURCE pins with low impedance star connection. In

Layout Examples, local signal ground planes are located on third layer to act as the return path for the local

circuitry, and connected to the SOURCE pins with vias between the third layer and the bottom layer.

9.5.1.4 Bypass Capacitors

The gate drive loop impedance must be minimized to obtain good performance. Although the gate driver is

integrated on package, the bypass capacitance for the driver is placed externally. As the GaN device is turned

off to a negative voltage, the impedance of the path to the external VNEG capacitor is included in the gate drive

loop. The VNEG capacitor must be placed close to VNEG and SOURCE pins. In the 节 9.5.2, the bypass

capacitors , C3 and C13, are located in the top layer and are connected to VNEG pins with vias and SOURCE

pins through the local signal ground plane.

The VDD pin bypass capacitors, C1 and C11, must also be placed close to the VDD pin with low impedance

connections.

9.5.1.5 Switch-Node Capacitance

GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching

losses. To preserve this low switching losses, additional capacitance added to the output node must be

minimized. The PCB capacitance at the switch node can be minimized by following these guidelines:

• Minimize overlap between the switch-node plane and other power and ground planes.

• Make the GND return path under the high-side device thinner while still maintaining a low-inductance path.

• Choose high-side isolator ICs and bootstrap diodes with low capacitance.

• Place the power inductor as close to the GaN device as possible.

• Power inductors must be constructed with a single-layer winding to minimize intra-winding capacitance.

• If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and

the GaN device to effectively shield the GaN device from the additional capacitance.

• If a back-side heat-sink is used, use the least amount of area of the switch-node copper coverage on the

bottom copper layer to improve the thermal dissipation.

9.5.1.6 Signal Integrity

The control signals to the LMG3522R030 must be protected from the high dv/dt caused by fast switching.

Coupling between the control signals and the drain can cause circuit instability and potential destruction. Route

the control signals (IN, FAULT and OC) over a ground plane placed on an adjacent layer. In Layout Example, for

example, all the signals are routed on layers close to the local signal ground plane.

34

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

Capacitive coupling between the traces for the high-side device and the static planes, such as PGND and

HVBUS, could cause common mode current and ground bounce. The coupling can be mitigated by reducing

overlap between the high-side traces and the static planes. For the high-side level shifter, ensure no copper from

either the input or output side extends beneath the isolator or the CMTI of the device can be compromised.

9.5.1.7 High-Voltage Spacing

Circuits using the LMG3522R030 involve high voltage, potentially up to 650 V. When laying out circuits using the

LMG3522R030, understand the creepage and clearance requirements for the application and how they apply to

the GaN device. Functional (or working) isolation is required between the source and drain of each transistor,

and between the high-voltage power supply and ground. Functional isolation or perhaps stronger isolation (such

as reinforced isolation) can be required between the input circuitry to the LMG3522R030 and the power

controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet your

isolation requirements.

If a heat sink is used to manage thermal dissipation of the LMG3522R030, ensure necessary electrical isolation

and mechanical spacing is maintained between the heat sink and the PCB.

9.5.1.8 Thermal Recommendations

The LMG3522R030 is a lateral device grown on a Si substrate. The thermal pad is connected to the source of

device. The LMG3522R030 can be used in applications with significant power dissipation, for example, hard-

switched power converters. In these converter, TI recommends a heat sink connected to the top side of

LMG3522R030. The heat sink can be applied with thermal interface materials (TIMs), like thermal pad with

electrical isolation.

Refer to the High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note for more

recommendations and performance data on thermal layouts.

Submit Document Feedback

35

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

9.5.2 Layout Examples

Correct layout of the LMG3522R030 and its surrounding components is essential for correct operation. The

layouts shown here reflect the GaN device schematic in 图 9-1. These layouts are shown to produce good

results and is intended as a guideline. However, it can be possible to obtain acceptable performance with

alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and

Orderable Information for the latest recommended PCB footprint of the device.

The the top-layer layout, mid-layer and bottom-layer layout are shown. The mid-layer layout includes the outlines

of the top level components to assist the reader in lining up the top-layer and mid-layer layouts.

Minimize the loops of C1,

C3, C11, C13.

Isolation boundary

图9-10. Half-Bridge Top-Layer Layout

Kelvin connections between

Low side signal

Source and signal ground plane

ground plane for

shielding

High side signal

ground plane for

shielding

Minimize the power loop by

using vertical structure and

nearest signal layer for return

图9-11. Half-Bridge Third-Layer (Light Grey) and Bottom-Layer (Dark Grey) Layout

36

Submit Document Feedback

Product Folder Links: LMG3522R030

LMG3522R030

ZHCSQH3 –NOVEMBER 2022

www.ti.com.cn

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

• Texas Instruments, High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note.

• Texas Instruments, A New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-

conditions.

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

FlyBuck^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

Submit Document Feedback

37

Product Folder Links: LMG3522R030

GENERIC PACKAGE VIEW

RQS 52

12 x 12, 0.65 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226769/A

www.ti.com

PACKAGE OUTLINE

RQS0052C

VQFN - 1 mm max height

S

C

A

L

E

1

.

2

0

PLASTIC QUAD FLATPACK - NO LEAD

12.1

11.9

B

A

8.2 0.1

12.1

11.9

PKG SYMM

(0.025)

0.1 MIN

(0.13)

A-A20.000

SECTION A-A

EXPOSED

THERMAL PAD

TYPICAL

(3.535)

7.635 0.1

(11.95)

1.00

0.85

C

SEATING PLANE

0.08 C

0.05

0.00

(12)

0.665

0.565

2X

(0.2)

TYP

0.9

0.8

PKG

52X

4X (0.35)

(0.23)

TYP

17

26

16

27

4X 0.975

1.1

1.0

4X

(2.8)

0.1

C A B

0.05

C

2X 8.45

A

PKG SYMM

26X

0.65

0.45

0.35

46X

0.1

C A B

C

42

1

0.05

4X (0.25)

52

43

PIN 1 ID

16X 0.65

2X 0.758

2X 1.285

2X 5.2

4226861/B 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package incorporates an exposed thermal pad that is designed to be attached directly to an external heat sink. This

optimizes the heat transfer from the integrated circuit (IC).

www.ti.com

EXAMPLE BOARD LAYOUT

RQS0052C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

PKG

(1.05) TYP

SOLDER MASK

OPENING

TYP

2X (0.665)

52

43

42

1

4X (1.1)

46X (0.45)

PKG SYMM

(11.35)

26X (0.65)

4X (0.975)

27

16

17

26

16X (0.65)

2X (3.915)

2X (0.758)

(11.35)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

METAL EDGE

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4226861/B 07/2021

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RQS0052C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (0.665)

PKG

4X (1.05)

43

52

42

4X (1.04)

1

48X (1.05)

46X (0.45)

PKG SYMM

(11.35)

26X (0.65)

4X (0.975)

27

16

26

17

2X (0.758)

16X (0.65)

2X (3.915)

(11.35)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 1, 16, 27 & 42: 95%

SCALE:8X

4226861/B 07/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMG3522R030RQSR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成驱动器、保护和温度报告功能的 650V 30mΩ GaN FET \| RQS \| 52 \| -40 to 150 驱动驱动器
文件：	总44页 (文件大小：3165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMG3522R030RQSR [TI]

相关型号：

LMG3522R030RQST

LMG3526R030

LMG3526R030RQSR

LMG3526R030RQST

LMG5200

LMG5200MOFR

LMG5200MOFT

LMG5278XUFC-00T

LMG6382QHFR

LMG6402PLFR

LMG7400PLFC

LMG7402PLFF