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LMH0318

ZHCSE54 –SEPTEMBER 2015

LMH0318 具有集成电缆驱动器的 3Gbps HD/SD SDI 时钟恢复器

1 特性

2 应用

1

•

支持 ST 424(3G)、292(HD)、259(SD)、MADI 和

DVB-ASI

•

兼容 SMPTE 的串行数字接口 (SDI)

广播视频路由器、交换机和监视器

数字视频处理和编辑

•

锁定至速率 2.97Gbps、1.485Gbps 或相应的

1/1.001 子速率以及 DVB-ASI

DVB-ASI 和分布式放大器

带有快速锁定时间的无参考运行，涵盖所有支持的

或选定的数据速率

3 说明

•

75Ω 和 100Ω 发送器输出

LMH0318 是一款具有集成电缆驱动器的 3Gbps 高清

(HD)/标清 (SD) SDI 时钟恢复器，设计用于驱动兼容

SMPTE-SDI 和 DVB-ASI 标准的串行视频数据。时钟

和数据恢复电路可消除积累的抖动并检测传入数据速

率，无需采用外部基准时钟。具有 75Ω 和 50Ω 输出

的集成驱动器支持多种多媒体选件，如同轴电缆和

FR4 印刷电路板 (PCB)。

集成了 2:1 复用输入，1:2 解复用/扇出输出

基于输入速率检测的自动转换率

片上眼图监视器

功耗仅 300mW，输入信号丢失时自动断电

可通过 SPI 或 SMBus 接口编程

单个 2.5V 电源运行

小型 4mm x 4mm 24 引脚 QFN 封装

工作温度范围：-40℃ 至 85℃

与 LMH1218 引脚兼容，可轻松升级至 12G

器件信息⁽¹⁾

部件号

LMH0318

封装

WQFN (24)

封装尺寸（标称值）

4mm x 4mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化 SPI 电路原理图

VDD

1 KW

0.01 mF

MODE_SEL

ENABLE

6

1

7

21

OUT0+

4.7 mF

OUT

11

IN0+

20

75W T-Line

4.7 mF

FPGA

100W Differential T-Line

12

OUT0-

19

IN0-

DAP

VSS

75W

24

10

LMH0318

VSS

8

OUT

IN1+

IN1-

4.7 mF

IN+

IN-

OUT1+

100W Differential T-Line

4.7 mF

23

FPGA

9

100W Differential T-Line

OUT1-

22

2

3

4

13

15

16

SS_N

SCK

MOSI

LOS_INT_N

MISO

LOCK

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS508

LMH0318

ZHCSE54 –SEPTEMBER 2015

www.ti.com.cn

8.4 Device Functional Modes........................................ 24

8.5 Programming .......................................................... 24

Application and Implementation ........................ 43

9.1 Application Information............................................ 43

9.2 Typical Application ................................................. 43

9.3 Do's and Don'ts....................................................... 48

9.4 Initialization Set Up ................................................. 48

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）............................................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

9

10 Power Supply Recommendations ..................... 48

11 Layout................................................................... 49

11.1 Layout Guidelines ................................................. 49

11.2 Layout Example .................................................... 49

11.3 Solder Profile......................................................... 50

12 器件和文档支持 ..................................................... 51

12.1 器件支持................................................................ 51

12.2 文档支持................................................................ 51

12.3 社区资源................................................................ 51

12.4 商标....................................................................... 51

12.5 静电放电警告......................................................... 51

12.6 Glossary................................................................ 51

13 机械封装和可订购信息 .......................................... 51

7.6 Recommended SMBus Interface AC Timing

Specifications........................................................... 11

7.7 Serial Parallel Interface (SPI) Bus Interface AC

Timing Specifications ............................................... 11

7.8 Typical Characteristics............................................ 12

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

8

4 修订历史记录

日期

修订版本

注释

2015 年 9 月

*

首次发布。

2

LMH0318

www.ti.com.cn

ZHCSE54 –SEPTEMBER 2015

5 说明（续）

LMH0318 的输入端集成了 2 对 1 多路复用器，支持在两个视频源之间进行选择，同时可编程均衡器可以补偿 PC

板损耗，以此延长信号范围。该片上时钟恢复器借助宽范围时钟和数据恢复 (CDR) 电路，在无需外部参考时钟和

环路滤波器组件的情况下，自动检测并锁定 270Mbps 至 2.97Gbps 的串行数据，从而简化了电路板设计并降低了

系统成本。经时钟恢复的串行数据可路由到 75Ω 或 50Ω 发送器输出或同时路由到这两个输出（1 对 2 扇出模

式）。输出电压摆幅兼容 ST 424、344、292 和 259 标准。

非破坏性眼图监视器支持实时测量串行数据，从而简化系统启动或现场调试过程。 LMH0318 与 LMH1218（具有

集成时钟恢复器的 12Gbps 电缆驱动器）引脚兼容。

6 Pin Configuration and Functions

24-Pin WQFN

Package RTWA0024A

(Top View)

VSS

24

VDD

IN1+

IN1-

7

8

23 OUT1+

22 OUT1-

21 VDD

9

DAP = GND

VSS

10

20 OUT0+

19 OUT0-

IN0+ 11

12

IN0-

3

LMH0318

ZHCSE54 –SEPTEMBER 2015

www.ti.com.cn

Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD

NAME

I/O

DESCRIPTION

NO.

CONTROL/INDICATOR I/O

Determines Device Configuration: SPI or SMBus

1 kΩ to VDD:

MODE_SEL

1

Input, 4-Level

Input, 2-Level

•

SPI mode. See Initialization Set Up

SS_N

2

3

4

SPI Slave Select. . This pin has internal pull up

Input, 2.5V

LVCMOS, 2-Level

SCK

SPI serial clock input

MOSI

Input, 2-Level

SPI Master Output / Slave Input. LMH0318 SPI data receive

No Connect

5,14,17,

18

RESERVED

Powers down device when pulled low

1 kΩ to VDD:

•

Power down until valid signal detected

Float(Default):

Reserved

20 kΩ to GND:

Reserved

1 kΩ to GND:

•

ENABLE

6

Input, 4-Level

•

Power down including signal detects and Reset Registers upon

power-up

Output,

LVCMOS Open

Drain, 2-Level

Programmable Interrupt caused by change in LOS, violation of internal

eye monitor threshold, or change in lock. External 4.7-kΩ pull-up resistor

is required. This pin is 3.3 V LVCMOS tolerant.

LOS_INT_N

MISO

13

15

Output, 2.5 V

LVCMOS, 2-Level

SPI Master Input / Slave Output. LMH0318 SPI data transmit

Indicates CDR lock detect status

High:

Output, 2.5V

LVCMOS, 2-Level

LOCK

16

•

CDR locked

Low:

•

CDR not locked

HIGH SPEED DIFFERENTIAL I/O

IN0+

11

12

8

Input, Analog

Inverting and non-inverting differential inputs. An on-chip 100 Ω

terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC

coupling capacitors.

IN0-

IN1+

IN1-

Inverting and non-inverting differential inputs. An on-chip 100 Ω

terminating resistor connects IN1+ to IN1-. Inputs require 4.7 µF AC

coupling capacitors.

9

Output, 75 Ω CML

OUT0+

OUT0-

20

19

Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating

resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC

coupling capacitors

Compatible

Output, 75 Ω CML

Compatible

OUT1+

OUT1-

23

22

Output, Analog

Inverting and non-inverting differential outputs. An on-chip 100 Ω

terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC

coupling capacitors

POWER

VDD

7, 21

2.5 V Supply

Ground

2.5 V ± 5%

VSS

10, 24

Connect directly to ground (GND)

Exposed DAP, connect to GND using at least 5 vias (see 图 23 )

DAP

Ground

4

LMH0318

www.ti.com.cn

ZHCSE54 –SEPTEMBER 2015

Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND

I/O

DESCRIPTION

NAME

NO.

1

Determines Device Configuration: SPI or SMBus

1 kΩ to GND: SMBUS mode. See Initialization Set Up

MODE_SEL

ADDR0

Input, 4-Level

2

4-level strap pins used to set the SMBus address of the device. The pin

state is read on power-up. The multi-level nature of these pins allows for

16 unique device addresses. Note SMBus section for further details. The

four strap options include:

1 kΩ to VDD:

•

Represents logic state 11’b

Input, 4-Level

ADDR1

15

Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17

20 kΩ to GND:

•

Represents logic state 01'b

1 kΩ to GND:

•

Represents logic state 00'b

SMBus clock input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is

required as per SMBus interface standard. This pin is 3.3 V LVCMOS

tolerant.

SCL

3

4

Input, 2-Level

SMBus data input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is

required as per SMBus interface standard. This pin is 3.3 V LVCMOS

tolerant.

I/O, Open Drain, 2-

Level

SDA

5,14,17,

18

RESERVED

No Connect

Powers down device when pulled low

1 kΩ to VDD:

•

Power down until valid signal detected

Float(Default): Reserved

20 kΩ to GND:

ENABLE

6

Input, 4-Level

•

Reserved

1 kΩ to GND:

Power down including signal detects and Reset Registers upon

power-up

•

Output, LVCMOS Programmable Interrupt caused by change in LOS, violation of internal

LOS_INT_N

LOCK

13

16

Open Drain, 2-

Level

eye monitor threshold, change in lock. External 4.7-kΩ pull-up resistor is

required. This pin is 3.3 V LVCMOS tolerant.

Indicates CDR lock Status

High:

Output, 2.5 V

LVCMOS, 2-Level

•

CDR locked

Low:

•

CDR not locked

HIGH SPEED DIFFERENTIAL I/O

IN0+

11

12

8

Input, Analog

Inverting and non-inverting differential inputs. An on-chip 100 Ω

terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC

coupling capacitors.

IN0-

IN1+

IN1-

Inverting and non-inverting differential inputs. An on-chip 100 Ω

terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC

coupling capacitors.

9

Output, 75 Ω CML

OUT0+

OUT0-

20

19

Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating

resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC

coupling capacitors

Compatible

Output, 75 Ω CML

Compatible

OUT1+

OUT1-

23

22

Output, Analog

Inverting and non-inverting differential outputs. An on-chip 100 Ω

terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC

coupling capacitors

VDD

VSS

DAP

7, 21

2.5 V Supply

Ground

2.5V ± 5%

10, 24

Connect directly to ground (GND)

Exposed DAP, connect to GND using at least 5 vias (see 图 23 )

Ground

5

LMH0318

ZHCSE54 –SEPTEMBER 2015

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.5

-30

MAX

2.75

4.0

UNIT

V

Supply Voltage (VDD to GND)

3.3 V Open drain I/O input/output voltage (SDA, SCL, LOS_INT_N)

2.5V LVCMOS Input/Output Voltage

High Speed input Voltage

V

2.75

30

V

High Speed Input Current

mA

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other

conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions

indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum

Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±4500

V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500

V may actually have higher performance.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

2.375

3

TYP

2.5

3.3

40

MAX

2.625

3.6

UNIT

V

Supply voltage⁽¹⁾

3.3 V Open drain I/O input/output voltage⁽¹⁾

Supply noise, 50 Hz to 10 MHz, sinusoidal

Ambient Temperature

V

mVpp

ºC

-40

25

85

1000

400

3.6

Source transmit differential launch amplitude

SMBus clock frequency (SCL) in SMBus slave mode

SMBUS SDA and SCL Voltage Level

SPI Clock Frequency

300

500

100

mV_P-P

kHz

V

10

20

MHz

(1) DC plus AC power should not exceed these limits.

7.4 Thermal Information

RTWA0024A

THERMAL METRIC⁽¹⁾⁽²⁾

UNIT

24 PINS

34

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

31.4

11.8

0.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

11.8

2.7

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient

temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.

6

LMH0318

www.ti.com.cn

ZHCSE54 –SEPTEMBER 2015

7.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

PD

Power dissipation

Locked 75 Ω OUT0 only

(800 mVpp), EOM

powered down

300

195

mW

Locked OUT1 only (600

mVpp, diff), EOM powered

down

Transient power during

CDR lock acquisition, 75 Ω

OUT0 and OUT1 powered

up, EOM powered down

400

195

500

mW

PD_RAW

Power dissipation in force EQ bypass, OUT0

RAW mode (CDR bypass) 720mVpp, OUT1 600mVpp

IN0 to OUT0 and OUT1 or

IN1 to OUT0 and OUT1

IN0 to OUT0, OUT1

powered down

160

80

mW

IN1 to OUT1, OUT0

powered down

4-LEVEL INPUT and 2.5 V LVCMOS DC SPECIFICATIONS

V_IH

High level input voltage

4-level input (MODE_SEL,

ADDR0/1, ENABLE pins)

0.95*VDD

0.67*VDD

0.33*VDD

0.1

V

V_IF

Float level input voltage

4-level input (MODE_SEL,

ADDR0/1, ENABLE pins)

V_I20K

V_IL

20K to GND input voltage 4-level input (MODE_SEL,

ADDR0/1, ENABLE pins)

Low level input voltage

4-level input (MODE_SEL,

ADDR0/1, ENABLE pins)

V_OH

V_OL

I_IH

High level output voltage

Low level output voltage

IOH = -3 mA

IOL = 3 mA

2

V

0.4

15

Input high leakage current V_input= VDD

SPI Mode: LVCMOS

µA

(SPI_SCK, SPI_SS_N)

pins

SMBus Mode: LVCMOS

(SMB_SDA, SMB_SCL)

pins

15

SMBus Mode: 4-Levels

(ADDR0, ADDR1) pins

20

44

80

µA

4-Levels (MODE_SEL,

ENABLE) pins

I_IL

Input low leakage current

Vinput = GND

SPI Mode: LVCMOS

(SPI_MOSI, SPI_SCK)

pins

-15

µA

Vinput = GND

SPI Mode: LVCMOS

(SPI_SS_N) pins

-37

-15

µA

SMBus Mode: LVCMOS

(SMB_SDA, SMB_SCL

pins

SMBus Mode: 4-Levels

(ADDR0, ADDR1) pins

-160

-93

-40

µA

4-Levels (MODE_SEL,

ENABLE) pins

7

LMH0318

ZHCSE54 –SEPTEMBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)

V_IH25

High level input voltage

Low level input voltage

Low level output voltage

Input high current

2.5 V Supply Voltage

1.75

3.6

0.8

0.4

40

V

V_IL

GND

V_OL

IOL = 1.25 mA

V

I_IH

VIN = 2.5 V, VDD = 2.5 V

VIN = GND, VDD = 2.5 V

20

μA

I_IL

Input low current

-10

10

SIGNAL DETECT

S_DH

Signal detect (default)

2.97 Gbps, EQ

22

16

9

mV_P-P

Assert threshold level⁽¹⁾⁽²⁾Pathological Pattern

2.97 Gbps, PLL

Pathological Pattern

2.97 Gbps, PRBS10

Pattern

S_DL

Signal detect (default)

De-assert threshold

level⁽¹⁾

2.97 Gbps EQ

Pathological Pattern

2.97 Gbps, PLL

Pathological Pattern

2.97 Gbps, PRBS10

Pattern

HIGH SPEED RECEIVE RX INPUTS (IN_n+, IN_n-)

R_RD

DC Input differential

resistance

75

100

125

Ω

RL_RX-SDD

Input differential return

loss⁽³⁾⁽⁴⁾

Measured with the device

powered up.

-14

-6.5

-20

dB

SDD11 10 MHz to 2 GHz

SDD11 2 GHz to 3 GHz

RL_RX-SCD

Differential to common

mode Input

Measure with the device

powered up.SCD11, 10

MHz to 3 GHz

conversion⁽³⁾⁽⁴⁾

HIGH SPEED OUTPUTS (OUT_n+, OUT_n-)

V_{VOD_OUT1}

Output differential

voltage⁽³⁾⁽⁴⁾

Default setting, 8T clock

pattern

400

720

600

-9

700

880

mV_P-P

dB

V_{VOD_OUT1_DE}

De-emphasis Level

VOD = 600mV, maximum

De-Emphasis with 16T

clock pattern

V_{VOD_OUT1_CLK}

V_{VOD_OUT0}

Clock output differential

voltage

2.97 GHz,1.485 GHz, and

270 MHz

560

800

100

mV_P-P

Ω

Output single ended

voltage at OUT0+ with

OUT0- terminated⁽⁵⁾⁽³⁾

Default setting

R_{DIFF_OUT1}

DC output differential

resistance

(1) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the

device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.

(2) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal

detect assert condition

(3) These limits are ensured by bench characterization and are not production tested.

(4) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board

(5) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in

75 Ohm.

8

LMH0318

www.ti.com.cn

ZHCSE54 –SEPTEMBER 2015

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_{DIFF_OUT0}

T_{R_F_OUT1}

T_{R_F_OUT0}

DC output single ended

resistance

75

Ω

Output rise/fall time

Full Slew Rate, 20% to

80% using 8T Pattern

45

ps

Output rise/fall time,

2.97 Gbps

1.485 Gbps

270 Mbps

2.97 Gbps

1.485 Gbps

270 Mbps

35

900

3

45

ps

(3)(4)

PRBS15

400

1500

18

T_{R_F_OUT0_delta}

Output rise/fall time

mismatch⁽³⁾⁽⁴⁾

3

18

72

500

V_{OVR_UDR_SHOOT}

Output overshoot,

undershoot^{(3) (4)}

3G/HD/SD Measured with

8T pattern

2.4%

±0.2

20

<10%

V_{DC_OFFSET}

V_{DC_WANDER}

DC offset

3G/HD/SD

V

DC wander

3G/HD/SD EQ

Pathological

mV

RL_{OUT0_S22}

OUT0 single ended 75-Ω

S22 5 MHz to 1.485 GHz

S22 1.485 GHz to 3 GHz

SDD22 10 MHz - 2 GHz

SDD22 2 GHz - 3 GHz

SCC22 10 MHz - 3 GHz

< -15

< -10

-20

dB

return loss^(3)(4)(6)

RL_{OUT1_SDD22}

OUT1 differential 100-Ω

return loss⁽⁴⁾⁽⁷⁾

-17

RL_{OUT1_SCC22}

OUT1 common mode 50-

-11

8

dB

Ω return loss⁽⁴⁾⁽⁷⁾

V_{VCM_OUT1_NOISE}

AC common mode voltage VOD = 0.6 Vpp, DE = 0dB,

mV_RMS

noise⁽⁴⁾

PRBS31, 2.97 Gbps

Reclocked Data

Raw Data

T_{RCK_LATENCY}

T_{RAW_LATENCY}

Latency reclocked

Latency CDR bypass

1.5 UI +195

230

ps

TRANSMIT OUTPUT JITTER SPECIFICATIONS

A_{J_OUT0}

Alignment jitter⁽⁴⁾

OUT0, PRBS15, 2.97

Gbps

0.045

0.06

0.91

UI

T_{J_OUT1}

R_{J_OUT1}

Total jitter (1E-12)⁽⁴⁾

Random jitter (rms)

OUT1, PRBS15 2.97 Gbps

OUT1, PRBS15, 2.97

Gbps

ps_RMS

D_{J_OUT1}

Deterministic jitter

OUT1, PRBS15, 2.97

Gbps

6.8

ps_P-P

(6) Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board

(7) Measure with the device powered up and outputs a clock signal.

9

LMH0318

ZHCSE54 –SEPTEMBER 2015

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Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CLOCK DATA RECOVERY

D_{DATA_RATE}

SMPTE 424⁽⁸⁾

SMPTE 292⁽⁸⁾

SMPTE 259M⁽⁸⁾

2.970

2.967

Gbps

1.485

1.4835

Gbps

Mbps

MHz

270

P_{PLL_BW}

PLL bandwidth at -3 dB

Measured with 0.2UI S_Jat

2.97 Gbps

5

Measured with 0.2UI S_Jat

1.485 Gbps

3

1

MHz

Measured with 0.2UI S_Jat

270 Mbps

J_TOL

Total input jitter tolerance

Lock time⁽³⁾⁽⁹⁾

TJ = D_J+ R_J+ S_J,

D_J+R_J= 0.15 UI

S_J/P_J, low to high upward

sweep (10 kHz to 10 MHz)

0.65

<5

UI

ms

°C

T_LOCK

From signal detected to

the lock asserted,

HEO/VEO lock monitor

disable, same setting for

2.97G, 1.485G and 270

MHz data rates

T_{TEMP_LOCK}

CDR lock with temperature Temperature Lock Range,

ramp

5ºC per minute ramp up

and down, -40ºC to 85ºC

operating range

125

(8) Data rate tolerance is within ±1000 ppm

(9) The total CDR lock time depends on number of rate settings enabled and application data rate

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7.6 Recommended SMBus Interface AC Timing Specifications^(1)(2)(3)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST

MIN

TYP

MAX

UNIT

CONDITIONS

f_SMB

t_BUF

Bus operating frequency

10

100

400

kHz

Bus free time between stop and

start condition

1.3

μs

Hold time after (repeated) start

condition

After this period, the first clock is

generated

t_HD:STA

0.6

μs

Repeated start condition setup

time

t_SU:STA

MODE_SEL = 0

t_SU:STO

t_HD:DAT

t_SU:DAT

t_LOW

t_HIGH

t_F

Stop condition setup time

Data hold time

0.6

0

μs

ns

μs

ns

Data setup time

100

1.3

0.6

Clock low period

Clock high period

50

300

SDA fall time read operation

SDA rise time read operation

t_R

(1) SMBus operation is available 20ms after power up

(2) These specifications support SMBus 2.0 specifications

(3) These Parameters are not production tested

7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications^(1)(2)(3)

Over operating free-air temperature range (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

f _SCK

T_SCK

t_PH

SCK frequency

MODE_SEL = 1

10

20

MHz

ns

μs

ns

SCK period

50

SCK pulse width high

SCK pulse width low

MOSI setup time

MOSI hold time

0.40*T_SCK

t_PL

t_SU

4

t_H

t_SSSu

t_SSH

t_SSOF

t_ODZ

t_OZD

SS_N setup time

SS_N hold time

14

4

18

SS_N off time

1

MISO driven to TRI-STATE time

20

MISO TRI-STATE-to-Driven

time

10

15

ns

t_OD

MISO output delay time

(1) Typical values are parametric norms at VDD = 2.5 V, TA = 25ºC, and recommended operating conditions at the time of product

characterization. Typical values are not production tested.

(2) These specifications support SPI 1.0 specifications.

(3) These Parameters are not production tested

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7.8 Typical Characteristics

Typical device characteristics at T_A= +25°C and VDD = 2.5 V, unless otherwise noted.

图 2. 75 Ω OUT0 PRBS10 at 1.485 Gbps

图 1. 75 Ω OUT0 PRBS10 at 2.97 Gbps

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8 Detailed Description

8.1 Overview

The LMH0318 is a 2.97Gbps/1.485Gbps/0.27Gbps multi-rate serial digital video data reclocker with integrated

cable driver intended for equalizing, reclocking, and driving data compatible to the SMPTE standards. It is a 2-

input, 2-output single-core chip, enabling 1:2 fan-out or 2:1 MUX operations. Each input has a 100 Ω continuous

time linear equalizer (CTLE) at the front-end, intended to compensate for loss over STP coax or FR-4 PCB trace.

The LMH0318 OUT0 is a 75 Ω cable driver compatible to the SMPTE requirements.

The referenceless Clock-and-Data Recovery (CDR) circuit selects between the two inputs based on user choice.

The reclocked output can be driven to one or two outputs. One of the outputs supports 100-Ω differential cable

connection, while the other output can drive a 75 Ω SMPTE specified cable while meeting transmitter

requirements as specified in SMPTE standard. The LMH0318 locks to all required SDI data rates, including

270Mbps, 1.485 Gbps, 1.4835 Gbps, 2.97 Gbps, and 2.967 Gbps. The LMH0318 is assembled in a 4 mm × 4

mm 24-pin QFN package. The chip can be programmed using SPI or SMBus interface.

8.2 Functional Block Diagram

Mux Control

Mute

OUT0(75 ꢀ )

LA

Loss Of

Signal

75 ꢀ BNC

FR4 EQ

100 ꢀ

FPGA/Cross Point

2

Raw

OUT1(100 ꢀ )

Retimed

Clock

FR4 EQ

100 ꢀ

FPGA/Cross Point

100 ꢀ Data or Clock

Mute

CDR

Polarity Control

Loss Of

Signal

Eye

Monitor

VCO

Control Logic Block

Status

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8.3 Feature Description

The LMH0318 data path consists of several key blocks as shown in the Functional Block Diagram. These key

circuits are:

•

Loss of Signal Detector

Continuous Time Linear Equalizer (CTLE) for FR4 Compensation

2:1 Multiplexer/1:2 Fanout

CDR

Eye Monitor

Differential Output Selection

75 Ω and 100 Ω Output Drivers

SMBus/SPI Configuration

8.3.1 Loss of Signal Detector

The LMH0318 supports two high speed differential input ports, with internal 100 Ω terminations. The inputs must

be AC coupled. The external AC coupling capacitor value should take into account the pathological low

frequency content. For most applications, the RC time constant of 4.7 µF AC coupling capacitor plus the 50 Ω

termination resistor is capable of handing the pathological video pattern's low frequency content.

The signal detect circuit is designed to assert when data traffic with a certain minimum amplitude is present at

the input of the device. It is also designed to de-assert, or remain de-asserted, when there is noise below certain

amplitude at the input to the device.

The LMH0318 has two signal detect circuits, one for each input. Each signal detect threshold can be set

independently. By default, both signal detects are powered on. The user selects IN1 or IN0 through SMBus/SPI

interface.

8.3.2 Continuous Time Linear Equalizer (CTLE)

The LMH0318 has receive-side equalization, and a key part is the Continuous Time Linear Equalizer (CTLE).

This circuit operates on the received differential signal and compensates for frequency-dependent loss due to the

transmission media. The CTLE applies gain to the input signal. This gain varies over frequency: higher

frequencies are boosted more than lower frequencies. The CTLE works to restore the input signal to full

amplitude across a wide range of frequencies.

The CTLE consists of 4 stages with each stage having two boost control bits. This allows 256 different boost

settings. CTLE boost levels are determined by summing the boost levels of the 4 stages. The CTLE is configured

manually. See LMH0318 Programming Guide (SNLU183) on how to quickly select the most appropriate CTLE

boost setting.

There are two CTLEs, one for each input, IN0 and IN1. Only one CTLE is enabled at a time, according to the

user input channel selection. If IN0 is selected, the CTLE for IN0 is powered on and the IN1 CTLE is powered

off. The CTLE is able to handle low loss channels without over-equalizing by bypassing the CTLE.

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Feature Description (接下页)

8.3.3 2:1 Multiplexer

A 2:1 input multiplexor connects IN0 and IN1 to the CDR. By default, IN0 is selected. To select IN1, the 2:1

multiplexer must be set. See LMH0318 Programming Guide (SNLU183) for detailed settings.

8.3.4 Clock and Data Recovery

By default, the equalized data is fed into the CDR for clock and data recovery. The CDR consists of a reference-

less Phase Frequency Detector (PFD), Charge Pump (CP), Voltage Controlled Oscillator (VCO), and Output

Data Multiplexer (Mux).

The inputs to the Phase and Frequency Detector (PFD) are the data after the CTLE as well as I and Q clocks

from the VCO. The LMH0318 will attempt to lock to the incoming data by tuning the VCO to phase-lock to the

incoming data rate.

The supported data rates are listed in the following table. See LMH0318 Programming Guide (SNLU183) for

further information on configuring the LMH0318 for different data rates.

表 1. Supported Data Rates

DATA RATE RANGE

2.97 Gbps, 2.967 Gbps

1.485 Gbps, 1.4835 Gbps

270 Mbps

CDR MODE

Enabled

COMMENT

Enabled

125 Mbps

Disabled

At 125 Mbps device is in CDR bypass

8.3.5 Eye Opening Monitor (EOM)

The LMH0318 has an on-chip eye opening monitor (EOM) which can be used to analyze, monitor, and diagnose

the performance of the link. The EOM operates on the post-equalized waveform, just prior to the data sampler.

Therefore, it captures the effects of all the equalization circuits within the receiver before the data is reclocked.

The EOM is operational for 1.485 Gbps and higher data rates.

The EOM monitors the post-equalized waveform in a time window that spans one unit interval and a configurable

voltage range that spans up to ±400 mV differential. The time window and voltage range are divided into 64

steps, so the result of the eye capture is a 64 × 64 matrix of “hits,” where each point represents a specific voltage

and phase offset relative to the main data sampler. The number of “hits” registered at each point needs to be

taken in context with the total number of bits observed at that voltage and phase offset in order to determine the

corresponding probability for that point. The number of bits observed at each point is configurable.

A common measurement performed by the EOM is the horizontal and vertical eye opening. The horizontal eye

opening (HEO) represents the width of the post-equalized eye at 0 V differential amplitude, measured in unit

intervals or picoseconds. The vertical eye opening (VEO) represents the height of the post-equalized eye,

measured midway between the mean zero crossing of the eye. This position in time approximates the CDR

sampling phase.

The resulting 64 × 64 matrix produced by the EOM can be processed by software and visualized in a number of

ways. Two common ways to visualize this data are shown in 图 20 and 图 21. These diagrams depict examples

of an eye monitor plot implemented by software. The first plot is an example of using the EOM data to plot a

basic eye using ASCII characters, which can be useful for simple diagnostics software. The second plot shows

the first derivative of the EOM data, revealing the density of hits and the actual waveforms and crossing that

comprise the eye.

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8.3.6 Fast EOM

Fast EOM is a mechanism that provides an option to read out EOM through SPI/SMBus interfaces by reading

the hits observed for each point of 64 × 64 points matrix. Since SPI interface operates at faster clock rate than

SMBus interface, the SPI master will have to wait until the EOM start bit, reg 0x24[0], goes low. This indicates

EOM samples are available and the SPI master can proceed to read register 0x25 and 0x26. See SPI Fast EOM

Operation and LMH0318 Programming Guide (SNLU183) for further details of Fast EOM operation.

8.3.6.1 SMBus Fast EOM Operation

In SMBus mode, the read on register 0x26 acts as an automatic trigger to read the next EOM count value:

1. Enable EOM (power it on), and set VRANGE=0. Write reg 0x24[7] to 1 to turn on fast EOM

2. Read register 0x25 as burst of 2 bytes (EOM hit count) and discard

3. Read register 0x25 as burst of 2 bytes (EOM hit count) and discard

4. Read register 0x25 as burst of 2 bytes (EOM hit count) and save

5. Perform Step 4 4095 times (64 × 64 cells)

8.3.6.2 SPI Fast EOM Operation

To perform EOM calculation over SPI:

1. Enable EOM (power it on), and set VRANGE=0. Write reg 0x24[7] to 1 to turn on fast EOM

2. Read reg 0x26 to initialize. Discard read data

3. Read Reg 0x24[0] which is EOM start bit. Wait for this bit to go low

4. Read register 0x26 EOM hit count and discard. Read on register 0x26 will automatically trigger the next Fast

Eye calculation

5. Read Reg 0x24[0]. Wait for this bit to go low

6. Do burst read on register 0x25 and 0x26 to get the EOM hit count value.

7. Repeat Steps 5 and 6 4095 times (64 × 64 cells)

8.3.7 LMH0318 Device Configuration

The control pins can be used to configure different operations depending on the functional modes as described

in 表 2.

表 2. Control Pins

FUNCTIONAL MODES

PIN #

1

PIN NAME

SPI

SMBus_Slave

1 kΩ to GND

MODE_SEL

1 kΩ to VDD

SPI_SS_N

SPI_SCK

SPI_MOSI

ENABLE

2

IN_OUT_SEL_SPI_SS_N_ADDR0

EQ_SCL_SCK

ADDR0

3

SMBUS_SCL

SMBUS SDA

ENABLE

4

OUT_CTRL_MOSI_SDA

ENABLE

6

13

15

16

LOS_INT_N

SPI_MISO

LOCK

LOS_INT_N

ADDR1

VOD_MISO_ADDR1

LOCK

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8.3.7.1 MODE_SEL

This pin can be configured in 4 possible ways:

1. 1 kΩ to VDD: This puts the part in SPI mode

2. Float (Default): Reserved

3. 20 kΩ to GND: Reserved

4. 1 kΩ to GND: This puts the part in SMBus mode

8.3.7.2 ENABLE

Normal operation when ENABLE is pulled high, and powers down the device when pulled low.

表 3. ENABLE Selection

ENABLE

1 kΩ to GND

POWER CONDITION

Power down device (signal detectors powered down, registers at reset state)

20 kΩ to GND

Float

Reserved

1 kΩ to VDD

Normal Operation

8.3.7.3 LOS_INT_N

LOS_INT_N pin is an open drain output. When the channel that has been selected cannot detect a signal at the

high-speed input pins (as defined by the assert levels), the pin pulls low. Pin 13 can be configured through share

register 0xFF[5] for interrupt functionality.

In SMBus/SPI mode, this pin can be configured as an interrupt. This pin is asserted low when there is an

interrupt and goes back high when the interrupt status register is read. There are 7 separate masks for different

interrupt sources. These interrupt sources are:

1. If there is a LOS transition on IN0, irrespective of the input channel selected (2 separate masks).

2. If there is a LOS transition on IN1, irrespective of the input channel selected (2 separate masks).

3. HEO or VEO goes below a certain threshold as specified in the registers (1 mask).

4. Lock transition, whether it is asserted or de-asserted – disabled by default (2 mask).

8.3.7.4 LOCK

Indicates the lock status of the CDR. When CDR is locked this pin is asserted high.

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8.3.7.5 SMBus MODE

The SMBus interface can also be used to control the device. If pin 1 (MODE_SEL) is pulled low through 1 kΩ to

GND, then Pins 3, 4 are configured as the SMBUS_SCL and SMBUS_SDA respectively. Pins 2, 15 are address

straps, ADDR0/ADDR1 respectively, during power up.

The maximum operating speed supported on the SMBus pins is 400 kHz.

表 4. SMBus MODE

7-Bit SLAVE

ADDRESS [HEX]

8-Bit WRITE

COMMAND [HEX]

ADDR0

ADDR1

ADDR0 [BINARY]

ADDR1 [BINARY]

1 kΩ to GND

20 kΩ to GND

Float

1 kΩ to GND

20 kΩ to GND

Float

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1A

1C

1E

20

22

24

26

28

2A

2C

2E

30

32

34

36

38

1 kΩ to VDD

1 kΩ to GND

20 kΩ to GND

Float

1 kΩ to VDD

1 kΩ to GND

20 kΩ to GND

Float

1 kΩ to VDD

1 kΩ to GND

20 kΩ to GND

Float

1 kΩ to VDD

Note: These are 7 bit addresses. Therefore, the LSB must be added to indicate read/write. LSB equal to zero

indicates write and 1 indicates SMBus read operation. For example, for 7 bit hex address 0x0D, the I2C hex

address byte is 0x1A to write and 0X1B to read.

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8.3.7.6 SMBus READ/WRITE Transaction

The System Management Bus (SMBus) is a two-wire serial interface through which various system component

chips can communicate with the master. Slave devices are identified by having a unique device address. The

two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the Master to all of the

Slave devices on the bus. SDA is a bidirectional data signal between the Master and Slave devices. The

LMH0318 SMBUS SCL and SDA signals are open drain and require external pull up resistors.

Start and Stop:

The Master generates Start and Stop conditions at the beginning and end of each transaction.

•

Start: High to low transition (falling edge) of SDA while SCL is high

Stop: Low to high transition (rising edge) of SDA while SCL is high

图 3. Start and Stop Conditions

The Master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The

transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the device pulls SDA

low, while a NACK is recorded if the line remains high.

图 4. Acknowledge (ACK)

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Writing data from a master to a slave comprises of 3 parts as noted in figure 图 5

•

The master begins with start condition followed by the slave device address with the R/W bit cleared

The 8-bit register address that will be written

The data byte to write

图 5. SMBus Write Operation

SMBus read operation consists of four parts

•

The master initiates the read cycle with start condition followed by slave device address with the R/W bit

cleared

•

The 8-bit register address that is to be read

After acknowledgment from the slave, the master initiates a re-start condition

The slave device address is resent followed with R/W bit set

After acknowledgment from the slave, the data is read back from the slave to the master. The last ACK is

high if there are no more bytes to read

图 6. SMBus Read Operation

t

LOW

t

HIGH

R

t

HD:STA

SCL

SDA

t

SU:STA

HD:DAT

F

t

BUF

SU:STO

t

SU:DAT

See

*

Note

ST

SP

ST

图 7. SMBus Timing Parameters

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8.3.7.7 SPI Mode

The SPI (Serial Peripheral Interface) bus standard can be used to control the device. The SPI Mode is enabled

when MODE_SEL Pin 1 is pulled high through the 1-kΩ resistor. The SPI bus comprises of 4 pins: Pin 2, Pin 3,

Pin 4, and Pin 15:

1. MOSI Pin 4: Master Output Slave Input. Configured as toggling input.

2. MISO Pin 15: Master Input, Slave Output: Configured as a toggling output

3. SS_N Pin 2: Slave Select (active low). Configured as toggling input.

4. SCK Pin 3: Serial clock (output from master). Configured as toggling input.

The maximum operating speed supported on the SPI bus is 20 MHz.

8.3.7.7.1 SPI READ/WRITE Transaction

Each SPI transaction to a single device is 17 bits long and is framed by SS_N asserted low. The MOSI input is

ignored and the MISO output is floated whenever SS_N is de-asserted (High).

The bits are shifted in left-to-right. The first bit is R/W, so it is 1 for reads and 0 for writes. Bits A7-A0 are the 8-bit

register address, and bits D7-D0 are the 8-bit read or write data. The prior SPI command, address, and data are

shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI transactions,

the MISO output signal is enabled asynchronously when SS_N becomes asserted.

R/W

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

图 8. MOSI Format

8.3.7.7.2 SPI Write Transaction Format

For SPI writes, the R/W bit is 0. SPI write transactions are 17 bits per device, and the command is executed on

the rising edge of SS_N, as shown in 图 9. The SPI transaction always starts on the rising edge of the clock.

图 9. MOSI Write Sequence

0

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

The signal timing for a SPI Write transaction is shown in 图 10. The “prime” values on MISO (for example, A7‟)

reflect the contents of the shift register from the previous SPI transaction, and are a "don’t-care" for the current

transaction.

t_SSOF

SS_N

t_SSH

t

PL

SSSU

PH

SCK

t

H

t

SU

MOSI

MISO

HiZ

D7

A7

A6

A5

A4

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

D0

0

todz

HiZ

R/W'

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

D7'

图 10. Signal Timing for a SPI Write Transaction

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8.3.7.7.3 SPI Read Transaction Format

An SPI read transaction is 34 bits per device consisting of two 17-bit frames. The first 17-bit read transaction,

first frame, shifts in the address to be read, followed by a dummy transaction, second frame, to shift out the 17-

bit read data. The R/W bit is 1 for the read transaction, as shown in 图 11.

The first 17 bits from the read transaction specifies 1-bit of RW and 8-bits of address A7-A0. The eight 1’s

following the address are ignored. The second dummy transaction acts like a read operation on address 0xFF

and needs to be ignored. However, the transaction is necessary in order to shift out the read data D7-D0 in the

last 8 bits of the MISO output.

The signal timing for a SPI read transaction is shown in 图 11. As with the SPI write, the “prime” values on MISO

during the first 16 clocks are a don’t-care for this portion of the transaction. Note, that the values shifted out on

MISO during the last 17 clocks reflect the read address and 8-bit read data for the current transaction.

SS_N

(host)

t

SSOF

t

SSOF

t

SSH

t

PL

SSSU PH

SCK

(host)

t

H

—8X1“

—17X1“

t

SU

MOSI

(host)

1

A7 A6 A5 A4 A3 A2 A1 A0

todz

tod

tozd

MISO

(device)

D

1

D

0

A

0

A

7

A

6

A

5

A

4

A

3

A

2

A

1

D

7

D

6

D

5

D

4

D

3

D

2

Don‘t Care

1

图 11. Signal Timing for a SPI Read Transaction

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8.3.7.8 SPI Daisy Chain

The LMH0318 includes an enhanced SPI controller that supports daisy-chaining the serial configuration data

among multiple LMH0318 devices. The LMH0318 device supports SPI Daisy Chain between devices with an 8-

bit SPI addressing scheme. Each LMH0318 device is directly connected to the SCK and SS_N pins of the Host.

However, only the first LMH0318 device in the chain is connected to the Host’s MOSI pin, and only the last

device in the chain is connected to the Host’s MISO pin. The MOSI pin of each intermediate LMH0318 device in

the chain is connected to the MISO pin of the previous LMH0318 device, thereby creating a serial shift register.

This architecture is shown in 图 12.

MISO

Device 1

Device 2

Device 3

Device N

Host

LMH0318

. . .

MOSI

MISO

MOSI

MISO

MOSI

MISO

MOSI

MISO

SCK

SS

图 12. Daisy-Chain Configuration

In a daisy-chain configuration of N LMH0318 devices, the Host conceptually sees a long shift register of length

17xN. Therefore the length of a Basic SPI Transaction, as described above, is 17xN; in other words, SS_N is

asserted for 17xN clock cycles.

8.3.7.8.1 SPI Daisy Chain Write Example

The following example make some assumptions:

The daisy-chain is 3 LMH0318 devices long, comprising Devices 1, 2, and 3 as shown in 图 12. Therefore, each

Basic SPI Transaction is 17x3 = 51 clocks long.

In 图 13, the following occurs at the end of the transaction:

•

Write 0x5A to register 0x12 in Device 3

Write 0x3C to register 0x34 in Device 2

Write 0x00 to register 0x56 in Device 1

Note that the bits are shifted out of MOSI left to right. The MISO pin is not shown as it reflects shift register

contents from a prior transaction.

MOSI

(Write)

0

0x12

0x5A

0

0x34

0x3C

0

0x56

0x00

图 13. MOSI Write Example

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8.3.7.8.2 SPI Daisy Chain Write Read Example

In 图 14 and 图 15, the following occurs at the end of the first transaction:

•

Write 0x22 to register 0x01 in Device 3

Latch the data from register 0x34 in Device 2

Write 0x44 to register 0x76 in Device 1

MOSI

(Host)

0

0x01

0x22

1

0x34

0xFF

0

0x76

0x44

图 14. SPI Daisy Chain Write Read First Frame Illustration

MOSI

(Host)

1

0

0xFF

0x01

0xFF

0x22

1

0xFF

0x34

0xFF

0x3C

1

0

0xFF

0x76

0xFF

0x44

MISO

(Host)

图 15. SPI Daisy Chain Write Read second Frame Illustration

8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration

A useful operation for the Host may be to detect the length of the daisy-chain. This is a simple matter of shifting

in a series of known data values (0x7F, 0xAA) in the example in 图 16. After N+1 writes, the known data value

will begin to appear on the Host's MISO pin.

MOSI

(Host)

1

x

0x7F

xx

0xAA

xx

1

x

0x7F

xx

0xAA

xx

1

0x7F

0xAA

MISO

(Host)

图 16. MOSI (Host)

8.3.8 Power-On Reset

The LMH0318 has an internal power-on reset (PoR) circuitry which initiates a self-clearing reset after the power

is applied to the VDD pins.

8.4 Device Functional Modes

The LMH0318 features can be programmed via SPI, or SMBus interface. LMH0318 Device Configuration

describes detailed operation using SPI, or SMBus interface.

8.5 Programming

For more information on device programming, See LMH0318 Programming Guide (SNLU183). Register

initialization is required at power-up or after reset. See Initialization Set Up

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8.5.1 Register Maps

The LMH0318 register set definition is organized into four groups:

1. Global Registers: Chip ID, Interrupt status, LOS registers

2. Receiver Registers: Equalizer boost settings and signal detect setting

3. CDR Registers: PLL control

4. Transmitter Registers: OUT0 and OUT1 parameter setting

The typical device initialization sequence for the LMH0318 includes the followings. For detailed register settings

See LMH0318 Programming Guide (SNLU183).

1. Shared Register Configuration

(a) Reading device ID

(b) Selecting interrupt on to LOS pin

(c) Settings up the register to access the channel registers

2. Channel Register Configuration

(a) CDR Reset

(b) Interrupt register configuration

(c) Optional Input/Output selection

(d) Optional VOD selection

(e) CDR Reset and Release

8.5.2 Global Registers

Table 5. Global Registers

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg_0x00 Share

SMBUS_addr3

SMBUS_addr2

SMBUS_addr1

SMBUS_addr0

Reserved

SMBus Observation

0x00

SMBus Address Observation

SMBus strap observation

7

6

5

4

3

2

1

0

R

0

R

0

R

0

RW

Reserved

0

Reserved

0

Reserved

0

Reset Shared Regs

Reg 0x04 Share

Reserved

0x01

0

Shared Register Reset

7

6

RW

rst_i2c_regs

1: Reset Shared Registers

0: Normal operation

0

5

4

3

2

1

0

Reserved

Reg 0x06 Share

Reserved

0

RW

0

1

Enable SMBus Strap

0x00

0

Allow SMBus strap observation

7

6

5

4

RW

0

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Table 5. Global Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

3

2

1

0

Test control[3]

0

RW

Set to >9 to allow strap observation on

share reg 0x00

Test control[2]

Test control[1]

Test control[0]

Reg 0xF0 Share

VERSION[7]

VERSION[6]

VERSION[5]

VERSION[4]

VERSION[3]

VERSION[2]

VERSION[1]

VERSION[0]

Reg 0xFF Control

Reserved

0

Device Version

0x01

Device Version

Device revision

7

6

5

4

3

2

1

0

RW

0

1

Channel Control

0x00

0

Enable Channel Control

7

6

RW

Reserved

0

los_int_bus_sel

1: Selects interrupt onto LOS pin

0: Selects signal detect onto LOS pin

5

0

RW

4

3

Reserved

0

RW

Reserved

en_ch_Access

1: Enables access to channel registers

0: Enables access to share registers

2

0

RW

1

0

Reserved

0

RW

Reserved

Reset_Channel_Regs

Reg_0x00 Channel

Reset all Channel Registers to Default

Values

0x00

7

6

5

4

3

Reserved

Rst_regs

0

1: Reset Channel Registers ( self

clearing )

2

0

0: Normal operation

1

0

Reserved

Reg_0x01 Channel

Reserved

LOS1

0

LOS_status

0x00

Signal Detect Status

7

6

5

4

3

2

0

RW

1: Loss of signal on IN1

0: Signal present on IN1

1

0

R

LOS0

1: Loss of signal on IN0

0: Signal present on IN0

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Table 5. Global Registers (continued)

FIELD REGISTER

REGISTER NAME

CDR_Status_1

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg_0x02 Channel

Reserved

0x00

CDR Status

7

6

5

4

3

2

1

0

R

Reserved

0

Reserved

0

cdr_status[4]

cdr_status[3]

Reserved

0

11: CDR locked

00: CDR not locked

0

Reserved

0

Reserved

0

Interrupt Status Register

Reg 0x54 Channel

Sigdet

0x00

Interrupt Status ( clears upon read )

1: Signal Detect from the selected input

asserted

0: Signal Detect from the selected input

de-asserted

7

0

R

cdr_lock_int

1: CDR Lock interrupt

0: No interrupt from CDR Lock

6

5

4

0

R

signal_det1_int

signal_det0_int

heo_veo_int

1: IN1 Signal Detect interrupt

0: No interrupt from IN1 Signal Detect

1: IN0 Signal Detect interrupt

0: No interrupt from IN0 Signal Detect

1: HEO_VEO Threshold reached

interrupt

3

0

R

0: No interrupt from HEO_VEO

cdr_lock_loss_int

1: CDR loss of lock interrupt

0: No interrupt from CDR lock

2

1

0

R

signal_det1_loss_int

signal_det0_loss_int

1: IN1 Signal Detect loss interrupt

0: No interrupt from IN1 Signal Detect

1: IN0 Signal Detect loss interrupt

0: No interrupt from IN0 Signal Detect

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Table 5. Global Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

Interrupt Mask

ADDRESS

Reg 0x56 Channel

Reserved

Interrupt Control

0x00

0

7

6

RW

cdr_lock_int_en

1: Enable Interrupt if CDR lock is

achieved

0: Disable interrupt if CDR lock is

achieved

0

signal_det1_int_en

signal_det0_int_en

heo_veo_int_en

1: Enable interrupt if IN1 Signal Detect

is asserted

0: Disable interrupt if IN1 Signal Detect

is asserted

5

4

RW

1: Enable interrupt if IN0 Signal Detect

is asserted

0: Disable interrupt if IN0 Signal Detect

is asserted

1: Enable interrupt if HEO-VEO

threshold is reached

0: Disable interrupt due to HEO-VEO

threshold

3

2

1

0

RW

cdr_lock_loss_int_en

1: Enable interrupt if CDR loses lock

0: Disable interrupt if CDR loses lock

signal_det1_loss_int_en

1: Enable interrupt if there is loss of

signal on IN1

0: Disable interrupt if there is loss of

signal on IN1

signal_det0_loss_int_en

1: Enable interrupt if there is loss of

signal on IN0

0: Disable interrupt if there is loss of

signal on IN0

0

RW

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8.5.3 Receiver Registers

Table 6. Receiver Registers

FIELD REGISTER

REGISTER NAME

EQ_Boost

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x03 Channel

4 Stage EQ Boost Levels. Read-back

value going to CTLE in reg_0x52. Used

for setting EQ value when reg_0x2D[3] is

high

0x80

7

6

5

4

3

2

1

0

eq_BST0[1]

eq_BST0[0]

eq_BST1[1]

eq_BST1[0]

eq_BST2[1]

eq_BST2[0]

eq_BST3[1]

eq_BST3[0]

Reg_0x0D Channel

Reserved

1

0

RW

2 Bits control for stage 0 of the CTLE.

Adapts during CTLE adaptation

0

2 Bits control for stage 1 of the CTLE.

Adapts during CTLE adaptation

0

2 Bits control for stage 2 of the CTLE.

Adapts during CTLE adaptation

0

2 Bits control for stage 3 of the CTLE.

Adapts during CTLE adaptation

0

SD_EQ

0x00

0

270 Mbps EQ Boost Setting

7

6

5

4

3

2

1

RW

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Mr_auto_eq_en_bypass

1: EQ Bypass for 270 Mbps

0: Use EQ Settings in reg0x03[7:0] for 270

Mbps

Note: If 0x13[1] mr_eq_en_bypass is set,

bypass would be set and auto-bypass has

no significance.

0

RW

EQ_SD_CONFIG

Reg 0x13 Channel

Reserved

0x90

1

Channel EQ Bypass and Power Down

7

6

RW

sd_0_PD

1: Power Down IN0 Signal Detect

0: IN0 Signal Detect normal operation

0

sd_1_PD

1: Power Down IN1 Signal Detect

0: IN1 Signal Detect normal operation

5

4

0

1

RW

Reserved

eq_PD_EQ

Controls the power-state of the selected

channel. The un-selected channel is

always powered-down

1: Powers down selected channel EQ

stage

3

0

RW

0: Powers up EQ of the selected channel

2

1

0

Reserved

0

RW

eq_en_bypass

1: Bypass stage 3 and 4 of CTLE

0: Enable Stage 3 and 4 of CTLE

Reserved

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Table 6. Receiver Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x14 Channel

Reserved

SD0_CONFIG

0x00

IN0 Signal Detect Threshold Setting

7

6

5

4

3

0

RW

Reserved

sd_0_refa_sel[1]

sd_0_refa_sel[0]

sd_0_refd_sel[1]

sd_0_refd_sel[0]

Controls signal detect S_DH- Assert [5:4],

S_DL- De-Assert [3:2], thresholds for IN0

0000: Default levels (nominal)

0101: Nominal -2 mV

1010: Nominal +5 mV

1111: Nominal +3 mV

2

0

RW

1

0

Reserved

0

RW

Reserved

0

SD1_CONFIG

Reg_0x15 Channel

Reserved

0x00

IN1 Signal Detect Threshold Setting

7

6

5

4

3

0

RW

Reserved

sd_1_refa_sel[1]

sd_1_refa_sel[0]

sd_1_refd_sel[1]

sd_1_refd_sel[0]

Controls signal detect S_DH- Assert [5:4],

S_DL- De-Assert [3:2], thresholds for IN1

0000: Default levels (nominal)

0101: Nominal -2 mV

1010: Nominal +5 mV

1111: Nominal +3 mV

2

0

RW

1

0

Reserved

0

RW

Reserved

0

0x88

1

EQ_BOOST_OV

Reg_0x2D Channel

Reserved

EQ Boost Override

7

6

5

4

RW

Reserved

0

Reserved

0

Reserved

0

reg_eq_bst_ov

1: Enable EQ boost over ride See

LMH0318 Programming Guide (SNLU183)

0: Disable EQ boost over ride

3

1

RW

2

1

0

Reserved

0

RW

Reserved

CTLE Setting

Reg_0x31 Channel

CTLE Mode of Operation and Input/Output

Mux Selection

0x00

0

7

6

Reserved

RW

adapt_mode[1]

adapt_mode[0]

00: Normal Operation - Manual CTLE

Setting

01: Test Mode - See the LMH0318

Programming Guide (SNLU183) for details

Other Settings - Invalid

00

5

4

3

2

1

Reserved

0

RW

Reserved

input_mux_ch_sel[1]

input_mux_ch_sel[0]

IN0/1 and OUT0/1 selection

00: selects IN0 and OUT0/1

01: selects IN0 and OUT0

10: selects IN1 and OUT1

11: selects IN1 and OUT0/1

0

RW

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Table 6. Receiver Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

LOW_RATE_

EQ_BST

Reg 0x3A Channel

HD and SD EQ Level

0x00

7

6

5

4

3

2

1

0

fixed_eq_BST0[1]

fixed_eq_BST0[0]

fixed_eq_BST1[1]

fixed_eq_BST1[0]

fixed_eq_BST2[1]

fixed_eq_BST2[0]

fixed_eq_BST3[1]

fixed_eq_BST3[0]

Reg_0x40 Channel

0

RW

When CTLE is operating in test mode,

Reg 0x3A[7:0] forces fixed EQ setting. In

normal operating manual mode Reg_0x03

forces EQ boost. See LMH0318

Programming Guide (SNLU183) for details

BST_Indx0

Index0 4 Stage EQ Boost. See LMH0318

Programming Guide (SNLU183)

0x00

7

6

5

4

3

2

1

0

I0_BST0[1]

I0_BST0[0]

I0_BST1[1]

I0_BST1[0]

I0_BST2[1]

I0_BST2[0]

I0_BST3[1]

I0_BST3[0]

Reg 0x41 Channel

I1_BST0[1]

I1_BST0[0]

I1_BST1[1]

I1_BST1[0]

I1_BST2[1]

I1_BST2[0]

I1_BST3[1]

I1_BST3[0]

Reg 0x42 Channel

I2_BST0[1]

I2_BST0[0]

I2_BST1[1]

I2_BST1[0]

I2_BST2[1]

I2_BST2[0]

I2_BST3[1]

I2_BST3[0]

0

RW

Index 0 Boost Stage 0 bit 1

Index 0 Boost Stage 0 bit 0

Index 0 Boost Stage 1 bit 1

Index 0 Boost Stage 1 bit 0

Index 0 Boost Stage 2 bit 1

Index 0 Boost Stage 2 bit 0

Index 0 Boost Stage 3 bit 1

Index 0 Boost Stage 3 bit 0

Index1 4 Stage EQ Boost.

Index 1 Boost Stage 0 bit 1

Index 1 Boost Stage 0 bit 0

Index 1 Boost Stage 1 bit 1

Index 1 Boost Stage 1 bit 0

Index 1 Boost Stage 2 bit 1

Index 1 Boost Stage 2 bit 0

Index 1 Boost Stage 3 bit 1

Index 1 Boost Stage 3 bit 0

Index2 4 Stage EQ Boost.

Index 2 Boost Stage 0 bit 1

Index 2 Boost Stage 0 bit 0

Index 2 Boost Stage 1 bit 1

Index 2 Boost Stage 1 bit 0

Index 2 Boost Stage 2 bit 1

Index 2 Boost Stage 2 bit 0

Index 2 Boost Stage 3 bit 1

Index 2 Boost Stage 3 bit 0

0

BST_Indx1

0x40

0

7

6

5

4

3

2

1

0

RW

1

0

BST_Indx2

0x80

1

7

6

5

4

3

2

1

0

RW

0

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Table 6. Receiver Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x43 Channel

I3_BST0[1]

I3_BST0[0]

I3_BST1[1]

I3_BST1[0]

I3_BST2[1]

I3_BST2[0]

I3_BST3[1]

I3_BST3[0]

Reg 0x44 Channel

I4_BST0[1]

I4_BST0[0]

I4_BST1[1]

I4_BST1[0]

I4_BST2[1]

I4_BST2[0]

I4_BST3[1]

I4_BST3[0]

Reg 0x45 Channel

I5_BST0[1]

I5_BST0[0]

I5_BST1[1]

I5_BST1[0]

I5_BST2[1]

I5_BST2[0]

I5_BST3[1]

I5_BST3[0]

Reg 0x46 Channel

I6_BST0[1]

I6_BST0[0]

I6_BST1[1]

I6_BST1[0]

I6_BST2[1]

I6_BST2[0]

I6_BST3[1]

I6_BST3[0]

Reg 0x47 Channel

I7_BST0[1]

I7_BST0[0]

I7_BST1[1]

I7_BST1[0]

I7_BST2[1]

I7_BST2[0]

I7_BST3[1]

I7_BST3[0]

BST_Indx3

0x50

Index3 4 Stage EQ Boost.

Index 3 Boost Stage 0 bit 1

Index 3 Boost Stage 0 bit 0

Index 3 Boost Stage 1 bit 1

Index 3 Boost Stage 1 bit 0

Index 3 Boost Stage 2 bit 1

Index 3 Boost Stage 2 bit 0

Index 3 Boost Stage 3 bit 1

Index 3 Boost Stage 3 bit 0

Index4 4 Stage EQ Boost.

Index 4 Boost Stage 0 bit 1

Index 4 Boost Stage 0 bit 0

Index 4 Boost Stage 1 bit 1

Index 4 Boost Stage 1 bit 0

Index 4 Boost Stage 2 bit 1

Index 4 Boost Stage 2 bit 0

Index 4 Boost Stage 3 bit 1

Index 4 Boost Stage 3 bit 0

Index5 4 Stage EQ Boost.

Index 5 Boost Stage 0 bit 1

Index 5 Boost Stage 0 bit 0

Index 5 Boost Stage 1 bit 1

Index 5 Boost Stage 1 bit 0

Index 5 Boost Stage 2 bit 1

Index 5 Boost Stage 2 bit 0

Index 5 Boost Stage 3 bit 1

Index 5 Boost Stage 3 bit 0

Index6 4 Stage EQ Boost.

Index 6 Boost Stage 0 bit 1

Index 6 Boost Stage 0 bit 0

Index 6 Boost Stage 1 bit 1

Index 6 Boost Stage 1 bit 0

Index 6 Boost Stage 2 bit 1

Index 6 Boost Stage 2 bit 0

Index 6 Boost Stage 3 bit 1

Index 6 Boost Stage 3 bit 0

Index7 4 Stage EQ Boost.

Index 7 Boost Stage 0 bit 1

Index 7 Boost Stage 0 bit 0

Index 7 Boost Stage 1 bit 1

Index 7 Boost Stage 1 bit 0

Index 7 Boost Stage 2 bit 1

Index 7 Boost Stage 2 bit 0

Index 7 Boost Stage 3 bit 1

Index 7 Boost Stage 3 bit 0

7

6

5

4

3

2

1

0

RW

1

0

1

0

BST_Indx4

BST_Indx5

BST_Indx6

BST_Indx7

0xC0

7

6

5

4

3

2

1

0

1

RW

1

0

0x90

7

6

5

4

3

2

1

0

1

0

RW

0

1

0

0x54

0

7

6

5

4

3

2

1

0

RW

1

0

1

0

1

0

0xA0

1

7

6

5

4

3

2

1

0

RW

0

1

0

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Table 6. Receiver Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x48 Channel

I8_BST0[1]

BST_Indx8

BST_Indx9

BST_Indx10

BST_Indx11

BSTIndx12

0xB0

Index8 4 Stage EQ Boost.

7

6

5

4

3

2

1

0

1

RW

0x95

RW

Index 8 Boost Stage 0 bit 1

Index 8 Boost Stage 0 bit 0

Index 8 Boost Stage 1 bit 1

Index 8 Boost Stage 1 bit 0

Index 8 Boost Stage 2 bit 1

Index 8 Boost Stage 2 bit 0

Index 8 Boost Stage 3 bit 1

Index 8 Boost Stage 3 bit 0

Index9 4 Stage EQ Boost.

Index 9 Boost Stage 0 bit 1

Index 9 Boost Stage 0 bit 0

Index 9 Boost Stage 1 bit 1

Index 9 Boost Stage 1 bit 0

Index 9 Boost Stage 2 bit 1

Index 9 Boost Stage 2 bit 0

Index 9 Boost Stage 3 bit 1

Index 9 Boost Stage 3 bit 0

Index10 4 Stage EQ Boost.

Index 10 Boost Stage 0 bit 1

Index 10 Boost Stage 0 bit 0

Index 10 Boost Stage 1 bit 1

Index 10 Boost Stage 1 bit 0

Index 10 Boost Stage 2 bit 1

Index 10 Boost Stage 2 bit 0

Index 10 Boost Stage 3 bit 1

Index 10 Boost Stage 3 bit 0

Index11 4 Stage EQ Boost.

Index 11 Boost Stage 0 bit 1

Index 11 Boost Stage 0 bit 0

Index 11 Boost Stage 1 bit 1

Index 11 Boost Stage 1 bit 0

Index 11 Boost Stage 2 bit 1

Index 11 Boost Stage 2 bit 0

Index 11 Boost Stage 3 bit 1

Index 11 Boost Stage 3 bit 0

Index12 4 Stage EQ Boost.

Index 12 Boost Stage 0 bit 1

Index 12 Boost Stage 0 bit 0

Index 12 Boost Stage 1 bit 1

Index 12 Boost Stage 1 bit 0

Index 12 Boost Stage 2 bit 1

Index 12 Boost Stage 2 bit 0

Index 12 Boost Stage 3 bit 1

Index 12 Boost Stage 3 bit 0

I8_BST0[0]

0

I8_BST1[1]

1

I8_BST1[0]

1

I8_BST2[1]

0

I8_BST2[0]

0

I8_BST3[1]

0

I8_BST3[0]

0

Reg 0x49 Channel

I9_BST0[1]

0X95

7

6

5

4

3

2

1

0

1

I9_BST0[0]

0

I9_BST1[1]

0

I9_BST1[0]

1

I9_BST2[1]

0

I9_BST2[0]

1

I9_BST3[1]

0

I9_BST3[0]

1

Reg 0x4A Channel

I10_BST0[1]

I10_BST0[0]

I10_BST1[1]

I10_BST1[0]

I10_BST2[1]

I10_BST2[0]

I10_BST3[1]

I10_BST3[0]

Reg 0x4B Channel

I11_BST0[1]

I11_BST0[0]

I11_BST1[1]

I11_BST1[0]

I11_BST2[1]

I11_BST2[0]

I11_BST3[1]

I11_BST3[0]

Reg 0x4C Channel

I12_BST0[1]

I12_BST0[0]

I12_BST1[1]

I12_BST1[0]

I12_BST2[1]

I12_BST2[0]

I12_BST3[1]

I12_BST3[0]

0x69

7

6

5

4

3

2

1

0

RW

1

0

1

0

1

0xD5

7

6

5

4

3

2

1

0

1

RW

0

1

0

1

0

1

0x99

1

7

6

5

4

3

2

1

0

RW

0

1

0

1

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Table 6. Receiver Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x4D Channel

I13_BST0[1]

BST_Indx13

0xA5

Index13 4 Stage EQ Boost.

Index 13 Boost Stage 0 bit 1

Index 13 Boost Stage 0 bit 0

Index 13 Boost Stage 1 bit 1

Index 13 Boost Stage 1 bit 0

Index 13 Boost Stage 2 bit 1

Index 13 Boost Stage 2 bit 0

Index 13 Boost Stage 3 bit 1

Index 13 Boost Stage 3 bit 0

Index14 4 Stage EQ Boost.

Index 14 Boost Stage 0 bit 1

Index 14 Boost Stage 0 bit 0

Index 14 Boost Stage 1 bit 1

Index 14 Boost Stage 1 bit 0

Index 14 Boost Stage 2 bit 1

Index 14 Boost Stage 2 bit 0

Index 14 Boost Stage 3 bit 1

Index 14 Boost Stage 3 bit 0

Index15 4 Stage EQ Boost.

Index 15 Boost Stage 0 bit 1

Index 15 Boost Stage 0 bit 0

Index 15 Boost Stage 1 bit 1

Index 15 Boost Stage 1 bit 0

Index 15 Boost Stage 2 bit 1

Index 15 Boost Stage 2 bit 0

Index 15 Boost Stage 3 bit 1

Index 15 Boost Stage 3 bit 0

7

6

5

4

3

2

1

0

1

RW

I13_BST0[0]

0

I13_BST1[1]

1

I13_BST1[0]

0

I13_BST2[1]

0

I13_BST2[0]

1

I13_BST3[1]

0

I13_BST3[0]

1

BST_Indx14

BST_Indx15

Active_EQ

Reg 0x4E Channel

I14_BST0[1]

0xE6

7

6

5

4

3

2

1

0

1

RW

I14_BST0[0]

1

I14_BST1[1]

1

I14_BST1[0]

0

I14_BST2[1]

0

I14_BST2[0]

1

I14_BST3[1]

1

I14_BST3[0]

0

Reg 0x4F Channel

I15_BST0[1]

0xF9

7

6

5

4

3

2

1

0

1

RW

I15_BST0[0]

I15_BST1[1]

1

I15_BST1[0]

1

I15_BST2[1]

1

I15_BST2[0]

0

I15_BST3[1]

0

I15_BST3[0]

1

Reg 0x52 Channel

eq_bst_to_ana[7]

eq_bst_to_ana[6]

eq_bst_to_ana[5]

eq_bst_to_ana[4]

eq_bst_to_ana[3]

eq_bst_to_ana[2]

eq_bst_to_ana[1]

eq_bst_to_ana[0]

Reg 0x55 Channel

Reserved

0x00

0

Active CTLE Boost Setting Read Back

Read-back returns CTLE boost settings

7

6

5

4

3

2

1

0

R

0

EQ_Control

0x00

0

EQ Adaptation Control

7

6

5

4

3

2

R

Reserved

0

RW

Reserved

0

Reserved

0

Reserved

0

Reserved

0

INIT_CDR_SM_4

At power-up, this bit needs to be set to

1'b. See initialization set up

1

0

RW

Reserved

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ZHCSE54 –SEPTEMBER 2015

8.5.4 CDR Registers

Table 7. CDR Registers

REGISTER

NAME

FIELD REGISTER

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x09 Channel

Reserved

Output_Mux_OV

0x00

Output Data Mux Override

7

6

0

RW

Reserved

1: Enable values from 0x1E[7:5] &

0x1C[7:5] to control output mux

0: Register 0x1C[3:2] determines the

output selection

5

Reg_bypass_pfd_ovd

0

RW

4

3

2

1

0

Reserved

Reg 0x0A Channel

Reserved

0

RW

0

CDR_Reset

0x50

0

CDR State Machine Reset

7

6

5

4

RW

1

0

1

1: Enable 0x0A[2] to control CDR Reset

0: Disable CDR Reset

3

2

reg_cdr_reset_ov

reg_cdr_reset_sm

0

RW

1: Enable CDR Reset if 0x0A[3] = 1'b

0: Disable CDR Reset if 0x0A[3] = 1'b

1

0

Reserved

0

RW

Reserved

CDR_Status

Reg 0x0C Channel

reg_sh_status_control[3]

reg_sh_status_control[2]

reg_sh_status_control[1]

reg_sh_status_control[0]

Reserved

0x08

0

CDR Status Control

7

6

5

4

3

2

1

0

RW

Determines what is shown in Reg 0x02.

See LMH0318 Programming Guide

(SNLU183)

0

1

Reserved

0

Reserved

0

Reserved

0

EOM Vrange Setting and EOM Power

Down Control

EOM_Vrange

Reg 0x11 Channel

eom_sel_vrange[1]

0xE0

7

6

Sets eye monitor ADC granularity if

0x2C[6] =0'b

00: 3.125 mV

01: 6.25 mV

10: 9.375 mV

11

RW

eom_sel_vrange[0]

11: 12.5 mV

0: EOM Operational

1: Power down EOM

5

eom_PD

1

4

3

2

1

0

Reserved

0

RW

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Table 7. CDR Registers (continued)

REGISTER

NAME

FIELD REGISTER

ADDRESS

BITS

DEFAULT

R/RW

DESCRIPTION

Full Temperature

Range

Reg 0x16 Channel

0x7A

Temperature Range Setting

7

6

5

4

3

2

1

0

INIT_CDR_SM_27

INIT_CDR_SM_26

INIT_CDR_SM_25

INIT_CDR_SM_24

INIT_CDR_SM_23

INIT_CDR_SM_22

INIT_CDR_SM_21

INIT_CDR_SM_20

Reg 0x23 Channel

0

RW

1

At power-up, this register needs to be set

to 0x25. See initialization set up

0

1

0

HEO_VEO_OV

0x40

1: Enable reg 0x24[1] to acquire HEO/VEO

0: Disable reg 0x24[1] to acquire HEO/VEO

7

eom_get_heo_veo_ov

0

RW

6

5

4

3

2

1

0

Reserved

1

RW

0x00

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

EOM_CNTL

Reg 0x24 Channel

0x00

Eye Opening Monitor Control Register

1: Enable Fast EOM mode

0: Disable fast EOM mode

7

6

fast_eom

Reserved

0

R

1: No zero crossing in the eye diagram

observed

0: Zero crossing in the eye diagram

detected

5

get_heo_veo_error_no_hits

0

R

get_heo_veo_error_no_ope

ning

1: Eye diagram is completely closed

0: Open eye diagram detected

4

0

R

3

2

Reserved

0

R

1: Acquire HEO & VEO(self-clearing)

0: Normal operation

1

0

eom_get_heo_veo

eom_start

0

RW

R

1: Starts EOM counter(self-clearing)

0: Normal operation

EOM_MSB

Reg 0x25 Channel

eom_count[15]

eom_count[14]

eom_count[13]

eom_count[12]

eom_count[11]

eom_count[10]

eom_count[9]

0x00

Eye opening monitor hits(MSB)

7

6

5

4

3

2

1

0

RW

MSBs of EOM counter

eom_count[8]

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Table 7. CDR Registers (continued)

REGISTER

NAME

FIELD REGISTER

ADDRESS

BITS

DEFAULT

R/RW

DESCRIPTION

EOM_LSB

Reg 0x26 Channel

eom_count[7]

eom_count[6]

eom_count[5]

eom_count[4]

eom_count[3]

eom_count[2]

eom_count[1]

eom_count[0]

Reg 0x27 Channel

heo[7]

0x00

Eye opening monitor hits(LSB)

7

6

5

4

3

2

1

0

RW

0

LSBs of EOM counter

Horizontal Eye Opening

0

HEO

0x00

7

6

5

4

3

2

1

0

R

heo[6]

0

heo[5]

0

HEO value. This is measured in 0-63

phase settings. To get HEO in UI, read

HEO, convert hex to dec, then divide by

64.

heo[4]

0

heo[3]

0

heo[2]

0

heo[1]

0

heo[0]

0

VEO

Reg 0x28 Channel

veo[7]

0x00

Vertical Eye Opening

7

6

5

4

3

2

1

0

R

veo[6]

veo[5]

0

This is measured in 0-63 vertical steps. To

get VEO in mV, read VEO, convert hex to

dec, then multiply by 3.125mV

veo[4]

0

veo[3]

0

veo[2]

0

veo[1]

0

veo[0]

0

Auto_EOM _Vrange

Reg 0x29 Channel

Reserved

eom_vrange_setting[1]

0x00

0

EOM Vrange Readback

7

6

RW

R

Auto Vrange readback of eye monitor

granularity

00: 3.125mV

01: 6.25mV

10: 9.375mV

00

5

eom_vrange_setting[0]

11: 12.5mV

4

3

2

1

0

Reserved

0

RW

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Table 7. CDR Registers (continued)

REGISTER

NAME

FIELD REGISTER

ADDRESS

BITS

DEFAULT

R/RW

DESCRIPTION

EOM Hit Timer

EOM_Timer_Thr

Reg 0x2A Channel

eom_timer_thr[7]

eom_timer_thr[6]

eom_timer_thr[5]

eom_timer_thr[4]

eom_timer_thr[3]

eom_timer_thr[2]

eom_timer_thr[1]

eom_timer_thr[0]

Reg 0x2C Channel

Reserved

0x30

7

6

5

4

3

2

1

0

RW

1

EOM timer for how long to check each

phase/voltage setting

0

VEO_Scale

0x32

0

VEO_Scale

7

6

RW

1: Enable Auto VEO scaling

0: VEO scaling based on Vrange Setting

(0x11[7:6])

veo_scale

0

5

4

3

2

1

0

Reserved

1

RW

Reserved

0

Reserved

0

Reserved

1

Reserved

0

HEO VEO Threshold

Reg 0x32 Channel

heo_int_thresh[3]

heo_int_thresh[2]

heo_int_thresh[1]

heo_int_thresh[0]

veo_int_thresh[3]

veo_int_thresh[2]

veo_int_thresh[1]

veo_int_thresh[0]

0x11

0

HEO/VEO Interrupt Threshold

7

6

5

4

3

2

1

0

RW

0

Compares HEO value, 0x27[7:0], vs

threshold 0x32[7:4] * 4

0

1

0

Compares VEO value, 0x28[7:0], vs

threshold 0x32[3:0 * 4

0

1

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Table 7. CDR Registers (continued)

REGISTER

NAME

FIELD REGISTER

ADDRESS

BITS

DEFAULT

R/RW

DESCRIPTION

CDR State Machine

Control

Reg 0x3E Channel

INIT_CDR_SM_3

0x80

1

CDR State Machine Setting

At power-up, this bit needs to be set to 0'b.

See initialization set up

7

RW

6

5

4

3

2

1

0

Reserved

0

RW

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

HEO_VEO_Lock

Reg 0x69 Channel

Reserved

0x0A

0

HEO/VEO Interval Monitoring

7

6

5

4

3

2

1

0

RW

Reserved

0

Reserved

0

Reserved

0

hv_lckmon_cnt_ms[3]

hv_lckmon_cnt_ms[2]

hv_lckmon_cnt_ms[1]

hv_lckmon_cnt_ms[0]

1

While monitoring lock, this sets the interval

time. Each interval is 6.5 ms. At default

condition, HEO_VEO Lock Monitor occurs

once every 65 ms.

0

1

0

CDR State Machine

Control

Reg 0x6A Channel

0x44

CDR State Machine Control

7

6

5

4

3

2

1

0

INIT_CDR_SM_57

INIT_CDR_SM_56

INIT_CDR_SM_55

INIT_CDR_SM_54

INIT_CDR_SM_53

INIT_CDR_SM_52

INIT_CDR_SM_51

INIT_CDR_SM_50

Reg 0xA0 Channel

Reserved

0

1

RW

0

At power-up, this register should be set to

0x00. See initialization set up

0

1

0

SMPTE_Rate_Enable

0x1f

0

SMPTE_Data_Rate_Lock_Restriction

7

6

5

RW

Reserved

0

Reserved

0

1: Enable CDR Lock to 270 Mbps

0: Disable CDR Lock to 270 Mbps

4

3

2

dvb_enable

hd_enable

3G_enable

1

RW

1: Enable CDR Lock to 1.485/1.4835 Gbps

0: Disable CDR Lock to 1.485/1.4835 Gbps

1: Enable CDR Lock to 2.97/2.967 Gbps

0: Disable CDR Lock to 2.97/2.967 Gbps

1

0

Reserved

1

RW

Reserved

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ZHCSE54 –SEPTEMBER 2015

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8.5.5 Transmitter Registers

Table 8. Transmitter Registers

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

OUT0 Mux Selection

ADDRESS

Reg 0x1C Channel

pfd_sel0_data_mux[2]

pfd_sel0_data_mux[1]

pfd_sel0_data_mux[0]

Out0_Mux_Select

0x18

7

6

0

RW

When 0x09[5] = 1'b OUT0 Mux

Selection can be controlled as follows:

000: Mute

001: 10 MHz Clock

010: Raw Data

100: Retimed Data

5

0

RW

Other Settings - Invalid

vco_clk_sel

When 0x09[5] = 1'b and 0x1E[[7:5] =

101'b OUT1 clock selection can be

controlled as follows:

1: OUT1 puts out line rate clock

0: OUT1 puts out 10MHz clock

4

3

1

RW

mr_drv_out_ctrl[1]

mr_drv_out_ctrl[0]

Controls both OUT0 and OUT1:

00:

OUT0: Mute

OUT1: Mute

01:

OUT0: Locked Reclocked Data /

Unlocked Raw Data

OUT1: Locked Output Clock / Unlocked

Mute

2

0

RW

10:

OUT0: Locked Reclocked Data /

Unlocked RAW

OUT1: Locked Reclocked Data /

Unlocked Raw

11:

OUT0: Forced Raw

OUT1: Forced Raw

1

0

Reserved

0

RW

Reserved

OUT1_Mux_Select

Reg 0x1E Channel

pfd_sel_data_mux[2]

pfd_sel_data_mux[1]

pfd_sel_data_mux[0]

0xE9

1

OUT1 Mux Selection

7

6

RW

When 0x09[5] = 1'b OUT0 Mux

Selection can be controlled as follows:

111: Mute

101: 10MHz Clock if reg 0x1c[4]=0 and

full rate clock if reg 0x1c[4] = 1

010: Full Rate Clock

1

5

1

RW

001: Retimed Data

000: Raw Data

Other Settings - Invalid

4

3

2

1

0

Reserved

0

1

0

1

RW

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ZHCSE54 –SEPTEMBER 2015

Table 8. Transmitter Registers (continued)

FIELD REGISTER

REGISTER NAME

OUT1 Invert

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Reg 0x1F Channel

pfd_sel_inv_out1

0x10

0

Invert OUT1 Polarity

1: Inverts OUT1 polarity

0: OUT1 Normal polarity

7

RW

6

5

4

3

2

1

0

Reserved

0

RW

Reserved

1

Reserved

0

Reserved

0

Reserved

0

Reserved

0

OUT0_VOD

Reg 0x80 Channel

drv_0_sel_vod[3]

drv_0_sel_vod[2]

drv_0_sel_vod[1]

drv_0_sel_vod[0]

0x54

0

OUT0 VOD_PD

7

6

5

RW

Controls OUTDriver 0 VOD Setting

0011: Nominal - 10%

0100: Nominal - 5%

0101: Nominal 800 mV

0110: Nominal + 5%

0111: Nominal + 10%

Other Settings - Invalid

1

0

4

1

RW

3

2

Reserved

0

1

RW

Reserved

mr_drv_0_ov

1: Enable 0x80[0] to override pin/sm

control

1

0

RW

0: Disable 0x80[0] to override pin/sm

control

sm_drv_0_PD

1: Power down OUT0

0: OUT1 in normal operating mode

OUT1_VOD

Reg 0x84 Channel

Reserved

0x04

OUT1 VOD Control

7

6

5

0

RW

drv_1_sel_vod[2]

drv_1_sel_vod[1]

drv_1_sel_vod[0]

OUTDriver1 VOD Setting

000: 570 mVDifferential(Diff) Peak to

Peak(PP)

010: 730 mV(Diff PP)

100: 900 mV(Diff PP)

110: 1035 mV(Diff PP)

4

3

0

RW

Reserved

drv_1_sel_scp

1: Enables short circuit protection on

OUT1

2

1

RW

0: Disable short circuit protection on

OUT1

mr_drv_1_ov

sm_drv_1_PD

1: Enable 0x80[0] to override pin/sm

control

0: Disable 0x80[0] to override pin/sm

control

1

0

RW

1: Power down OUT1 driver

0: OUT1 in normal operating mode

OUT1_DE

Reg 0x85

Reserved

0x00

OUT1 DE Control

7

6

5

4

0

RW

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ZHCSE54 –SEPTEMBER 2015

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Table 8. Transmitter Registers (continued)

FIELD REGISTER

REGISTER NAME

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

drv_1_dem_range

drv_1_dem[2]

3

2

1

0

RW

Controls de-emphasis of 50 Ω Driver

0000: DE Disabled

0001: 0.2 dB

drv_1_dem[1]

0010: 1.8 dB

.........

0111: 11 dB

drv_1_dem[0]

0

RW

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ZHCSE54 –SEPTEMBER 2015

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMH0318 is a single channel SDI reclocker with integrated cable driver that supports different application

spaces. The following sections describe the typical use cases and common implementation practices.

9.1.1 General Guidance for All Applications

The LMH0318 supports two modes of configuration: SPI Mode, and SMBus Mode. Once one of these two control

mechanism is chosen, pay attention to the PCB layout for the high speed signals. The LMH0318 has strong

equalization capabilities that allow it to recover data over lossy channels. As a result, the optimal placement for

the LMH0318 is with the higher loss channel at its input and lower loss channel segment at the output in order to

meet the various SMPTE requirements. The SMPTE specifications also define the use of AC coupling capacitors

for transporting uncompressed serial data streams with heavy low frequency content. This specification requires

the use of a 4.7 µF AC coupling capacitor to avoid low frequency DC wander. The 75 Ω signal is also required to

meet certain rise/fall timing to facilitate highest eye opening for the receiving device. The LMH0318 built-in 75 Ω

termination minimizes parasitic, improving overall signal integrity. Note: When the FPGA is not transmitting valid

SMPTE data, the FPGA output should be muted (P=N).

9.2 Typical Application

VDD

1 KW

0.01 mF

MODE_SEL

0.01 mF

ENABLE

6

1

7

21

OUT0+

4.7 mF

OUT

11

IN0+

20

75W T-Line

4.7 mF

FPGA

100W Differential T-Line

12

OUT0-

19

IN0-

DAP

VSS

75W

24

10

LMH0318

VSS

8

OUT

IN1+

IN1-

4.7 mF

IN+

IN-

OUT1+

100W Differential T-Line

4.7 mF

23

FPGA

9

100W Differential T-Line

OUT1-

22

2

3

4

13

15

16

SS_N

SCK

MOSI

LOS_INT_N

MISO

LOCK

图 17. LMH0318 SPI Mode Configuration

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ZHCSE54 –SEPTEMBER 2015

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Typical Application (接下页)

SMPTE specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, 3Gb/s and

higher data rates over coaxial cables. One of the requirements is meeting the required return loss. This

requirement specifies how closely the port resembles 75 Ω impedance across a specified frequency band.

Output return loss is dependent on board design. The LMH0318 meets this requirement. To gain additional

return loss margin, a return loss network, as shown in 图 18, can be used on the output .

VDD

1 KW

0.01 mF

3.3 nH

MODE_SEL

0.01 mF

ENABLE

6

1

7

21

OUT0+

4.7 mF

75 W

OUT

11

IN0+

20

75W T-Line

75 W

FPGA

100W Differential T-Line 4.7 mF

12

OUT0-

19

IN0-

75 W

DAP

VSS

3.3 nH

24

10

LMH0318

VSS

8

OUT

IN1+

IN1-

4.7 mF

IN+

IN-

OUT1+

4.7 mF

100W Differential T-Line

23

FPGA

9

100W Differential T-Line

OUT1-

22

2

3

4

13

15

16

SS_N

SCK

MOSI

LOS_INT_N

MISO

LOCK

图 18. LMH0318 SPI Mode Configuration with Return Loss Network

9.2.1 Design Requirements

For the LMH0318 design example, the requirements noted in 表 9 apply.

表 9. LMH0318 Design Parameters

DESIGN PARAMETER

REQUIREMENT

Required. 4.7 µF AC coupling capacitors are recommended.

Capacitors may be implemented on the PCB or in the connector.

Input AC coupling capacitors

Required. Both OUT0 and OUT1 require AC coupling capacitors.

OUT0 AC Coupling capacitors is expected to be 4.7 µF to comply

with SMPTE wander requirement.

Output AC coupling capacitors

To minimize power supply noise, use 0.01 µF capacitors as close to

the device VDD pins as possible.

DC Power Supply Coupling Capacitors

Distance from Device to BNC

Keep this distance as short as possible.

Design differential trace impedance of IN0, IN1, and OUT1 with 100

Ω ± 5%, single-ended trace impedance for OUT0 with 75 Ω ± 5%

High Speed IN0, IN1, OUT0, and OUT1 trace impedance

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ZHCSE54 –SEPTEMBER 2015

VDD

MODE_SEL

0.01 mF

1 KW

0.01 mF

ENABLE

1

6

7

21

4.7 mF

OUT

11

12

OUT0+

IN0+

20

19

75W T-Line

4.7 mF

100W Differential T-Line

4.7 mF

FPGA

OUT0-

IN0-

DAP

VSS

75W

LMH0318

24

10

VSS

8

9

OUT

IN1+

IN1-

4.7 mF

IN+

OUT1+

FPGA

4.7 mF

100W Differential T-Line

23

FPGA

100W Differential T-Line

IN-

OUT1-

22

2

15

3

4

13

16

ADDR0

ADDR1

SCL

SDA

LOS_INT_N

LOCK

图 19. LMH0318 SMBus Mode Configuration

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ZHCSE54 –SEPTEMBER 2015

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

1. Maximum power draw for PCB regulator selection. In this case, use the transient CDR power (during

acquisition) specified in the datasheet, multiplied by the number of channels.

2. Maximum operational power for thermal calculation. For thermal calculation, use the locked power number.

Transient power consumption is only observed during lock acquisition, which typically lasts for <5ms.

Additional margin can be applied in case of unsupported data rates being applied which extend the lock time.

Note that the CDR should operate in bypass mode for any unsupported data rates.

3. Consult the BNC vendor for optimum BNC landing pattern.

4. Use IBIS-AMI model for simple channel simulation before PCB layout.

5. Closely compare schematic against typical connection diagram in the data sheet.

6. Plan out the PCB layout and component placement to minimize parasitic.

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9.2.3 Application Curves

Two common ways to visualize this data are shown in 图 20 and 图 21. These diagrams depict examples of eye

monitor plot implemented by software. The first plot is an example of using the EOM data to plot a basic eye

using ASCII characters, which can be useful for simple diagnostics software. The second plot shows the first

derivative of the EOM data, revealing the density of hits and the actual waveforms and crossing that comprise

the eye. Measurements were done at default operating conditions.

图 20. Internal Input Eye Monitor Plot at 2.97 Gbps,

PRBS10

图 21. Internal Eye Monitor Hit Density Plot at 2.97 Gbps,

PRBS10

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9.3 Do's and Don'ts

In order to meet SMPTE standard requirements for jitter, AC timing, and return loss use the following guidelines:

1. Do place BNC as close to the device as possible.

2. Do consult BNC vendor to provide optimum landing pad for the BNC to comply with the required

specifications.

3. Place return loss network as close to the device as possible.

4. Do pay attention to the recommended solder paste to ensure reliable GND connection to DAP.

5. Do use control impedance for both 100 Ω and 75 Ω for IN0/1 and OUT0/1.

9.4 Initialization Set Up

After power up or register reset write the initialization sequences in 表 10.

表 10. LMH0318 Register Initialization

DESCRIPTION

ADDRESS [Hex]

0xFF

VALUE [Hex]

0x04

Enable Channel Registers

Enable Full Temperature Range

0x16

0x25

0x3E

0x00

Initialize CDR State Machine Control

0x55

0x02

0x6A

0x00

(2)

Restore media CTLE setting⁽¹⁾

Reset CDR

0x03

xx

0x0A

0x5C

0x50

Release Reset

0x0A

(1) See LMH0318 Programming Guide (SNLU183) on how to quickly select the most appropriate CTLE boost setting.

(2) xx Value depends on media loss characteristics

10 Power Supply Recommendations

Follow these general guidelines when designing the power supply:

1. The power supply should be designed to provide the recommended operating conditions in terms of DC

voltage, AC noise, and start-up ramp time.

2. The maximum current draw for the LMH0318 is provided in the data sheet. This figure can be used to

calculate the maximum current the supply must provide. Current consumption can be derived from the typical

power consumption specification in the data sheet.

3. The LMH0318 does not require any special power supply filtering, provided the recommended operating

conditions are met. Only standard supply decoupling is required.

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11 Layout

11.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Set trace impedances to 75 Ω ± 5% single ended, 100 Ω ± 5% differential.

2. Maintain the same signal reference plane for 75 Ω single-end trace, and reference plane for 100 Ω

differential traces.

3. Use the smallest size surface mount components.

4. Use solid planes. Provide GND or VDD relief under the component pads to minimize parasitic capacitance.

5. Select trace widths that minimize the impedance mismatch along the signal path.

6. Select a board stack-up that supports 75 Ω or 50 Ω single-end trace, 100 Ω coupled differential traces.

7. Use surface mount ceramic capacitors.

8. Place return loss network as close to the device as possible.

9. Maintain symmetry on the complimentary signals.

10. Route 100 Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).

11. Avoid sharp bends; use 45-degree or radial bends.

12. Walk along the signal path, identify geometry changes and estimate their impedance changes.

13. Maintain 75 Ω impedance with a well-designed connectors’ footprint.

14. Consult a 3-D simulation tool to guide layout decisions.

15. Use the shortest path for VDD and Ground hook-ups; connect pin to planes with vias to minimize or

eliminate trace.

16. When a high speed trace changes layer, provide at least 2 return vias to improve current return path.

11.2 Layout Example

The following example layout demonstrates how the thermal pad should be laid out using standard WQFN board

routing guidelines.

Note: Thermal pad is divided into 4 squares with solder paste

图 22. LMH0318 Recommended Four Squares Solder Paste

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ZHCSE54 –SEPTEMBER 2015

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Layout Example (接下页)

5 Vias without solder paste are located between 4 squares solder paste

图 23. LMH0318 Recommended Solder Paste Mask and vias

Top etch plus traces

图 24. Example Layout

11.3 Solder Profile

The LMH0318 RTW024A Package solder profile and solder paste material can be found at the following link:

SNOA401

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LMH0318

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12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

如需支持，请访问以下网站：

•

TI 工程师 (E2E) 社区：http://e2e.ti.com/

E2E 社区高速接口论坛：http://e2e.ti.com/support/interface/high_speed_interface/

12.2 文档支持

12.2.1 相关文档ꢀ


型号：	LMH0318RTWT
厂家：	TEXAS INSTRUMENTS
描述：	具有集成电缆驱动器的 3G HD/SD SDI 时钟恢复器 \| RTW \| 24 \| -40 to 85 时钟驱动驱动器
文件：	总57页 (文件大小：1214K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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