LMH0356SQ-40/NOPB [TI]
具有 4:1 输入多路复用器和 FR4 均衡器的 3G HD/SD SDI 时钟恢复器 | RSB | 40 | -40 to 85;
| 型号： | LMH0356SQ-40/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 4:1 输入多路复用器和 FR4 均衡器的 3G HD/SD SDI 时钟恢复器 | RSB | 40 | -40 to 85 时钟 商用集成电路 复用器 |
| 文件： | 总30页 (文件大小：1024K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH0356
SNLS270L –AUGUST 2007–REVISED JANUARY 2016
LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs
1 Features
3 Description
The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1
Input Mux and FR4 EQs retimes serial digital video
data conforming to the SMPTE ST-424, ST-292, and
ST-259 standards. The LMH0356 operates at serial
data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps,
2.967 Gbps, and 2.97 Gbps. The LMH0356 supports
DVB-ASI operation at 270 Mbps. The LMH0356
includes an integrated 4:1 input multiplexer for
selecting one of four input data streams for retiming.
In addition, the four inputs of the LMH0356 each have
an FR4 equalizer capable of equalizing 0 to 30 inches
of FR4 trace length.
1
•
Supports SMPTE ST-424, ST-292, and ST-259
Serial Digital Video Standards
•
Supports 270-Mbps, 1.483-Gbps, 1.485-Gbps,
2.967-Gbps, and 2.97-Gbps Serial Data Rate
Operation
•
•
•
•
•
Supports DVB-ASI at 270 Mbps
Single 3.3-V Supply Operation
430-mW Typical Power Consumption
Integrated 4:1 Multiplexed Input
0 to 30-inch FR4 Equalizer on Each Multiplexed
Input
The LMH0356 automatically detects the incoming
data rate and adjusts itself to retime the incoming
data to suppress accumulated jitter. The LMH0356
recovers the serial data-rate clock and optionally
provides it as an output. The LMH0356 has two
differential serial data outputs; the second output may
be selected as a low-jitter, data-rate clock output.
Controls and indicators are: serial clock or second
serial data output select, manual rate select input,
SD/HD rate indicator output, lock detect output,
auto/manual data bypass, output mute, and device
enable. The serial data inputs, outputs, and serial
clock outputs are differential LVPECL compatible.
The CML serial data and serial clock outputs are
suitable for driving 100-Ω differentially terminated
networks. The control logic inputs and outputs are
LVCMOS compatible.
•
•
Two Differential, Reclocked Outputs
Choice of Second Reclocked Output or
Recovered Clock Output
•
Single 27-MHz External Crystal or Reference
Clock Input
•
•
•
•
•
•
Manual Rate Select Input
SD/HD Operating Rate Indicator Output
Lock Detect Indicator Output
Output Mute Function for Data and Clock
Auto/Manual Reclocker Bypass
Power Saver Mode With Device Power-Down
Control (10-mW Typical Power Consumption in
Disabled State)
•
Differential LVPECL-Compatible Serial Data
Inputs and Outputs
Device Information(1)
PART NUMBER
PACKAGE
WQFN (40)
WQFN (48)
BODY SIZE (NOM)
5.00 mm x 5.00 mm
7.00 mm x 7.00 mm
•
•
•
•
LVCMOS Control Inputs and Indicator Outputs
48-Pin WQFN or 40-Pin WQFN Package
Industrial Temperature Range: –40°C to 85°C
LMH0356
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
48-Pin WQFN Version Footprint-Compatible with
the LMH0056 and LMH0036
Functional Block Diagram
2 Applications
SCO_EN
HD
SD/
BYPASS/
AUTO BYPASS
RATE0
CONTROL LOGIC
LOCK DETECT
•
SDTV/HDTV and 3-Gbps Serial Digital Video
Interfaces for:
RATE1
ENABLE
V
CCO
BYPASS
50
–
–
Digital Video Routers and Switchers
50
XTAL IN/EXT CLK
SCO/SDO2
SCO/SDO2
XTAL OUT
LOOP FILTER 1
Digital Video Processing and Editing
Equipment
VCO / PLL
LOOP FILTER 2
O/P MUTE
V
CCO
–
–
DVB-ASI Equipment
SDI0
SDI0
EQUALIZER
50
Video Standards and Format Converters
50
SDI1
SDI1
EQUALIZER
EQUALIZER
EQUALIZER
SDO
SDO
RETIMER / FIFO
SDI2
SDI2
SDI3
SDI3
SEL0
SEL1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH0356
SNLS270L –AUGUST 2007–REVISED JANUARY 2016
www.ti.com
Table of Contents
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes ....................................... 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ..................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 DC Electrical Characteristics .................................... 7
7.6 AC Electrical Characteristics..................................... 8
7.7 AC Timing Requirements.......................................... 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
9
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1 Community Resources.......................................... 21
12.2 Trademarks........................................................... 21
12.3 Electrostatic Discharge Caution............................ 21
12.4 Glossary................................................................ 21
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (April 2013) to Revision L
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes
section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ............................. 1
2
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SNLS270L –AUGUST 2007–REVISED JANUARY 2016
5 Description (continued)
The LMH0356 is powered from a single 3.3-V supply. Power dissipation is typically 430 mW. The device is
available in two space-saving packages: a 7-mm x 7-mm, 48-pin WQFN and even more space-efficient
5-mm x 5-mm, 40-pin WQFN package.
6 Pin Configuration and Functions
RHS Package
48-Pin WQFN
Top View
48
47
46
45
44
43
42
41
40
39
38
37
SDI0
SDI0
1
2
36
35
34
33
32
31
30
29
28
27
26
25
SD/HD
V
CC
3
V
V
CC
CC
SDI1
SDI1
SDO
SDO
4
5
V
6
CC
V
V
CC
LMH0356SQ
(top view)
SDI2
7
CC
SCO/SDO2
SCO/SDO2
8
SDI2
ENABLE
9
V
EE
SDI3
SDI3
10
11
12
V
EE
V
EE
V
CC
13
14
15
16
17
18
19
20
21
22
23
24
The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the
negative power supply voltage.
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RSB Package
40-Pin WQFN
Top View
40
39
38
37
36
35
34
33
32
31
SDI0
SDI0
V
V
1
2
30
29
28
27
26
25
24
23
22
21
CC
CC
SDO
SDO
3
V
CC
SDI1
4
5
V
CC
SDI1
SDI2
LMH0356SQ-40
(top view)
SCO/SDO2
6
7
SCO/SDO2
LOCK DET
NC
SDI2
ENABLE
SDI3
8
9
NC
10
SDI3
11
12
13
14
15
16
17
18
19
20
The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the
negative power supply voltage.
Pin Functions
PIN
DESCRIPTION
WQFN
48 PIN
WQFN
40 PIN
NAME
BYPASS/
AUTO BYPASS
15
14
Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has
an internal pulldown.
ENABLE
LF1
9
8
Device Enable. Powers down device when low. This pin has an internal pullup.
43
44
24
16
35
36
23
15
Loop Filter.
LF2
Loop Filter.
LOCK DETECT
OUTPUT MUTE
PLL Lock Detect output (active high).
Data and Clock Output Mute input. Mutes the output when low. This pin has an
internal pullup.
RATE0
45
46
28
29
37
37
38
24
25
32
Data Rate select input. This pin has an internal pulldown.
Data Rate select input. This pin has an internal pulldown.
Serial Clock or Serial Data Output 2 Complement.
Serial Clock or Serial Data Output 2 True.
RATE1
SCO/SDO2
SCO/SDO2
SCO_EN
Serial Clock or Serial Data 2 Output select. Sets second output to output the
clock when high and the data when low. This pin has an internal pulldown.
SD/HD
36
31
Data Rate Range output. Output is high for SD and low for HD or 3G.
4
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Pin Functions (continued)
PIN
DESCRIPTION
WQFN
48 PIN
WQFN
40 PIN
NAME
SDI0
SDI0
SDI1
SDI1
SDI2
SDI2
SDI3
SDI3
SDO
SDO
SEL0
SEL1
1
2
1
2
Data Input 0 True.
Data Input 0 Complement.
Data Input 1 True.
4
4
5
5
Data Input 1 Complement.
Data Input 2 True.
7
6
8
7
Data Input 2 Complement.
Data Input 3 True.
10
11
32
33
47
48
9
10
27
28
39
40
Data Input 3 Complement.
Data Output Complement.
Data Output True.
Data Input select input. This pin has an internal pulldown.
Data Input select input. This pin has an internal pulldown.
3, 6, 12, 14,
30, 31, 34,
35,
3, 11, 13, 26,
29, 30
VCC
Positive power supply input.
DAP, 13, 17,
19, 20, 21,
23, 25, 26,
27, 38, 39,
40, 41, 42
12, 17, 18,
20, 33, 34
VEE
Negative power supply input.
XTAL IN/EXT CLK
XTAL OUT
NC
18
22
—
16
19
Crystal or External Oscillator input.
Crystal Oscillator output.
No connect.
21, 22
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SNLS270L –AUGUST 2007–REVISED JANUARY 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage (VCC – VEE
)
4
v
Logic supply voltage
VEE – 0.15
VCC + 0.15
V
Vi = VEE – 0.15 V
Vi = VCC + 0.15 V
–5
Logic input current (single input)
mA
5
Logic output voltage
VEE – 0.15
–8
VCC + 0.15
V
Logic output source/sink current
Serial data output sink current
Junction temperature (TJ)
8
mA
mA
°C
24
125
150
Storage temperature (Tstg
)
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
V(ESD)
Electrostatic discharge
±1250
±400
V
Machine model (MM)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1250 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3 – 5%
VEE
NOM
MAX
3.3 + 5%
VCC
UNIT
V
Supply voltage
Logic input voltage
V
Differential serial input voltage
Serial data or clock output sink current
Operating free-air temperature
800 – 10%
800 + 10%
16
mV
mA
°C
–40
85
7.4 Thermal Information
LMH0356
THERMAL METRIC(1)
RHS (WQFN)
RSB (WQFN)
40 PINS
31.2
UNIT
48 PINS
28.3
8.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJC(bot)
16.8
1.3
1.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6
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7.5 DC Electrical Characteristics
over supply voltage and recommended operating temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
Logic input voltage high level
Logic input voltage low level
Logic input current high level
Logic input current low level
Logic output voltage high level
Logic output voltage low level
Serial input voltage, differential
Input common mode voltage
2
VCC
0.8
65
VIL
VEE
V
IIH
VIH = VCC
47
µA
µA
V
IIL
VIL = VEE
−18
−25
VOH
VOL
VSDID
VCMI
IOH = −2 mA
IOL = 2 mA
2
VEE + 0.6
1600
V
(3)
SDI
200
mVP-P
V
(3)
VSDID = 200 mV
VEE + 0.95
VCC − 0.2
Serial data output voltage,
differential
SDO, SDO2 100-Ω differential
load
VSDOD
620
750
525
750
880
mVP-P
mVP-P
mVP-P
SCO 100-Ω differential load,
400
650
150
(3)
2970 MHz
Serial clock output voltage,
differential
VSCOD
SCO 100-Ω differential load,
1485 or 270 MHz
SDO, SCO 100-Ω differential
load
VCMO
Output common mode voltage
V
CC − VSDOD
V
2970 Mbps, device enabled
130
3
mA
mA
Power supply current, 3.3-V
supply, total
ICC
Device disabled
(ENABLE = 0)
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to
VEE (equal to zero volts).
(2) Typical values are stated for: VCC = 3.3 V, TA = 25°C.
(3) This parameter is ensured by characterization over voltage and temperature limits.
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7.6 AC Electrical Characteristics
over supply voltage and recommended operating temperature ranges (unless otherwise noted)(1)
PARAMETER
Serial data rate
Serial data rate
Serial data rate
Serial input jitter tolerance 270 Mbps(2)(3)(4)
Serial input jitter tolerance 270 Mbps(2)(3)(5)
Serial input jitter tolerance 1483 or 1485 Mbps(2)(3)(4)
Serial input jitter tolerance 1483 or 1485 Mbps(2)(3)(5)
Serial input jitter tolerance 2967 or 2970 Mbps(2)(3)(4)
TEST CONDITIONS
MIN
TYP
270
MAX
UNIT
Mbps
Mbps
Mbps
UIP-P
UIP-P
UIP-P
UIP-P
UIP-P
BRSD
ST-259
ST-292
ST-424
BRSD
1483, 1485
2967, 2970
BRSD
TOLJIT
TOLJIT
TOLJIT
TOLJIT
TOLJIT
TOLJIT
>6
>0.6
>6
>0.6
>6
Serial input jitter tolerance 2967 or 2970 Mbps
>0.6
UIP-P
(2) (3) (5)
tJIT
tJIT
tJIT
Serial data output jitter
Serial data output jitter
Serial data output jitter
270 Mbps(3)(6)
1483 or 1485 Mbps(3)(7)
2967 or 2970 Mbps(3)(8)
0.01
0.04
0.08
0.03
0.05
0.09
UIP-P
UIP-P
UIP-P
270-Mbps,
<0.1-dB Peaking
275
1.5
kHz
MHz
MHz
MHz
MHz
MHz
MHz
1485-Mbps,
<0.1-dB Peaking
BWLOOP
Loop bandwidth
2970 Mbps,
<0.1-dB Peaking
2.75
270
FCO
FCO
FCO
FCO
FCO
Serial clock output
frequency
270-Mbps data rate
1483-Mbps data rate
1485-Mbps data rate
2967-Mbps data rate
2970-Mbps data rate
Serial clock output
frequency
1483
1485
2967
Serial clock output
frequency
Serial clock output
frequency
Serial clock output
frequency
2970
2
MHz
tJIT
Serial Clock Output Jitter
3
psRMS
(3)
SCALG
Serial clock output
alignment with respect to
data interval
See
40%
45%
60%
55%
(3)
SCODC
FREF
Serial clock output duty
cycle
See
Reference clock
frequency
27
MHz
ppm
FTOL
Reference clock
frequency tolerance
±50
(1) Typical values are stated for: VCC = 3.3 V, TA = 25°C.
(2) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
(3) This parameter is ensured by characterization over voltage and temperature limits.
(4) Refer to A1 in Figure 1 of SMPTE RP 184-1996.
(5) Refer to A2 in Figure 1 of SMPTE RP 184-1996.
(6) PRBS 210– 1, input jitter = 31 psP-P
(7) PRBS 210– 1, input jitter = 24 psP-P
(8) PRBS 210– 1, input jitter = 22 psP-P
.
.
.
8
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7.7 AC Timing Requirements
MIN
NOM
MAX
UNIT
ms
ns
(1)
TACQ
tr, tf
tr, tf
tr, tf
tr, tf
tr, tf
tr, tf
Acquisition time
See
15
Logic inputs rise/fall time
Input rise/fall time
10%–90%
1.5
(2)
20%–80%, 270 Mbps
1500
270
ps
(2)
(2)
Input rise/fall time
20%–80%, 1483 or 1485 Mbps
20%–80%, 2967 or 2970 Mbps
10%–90%
ps
Input rise/fall time
135
ps
Logic outputs rise/fall time
Output rise/fall time
1.5
90
ns
(3) (4)
20%–80%
130
ps
(1) Measured from first SDI transition until Lock Detect output goes high (true).
(2) This specification is ensured by design.
(3) RL = 100-Ω differential.
(4) This parameter is ensured by characterization over voltage and temperature limits.
SDI
NO DATA
270 MBPS DATA
NO DATA
1485 MBPS DATA
NO DATA
T
ACQ
T
T
ACQ
T
2
2
Lock
Dete
ct
T
1
T
1
T
1
SD/HD
SDI
NO DATA
270 MBPS DATA
1485 MBPS DATA
2970 MBPS DATA
270 MBPS DATA
T
ACQ
T
ACQ
T
ACQ
T
ACQ
T
T
T
2
2
2
Lock
Dete
ct
T
1
T
1
T
1
T
1
T
1
SD/HD
TACQ = Acquisition Time, defined in AC Timing Requirements
T1 = Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27-MHz clock
period)
T2 = Time from SDI input change until Lock Detect deassertion, 1 ms maximum. SD/HD output is not valid during this
time.
Figure 1. SDI, Lock Detect, and SD/HD Timing
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8 Detailed Description
8.1 Overview
The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs is used in many types of digital
video signal processing equipment. Supported serial digital video standards are ST-259, ST-292, and ST-424.
Corresponding serial data rates are 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. DVB-ASI
data at 270 Mbps may also be retimed. The LMH0356 retimes the serial data stream to suppress accumulated
jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output
either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial clock or second serial
data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and
output mute.
Serial data inputs are CML and LVPECL compatible. Serial data and clock outputs are differential CML and
produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100-Ω
differential loads. The differential output level is 750 mVP-P into 100-Ω AC- or DC-coupled differential loads. Logic
inputs and outputs are LVCMOS compatible.
The device package is a 48-pin WQFN or a 40-pin WQFN. Both package options have an exposed die attach
pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the primary electrical
terminal for the device. This terminal must be connected to the negative power supply or circuit ground.
8.2 Functional Block Diagram
SCO_EN
HD
SD/
BYPASS/
AUTO BYPASS
RATE0
CONTROL LOGIC
LOCK DETECT
RATE1
ENABLE
V
CCO
BYPASS
50
50
XTAL IN/EXT CLK
SCO/SDO2
SCO/SDO2
XTAL OUT
LOOP FILTER 1
VCO / PLL
LOOP FILTER 2
O/P MUTE
V
CCO
SDI0
SDI0
EQUALIZER
50
50
SDI1
SDI1
EQUALIZER
EQUALIZER
EQUALIZER
SDO
SDO
RETIMER / FIFO
SDI2
SDI2
SDI3
SDI3
SEL0
SEL1
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8.3 Feature Description
8.3.1 Functional Block Description
8.3.1.1 Serial Data Input and Outputs
The differential serial data inputs, SDI0-SDI3, accept serial digital video data at the rates specified in Table 1.
Figure 2 shows the equivalent input circuit for SDI[3:0] and SDI[3:0]. The serial data inputs are differential
LVPECL compatible. These inputs have 50-Ω internal terminations (100-Ω differential) with an internal bias as
shown in Figure 2. These inputs are intended to be DC-coupled to devices such as the LMH0344 adaptive cable
equalizer. DC-coupled inputs must be kept within the specified common mode range. The inputs may be AC-
coupled if the input signal is outside the input common mode range of the device (such as when interfacing to 5-
V PECL), and in that case the bias is supplied internally so no additional input biasing is required. See Figure 2
for more information on input interfacing.
The LMH0356 provides four independent, equalized and multiplexed data inputs. The active input channel is
selected via the SEL0 and SEL1 pins, as shown in Table 2. The equalizer on each of the four inputs is capable
of equalizing up to 30 inches of FR4 trace without the need for programming for different trace lengths or data
rates.
The LMH0356 has two retimed, differential, serial data outputs: SDO and SCO/SDO2. These outputs provide
low-jitter, differential, retimed data to devices such as the LMH0302 cable driver. Output SCO/SDO2 is
multiplexed and can provide either a second serial data output or a serial clock output. Figure 3 shows the
equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2.
The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the
SCO/SDO2 output provides a serial clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial
data.
Both differential serial data outputs, SDO and SCO/SDO2, are muted when the OUTPUT MUTE input is a logic
low level. SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial
clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels.
The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50-Ω pullups and
are suitable for driving AC- or DC-coupled, 100-Ω center-tapped, AC-grounded or 100-Ω un-center-tapped,
differentially terminated networks.
VCC
20 kW
1 pF
80 kW
VCC
VCC
2 kW
2 kW
50W
network
50W
network
SDI[3:0]
SDI[3:0]
Figure 2. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0])
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Feature Description (continued)
V
CC
V
CC
V
CC
50W
50W
SDO, SCO/SDO2
SDO, SCO/SDO2
Figure 3. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
8.3.1.2 Operating Serial Data Rates
This device operates at serial data rates of 270 Mbps, 1483 Mbps, 1485 Mbps, 2967 Mbps, and 2970 Mbps. The
device does not lock to harmonics of these rates. The device does not lock and automatically enters the
reclocker bypass mode for the following data rates: 143 Mbps, 177 Mbps, 360 Mbps, and 540 Mbps.
8.3.1.3 Serial Data Clock/Serial Data 2 Output
The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second
retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being
processed. When operating as a serial clock output, the rising edge of the clock is positioned within the
corresponding serial data bit interval within 10% of the center of the data interval.
Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low
level. This output functions as the serial clock output when the SCO_EN input is a logic-high level. The SCO_EN
input has an internal pulldown device and the default state of SCO_EN is low (serial data output 2 enabled).
SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is activated
and this output is functioning as a serial clock output, the output is muted. If an unsupported data rate is used
while in Auto Bypass mode with this output functioning as a serial clock output, the output is invalid.
8.3.2 Control Inputs and Indicator Outputs
8.3.2.1 Serial Data Rate Selector
The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. RATE[1:0] pins
have internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high
condition. This input also serves to place the device in a test mode. The codes shown in Table 1 select the
desired operating serial data rate. The LMH0356 then enters either the Auto-Rate Detect mode or a single
operating rate. Selecting the 270-Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI
data is MPEG2 coded data that is transmitted in 8B10B coding. The device reclocks this data without harmonic
locking.
Table 1. Data Rate Select Input Codes
RATE [1:0]
CODE
DATA RATE OR MODE
COMMENTS
00
Auto-Rate Detect mode
01
270 Mbps
May be used to support DVB-ASI operation
10
1483/1485 Mbps, 2967/2970 Mbps
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8.3.2.2 Serial Data Input Selector
The Serial Data Input Selector (SEL [1:0]) allows the user to select the active input channel. Table 2 shows the
input selected for a given state of SEL [1:0]. The SEL pins have internal pulldowns.
Table 2. Data Input Select Codes
SEL [1:0] CODE
SELECTED INPUT
00
01
10
11
SDI0
SDI1
SDI2
SDI3
8.3.2.3 Lock Detect
The Lock Detect output, when high, indicates that data is being received and the PLL is locked. Lock Detect may
be connected to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being
received. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 3.
8.3.2.4 OUTPUT MUTE
The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock
Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to Lock Detect, then
the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function;
see Table 3. OUTPUT MUTE has an internal pullup device to enable the output by default.
8.3.2.5 Bypass/AUTO BYPASS
The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this
input is low, the device automatically bypasses the reclocking function when the device is in an unlocked
condition or the detected data rate is a rate which the device does not support. Note that when the Bypass/Auto
Bypass input is set high, Lock Detect remains low. See Table 3. BYPASS/AUTO BYPASS has an internal
pulldown device.
Table 3. Control Functionality
LOCK DETECT
OUTPUT MUTE
BYPASS/AUTO BYPASS
DEVICE STATUS
PLL unlocked, reclocker bypassed
0
1
X
0
1
1
X
0
1
PLL locked to supported data rate, reclocker not bypassed
Outputs muted
0
X
X
0
LOCK DETECT
LOCK DETECT
Outputs muted
PLL locked to supported data rate, reclocker not bypassed
8.3.2.6 SD/HD
The SD/HD output indicates whether the LMH0356 is processing SD or HD / 3 Gbps data rates. It may be used
to control another device such as the LMH0302 cable driver. When this output is high it indicates that the data
rate is 270 Mbps. When low, the indicated data rate is 1483, 1485, 2967, or 2970 Mbps. The SD/HD output is a
registered function and is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is
not locked (the Lock Detect output is low), the SD/HD output defaults to HD (low). The SD/HD output is
undefined for a short time after lock detect assertion or de-assertion due to a data rate change on SDI. See
Figure 1 for a timing diagram showing the relationship between SDI, Lock Detect, and SD/HD.
8.3.2.7 SCO_EN
Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial clock or second serial
data output. SCO/SDO2 functions as a serial clock when SCO_EN is high. This pin has an internal pulldown
device. The default state (low) enables the SCO/SDO2 output as a second serial data output.
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8.3.2.8 ENABLE
The ENABLE pin is used to enable or disable the LMH0356. When the device is disabled, the output drivers and
most of the internal circuitry are powered down. The crystal oscillator and external clock reference circuitry
(XTAL IN and XTAL OUT) remain active regardless of the state of ENABLE, allowing the 27-MHz reference clock
signal to be generated and passed on to additional reclockers. The ENABLE pin is active high and has an
internal pullup device to enable the LMH0356 by default.
8.3.2.9 Crystal or External Clock Reference
The LMH0356 uses a 27-MHz crystal or external clock signal as a timing reference input. A 27-MHz parallel
resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins.
Alternatively, a 27-MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a
suitable crystal are given in Table 4.
Table 4. Crystal Parameters
PARAMETER
VALUE
Frequency
27 MHz
Frequency stability
Operating mode
Load capacitance
Shunt capacitance
Series resistance
±50 ppm at recommended drive level
Fundamental mode, parallel resonant
20 pF
7 pF
40 Ω (maximum)
100 µW
Recommended drive level
Maximum drive level
500 µW
Operating temperature
−10°C to 60°C
8.4 Device Functional Modes
The LMH0356 features are programmed using pin control. Refer to Control Inputs and Indicator Outputs for
details.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs is used in many types of digital
video signal processing equipment.
9.2 Typical Application
Figure 4 and Figure 5 show typical system and application circuits for the 48-pin WQFN version of the LMH0356.
0-20" FR4
LMH0344
0-30" FR4
Equalizer
LMH0344
Equalizer
DS25CP104
4x4 LVDS
Crosspoint
LMH0344
Equalizer
LMH0302
Cable Driver
LMH0344
Equalizer
LMH0356
Reclocker
LMH0302
Cable Driver
LMH0344
Equalizer
LMH0344
Equalizer
DS25CP104
4x4 LVDS
Crosspoint
LMH0344
Equalizer
LMH0344
Equalizer
Figure 4. System Block Diagram
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Typical Application (continued)
SCO_EN
RATE0
RATE1
56 nF
SEL0
SEL1
V
V
CC
CC
36
1
2
SDI0
SDI0
SD/HD
SD/HD
Differential
Data Input 0
35
34
V
CC
V
CC
3
V
CC
4
33
32
31
30
29
SDI1
SDO
Differential
Data Input 1
Data
Output
5
SDI1
SDO
6
V
CC
V
V
CC
LMH0356
7
SDI2
Differential
Data Input 2
CC
8
SCO/SDO2
SDI2
Clock Output or
2nd Data Output
9
28
27
26
25
ENABLE
SDI3
SCO/SDO2
10
11
12
V
EE
Differential
Data Input 3
V
EE
V
EE
SDI3
V
CC
DAP
V
CC
ENABLE
27 MHz
LOCK DET
BYPASS/AUTO BP
OP MUTE
39 pF
39 pF
Figure 5. Application Circuit
ENABLE has an internal pullup to enable the device by default. This pin may be pulled low to put the LMH0356
into a powered down mode.
BP/AUTO BP has an internal pulldown to enable Auto Bypass mode by default. This pin may be pulled high to
force the LMH0356 to bypass all data.
OP MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the
outputs.
The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27-MHz crystal and the proper loading. The crystal
should match the parameters described in Table 4. Alternately, a 27-MHz LVCMOS compatible clock signal may
be input to XTAL IN/EXT CLK.
The active high LOCK DET output provides an indication that proper data is being received and the PLL is
locked.
The SD/HD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0302) in order to
properly set the cable driver’s edge rate for SMPTE compliance. It defaults to HD/3G (low) when the LMH0356 is
not locked.
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Typical Application (continued)
SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled
high to set the second output as a serial clock.
The external loop filter capacitor (between LF1 and LF2) must be 56 nF. This is the only supported value; the
loop filter capacitor must not be changed.
RATE0 and RATE1 have internal pulldowns to select Auto-Rate Detect mode by default. These pins may also be
used to set the device to SD mode or HD/3G mode.
SEL0 and SEL1 have internal pulldowns to select the SDI0 input by default.
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 5 as the input parameters.
Table 5. LMH0356 Design Parameters
DESIGN PARAMETER
Input AC-coupling capacitors
REQUIREMENTS
The user should check output common mode voltage of the device attached
to SDI pins. If AC-coupling capacitor is required, AC-coupling capacitor is
expected to be 4.7 μF ±10%. Refer to Input Output Interfacing for details.
The user should check input common mode voltage of the device attached to
SDO pins. If AC-coupling capacitor is required, AC-coupling capacitor is
expected to be 4.7 μF ±10%. Refer to Input Output Interfacing for details.
Output AC-coupling capacitors
De-coupling capacitors are required to minimize power supply ripple noise.
Place 4.7-μF and 0.1-μF surface mount ceramic capacitors as close to the
device VCC pin as possible .
DC power supply coupling capacitors
SDI± and SDO± must be routed with coupled board traces with 100-Ω ± 5%
differential impedance.
High-speed SDI and SDO trace impedance
Use of ENABLE, RATE0/1, SCO_EN, OP MUTE, and
BP/AUTO BP pins
Set these pins for desired operating mode.
Use this pin for lock indication or to OP MUTE pin to enable output when
locked.
LOCK DET pin
SD/HD Pin
Use SD/HD to set cable driver edge rate or to FPGA for lock rate monitoring.
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
1. Check that the power supply meets the DC and AC requirements in DC Electrical Characteristics.
2. Select the proper pull-high or pull-low resistors for ENABLE, RATE0/1, SCO_EN, OP MUTE, and BP/AUTO
BP pins.
3. Use SD/HD output signal to set the cable driver edge rate.
4. Refer to Input Output Interfacing for Input or Output DC- or AC-coupling.
5. Choose small 0402 surface mount ceramic capacitors for AC-coupling and bypass capacitors.
6. Pay close attention to high speed printed circuit board layout for the high speed SDI± and SDO± signals.
7. Plan out overall system jitter budget with AC Electrical Characteristics in mind.
9.2.2.1 Input Output Interfacing
The inputs are LVPECL compatible. The LMH0356 has a wide input common mode range, and in most cases
the input should be DC-coupled. For DC-coupling, the inputs must be kept within the common mode range
specified in DC Electrical Characteristics.
Figure 6 shows an example of a DC-coupled interface between the LMH0344 cable equalizer and the LMH0356.
The LMH0344 output common mode voltage and voltage swing are within the range of the input common mode
voltage and voltage swing of the LMH0356. In this figure, the LMH0344 cable equalizer restores the signal after
the coaxial cable. The LMH0356 FR4 equalizer restores the signal after the loss due to the FR4 trace. The
LMH0356 inputs have 50-Ω internal terminations (100-Ω differential) to terminate the transmission line, so no
additional components are required.
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The outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second output that
may be set as the serial clock or a second data output. Both outputs are always active. The LMH0356 output
should be DC-coupled to the input of the receiving device as long as the common mode ranges of both devices
are compatible.
Figure 7 shows an example of a DC-coupled interface between the LMH0356 and LMH0302 cable driver. All that
is required is a 100-Ω differential termination as shown. The resistor should be placed as close to the LMH0302
input as possible. If desired, this network may be terminated with two 50-Ω resistors and a center tap capacitor to
ground in place of the single 100-Ω resistor.
The LMH0356 has multiple ground connections, however; the primary ground connection is through the large
exposed DAP. The DAP must be connected to ground for proper operation of the LMH0356.
LMH0344
3G/HD/SD
SDI Cable Equalizer
Coaxial Cable
1.0 mF
75W
SDI SDO
SDI SDO
SDI0
0-30" FR4 Trace
LMH0356
1.0 mF
3.9 nH
SDI0
75W
37.4W
Figure 6. DC Input Interface
+3.3V
75W
75W
LMH0302
3G/HD/SD
5.6 nH
SDI Cable Driver
Coaxial Cable
4.7 mF
4.7 mF
75W
SDI
SDO
SDO
100W
LMH0356
Coaxial Cable
75W
75W
SDO
SDI
SDO
SD/HD
SD/HD
75W
5.6 nH
Figure 7. DC Output Interface
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9.2.3 Application Curves
Figure 8. 2.97-Gbps Signal Before FR4 Equalization
Figure 9. 2.97-Gbps Signal After FR4 Equalization
(0.23-UI Jitter)
(0.6-UI Jitter)
Figure 10. 2.97-Gbps Signal After Reclocking
(0.06-UI Jitter)
10 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply must be designed to provide the recommended operating conditions in terms of DC
voltage.
2. The maximum current consumption for the LMH0356 is provided in the data sheet. This figure can be used
to calculate the maximum current the supply must provide.
3. Place 4.7-μF bulk capacitor and 0.1-μF de-coupling capacitors as close to LMH0356 VCC pins as possible.
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11 Layout
11.1 Layout Guidelines
Figure 11 shows a typical PCB layout for the 48-pin WQFN version of the LMH0356. The following guidelines are
recommended for designing the board layout for the LMH0356:
1. Choose a suitable board stack-up such that it supports 100-Ω differential trace routing on board layer 1. This
is typically done with layer 2 ground plane reference for the 100-Ω differential traces.
2. Place 56-nF loop filter capacitor as close to the loop filter pins as possible.
3. Use coupled differential traces with 100-Ω ± 5% impedance for signal routing to SDI± and SDO± pins. These
are usually 5 to 8-mil trace width reference to a ground plane at layer 2.
4. DAP of the package must be connected to the ground plane through an array of via. These nine vias are
solder-masked to avoid solder flowing into the plated-through holes during the board manufacturing process.
DAP is divided into 16 squares (1.09 mm × 1.09 mm) inside 5.1-mm × 5.1-mm landing pad.
5. Connect supply pins VCC and VEE to the power and ground planes with short via. The via is usually placed
tangent to the supply pin landing pad with the shortest trace possible.
6. Power supply bypass capacitors must be placed close to the supply pin. They are commonly placed at the
bottom layer sharing the ground connector of the DAP.
11.2 Layout Example
Figure 11 shows a typical PCB layout for the 48-pin WQFN version of the LMH0356.
56nF
38
37
48 47 46 45 44 43 42 41 40 39
{5L0
1
2
36
35
____
{5L0
VCC
3
4
5
6
34
33
32
31
{50
___
_
{50
{5L1
____
{5L1
VCC
{5L2
____
{5L2
7
8
30
29
{/0ꢀ{5h2
________
{/0ꢀ{5h2
VCC
{5L3
9
28
27
10
____
{5L3
11
12
26
25
VCC
13 14 15 16 17 18 19 20 21 22 23 24
Figure 11. LMH0356 PCB Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH0356SQ-40/NOPB
LMH0356SQ/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RSB
RHS
RSB
RHS
40
48
40
48
1000 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
L0356
L0356
L0356
L0356
SN
SN
SN
LMH0356SQE-40/NOPB
LMH0356SQE/NOPB
250
250
RoHS & Green
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH0356SQ-40/NOPB
LMH0356SQ/NOPB
WQFN
WQFN
RSB
RHS
RSB
RHS
40
48
40
48
1000
1000
250
178.0
330.0
178.0
178.0
12.4
16.4
12.4
16.4
5.3
7.3
5.3
7.3
5.3
7.3
5.3
7.3
1.3
1.3
1.3
1.3
8.0
12.0
8.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
LMH0356SQE-40/NOPB WQFN
LMH0356SQE/NOPB WQFN
250
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH0356SQ-40/NOPB
LMH0356SQ/NOPB
WQFN
WQFN
WQFN
WQFN
RSB
RHS
RSB
RHS
40
48
40
48
1000
1000
250
208.0
356.0
208.0
208.0
191.0
356.0
191.0
191.0
35.0
35.0
35.0
35.0
LMH0356SQE-40/NOPB
LMH0356SQE/NOPB
250
Pack Materials-Page 2
PACKAGE OUTLINE
RSB0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
0.5
0.3
PIN 1 INDEX AREA
0.3
0.2
5.1
4.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIM A
OPT 1 OPT 1
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2X 3.6
(A) TYP
EXPOSED
THERMAL PAD
11
20
36X 0.4
10
21
2X
41
SYMM
3.6
3.6 0.1
SEE TERMINAL
DETAIL
1
30
0.25
0.15
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
C A B
(0.2) TYP
SYMM
0.5
0.3
0.05
40X
4215000/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSB0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.6)
SYMM
40
31
40X (0.6)
40X (0.2)
1
30
36X (0.4)
4X
(1.55)
41
SYMM
(1.23)
(4.8)
(
0.2) TYP
VIA
10
21
(R0.05)
TYP
11
(1.23) TYP
20
4X (1.55)
(4.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4215000/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSB0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.23) TYP
9X ( 1.03)
40
31
40X (0.6)
1
41
30
40X (0.2)
36X (0.4)
SYMM
(1.23)
TYP
(4.8)
(R0.05) TYP
10
21
METAL
TYP
20
11
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 41
73.7% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4215000/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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