LMH1218RTWT [TI]
具有集成时钟恢复器的 12G SDI 电缆驱动器 | RTW | 24 | -40 to 85;型号: | LMH1218RTWT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成时钟恢复器的 12G SDI 电缆驱动器 | RTW | 24 | -40 to 85 时钟 驱动 驱动器 |
文件: | 总58页 (文件大小:2304K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LMH1218
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
具有集成时钟恢复器的 LMH1218 低功耗超高清电缆驱动器
1 特性
3 说明
1
•
支持 ST-2082(推荐)、ST-2081(推荐)、
LMH1218 是一款具有集成时钟恢复器的低功耗电缆驱
动器,可驱动符合 SMPTE-SDI、SMPTE 2022-5/6、
10GbE 以太网和 DVB-ASI 标准的串行视频数据。
LMH1218 支持高达 11.88Gbps 的数据传输速率,可
以在 4K/8K 应用中实现超高清视频 显示。LMH1218
具有 75Ω 和 50Ω 的发送器输出,支持同轴电缆、光纤
及 FR-4 PCB 等多种介质选项。
SMPTE 424M、344M、292M、259M、DVB-
ASI、SFF-8431 (SFP+) 和适用于 SMPTE 2022-
5/6 的 10GbE 以太网
•
•
锁定为以下速率:11.88Gbps、5.94Gbps、
2.97Gbps、1.485Gbps 或 1.001 分频子速率、
DVB-ASI (270Mbps) 和 10GbE (10.3125Gbps)
无基准,锁定迅速,涵盖所有支持的或选定的数据
速率
LMH1218 的输入端集成了 2:1 多路复用器,支持在两
个视频源之间进行选择,同时可编程均衡器可以补偿印
刷电路板损耗,以此延长信号传输距离。该片上时钟恢
复器借助宽范围时钟和数据恢复 (CDR) 电路,在无需
外部参考时钟和环路滤波器组件的情况下,自动检测并
锁定 270Mbps 至 11.88Gbps 的串行数据,从而简化
了电路板设计并降低了系统成本。经时钟恢复的串行数
据可路由到 75Ω 或 50Ω 发送器输出或同时路由到这两
个输出(1 对 2 扇出模式)。输出电压摆幅兼容 SFF-
8431 (SFP+)、ST-2082/1(推荐)、SMPTE 424M、
344M、292M 以及 259M 标准。
•
•
•
•
•
•
•
•
•
75Ω 和 100Ω 发送器输出
集成了 2:1 复用输入,1:2 解复用/扇出输出
基于输入速率检测的自动转换率
片上眼图监视器
功耗仅 300mW,输入信号丢失时自动断电
可通过 SPI 或 SMBus 接口进行编程
2.5V 单电源运行
小型 4mm × 4mm 24 引脚 WQFN 封装
运行温度范围:–40°C 至 +85°C
2 应用
非破坏性眼图监视器支持实时测量串行数据,从而简化
系统启动或现场调试过程。LMH1218 可通过 SPI 或
SMBus 接口进行编程。
•
•
•
•
•
UHDTV/4K/8K/HDTV/SDTV 视频
数字视频路由器和交换机
数字视频处理和编辑
器件信息(1)
DVB-ASI 和分布式放大器
适用于 SMPTE 2022-5/6 的 10GbE 以太网
器件型号
LMH1218
封装
WQFN (24)
封装尺寸(标称值)
4.00mm × 4.00mm
(1) 如需了解所有可用封装,请参阅产品说明书末尾的可订购产品
附录。
简化 SPI 电路原理图
VDD
MODE_SEL
ENABLE
0.1 mF
0.01 mF
4.7 mF
4.7 mF
OUT
IN0+
IN0-
OUT0+
LMH1218
75W T-Line
FPGA
FPGA
100W Differential T-Line
OUT0-
OUT
4.7 mF
DAP
VSS
75W
VSS
4.7 mF
OUT
OUT
IN1+
IN1-
OUT1+
IN+
IN-
100W Differential T-Line
Optical Module
100W Differential T-Line
OUT1-
SS_N
SCK
MOSI
LOS_INT_N
MISO
LOCK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS474
LMH1218
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
www.ti.com.cn
目录
7.5 Programming .......................................................... 25
7.6 Register Maps......................................................... 26
Application and Implementation ........................ 44
8.1 Application Information............................................ 44
8.2 Typical Application ................................................. 44
8.3 Do's and Don'ts....................................................... 47
8.4 Initialization Set Up ................................................. 47
Power Supply Recommendations...................... 47
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
8
9
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Example .................................................... 48
10.3 Solder Profile......................................................... 49
11 器件和文档支持 ..................................................... 50
11.1 器件支持................................................................ 50
11.2 文档支持................................................................ 50
11.3 接收文档更新通知 ................................................. 50
11.4 社区资源................................................................ 50
11.5 商标....................................................................... 50
11.6 静电放电警告......................................................... 50
11.7 术语表 ................................................................... 50
12 机械、封装和可订购信息....................................... 50
6.6 Recommended SMBus Interface AC Timing
Specifications........................................................... 12
6.7 Serial Parallel Interface (SPI) Bus Interface AC
Timing Specifications ............................................... 12
6.8 Typical Characteristics............................................ 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 25
7
4 修订历史记录
Changes from Revision D (December 2017) to Revision E
Page
•
•
•
Changed the note under Float(Default) setting from: Reserved to: Power down until valid signal detected......................... 5
Changed MISO pin I/O description from 3-Level back to 2-Level.......................................................................................... 5
Changed the Acknowledge (ACK) graphic text from: Clock Line Held Low by Receiver While Interrupt is Serviced to:
Host may held clock line low to delay transaction................................................................................................................ 20
•
•
•
Changed Channel Register 0x80 default from: 0xXX to: 0x20 ............................................................................................ 43
Changed the OUT0_VOD bit 7 default from x to 0............................................................................................................... 43
Changed the bit description for the OUT0_VOD bits 7-3 from: drv_0_sel_vod[3:0] default value may change from
part to part to: drv_0_sel_vod[3:0] is typically 42 mV per step. ........................................................................................... 43
•
•
•
Changed the OUT0_VOD bit 6 default from x to 0............................................................................................................... 43
Changed the OUT0_VOD bit 5 default from x to 1............................................................................................................... 43
Changed the OUT0_VOD bit 4 default from x to 0............................................................................................................... 43
Changes from Revision C (December 2016) to Revision D
Page
•
Changed Channel Register 0x80 default value from 0101 0100’b to XXXX 0000’b............................................................ 43
Changes from Revision B (February 2016) to Revision C
Page
•
•
•
Changed MISO pin I/O description from 2-Level to 3-Level................................................................................................... 5
Added test conditions to the source transmit differential launch amplitude parameters ........................................................ 7
Changed OUT0 VOD_Scaling_PD description for bits 7 through 4..................................................................................... 43
2
版权 © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Changes from Revision A (March 2015) to Revision B
Page
•
•
•
•
•
•
Changed ESD Ratings for Human-body model (HBM) From: ±2500 To ±4500 ................................................................... 7
Added typical launch amplitude for 20 and 30 inch FR4 trace in the Recommended Operating Conditions ........................ 7
Added new Note to the Electrical Characteristics: "ATE Production tested using DC method.."........................................... 9
Changed the VVOD_OUT0 row information and values in the Electrical Characteristics............................................................ 9
Added MAX value of 45 ps to TR_F_OUT0 in the Electrical Characteristics............................................................................. 10
Changed the TYP value From: 900 To: 950 ps, Added MIN and MAX values to TR_F_OUT0 (270 Mbps) in the
Electrical Characteristics ...................................................................................................................................................... 10
•
•
Changed the TYP value to 3 ps, Added MAX value of 18 ps to TR_F_OUT0_delta in the Electrical Characteristics.................. 10
Changed the TYP value From: 100 To: 72 ps, Added MAX value of 500 ps to TR_F_OUT0_delta (270 Mbps) in the
Electrical Characteristics ...................................................................................................................................................... 10
•
•
•
•
Changed the VOVR_UDR_SHOOT row information and values in the Electrical Characteristics ................................................. 10
Added tSU MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications(4)(5) .......................... 12
Added tH MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications(4)(5) ............................ 12
Added tSSSu MIN = 14 ns, Changed TYP value From: 14 To: 18 ns in the Serial Parallel Interface (SPI) Bus Interface
AC Timing Specifications(4)(5) .............................................................................................................................................. 12
•
•
Added tSSh MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications(4)(5) ......................... 12
Added Selective Data Rate Lock in Application and Implementation section. .................................................................... 47
Copyright © 2015–2018, Texas Instruments Incorporated
3
LMH1218
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
www.ti.com.cn
Changes from Original (February 2015) to Revision A
Page
•
已更改 文档状态产品预览至量产数据 ..................................................................................................................................... 1
5 Pin Configuration and Functions
RTW Package
24-Pin WQFN
(Top View)
VSS
24
VDD
IN1+
IN1-
7
8
23 OUT1+
22 OUT1-
21 VDD
9
DAP = GND
VSS
10
20 OUT0+
19 OUT0-
IN0+ 11
12
IN0-
4
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
PIN
TYPE
DESCRIPTION
NAME
NO.
CONTROL/INDICATOR I/O
Powers down device when pulled low
1 kΩ to VDD:
•
Power down until valid signal detected
Float(Default):
•
Power down until valid signal detected
ENABLE
6
Input, 4-Level
20 kΩ to GND:
•
Reserved
1 kΩ to GND:
Power down including signal detects and Reset Registers upon
power-up
•
Indicates CDR lock detect status
High:
Output, 2.5-V
LVCMOS, 2-Level
LOCK
16
•
CDR locked
Low:
•
CDR not locked
Output,
Programmable Interrupt caused by change in LOS, violation of internal
LOS_INT_N
MISO
13
15
1
LVCMOS Open- eye monitor threshold, or change in lock. External 4.7-kΩ pullup resistor is
Drain, 2-Level
required. This pin is 3.3-V LVCMOS tolerant.
Output, 2.5-V
LVCMOS, 2-Level
SPI Master Input / Slave Output. LMH1218 SPI data transmit
Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
MODE_SEL
Input, 4-Level
•
SPI mode. See Initialization Set Up.
MOSI
4
Input, 2-Level
—
SPI Master Output / Slave Input. LMH1218 SPI data receive
No Connect
RESERVED
5, 17, 18
Input, 2.5V
LVCMOS, 2-Level
SCK
3
SPI serial clock input
SMPTE_10GbE
SS_N
14
2
—
No Connect
Input, 2-Level
SPI Slave Select. This pin has internal pullup
HIGH-SPEED DIFFERENTIAL I/O
IN0+
11
12
8
Input, Analog
Input, Analog
Input, Analog
Input, Analog
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN0+ to IN0-. Inputs require 4.7-µF, AC-coupling
capacitors.
IN0–
IN1+
IN1–
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN1+ to IN1-. Inputs require 4.7-µF, AC-coupling
capacitors.
9
Output, 75-Ω CML
OUT0+
OUT0–
20
19
Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating
resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7-µF, AC-
coupling capacitors
Compatible
Output, 75-Ω CML
Compatible
OUT1+
OUT1–
POWER
23
22
Output, Analog
Output, Analog
Inverting and noninverting differential outputs. An on-chip 100-Ω
terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7-µF,
AC-coupling capacitors
Exposed DAP, connect to GND using at least 5 vias (see package
drawing)
DAP
—
Ground
VDD
VSS
7, 21
2.5-V Supply
Ground
2.5 V ± 5%
Ground
10, 24
Copyright © 2015–2018, Texas Instruments Incorporated
5
LMH1218
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
www.ti.com.cn
Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
PIN
TYPE
DESCRIPTION
NAME
NO.
ADDR0
ADDR1
2
4-level strap pins used to set the SMBus address of the device. The pin
state is read on power-up. The multi-level nature of these pins allows for
16 unique device addresses. Note the SMBus section for further details.
The four strap options include:
1 kΩ to VDD:
•
Represents logic state 11’b
Input, 4-Level
15
Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
•
Represents logic state 01'b
1 kΩ to GND:
•
Represents logic state 00'b
Powers down device when pulled low
1 kΩ to VDD:
•
Power down until valid signal detected
Float(Default): Reserved
20 kΩ to GND:
ENABLE
6
Input, 4-Level
•
Reserved
1 kΩ to GND:
Power down including signal detects and Reset Registers upon
power-up
•
Indicates CDR lock Status
High:
Output, 2.5-V
LVCMOS, 2-Level
LOCK
16
13
•
CDR locked
Low:
CDR not locked
•
Output, LVCMOS Programmable Interrupt caused by change in LOS, violation of internal
LOS_INT_N
Open-Drain, 2-
Level
eye monitor threshold, change in lock. External 4.7-kΩ pullup resistor is
required. This pin is 3.3-V LVCMOS tolerant.
Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
MODE_SEL
RESERVED
1
Input, 4-Level
—
5, 17, 18
No Connect
SMBus clock input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is
required as per SMBus interface standard. This pin is 3.3-V LVCMOS
tolerant.
SCL
SDA
3
Input, 2-Level
SMBus data input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is
required as per SMBus interface standard. This pin is 3.3-V LVCMOS
tolerant.
I/O, Open-Drain, 2-
Level
4
SMPTE_10GbE
14
No Connect
HIGH-SPEED DIFFERENTIAL I/O
Exposed DAP, connect to GND using at least 5 vias (see package
drawing)
DAP
—
Ground
IN0+
IN0–
IN1+
IN1–
11
12
8
Input, Analog
Input, Analog
Input, Analog
Input, Analog
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling
capacitors.
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling
capacitors.
9
Output, 75-Ω CML
OUT0+
OUT0–
20
19
Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating
resistor connects OUT0+ and OUT0– to VDD. Outputs require 4.7-µF, AC-
coupling capacitors
Compatible
Output, 75-Ω CML
Compatible
OUT1+
OUT1–
23
22
Output, Analog
Output, Analog
Inverting and noninverting differential outputs. An on-chip 100 Ω
terminating resistor connects OUT1+ to OUT1–. Outputs require 4.7-µF,
AC-coupling capacitors
VDD
VSS
7, 21
2.5-V Supply
Ground
2.5 V ± 5%
Ground
10, 24
6
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–30
MAX
2.75
UNIT
V
Supply voltage (VDD to GND)
3.3-V open-drain I/O input and output voltage (SDA, SCL, LOS_INT_N)
2.5-V LVCMOS input and output voltage
High-speed input voltage
4.0
V
VDD + 0.5
VDD + 0.5
30
V
V
High-speed input current
mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
2.375
3
TYP
2.5
3.3
40
MAX
2.625
3.6
UNIT
V
Supply voltage(1)
3.3-V open-drain I/O input and output voltage
Supply noise, 50 Hz to 10 MHz, sinusoidal(1)
Ambient temperature
V
mVP-P
ºC
–40
300
25
85
Source transmit differential launch
amplitude (up to 20 inch FR4 trace)
PRBS15, EQ, and PLL pathological pattern. Reg
0x03 = 0x50
500
1000
mVP-P
mVP-P
Source transmit differential launch
amplitude (up to 35 inch FR4 trace)
PRBS15, EQ, and PLL pathological pattern. Reg
0x03 = 0x95
600
700
100
800
SMBus clock frequency (SCL) in SMBus slave mode
SMBUS SDA and SCL voltage level
SPI clock frequency
400
3.6
20
kHz
V
10
MHz
(1) DC plus AC power should not exceed these limits.
6.4 Thermal Information
RTW (WQFN)
THERMAL METRIC(1)(2)
UNIT
24 PINS
34
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
31.4
11.8
0.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
11.8
2.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient
temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.
Copyright © 2015–2018, Texas Instruments Incorporated
7
LMH1218
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
www.ti.com.cn
6.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
Locked 75 Ω OUT0 only
(800 mVpp), EOM
powered down
300
195
mW
mW
Locked OUT1 only (600
mVpp, diff), EOM powered
down
PD
Power dissipation
Transient power during
CDR lock acquisition, 75 Ω
OUT0 and OUT1 powered
up, EOM powered down
400
195
500
mW
mW
EQ bypass, OUT0
720mVpp, OUT1 600mVpp
IN0 to OUT0 and OUT1 or
IN1 to OUT0 and OUT1
Power dissipation in force
RAW mode (CDR bypass) IN0 to OUT0, OUT1
powered down
PD_RAW
160
80
mW
mW
IN1 to OUT1, OUT0
powered down
4-LEVEL INPUT AND 2.5 V LVCMOS DC SPECIFICATIONS
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
VIH
High level input voltage
Float level input voltage
20K to GND input voltage
Low level input voltage
0.95 × VDD
0.67 × VDD
0.33 × VDD
0.1
V
V
V
V
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
VIF
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
VI20K
VIL
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
VOH
VOL
High level output voltage
Low level output voltage
IOH = -3 mA
IOL = 3 mA
2
V
V
0.4
15
Vinput = VDD
SPI Mode: LVCMOS
(SPI_SCK, SPI_SS_N)
pins
µA
µA
SMBus Mode: LVCMOS
(SMB_SDA, SMB_SCL)
pins
15
IIH
Input high leakage current
SMBus Mode: 4-Levels
(ADDR0, ADDR1) pins
20
20
44
44
80
80
µA
µA
4-Levels (MODE_SEL,
ENABLE) pins
Vinput = GND
SPI Mode: LVCMOS
(SPI_MOSI, SPI_SCK)
pins
–15
µA
Vinput = GND
SPI Mode: LVCMOS
(SPI_SS_N) pins
–37
–15
µA
µA
IIL
Input low leakage current
SMBus Mode: LVCMOS
(SMB_SDA, SMB_SCL
pins
SMBus Mode: 4-Levels
(ADDR0, ADDR1) pins
–160
–160
–93
–93
–40
–40
µA
µA
4-Levels (MODE_SEL,
ENABLE) pins
8
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
VIH25
High level input voltage
Low level input voltage
Low level output voltage
Input high current
2.5-V Supply Voltage
1.75
3.6
0.8
0.4
40
V
V
VIL
GND
VOL
IOL = 1.25 mA
V
IIH
VIN = 2.5 V, VDD = 2.5 V
VIN = GND, VDD = 2.5 V
20
μA
μA
IIL
Input low current
-10
10
SIGNAL DETECT
11.88 Gbps, SMPTE (EQ,
PLL) Pathological Pattern
26
30
21
20
15
12
mVP-P
mVP-P
mVP-P
mVP-P
mVP-P
mVP-P
Signal detect (default)
10.3125 Gbps, 1010 Clock
SDH
Assert threshold level(1)(2) Pattern, no media
10.3125 Gbps, PRBS31
Pattern
11.88 Gbps, SMPTE (EQ,
PLL) Pathological Patterns
Signal detect (default)
De-assert threshold
level(1)
10.3125 Gbps, 1010 Clock
Pattern
SDL
10.3125 Gbps, PRBS31
Pattern
HIGH-SPEED RECEIVE RX INPUTS (IN_n+, IN_n–)
DC Input differential
resistance
R_RD
75
100
–14
125
Ω
Measured with the device
powered up.
dB
Input differential return
loss(3)
SDD11 10 MHz to 2 GHz
RLRX-SDD
SDD11 2 GHz to 6 GHz
SDD11 6 GHz to 12 GHz
–6.5
–6.5
dB
dB
Measure with the device
powered up.SCD11, 10
MHz to 12 GHz
Differential to common
RLRX-SCD
–20
dB
mode Input conversion(3)
HIGH-SPEED OUTPUTS (OUT_n+, OUT_n–)
Output differential
VVOD_OUT1
Default setting, 8T clock
pattern
400
720
600
–9
700
880
mVP-P
dB
voltage(3)(4)
VOD = 600 mV, maximum
De-Emphasis with 16T
clock pattern
VVOD_OUT1_DE
VVOD_OUT1_CLK
VVOD_OUT0
De-emphasis Level
Clock output differential
voltage
2.97 GHz,1.485 GHz, 297
MHz, and 270 MHz
560
778
mVP-P
mVP-P
Output single ended
voltage at OUT0+ with
Default setting
OUT0– terminated(3)(4) (5)
DC output differential
resistance
RDIFF_OUT1
RDIFF_OUT0
TR_F_OUT1
100
75
Ω
Ω
DC output single-ended
resistance
Full Slew Rate, 20% to
80% using 8T Pattern
Output rise/fall time
45
ps
(1) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the
device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.
(2) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal
detect assert condition
(3) These limits are ensured by bench characterization and are not production tested.
(4) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board
(5) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in
75 Ω.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
11.88 Gbps
MIN
TYP
35
35
35
35
950
3
MAX
45
UNIT
ps
5.94 Gbps
2.97 Gbps
1.485 Gbps
270 Mbps
11.88 Gbps
5.94 Gbps
2.97 Gbps
1.485 Gbps
270 Mbps
45
ps
Output rise/fall time,
TR_F_OUT0
45
ps
PRBS10(3)(4)
45
ps
400
1500
18
ps
ps
3
18
ps
Output rise/fall time
mismatch(3)(4)
TR_F_OUT0_delta
3
18
ps
3
18
ps
72
500
ps
Output overshoot,
undershoot(3) (4)
DC offset(3)
12G/6G/3G/HD/SD
Measured with 8T pattern
VOVR_UDR_SHOOT
VDC_OFFSET
2.4%
±0.2
20
3.4%
12G/6G/3G/HD/SD
V
12G/6G/3G/HD/SD EQ
Pathological
VDC_WANDER
DC wander(3)
mV
S22 5 MHz to 1.485 GHz
S22 1.485 GHz to 3 GHz
S22 3 GHz to 6 GHz
< –15
< –10
< –7
< –4
–20
dB
dB
dB
dB
dB
dB
dB
OUT0 single-ended 75-Ω
RLOUT0_S22
return loss(3)(4)(6)
S22 6 GHz to 12 GHz
SDD22 10 MHz - 2 GHz
SDD22 2 GHz - 6 GHz
SDD22 6 GHz - 11.1 GHz
OUT1 differential 100-Ω
RLOUT1_SDD22
–17
return loss(3)(4)(7)
–14
SCC22 10 MHz - 4.75
GHz
–11
–12
8
dB
dB
OUT1 common-mode 50-
RLOUT1_SCC22
Ω return loss(3)(4)(7)
SCC22 4.75 GHz - 11.1
GHz
AC common-mode voltage VOD = 0.6 Vpp, DE = 0dB,
VVCM_OUT1_NOISE
mVRMS
noise(3)(4)
PRBS31, 10.3125 Gbps
Reclocked Data
Raw Data
TRCK_LATENCY
TRAW_LATENCY
Latency reclocked
Latency CDR bypass
1.5 UI +195
230
ps
ps
TRANSMIT OUTPUT JITTER SPECIFICATIONS
OUT0, PRBS15, 11.88
Gbps
AJ_OUT0
TJ_OUT1
RJ_OUT1
DJ_OUT1
Alignment jitter(3)(4)
Total jitter (1E-12)(3)(4)
Random jitter (rms)
Deterministic jitter
0.18
0.12
0.38
7
UI
UI
OUT1, PRBS15 10.3125
Gbps
OUT1, PRBS15, 10.3125
Gbps
psRMS
psP-P
OUT1, PRBS15, 10.3125
Gbps
OUT1, RAW MODE (CDR
bypass)
DJ_OUT1_RAW
Deterministic jitter
PRBS15, 11.88 Gbps, 35
inch FR4 trace, EQ=0x95,
VID = 800mVpp
25
psP-P
(6) Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board
(7) Measure with the device powered up and outputs a clock signal.
10
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK DATA RECOVERY
11.88,
11.868
ST-2082 (proposed)(8)
Gbps
ST-2081 (proposed)(8)
SMPTE 424(8)
5.94, 5.934
2.97, 2.967
Gbps
Gbps
DDATA_RATE
1.485,
1.4835
SMPTE 292(8)
Gbps
SMPTE 259M(8)
10 GbE(8)
270
Mbps
Gbps
10.3125
Measured with 0.2UI SJ at
10.3125 Gbps
8
13
7
MHz
MHz
MHz
MHz
MHz
MHz
Measured with 0.2UI SJ at
11.88 Gbps
Measured with 0.2UI SJ at
5.94 Gbps
PPLL_BW
PLL bandwidth at –3 dB
Measured with 0.2UI SJ at
2.97 Gbps
5
Measured with 0.2UI SJ at
1.485 Gbps
3
Measured with 0.2UI SJ at
270 Mbps
1
TJ = DJ + RJ + SJ,
DJ+RJ = 0.15 UI
SJ/PJ, low to high upward
sweep (10 kHz to 80 MHz)
JTOL
Total input jitter tolerance
0.65
<5
UI
ms
°C
From signal detected to
the lock asserted,
HEO/VEO lock monitor
disable, same setting for
11.88G, 5.94G, 2.97G,
1.485G and 270-MHz data
rates
TLOCK
Lock time(3)(9)
Temperature Lock Range,
CDR lock with temperature 5ºC per minute ramp up
TTEMP_LOCK
125
ramp
and down, –40ºC to 85ºC
operating range
(8) Data rate tolerance is within ±1000 ppm
(9) The total CDR lock time depends on number of rate settings enabled and application data rate
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6.6 Recommended SMBus Interface AC Timing Specifications(1)(2)(3)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSMB
tBUF
Bus operating frequency
MODE_SEL = 0
10
100
400
kHz
Bus free time between stop and start
condition
1.3
μs
Hold time after (repeated) start condition
After this period, the first clock is
generated
tHD:STA
0.6
μs
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tLOW
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
μs
μs
ns
ns
μs
μs
ns
ns
Data setup time
100
1.3
0.6
Clock low period
tHIGH
tF
Clock high period
50
300
300
SDA fall time read operation
SDA rise time read operation
tR
(1) SMBus operation is available 20ms after power up
(2) These specifications support SMBus 2.0 specifications
(3) These Parameters are not production tested
6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications(1)(2)
Over operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
20
UNIT
f SCK
TSCK
tPH
SCK frequency
MODE_SEL = 1
10
MHz
ns
ns
ns
ns
ns
ns
ns
μs
SCK period
50
SCK pulse width high
SCK pulse width low
MOSI setup time
MOSI hold time
0.4 × TSCK
tPL
0.4 × TSCK
tSU
4
4
4
4
tH
tSSSu
tSSH
tSSOF
tODZ
tOZD
SS_N setup time
SS_N hold time
14
4
18
4
SS_N off time
1
MISO driven to TRI-STATE time
20
ns
MISO TRI-STATE-to-Driven
time
10
15
ns
ns
tOD
MISO output delay time
(1) Typical values are parametric norms at VDD = 2.5 V, TA = 25ºC, and recommended operating conditions at the time of product
characterization. Typical values are not production tested.
(2) These specifications support SPI 1.0 specifications.
12
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6.8 Typical Characteristics
Typical device characteristics at TA = +25°C and VDD = 2.5 V, unless otherwise noted.
图 2. 10.3125 Gbps 50 Ω OUT1
图 1. 11.88 Gbps 50 Ω OUT1
图 3. 11.88 Gbps 75 Ω OUT0
图 5. 2.97 Gbps 75 Ω OUT0
图 4. 5.94 Gbps 75 Ω OUT0
图 6. 1.485 Gbps 75 Ω OUT0
图 8. 11.88 Gbps Internal Eye Monitor Hit Density Plot
图 7. Internal Input Eye Monitor Plot
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7 Detailed Description
7.1 Overview
The LMH1218 is a 11.88Gbps/5.94Gbps/2.97Gbps/1.485Gbps/0.27Gbps/10GbE multi-rate serial digital video
data cable driver with integrated reclocker intended for equalizing, reclocking, and driving data compatible to the
SMPTE standards, proposed ST-2081/2, and 10GbE specifications. It is a 2-input, 2-output single-core chip,
enabling 1:2 fan-out or 2:1 MUX operation. Each input has a 100-Ω continuous time linear equalizer (CTLE) at
the front-end, intended to compensate for loss over STP coax, fiber, or FR-4 backplane. OUT1 is a 100-Ω driver
compatible to 10GbE SFF-8431 optical module requirements. The LMH1218 OUT0 is a 75-Ω cable driver
compatible to the SMPTE and proposed ST-2081/2 requirements.
The referenceless Clock-and-Data Recovery (CDR) circuit selects between the two inputs based on user choice.
The reclocked output can be driven to one or two outputs. One of the outputs supports 100-Ω differential cable
connection, while the other output can drive a 75-Ω SMPTE specified cable while meeting transmitter
requirements as specified in SMPTE standard. The LMH1218 locks to all required SDI data rates, including
270Mbps, 1.485 Gbps, 1.4835 Gbps, 2.97 Gbps, 2.967 Gbps, 5.94 Gbps, 5.934 Gbps, 11.88 Gbps, and 11.868
Gbps as well as 10.3125 Gbps. The LMH1218 is assembled in a 4 mm × 4 mm 24-pin QFN package. The chip
can be programmed using SPI or SMBus interface.
7.2 Functional Block Diagram
Mux Control
Mute
OUT0(75 ꢀ )
LA
Loss Of
Signal
75 ꢀ BNC
FR4 EQ
100 ꢀ
FPGA/Cross Point
2
2
Raw
OUT1(100 ꢀ )
Retimed
Clock
FR4 EQ
100 ꢀ
FPGA/Cross Point
100 ꢀ Data or Clock
Mute
CDR
Polarity Control
Loss Of
Signal
Eye
Monitor
VCO
Control Logic Block
Status
14
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7.3 Feature Description
The LMH1218 data path consists of several key blocks as shown in the Functional Block Diagram. These key
circuits are:
•
•
•
•
•
•
•
•
Loss of Signal Detector
Continuous Time Linear Equalizer (CTLE) for FR4 Compensation
2:1 Multiplexer/1:2 Fanout
CDR
Eye Monitor
Differential Output Selection
75-Ω and 100-Ω Output Drivers
SMBus/SPI Configuration
7.3.1 Loss of Signal Detector
The LMH1218 supports two high speed differential input ports, with internal 100-Ω terminations. The inputs must
be AC coupled. The external AC coupling capacitor value should take into account the pathological low
frequency content. For most applications, the RC time constant of 4.7 µF AC coupling capacitor plus the 50-Ω
termination resistor is capable of handing the pathological video pattern's low frequency content.
The signal detect circuit is designed to assert when data traffic with a certain minimum amplitude is present at
the input of the device. It is also designed to de-assert, or remain de-asserted, when there is noise below certain
amplitude at the input to the device.
The LMH1218 has two signal detect circuits, one for each input. Each signal detect threshold can be set
independently. By default, both signal detects are powered on. The user selects IN1 or IN0 through SMBus/SPI
interface.
7.3.2 Continuous Time Linear Equalizer (CTLE)
The LMH1218 has receive-side equalization, and a key part is the Continuous Time Linear Equalizer (CTLE).
This circuit operates on the received differential signal and compensates for frequency-dependent loss due to the
transmission media. The CTLE applies gain to the input signal. This gain varies over frequency: higher
frequencies are boosted more than lower frequencies. The CTLE works to restore the input signal to full
amplitude across a wide range of frequencies.
The CTLE consists of 4 stages with each stage having two boost control bits. This allows 256 different boost
settings. CTLE boost levels are determined by summing the boost levels of the 4 stages. The CTLE is configured
manually. Refer to LMH1218 Programming Guide (SNLU174) on how to quickly select the most appropriate
CTLE boost setting.
There are two CTLEs, one for each input, IN0 and IN1. Only one CTLE is enabled at a time, according to the
user input channel selection. If IN0 is selected, the CTLE for IN0 is powered on and the IN1 CTLE is powered
off. The CTLE compensates for up to 27 dB of loss at 6 GHz. The CTLE is able to handle low loss channels
without over-equalizing by bypassing the CTLE.
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Feature Description (接下页)
7.3.3 2:1 Multiplexer
A 2:1 input multiplexor connects IN0 and IN1 to the CDR. By default, IN0 is selected. To select IN1, the 2:1
multiplexer must be set. Refer to LMH1218 Programming Guide (SNLU174) for detailed settings.
7.3.4 Clock and Data Recovery
By default, the equalized data is fed into the CDR for clock and data recovery. The CDR consists of a reference-
less Phase Frequency Detector (PFD), Charge Pump (CP), Voltage Controlled Oscillator (VCO), and Output
Data Multiplexer (Mux).
The inputs to the Phase and Frequency Detector (PFD) are the data after the CTLE as well as I and Q clocks
from the VCO. The LMH1218 will attempt to lock to the incoming data by tuning the VCO to phase-lock to the
incoming data rate.
The supported data rates are listed in the following table. Refer to LMH1218 Programming Guide (SNLU174) for
further information on configuring the LMH1218 for different data rates.
表 1. Supported Data Rates
DATA RATE RANGE
11.88 Gbps, 11.868 Gbps
5.94Gbps, 5.934 Gbps
2.97 Gbps, 2.967 Gbps
1.485 Gbps, 1.4835 Gbps
270 Mbps
CDR MODE
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
COMMENT
10.3125 Gbps
125 Mbps
At 125 Mbps device is in CDR bypass
At 1.25 Gbps device is in CDR bypass
1.25 Gbps
7.3.5 Eye Opening Monitor (EOM)
The LMH1218 has an on-chip eye opening monitor (EOM) which can be used to analyze, monitor, and diagnose
the performance of the link. The EOM operates on the post-equalized waveform, just prior to the data sampler.
Therefore, it captures the effects of all the equalization circuits within the receiver before the data is reclocked.
The EOM is operational for 1.485 Gbps and higher data rates.
The EOM monitors the post-equalized waveform in a time window that spans one unit intervals and a
configurable voltage range that spans up to ±400 mV differential. The time window and voltage range are divided
into 64 steps, so the result of the eye capture is a 64 × 64 matrix of “hits,” where each point represents a specific
voltage and phase offset relative to the main data sampler. The number of “hits” registered at each point needs
to be taken in context with the total number of bits observed at that voltage and phase offset in order to
determine the corresponding probability for that point. The number of bits observed at each point is configurable.
A common measurement performed by the EOM is the horizontal and vertical eye opening. The horizontal eye
opening (HEO) represents the width of the post-equalized eye at 0-V differential amplitude, measured in unit
intervals or picoseconds. The vertical eye opening (VEO) represents the height of the post-equalized eye,
measured midway between the mean zero crossing of the eye. This position in time approximates the CDR
sampling phase.
The resulting 64 × 64 matrix produced by the EOM can be processed by software and visualized in a number of
ways. Two common ways to visualize this data are shown in 图 7 and 图 8. These diagrams depict examples of
eye monitor plot implemented by software. The first plot is an example of using the EOM data to plot a basic eye
using ASCII character, which can be useful for simple diagnostics software. The second plot shows the first
derivative of the EOM data, revealing the density of hits and the actual waveforms and crossing that comprise
the eye.
16
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7.3.6 Fast EOM
Fast EOM is a mechanism that provides an option to read out EOM through SPI/SMBus interfaces by reading
the hits observed for each point of 64 × 64 points matrix. Since SPI interface operates at faster clock rate than
SMBus interface, the SPI master will have to wait until the EOM start bit, reg 0x24[0], goes low. This indicates
EOM samples are available and the SPI master can proceed to read register 0x25 and 0x26. Refer to LMH1218
Programming Guide (SNLU174) for further details of Fast EOM operation.
7.3.6.1 SMBus Fast EOM Operation
In SMBus mode, the read on register 0x26 acts as an automatic trigger to read the next EOM count value:
1. Enable EOM (power it on), and set VRANGE=0. Write Reg 0x24[7] to 1 to turn on fast EOM
2. Do burst read register 0x25 and 0x26 (EOM hit count) and discard
3. Do burst read register 0x25 and 0x26 (EOM hit count) and discard
4. Do burst read register 0x25 and 0x26 (EOM hit count) and save
5. Perform Step 4 4095 times (64 × 64 cells)
7.3.6.2 SPI Fast EOM Operation
To perform EOM calculation over SPI:
1. Enable EOM (power it on), and set VRANGE=0. Write Reg 0x24[7] to 1 to turn on fast EOM
2. Read Reg 0x26 to initialize. Discard read data
3. Read Reg 0x24[0] which is EOM start bit. Wait for this bit to go low
4. Read register 0x26 EOM hit count and discard. Read on register 0x26 will automatically trigger the next Fast
Eye calculation
5. Read Reg 0x24[0]. Wait for this bit to go low
6. Do burst read on register 0x25 and 0x26 to get the EOM count value.
7. Repeat Steps 5 and 6 4095 times (64 × 64 cells)
7.3.7 LMH1218 Device Configuration
The control pins can be used to configure different operations depending on the functional modes as described
in 表 2.
表 2. Control Pins
FUNCTIONAL MODES
PIN #
1
PIN NAME
SPI
SMBus_Slave
1 kΩ to GND
MODE_SEL
1 kΩ to VDD
SPI_SS_N
SPI_SCK
SPI_MOSI
ENABLE
2
IN_OUT_SEL_SPI_SS_N_ADDR0
EQ_SCL_SCK
ADDR0
3
SMBUS_SCL
SMBUS SDA
ENABLE
4
OUT_CTRL_MOSI_SDA
ENABLE
6
13
15
16
LOS_INT_N
LOS_INT_N
SPI_MISO
LOCK
LOS_INT_N
ADDR1
VOD_MISO_ADDR1
LOCK
LOCK
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7.3.7.1 MODE_SEL
This pin can be configured in 4 possible ways:
1. 1 kΩ to VDD: This puts the part in SPI mode
2. Float (Default): Reserved
3. 20 kΩ to GND: Reserved
4. 1 kΩ to GND: This puts the part in SMBus mode
7.3.7.2 ENABLE
Normal operation when ENABLE is pulled high, and powers down the device when pulled low.
表 3. ENABLE Selection
ENABLE
1 kΩ to GND
POWER CONDITION
Power down device (signal detectors powered down, registers at reset state)
20 kΩ to GND
Float
Reserved
Reserved
1 kΩ to VDD
Normal Operation
7.3.7.3 LOS_INT_N
LOS_INT_N pin is an open drain output. When the channel that has been selected cannot detect a signal at the
high-speed input pins (as defined by the assert levels), the pin pulls low. Pin 13 can be configured through share
register 0xFF[5] for interrupt functionality.
In SMBus/SPI mode, this pin can be configured as an interrupt. This pin is asserted low when there is an
interrupt and goes back high when the interrupt status register is read. There are 7 separate masks for different
interrupt sources. These interrupt sources are:
1. If there is a LOS transition on IN0, irrespective of the input channel selected (2 separate masks).
2. If there is a LOS transition on IN1, irrespective of the input channel selected (2 separate masks).
3. HEO or VEO goes below a certain threshold as specified in the registers (1 mask).
4. Lock transition, whether it is asserted or de-asserted – disabled by default (2 mask).
7.3.7.4 LOCK
Indicates the lock status of the CDR. When CDR is locked this pin is asserted high.
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7.3.7.5 SMBus MODE
The SMBus interface can also be used to control the device. If pin 1 (MODE_SEL) is pulled low through 1 kΩ to
GND, then Pins 3, 4 are configured as the SMBUS_SCL and SMBUS_SDA respectively. Pins 2, 15 are address
straps, ADDR0/ADDR1 respectively, during power up.
The maximum operating speed supported on the SMBus pins is 400 kHz.
表 4. SMBus MODE
7-Bit SLAVE
ADDRESS [HEX]
8-Bit WRITE
COMMAND [HEX]
ADDR0
ADDR1
ADDR0 [BINARY]
ADDR1 [BINARY]
1 kΩ to GND
1 kΩ to GND
1 kΩ to GND
1 kΩ to GND
20 kΩ to GND
20 kΩ to GND
20 kΩ to GND
20 kΩ to GND
Float
1 kΩ to GND
20 kΩ to GND
Float
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
1 kΩ to VDD
1 kΩ to GND
20 kΩ to GND
Float
1 kΩ to VDD
1 kΩ to GND
20 kΩ to GND
Float
Float
Float
Float
1 kΩ to VDD
1 kΩ to GND
20 kΩ to GND
Float
1 kΩ to VDD
1 kΩ to VDD
1 kΩ to VDD
1 kΩ to VDD
1 kΩ to VDD
Note: These are 7 bit addresses. Therefore, the LSB must be added to indicate read/write. LSB equal to zero
indicates write and 1 indicates SMBus read operation. For example, for 7 bit hex address 0x0D, the I2C hex
address byte is 0x1A to write and 0X1B to read.
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7.3.7.6 SMBus READ/WRITE Transaction
The System Management Bus (SMBus) is a two-wire serial interface through which various system component
chips can communicate with the master. Slave devices are identified by having a unique device address. The
two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the Master to all of the
Slave devices on the bus. SDA is a bidirectional data signal between the Master and Slave devices. The
LMH1218 SMBUS SCL and SDA signals are open drain and require external pull up resistors.
Start and Stop:
The Master generates Start and Stop conditions at the beginning and end of each transaction.
•
•
Start: High to low transition (falling edge) of SDA while SCL is high
Stop: Low to high transition (rising edge) of SDA while SCL is high
图 9. Start and Stop Conditions
The Master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The
transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the device pulls SDA
low, while a NACK is recorded if the line remains high.
Acknowledge
Signal From Receiver
SDA
MSB
SCL
1
2
3 - 6
7
8
9
1
2
3 - 8
9
S
P
ACK
ACK
Start
Stop
Condition
Condition
Byte Complete
Interrupt Within
Receiver
Host may hold
clock line low to
delay transaction
图 10. Acknowledge (ACK)
20
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Writing data from a master to a slave comprises of 3 parts as noted in figure 图 11
•
•
•
The master begins with start condition followed by the slave device address with the R/W bit cleared
The 8-bit register address that will be written
The data byte to write
图 11. SMBus Write Operation
SMBus read operation consists of four parts
•
The master initiates the read cycle with start condition followed by slave device address with the R/W bit
cleared
•
•
•
•
The 8-bit register address that is to be read
After acknowledgment from the slave, the master initiates a re-start condition
The slave device address is resent followed with R/W bit set
After acknowledgment from the slave, the data is read back from the slave to the master. The last ACK is
high if there are no more bytes to read
图 12. SMBus Read Operation
t
LOW
t
t
HIGH
R
t
HD:STA
SCL
SDA
t
t
t
SU:STA
HD:DAT
F
t
t
BUF
SU:STO
t
SU:DAT
See
*
Note
ST
SP
SP
ST
图 13. SMBus Timing Parameters
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7.3.7.7 SPI Mode
The SPI (Serial Peripheral Interface) bus standard can be used to control the device. The SPI Mode is enabled
when MODE_SEL Pin 1 is pulled high through the 1-kΩ resistor. The SPI bus comprises of 4 pins: Pin 2, Pin 3,
Pin 4, and Pin 15:
1. MOSI Pin 4: Master Output Slave Input. Configured as toggling input.
2. MISO Pin 15: Master Input, Slave Output: Configured as a toggling output
3. SS_N Pin 2: Slave Select (active low). Configured as toggling input.
4. SCK Pin 3: Serial clock (output from master). Configured as toggling input.
The maximum operating speed supported on the SPI bus is 20 MHz.
7.3.7.7.1 SPI READ/WRITE Transaction
Each SPI transaction to a single device is 17 bits long and is framed by SS_N asserted low. The MOSI input is
ignored and the MISO output is floated whenever SS_N is de-asserted (High).
The bits are shifted in left-to-right. The first bit is R/W, so it is 1 for reads and 0 for writes. Bits A7-A0 are the 8-bit
register address, and bits D7-D0 are the 8-bit read or write data. The prior SPI command, address, and data are
shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI transactions,
the MISO output signal is enabled asynchronously when SS_N becomes asserted.
R/W
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
图 14. MOSI
7.3.7.7.2 SPI Write Transaction Format
For SPI writes, the R/W bit is 0. SPI write transactions are 17 bits per device, and the command is executed on
the rising edge of SS_N, as shown in 图 15. The SPI transaction always starts on the rising edge of the clock.
图 15. MOSI
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
The signal timing for a SPI Write transaction is shown in 图 16. The “prime” values on MISO (for example, A7‟)
reflect the contents of the shift register from the previous SPI transaction, and are a "don’t-care" for the current
transaction.
tSSOF
SS_N
tSSH
t
t
t
PL
SSSU
PH
SCK
t
H
t
SU
MOSI
MISO
HiZ
D7
A7
A6
A5
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
D0
0
todz
HiZ
R/W'
A7'
A6'
A5'
A4'
A3'
A2'
A1'
A0'
D6'
D5'
D4'
D3'
D2'
D1'
D0'
D7'
图 16. Signal Timing for a SPI Write Transaction
22
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7.3.7.7.3 SPI Read Transaction Format
A SPI read transaction is 34 bits per device consisting of two 17 bits frames. The first 17-bit read transaction, first
frame, shifts in the address to be read, followed by a dummy transaction, second frame, to shift out 17-bit read
data. The R/W bit is 1 for the read transaction, as shown in 图 17.
The first 17 bits from the read transaction specifies 1-bit of RW and 8-bits of address A7-A0 in the first 8 bits. The
eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on address
0xFF and needs to be ignored. However, the transaction is necessary in order to shift out the read data D7-D0 in
the last 8 bits of the MISO output.
The signal timing for a SPI Read Transaction is shown in 图 17. As with the SPI Write, the “prime” values on
MISO during the first 16 clocks are a don’t-care for this portion of the transaction. Note, however, that the values
shifted out on MISO during the last 17 clocks reflect the read address and 8-bit read data for the current
transaction.
SS_N
(host)
t
SSOF
t
SSOF
t
SSH
t
t
t
PL
SSSU PH
SCK
(host)
t
H
—8X1“
—17X1“
t
SU
MOSI
(host)
1
A7 A6 A5 A4 A3 A2 A1 A0
todz
tod
tozd
MISO
(device)
D
1
D
0
A
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
D
7
D
6
D
5
D
4
D
3
D
2
Don‘t Care
1
图 17. Signal Timing for a SPI Read Transaction
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7.3.7.8 SPI Daisy Chain
The LMH1218 includes an enhanced SPI controller that supports daisy-chaining the serial configuration data
among multiple LMH1218 devices. The LMH1218 device supports SPI Daisy Chain between devices with an 8-
bit SPI addressing scheme. Each LMH1218 device is directly connected to the SCK and SS_N pins of the Host.
However, only the first LMH1218 device in the chain is connected to the Host’s MOSI pin, and only the last
device in the chain is connected to the Host’s MISO pin. The MOSI pin of each intermediate LMH1218 device in
the chain is connected to the MISO pin of the previous LMH1218 device, thereby creating a serial shift register.
This architecture is shown in 图 18:
MISO
Device 1
Device 2
Device 3
Device N
Host
LMH1218
LMH1218
LMH1218
LMH1218
. . .
MOSI
MOSI
MISO
MOSI
MISO
MOSI
MISO
MOSI
MISO
SCK
SS
图 18. Daisy-Chain Configuration
In a daisy-chain configuration of N LMH1218 devices, the Host conceptually sees a long shift register of length
17xN. Therefore the length of a Basic SPI Transaction, as described above, is 17xN; in other words, SS_N is
asserted for 17xN clock cycles.
7.3.7.8.1 SPI Daisy Chain Write Example
The following example make some assumptions:
The daisy-chain is 3 LMH1218 devices long, comprising Devices 1, 2, and 3 as shown in 图 18. Therefore, each
Basic SPI Transaction is 17x3 = 51 clocks long.
In 图 19, the following occurs at the end of the transaction:
•
•
•
Write 0x5A to register 0x12 in Device 3
Write 0x3C to register 0x34 in Device 2
Write 0x00 to register 0x56 in Device 1
Note that the bits are shifted out of MOSI left to right. The MISO pin is not shown as it reflects shift register
contents from a prior transaction.
MOSI
(Write)
0
0x12
0x5A
0
0x34
0x3C
0
0x56
0x00
图 19. MOSI Write
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7.3.7.8.2 SPI Daisy Chain Write Read Example
In 图 20 and 图 21, the following occurs at the end of the first transaction:
•
•
•
Write 0x22 to register 0x01 in Device 3
Latch the data from register 0x34 in Device 2
Write 0x44 to register 0x76 in Device 1
MOSI
(Host)
0
0x01
0x22
1
0x34
0xFF
0
0x76
0x44
图 20. SPI Daisy Chain Write Read First Frame Illustration
MOSI
(Host)
1
0
0xFF
0x01
0xFF
0x22
1
1
0xFF
0x34
0xFF
0x3C
1
0
0xFF
0x76
0xFF
0x44
MISO
(Host)
图 21. SPI Daisy Chain Write Read second Frame Illustration
7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
A useful operation for the Host may be to detect the length of the daisy-chain. This is a simple matter of shifting
in a series of known data values (0x7F, 0xAA) in the example in 图 22. After N+1 writes, the known data value
will begin to appear on the Host's MISO pin.
MOSI
(Host)
1
x
0x7F
xx
0xAA
xx
1
x
0x7F
xx
0xAA
xx
1
1
0x7F
0x7F
0xAA
0xAA
MISO
(Host)
图 22. MOSI (Host)
7.3.8 Power-On Reset
The LMH1218 has an internal power-on reset (PoR) circuitry which initiates a self-clearing reset after the power
is applied to the VDD pins.
7.4 Device Functional Modes
The LMH1218 features can be programmed via SPI, or SMBus interface. LMH1218 Device Configuration
describes detailed operation using SPI, or SMBus interface.
7.5 Programming
For more information on device programming, refer to LMH1218 Programming Guide (SNLU174). Register
initialization is required at power-up or after reset. See Initialization Set Up
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7.6 Register Maps
The LMH1218 register set definition is divided into four groups:
1. Global Registers: Chip ID, Interrupt status, LOS registers
2. Receiver Registers: Equalizer boost settings and signal detect setting
3. CDR Registers: PLL control
4. Transmitter Registers: OUT0 and OUT1 parameter setting
Additionally, the global register is divided into share and channel registers. Share registers define chip ID, device
revision while channel registers are feature-specific.
The typical device initialization sequence for the LMH1218 includes the followings. For detailed register settings
refer to LMH1218 Programming Guide (SNLU174).
1. Shared Register Configuration
a. Reading device ID
b. Selecting interrupt on to LOS pin
c. Settings up the register to access the channel registers
2. Channel Register Configuration
a. CDR Reset
b. Interrupt register configuration
c. CDR data rate selection
d. Optional Input/Output selection
e. Optional VOD selection
f. CDR Reset and Release
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Register Maps (接下页)
7.6.1 Global Registers
Table 5. Global Registers
FIELD REGISTER
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
ADDRESS
Reg_0x00 Share
SMBUS_addr3
SMBUS_addr2
SMBUS_addr1
SMBUS_addr0
Reserved
SMBus Observation
0x00
SMBus Address Observation
7
6
5
4
3
2
1
0
0
0
R
R
SMBus strap observation
0
R
0
R
0
RW
RW
RW
RW
Reserved
0
Reserved
0
Reserved
0
Reset Shared Regs
Reg 0x04 Share
Reserved
0x01
0
Shared Register Reset
7
6
RW
RW
1: Reset Shared Registers
0: Normal operation
rst_i2c_regs
0
5
4
3
2
1
0
Reserved
0
0
RW
RW
RW
RW
RW
RW
Reserved
Reserved
0
Reserved
0
Reserved
0
Reserved
1
Enable SMBus Strap
Reg 0x06 Share
Reserved
0x00
0
Allow SMBus strap observation
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
0
Reserved
0
Reserved
0
Test control[3]
Test control[2]
Test control[1]
Test control[0]
Reg 0xF0 Share
VERSION[7]
VERSION[6]
VERSION[5]
VERSION[4]
VERSION[3]
VERSION[2]
VERSION[1]
VERSION[0]
0
0
Set to >9 to allow strap observation on
share reg 0x00
0
0
Device Version
0x01
0
Device Version
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
Device revision
0
0
0
1
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Register Maps (接下页)
Table 5. Global Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
Device ID
BITS
DEFAULT
R/RW
DESCRIPTION
Reg 0xF1 Share
0x60
Device ID
Device ID
7
6
5
4
3
2
1
0
DEVICE_ID[7]
DEVICE_ID[6]
DEVICE_ID[5]
DEVICE_ID[4]
DEVICE_ID[3]
DEVICE_ID[2]
DEVICE_ID[1]
DEVICE_ID[0]
Reg 0xFF Control
Reserved
0
1
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
0
0
Channel Control
0x00
0
Enable Channel Control
7
6
RW
RW
Reserved
0
1: Selects interrupt onto LOS pin
0: Select signal detect onto LOS pin
5
los_int_bus_sel
0
RW
4
3
Reserved
Reserved
0
0
RW
RW
1: Enables access to channel registers
0: Enable access to share register
2
en_ch_Access
0
RW
1
0
Reserved
Reserved
0
0
RW
RW
Reset_Channel_Regs
Reset all Channel Registers to Default
Values
Reg_0x00 Channel
0x00
7
6
5
4
3
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
1: Reset Channel Registers ( self
clearing )
2
Rst_regs
0
0: Normal operation
1
0
Reserved
0
Reserved
0
LOS_status
Reg_0x01 Channel
Reserved
0x00
Signal Detect Status
7
6
5
4
3
2
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
Reserved
Reserved
Reserved
Reserved
Reserved
1: Loss of signal on IN1
0: Signal present on IN1
1
0
LOS1
LOS0
0
0
R
R
1: Loss of signal on IN0
0: Signal present on IN0
28
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Register Maps (接下页)
Table 5. Global Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
CDR_Status_1
BITS
DEFAULT
R/RW
DESCRIPTION
Reg_0x02 Channel
Reserved
0x00
CDR Status
7
6
5
4
3
2
1
0
0
R
R
R
R
R
R
R
R
Reserved
0
Reserved
0
cdr_status[4]
cdr_status[3]
Reserved
0
0
11: CDR locked
00: CDR not locked
0
Reserved
0
Reserved
0
Interrupt Status Register
Reg 0x54 Channel
0x00
Interrupt Status ( clears upon read )
1: Signal Detect from the selected input
asserted
0: Signal Detect from the selected input
de-asserted
7
Sigdet
0
R
1: CDR Lock interrupt
0: No interrupt from CDR Lock
6
5
4
cdr_lock_int
0
0
0
R
R
R
1: IN1 Signal Detect interrupt
0: No interrupt from IN1 Signal Detect
signal_det1_int
signal_det0_int
1: IN0 Signal Detect interrupt
0: No interrupt from IN0 Signal Detect
1: HEO_VEO Threshold reached
interrupt
3
heo_veo_int
0
R
0: No interrupt from HEO_VEO
1: CDR loss of lock interrupt
0: No interrupt from CDR lock
2
1
0
cdr_lock_loss_int
0
0
0
R
R
R
1: IN1 Signal Detect loss interrupt
0: No interrupt from IN1 Signal Detect
signal_det1_loss_int
signal_det0_loss_int
1: IN0 Signal Detect loss interrupt
0: No interrupt from IN0 Signal Detect
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Register Maps (接下页)
Table 5. Global Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
Interrupt Mask
Interrupt Control
Reg 0x56 Channel
Reserved
0x00
0
7
6
RW
RW
1: Enable Interrupt if CDR lock is
achieved
0: Disable interrupt if CDR lock is
achieved
cdr_lock_int_en
0
0
0
1: Enable interrupt if IN1 Signal Detect
is asserted
0: Disable interrupt if IN1 Signal Detect
is asserted
5
4
signal_det1_int_en
signal_det0_int_en
RW
RW
1: Enable interrupt if IN0 Signal Detect
is asserted
0: Disable interrupt if IN0 Signal Detect
is asserted
1: Enable interrupt if HEO-VEO
threshold is reached
0: Disable interrupt due to HEO-VEO
threshold
3
2
1
heo_veo_int_en
0
0
0
RW
RW
RW
1: Enable interrupt if CDR loses lock
0: Disable interrupt if CDR loses lock
cdr_lock_loss_int_en
signal_det1_loss_int_en
1: Enable interrupt if there is loss of
signal on IN1
0: Disable interrupt if there is loss of
signal on IN1
1: Enable interrupt if there is loss of
signal on IN0
0: Disable interrupt if there is loss of
signal on IN0
0
signal_det0_loss_int_en
0
RW
30
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7.6.2 Receiver Registers
Table 6. Receiver Registers
FIELD REGISTER
REGISTER NAME
EQ_Boost
BITS
DEFAULT
R/RW
DESCRIPTION
ADDRESS
Reg 0x03 Channel
4 Stage EQ Boost Levels. Read-back
value going to CTLE in reg_0x52. Used
for setting EQ value when reg_0x2D[3] is
high
0x80
7
6
5
4
3
2
1
0
eq_BST0[1]
eq_BST0[0]
eq_BST1[1]
eq_BST1[0]
eq_BST2[1]
eq_BST2[0]
eq_BST3[1]
eq_BST3[0]
Reg_0x0D Channel
Reserved
1
0
RW
RW
RW
RW
RW
RW
RW
RW
2 Bits control for stage 0 of the CTLE.
Adapts during CTLE adaptation
0
2 Bits control for stage 1 of the CTLE.
Adapts during CTLE adaptation
0
0
2 Bits control for stage 2 of the CTLE.
Adapts during CTLE adaptation
0
0
2 Bits control for stage 3 of the CTLE.
Adapts during CTLE adaptation
0
SD_EQ
0x00
0
270 Mbps EQ Boost Setting
7
6
5
4
3
2
1
RW
RW
RW
RW
RW
RW
RW
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Mr_auto_eq_en_bypass
1: EQ Bypass for 270 Mbps
0: Use EQ Settings in reg0x03[7:0] for 270
Mbps
Note: If 0x13[1] mr_eq_en_bypass is set,
bypass would be set and auto-bypass has
no significance.
0
0
RW
EQ_SD_CONFIG
Reg 0x13 Channel
Reserved
0x90
1
Channel EQ Bypass and Power Down
7
6
RW
RW
sd_0_PD
1: Power Down IN0 Signal Detect
0: IN0 Signal Detect normal operation
0
sd_1_PD
1: Power Down IN1 Signal Detect
0: IN1 Signal Detect normal operation
5
4
0
1
RW
RW
Reserved
eq_PD_EQ
Controls the power-state of the selected
channel. The un-selected channel is
always powered-down
1: Powers down selected channel EQ
stage
3
0
RW
0: Powers up EQ of the selected channel
2
1
0
Reserved
0
0
0
RW
RW
RW
eq_en_bypass
1: Bypass stage 3 and 4 of CTLE
0: Enable Stage 3 and 4 of CTLE
Reserved
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Table 6. Receiver Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
SD0_CONFIG
BITS
DEFAULT
R/RW
DESCRIPTION
Reg 0x14 Channel
Reserved
0x00
IN0 Signal Detect Threshold Setting
7
6
5
4
3
0
0
0
0
0
RW
RW
RW
RW
RW
Reserved
sd_0_refa_sel[1]
sd_0_refa_sel[0]
sd_0_refd_sel[1]
sd_0_refd_sel[0]
Controls signal detect SDH- Assert [5:4],
SDL- De-Assert [3:2], thresholds for IN0
0000: Default levels (nominal)
0101: Nominal -2 mV
1010: Nominal +5 mV
1111: Nominal +3 mV
2
0
RW
1
0
Reserved
0
RW
RW
Reserved
0
SD1_CONFIG
Reg_0x15 Channel
Reserved
0x00
IN1 Signal Detect Threshold Setting
7
6
5
4
3
0
0
0
0
0
RW
RW
RW
RW
RW
Reserved
sd_1_refa_sel[1]
sd_1_refa_sel[0]
sd_1_refd_sel[1]
sd_1_refd_sel[0]
Controls signal detect SDH- Assert [5:4],
SDL- De-Assert [3:2], thresholds for IN1
0000: Default levels (nominal)
0101: Nominal -2 mV
1010: Nominal +5 mV
1111: Nominal +3 mV
2
0
RW
1
0
Reserved
0
RW
RW
Reserved
0
0x88
1
EQ_BOOST_OV
Reg_0x2D Channel
Reserved
EQ Boost Override
7
6
5
4
RW
RW
RW
RW
Reserved
0
Reserved
0
Reserved
0
reg_eq_bst_ov
1: Enable EQ boost over ride- refer to
theLMH1218 Programming Guide
(SNLU174)
3
1
RW
0: Disable EQ boost over ride
2
1
0
Reserved
0
0
0
RW
RW
RW
Reserved
Reserved
CTLE Setting
Reg_0x31 Channel
CTLE Mode of Operation and Input/Output
Mux Selection
0x00
0
7
6
Reserved
RW
RW
adapt_mode[1]
adapt_mode[0]
00: Normal Operation - Manual CTLE
Setting
01: Test Mode - Refer to the LMH1218
Programming Guide (SNLU174)
Other Settings - Invalid
00
5
4
3
2
1
Reserved
0
0
0
0
RW
RW
RW
RW
Reserved
Reserved
input_mux_ch_sel[1]
input_mux_ch_sel[0]
IN0/1 and OUT0/1 selection
00: selects IN0 and OUT0/1
01: selects IN0 and OUT0
10: selects IN1 and OUT1
11: selects IN1 and OUT0/1
0
0
RW
32
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Table 6. Receiver Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
HD and SD EQ Level
LOW_RATE_
EQ_BST
Reg 0x3A Channel
0x00
7
6
5
4
3
2
1
0
fixed_eq_BST0[1]
fixed_eq_BST0[0]
fixed_eq_BST1[1]
fixed_eq_BST1[0]
fixed_eq_BST2[1]
fixed_eq_BST2[0]
fixed_eq_BST3[1]
fixed_eq_BST3[0]
Reg_0x40 Channel
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
When CTLE is operating in test mode,
Reg 0x3A[7:0] forces fixed EQ setting for
data rates <= 3Gbps. In normal operating
manual mode Reg_0x03 forces EQ boost.
Note LMH1218 Programming Guide
(SNLU174) for details
BST_Indx0
Index0 4 Stage EQ Boost. Note LMH1218
Programming Guide (SNLU174) for details
0x00
7
6
5
4
3
2
1
0
I0_BST0[1]
I0_BST0[0]
I0_BST1[1]
I0_BST1[0]
I0_BST2[1]
I0_BST2[0]
I0_BST3[1]
I0_BST3[0]
Reg 0x41 Channel
I1_BST0[1]
I1_BST0[0]
I1_BST1[1]
I1_BST1[0]
I1_BST2[1]
I1_BST2[0]
I1_BST3[1]
I1_BST3[0]
Reg 0x42 Channel
I2_BST0[1]
I2_BST0[0]
I2_BST1[1]
I2_BST1[0]
I2_BST2[1]
I2_BST2[0]
I2_BST3[1]
I2_BST3[0]
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Index 0 Boost Stage 0 bit 1
Index 0 Boost Stage 0 bit 0
Index 0 Boost Stage 1 bit 1
Index 0 Boost Stage 1 bit 0
Index 0 Boost Stage 2 bit 1
Index 0 Boost Stage 2 bit 0
Index 0 Boost Stage 3 bit 1
Index 0 Boost Stage 3 bit 0
Index1 4 Stage EQ Boost.
Index 1 Boost Stage 0 bit 1
Index 1 Boost Stage 0 bit 0
Index 1 Boost Stage 1 bit 1
Index 1 Boost Stage 1 bit 0
Index 1 Boost Stage 2 bit 1
Index 1 Boost Stage 2 bit 0
Index 1 Boost Stage 3 bit 1
Index 1 Boost Stage 3 bit 0
Index2 4 Stage EQ Boost.
Index 2 Boost Stage 0 bit 1
Index 2 Boost Stage 0 bit 0
Index 2 Boost Stage 1 bit 1
Index 2 Boost Stage 1 bit 0
Index 2 Boost Stage 2 bit 1
Index 2 Boost Stage 2 bit 0
Index 2 Boost Stage 3 bit 1
Index 2 Boost Stage 3 bit 0
0
0
0
0
0
0
BST_Indx1
0x40
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
0
0
0
BST_Indx2
0x80
1
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
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33
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www.ti.com.cn
Table 6. Receiver Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
BST_Indx3
BITS
DEFAULT
R/RW
DESCRIPTION
Reg 0x43 Channel
I3_BST0[1]
I3_BST0[0]
I3_BST1[1]
I3_BST1[0]
I3_BST2[1]
I3_BST2[0]
I3_BST3[1]
I3_BST3[0]
Reg 0x44 Channel
I4_BST0[1]
I4_BST0[0]
I4_BST1[1]
I4_BST1[0]
I4_BST2[1]
I4_BST2[0]
I4_BST3[1]
I4_BST3[0]
Reg 0x45 Channel
I5_BST0[1]
I5_BST0[0]
I5_BST1[1]
I5_BST1[0]
I5_BST2[1]
I5_BST2[0]
I5_BST3[1]
I5_BST3[0]
Reg 0x46 Channel
I6_BST0[1]
I6_BST0[0]
I6_BST1[1]
I6_BST1[0]
I6_BST2[1]
I6_BST2[0]
I6_BST3[1]
I6_BST3[0]
Reg 0x47 Channel
I7_BST0[1]
I7_BST0[0]
I7_BST1[1]
I7_BST1[0]
I7_BST2[1]
I7_BST2[0]
I7_BST3[1]
I7_BST3[0]
0x50
Index3 4 Stage EQ Boost.
Index 3 Boost Stage 0 bit 1
Index 3 Boost Stage 0 bit 0
Index 3 Boost Stage 1 bit 1
Index 3 Boost Stage 1 bit 0
Index 3 Boost Stage 2 bit 1
Index 3 Boost Stage 2 bit 0
Index 3 Boost Stage 3 bit 1
Index 3 Boost Stage 3 bit 0
Index4 4 Stage EQ Boost.
Index 4 Boost Stage 0 bit 1
Index 4 Boost Stage 0 bit 0
Index 4 Boost Stage 1 bit 1
Index 4 Boost Stage 1 bit 0
Index 4 Boost Stage 2 bit 1
Index 4 Boost Stage 2 bit 0
Index 4 Boost Stage 3 bit 1
Index 4 Boost Stage 3 bit 0
Index5 4 Stage EQ Boost.
Index 5 Boost Stage 0 bit 1
Index 5 Boost Stage 0 bit 0
Index 5 Boost Stage 1 bit 1
Index 5 Boost Stage 1 bit 0
Index 5 Boost Stage 2 bit 1
Index 5 Boost Stage 2 bit 0
Index 5 Boost Stage 3 bit 1
Index 5 Boost Stage 3 bit 0
Index6 4 Stage EQ Boost.
Index 6 Boost Stage 0 bit 1
Index 6 Boost Stage 0 bit 0
Index 6 Boost Stage 1 bit 1
Index 6 Boost Stage 1 bit 0
Index 6 Boost Stage 2 bit 1
Index 6 Boost Stage 2 bit 0
Index 6 Boost Stage 3 bit 1
Index 6 Boost Stage 3 bit 0
Index7 4 Stage EQ Boost.
Index 7 Boost Stage 0 bit 1
Index 7 Boost Stage 0 bit 0
Index 7 Boost Stage 1 bit 1
Index 7 Boost Stage 1 bit 0
Index 7 Boost Stage 2 bit 1
Index 7 Boost Stage 2 bit 0
Index 7 Boost Stage 3 bit 1
Index 7 Boost Stage 3 bit 0
7
6
5
4
3
2
1
0
0
RW
RW
RW
RW
RW
RW
RW
RW
1
0
1
0
0
0
0
BST_Indx4
BST_Indx5
BST_Indx6
BST_Indx7
0xC0
7
6
5
4
3
2
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
0
0
0
0x90
7
6
5
4
3
2
1
0
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
1
0
0
0
0
0x54
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
1
0
1
0
1
0
0
0xA0
1
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
1
0
0
0
0
0
34
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Table 6. Receiver Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
BST_Indx8
BST_Indx9
BST_Indx10
BST_Indx11
BSTIndx12
Reg 0x48 Channel
I8_BST0[1]
0xB0
Index8 4 Stage EQ Boost.
Index 8 Boost Stage 0 bit 1
Index 8 Boost Stage 0 bit 0
Index 8 Boost Stage 1 bit 1
Index 8 Boost Stage 1 bit 0
Index 8 Boost Stage 2 bit 1
Index 8 Boost Stage 2 bit 0
Index 8 Boost Stage 3 bit 1
Index 8 Boost Stage 3 bit 0
Index9 4 Stage EQ Boost.
Index 9 Boost Stage 0 bit 1
Index 9 Boost Stage 0 bit 0
Index 9 Boost Stage 1 bit 1
Index 9 Boost Stage 1 bit 0
Index 9 Boost Stage 2 bit 1
Index 9 Boost Stage 2 bit 0
Index 9 Boost Stage 3 bit 1
Index 9 Boost Stage 3 bit 0
Index10 4 Stage EQ Boost.
Index 10 Boost Stage 0 bit 1
Index 10 Boost Stage 0 bit 0
Index 10 Boost Stage 1 bit 1
Index 10 Boost Stage 1 bit 0
Index 10 Boost Stage 2 bit 1
Index 10 Boost Stage 2 bit 0
Index 10 Boost Stage 3 bit 1
Index 10 Boost Stage 3 bit 0
Index11 4 Stage EQ Boost.
Index 11 Boost Stage 0 bit 1
Index 11 Boost Stage 0 bit 0
Index 11 Boost Stage 1 bit 1
Index 11 Boost Stage 1 bit 0
Index 11 Boost Stage 2 bit 1
Index 11 Boost Stage 2 bit 0
Index 11 Boost Stage 3 bit 1
Index 11 Boost Stage 3 bit 0
Index12 4 Stage EQ Boost.
Index 12 Boost Stage 0 bit 1
Index 12 Boost Stage 0 bit 0
Index 12 Boost Stage 1 bit 1
Index 12 Boost Stage 1 bit 0
Index 12 Boost Stage 2 bit 1
Index 12 Boost Stage 2 bit 0
Index 12 Boost Stage 3 bit 1
Index 12 Boost Stage 3 bit 0
7
6
5
4
3
2
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
0x95
RW
RW
RW
RW
RW
RW
RW
RW
I8_BST0[0]
0
I8_BST1[1]
1
I8_BST1[0]
1
I8_BST2[1]
0
I8_BST2[0]
0
I8_BST3[1]
0
I8_BST3[0]
0
Reg 0x49 Channel
I9_BST0[1]
0X95
7
6
5
4
3
2
1
0
1
I9_BST0[0]
0
I9_BST1[1]
0
I9_BST1[0]
1
I9_BST2[1]
0
I9_BST2[0]
1
I9_BST3[1]
0
I9_BST3[0]
1
Reg 0x4A Channel
I10_BST0[1]
I10_BST0[0]
I10_BST1[1]
I10_BST1[0]
I10_BST2[1]
I10_BST2[0]
I10_BST3[1]
I10_BST3[0]
Reg 0x4B Channel
I11_BST0[1]
I11_BST0[0]
I11_BST1[1]
I11_BST1[0]
I11_BST2[1]
I11_BST2[0]
I11_BST3[1]
I11_BST3[0]
Reg 0x4C Channel
I12_BST0[1]
I12_BST0[0]
I12_BST1[1]
I12_BST1[0]
I12_BST2[1]
I12_BST2[0]
I12_BST3[1]
I12_BST3[0]
0x69
7
6
5
4
3
2
1
0
0
RW
RW
RW
RW
RW
RW
RW
RW
1
1
0
1
0
0
1
0xD5
7
6
5
4
3
2
1
0
1
1
RW
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0x99
1
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
1
0
0
1
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Table 6. Receiver Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
BST_Indx13
BITS
DEFAULT
R/RW
DESCRIPTION
Reg 0x4D Channel
I13_BST0[1]
I13_BST0[0]
I13_BST1[1]
I13_BST1[0]
I13_BST2[1]
I13_BST2[0]
I13_BST3[1]
I13_BST3[0]
Reg 0x4E Channel
I14_BST0[1]
I14_BST0[0]
I14_BST1[1]
I14_BST1[0]
I14_BST2[1]
I14_BST2[0]
I14_BST3[1]
I14_BST3[0]
Reg 0x4F Channel
I15_BST0[1]
I15_BST0[0]
I15_BST1[1]
I15_BST1[0]
I15_BST2[1]
I15_BST2[0]
I15_BST3[1]
I15_BST3[0]
Reg 0x52 Channel
eq_bst_to_ana[7]
eq_bst_to_ana[6]
eq_bst_to_ana[5]
eq_bst_to_ana[4]
eq_bst_to_ana[3]
eq_bst_to_ana[2]
eq_bst_to_ana[1]
eq_bst_to_ana[0]
Reg 0x55 Channel
Reserved
0xA5
Index13 4 Stage EQ Boost.
Index 13 Boost Stage 0 bit 1
Index 13 Boost Stage 0 bit 0
Index 13 Boost Stage 1 bit 1
Index 13 Boost Stage 1 bit 0
Index 13 Boost Stage 2 bit 1
Index 13 Boost Stage 2 bit 0
Index 13 Boost Stage 3 bit 1
Index 13 Boost Stage 3 bit 0
Index14 4 Stage EQ Boost.
Index 14 Boost Stage 0 bit 1
Index 14 Boost Stage 0 bit 0
Index 14 Boost Stage 1 bit 1
Index 14 Boost Stage 1 bit 0
Index 14 Boost Stage 2 bit 1
Index 14 Boost Stage 2 bit 0
Index 14 Boost Stage 3 bit 1
Index 14 Boost Stage 3 bit 0
Index15 4 Stage EQ Boost.
Index 15 Boost Stage 0 bit 1
Index 15 Boost Stage 0 bit 0
Index 15 Boost Stage 1 bit 1
Index 15 Boost Stage 1 bit 0
Index 15 Boost Stage 2 bit 1
Index 15 Boost Stage 2 bit 0
Index 15 Boost Stage 3 bit 1
Index 15 Boost Stage 3 bit 0
7
6
5
4
3
2
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
0
1
0
0
1
0
1
BST_Indx14
BST_Indx15
Active_EQ
0xE6
7
6
5
4
3
2
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
1
1
0
0
1
1
0
0xF9
7
6
5
4
3
2
1
0
1
1
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
0
0
1
0x00
0
Active CTLE Boost Setting Read Back
Read-back returns CTLE boost settings
Low Rate <=3G EQ Adaptation Control
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
EQ_Control
0x00
0
7
6
5
4
3
2
R
Reserved
0
RW
RW
RW
RW
RW
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
At power-up, this bit needs to be set to
1'b. See initialization set up
1
0
0
0
RW
RW
Reserved
36
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
www.ti.com.cn
ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
7.6.3 CDR Registers
Table 7. CDR Registers
REGISTER
NAME
FIELD REGISTER
BITS
DEFAULT
R/RW
DESCRIPTION
ADDRESS
Reg 0x09 Channel
Reserved
Output_Mux_OV
0x00
Output Data Mux Override
7
6
0
0
RW
RW
Reserved
1: Enable values from 0x1E[7:5] &
0x1C[7:5] to control output mux
0: Register 0x1C[3:2] determines the
output selection
5
Reg_bypass_pfd_ovd
0
RW
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reg 0x0A Channel
Reserved
Reserved
Reserved
Reserved
0
0
RW
RW
RW
RW
RW
0
0
0
CDR_Reset
0x50
0
CDR State Machine Reset
7
6
5
4
RW
RW
RW
RW
1
0
1
1: Enable 0x0A[2] to control CDR Reset
0: Disable CDR Reset
3
2
reg_cdr_reset_ov
reg_cdr_reset_sm
0
0
RW
RW
1: Enable CDR Reset if 0x0A[3] = 1'b
0: Disable CDR Reset if 0x0A[3] = 1'b
1
0
Reserved
0
0
RW
RW
Reserved
CDR_Status
Reg 0x0C Channel
reg_sh_status_control[3]
reg_sh_status_control[2]
reg_sh_status_control[1]
reg_sh_status_control[0]
Reserved
0x08
0
CDR Status Control
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Determines what is shown in Reg 0x02.
Note LMH1218 Programming Guide
(SNLU174) for details
0
0
0
1
Reserved
0
Reserved
0
Reserved
0
EOM Vrange Setting and EOM Power
Down Control
EOM_Vrange
Reg 0x11 Channel
eom_sel_vrange[1]
0xE0
7
6
Sets eye monitor ADC granularity if
0x2C[6] =0'b
00: 3.125 mV
01: 6.25 mV
10: 9.375 mV
11
RW
RW
eom_sel_vrange[0]
11: 12.5 mV
0: EOM Operational
1: Power down EOM
5
eom_PD
1
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
RW
RW
RW
RW
RW
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www.ti.com.cn
Table 7. CDR Registers (continued)
REGISTER
NAME
FIELD REGISTER
BITS
DEFAULT
R/RW
DESCRIPTION
ADDRESS
Full Temperature
Range
Reg 0x16 Channel
0x7A
Temperature Range Setting
7
6
5
4
3
2
1
0
Reserved
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
1
Reserved
1
Reserved
1
1
At power-up, this register needs to be set
to 0x25. See initialization set up
Reserved
Reserved
0
Reserved
1
Reserved
0
HEO_VEO_OV
Reg 0x23 Channel
0x40
1: Enable reg 0x24[1] to acquire HEO/VEO
0: Disable reg 0x24[1] to acquire HEO/VEO
7
eom_get_heo_veo_ov
0
RW
6
5
4
3
2
1
0
Reserved
1
RW
RW
RW
RW
RW
RW
RW
0x00
Reserved
0
Reserved
0
0
Reserved
Reserved
0
Reserved
0
Reserved
0
EOM_CNTL
Reg 0x24 Channel
0x00
Eye Opening Monitor Control Register
1: Enable Fast EOM mode
0: Disable fast EOM mode
7
6
fast_eom
Reserved
0
0
RW
R
1: No zero crossing in the eye diagram
observed
0: Zero crossing in the eye diagram
detected
5
get_heo_veo_error_no_hits
0
R
get_heo_veo_error_no_ope
ning
1: Eye diagram is completely closed
0: Open eye diagram detected
4
0
R
3
2
1
0
Reserved
0
0
R
R
Reserved
eom_get_heo_veo
eom_start
0
RW
R
Acquire HEO & VEO(self-clearing)
Starts EOM counter(self-clearing)
Eye opening monitor hits(MSB)
0
EOM_MSB
Reg 0x25 Channel
eom_count[15]
eom_count[14]
eom_count[13]
eom_count[12]
eom_count[11]
eom_count[10]
eom_count[9]
eom_count[8]
0x00
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
MSBs of EOM counter
0
0
0
0
38
Copyright © 2015–2018, Texas Instruments Incorporated
LMH1218
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ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Table 7. CDR Registers (continued)
REGISTER
NAME
FIELD REGISTER
ADDRESS
BITS
DEFAULT
R/RW
DESCRIPTION
EOM_LSB
Reg 0x26 Channel
eom_count[7]
eom_count[6]
eom_count[5]
eom_count[4]
eom_count[3]
eom_count[2]
eom_count[1]
eom_count[0]
Reg 0x27 Channel
heo[7]
0x00
Eye opening monitor hits(LSB)
7
6
5
4
3
2
1
0
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
LSBs of EOM counter
Horizontal Eye Opening
0
0
0
0
HEO
0x00
7
6
5
4
3
2
1
0
0
R
R
R
R
R
R
R
R
heo[6]
0
heo[5]
0
HEO value. This is measured in 0-63
phase settings. To get HEO in UI, read
HEO, convert hex to dec, then divide by
64.
heo[4]
0
heo[3]
0
heo[2]
0
heo[1]
0
heo[0]
0
VEO
Reg 0x28 Channel
veo[7]
0x00
Vertical Eye Opening
7
6
5
4
3
2
1
0
0
0
R
R
R
R
R
R
R
R
veo[6]
veo[5]
0
This is measured in 0-63 vertical steps. To
get VEO in mV, read VEO, convert hex to
dec, then multiply by 3.125mV
veo[4]
0
veo[3]
0
veo[2]
0
veo[1]
0
veo[0]
0
Auto_EOM _Vrange
Reg 0x29 Channel
Reserved
eom_vrange_setting[1]
0x00
0
EOM Vrange Readback
7
6
RW
R
Auto Vrange readback of eye monitor
granularity
00: 3.125mV
01: 6.25mV
10: 9.375mV
00
5
eom_vrange_setting[0]
11: 12.5mV
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
RW
RW
RW
RW
RW
Copyright © 2015–2018, Texas Instruments Incorporated
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www.ti.com.cn
Table 7. CDR Registers (continued)
REGISTER
NAME
FIELD REGISTER
BITS
DEFAULT
R/RW
DESCRIPTION
EOM Hit Timer
ADDRESS
Reg 0x2A Channel
eom_timer_thr[7]
eom_timer_thr[6]
eom_timer_thr[5]
eom_timer_thr[4]
eom_timer_thr[3]
eom_timer_thr[2]
eom_timer_thr[1]
eom_timer_thr[0]
Reg 0x2C Channel
Reserved
EOM_Timer_Thr
0x30
7
6
5
4
3
2
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
1
1
EOM timer for how long to check each
phase/voltage setting
0
0
0
0
VEO_Scale
0x32
0
VEO_Scale
7
6
RW
RW
1: Enable Auto VEO scaling
0: VEO scaling based on Vrange Setting
(0x11[7:6])
veo_scale
0
5
4
3
2
1
0
Reserved
1
RW
RW
RW
RW
RW
RW
Reserved
1
Reserved
0
0
Reserved
Reserved
1
Reserved
0
Rate_Subrate
Reg_0x2F Channel
RATE[1]
0x06
0
SMPTE_10GbE Selection
7
6
RW
RW
00: SMPTE Enable
01: 10G Ethernet Enable
Other Settings - Invalid
RATE[0]
0
5
4
3
2
1
0
Reserved
0
0
RW
RW
RW
RW
RW
R
Reserved
Reserved
0
Reserved
1
Reserved
1
Reserved
0
HEO VEO Threshold
Reg 0x32 Channel
heo_int_thresh[3]
heo_int_thresh[2]
heo_int_thresh[1]
heo_int_thresh[0]
veo_int_thresh[3]
veo_int_thresh[2]
veo_int_thresh[1]
veo_int_thresh[0]
0x11
0
HEO/VEO Interrupt Threshold
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
Compares HEO value, 0x27[7:0], vs
threshold 0x32[7:4] * 4
0
1
0
0
Compares VEO value, 0x28[7:0], vs
threshold 0x32[3:0 * 4
0
1
40
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ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Table 7. CDR Registers (continued)
REGISTER
NAME
FIELD REGISTER
ADDRESS
BITS
DEFAULT
R/RW
DESCRIPTION
CDR State Machine
Control
Reg 0x3E Channel
Reserved
0x80
1
CDR State Machine Setting
At power-up, this bit needs to be set to 0'b.
See initialization set up
7
RW
6
5
4
3
2
1
0
Reserved
0
0
RW
RW
RW
RW
RW
RW
RW
Reserved
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
HEO_VEO_Lock
Reg 0x69 Channel
Reserved
0x0A
0
HEO/VEO Interval Monitoring
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
0
Reserved
0
Reserved
0
hv_lckmon_cnt_ms[3]
hv_lckmon_cnt_ms[2]
hv_lckmon_cnt_ms[1]
hv_lckmon_cnt_ms[0]
1
While monitoring lock, this sets the interval
time. Each interval is 6.5 ms. At default
condition, HEO_VEO Lock Monitor occurs
once every 65 ms.
0
1
0
CDR State Machine
Control
Reg 0x6A Channel
0x44
CDR State Machine Control
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reg 0xA0 Channel
Reserved
Reserved
Reserved
0
1
RW
RW
RW
RW
RW
RW
RW
RW
0
0
At power-up, this register should be set to
0x00. See initialization set up
0
1
0
0
SMPTE_Rate_Enable
0x1f
0
SMPTE_Data_Rate_Lock_Restriction
7
6
5
RW
RW
RW
0
0
1: Enable CDR Lock to 270 Mbps
0: Disable CDR Lock to 270 Mbps. Note
LMH1218 Programming Guide (SNLU174)
for details
4
dvb_enable
1
RW
1: Enable CDR Lock to 1.485/1.4835 Gbps
0: Disable CDR Lock to 1.485/1.4835 Gbps
3
2
1
0
hd_enable
3G_enable
6G_enable
12G_enable
1
1
1
1
RW
RW
RW
RW
1: Enable CDR Lock to 2.97/2.967 Gbps
0: Disable CDR Lock to 2.97/2.967 Gbps
1: Enable CDR Lock to 5.94/5.934 Gbps
0: Disable CDR Lock to 5.94/5.934 Gbps
1: Enable CDR Lock to 11.88/11.868 Gbps
0: Disable CDR Lock to 11.88/11.868 Gbps
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7.6.4 Transmitter Registers
Table 8. Transmitter Registers
FIELD REGISTER
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
OUT0 Mux Selection
ADDRESS
Reg 0x1C Channel
pfd_sel0_data_mux[2]
pfd_sel0_data_mux[1]
Out0_Mux_Select
0x18
7
6
0
0
RW
RW
When 0x09[5] = 1'b OUT0 Mux
Selection can be controlled as follows:
000: Mute
001: 10 MHz Clock
010: Raw Data
100: Retimed Data
5
pfd_sel0_data_mux[0]
0
RW
Other Settings - Invalid
When 0x09[5] = 1'b and 0x1E[[7:5] =
101'b OUT1 clock selection can be
controlled as follows:
4
3
VCO_Div40
1
1
RW
RW
1: OUT1 puts out line rate clock for 3G
and below and 297 MHz clock for 5.94
Gbps and 11.88Gbps
0: OUT1 puts out 10MHz clock
mr_drv_out_ctrl[1]
Controls both OUT0 and OUT1:
00:
OUT0: Mute
OUT1: Mute
01:
OUT0: Locked Reclocked Data /
Unlocked Raw Data
OUT1: Locked Output Clock / Unlocked
Mute
2
mr_drv_out_ctrl[0]
0
RW
10:
OUT0: Locked Reclocked Data /
Unlocked RAW
OUT1: Locked Reclocked Data /
Unlocked Raw
11:
OUT0: Forced Raw
OUT1: Forced Raw
1
0
Reserved
0
0
RW
RW
Reserved
OUT1_Mux_Select
Reg 0x1E Channel
pfd_sel_data_mux[2]
pfd_sel_data_mux[1]
0xE9
1
OUT1 Mux Selection
7
6
RW
RW
When 0x09[5] = 1'b OUT0 Mux
Selection can be controlled as follows:
111: Mute
1
101: 10MHz Clock if reg 0x1c[4]=0 and
divided by 40 if reg 0x1c[4] = 1
010: Full Rate Clock
5
pfd_sel_data_mux[0]
1
RW
001: Retimed Data
000: Raw Data
Other Settings - Invalid
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
0
0
1
RW
RW
RW
RW
RW
42
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ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Table 8. Transmitter Registers (continued)
FIELD REGISTER
ADDRESS
REGISTER NAME
OUT1 Invert
BITS
DEFAULT
R/RW
DESCRIPTION
Invert OUT1 Polarity
Reg 0x1F Channel
0x10
0
1: Inverts OUT1 polarity
0: OUT1 Normal polarity
7
pfd_sel_inv_out1
RW
6
5
4
3
2
1
0
Reserved
0
0
RW
RW
RW
RW
RW
RW
RW
Reserved
Reserved
1
Reserved
0
Reserved
0
Reserved
0
Reserved
0
OUT0_VOD
Reg 0x80 Channel
drv_0_sel_vod[3]
drv_0_sel_vod[2]
drv_0_sel_vod[1]
drv_0_sel_vod[0]
Reserved
0x20
0
OUT0 VOD_Scaling_PD
7
6
5
4
3
2
RW
RW
RW
RW
RW
RW
drv_0_sel_vod[3:0] is typically 42 mV
per step. Refer to the LMH1218
Programming Guide (SNLU174) for
setting OUT0 VOD
0
1
0
0
Reserved
0
1: Enable 0x80[0] to override pin/sm
control
1
0
mr_drv_0_ov
0
0
RW
RW
0: Disable 0x80[0] to override pin/sm
control
1: Power down OUT0
0: OUT1 in normal operating mode
sm_drv_0_PD
OUT1_VOD
Reg 0x84 Channel
Reserved
0x04
OUT1 VOD Control
7
6
5
0
0
0
RW
RW
RW
drv_1_sel_vod[2]
drv_1_sel_vod[1]
OUTDriver1 VOD Setting
000: 570 mVDifferential(Diff) Peak to
Peak(PP)
010: 730 mV(Diff PP)
100: 900 mV(Diff PP)
110: 1035 mV(Diff PP)
4
3
drv_1_sel_vod[0]
Reserved
0
0
RW
RW
1: Enables short circuit protection on
OUT1
2
drv_1_sel_scp
1
RW
0: Disable short circuit protection on
OUT1
1: Enable 0x80[0] to override pin/sm
control
1
0
mr_drv_1_ov
sm_drv_1_PD
0
0
RW
RW
0: Disable 0x80[0] to override pin/sm
control
1: Power down OUT1 driver
0: OUT1 in normal operating mode
OUT1_DE
Reg 0x85
0x00
OUT1 DE Control
7
6
5
4
3
2
1
0
Reserved
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
Reserved
Reserved
drv_1_dem_range
drv_1_dem[2]
drv_1_dem[1]
drv_1_dem[0]
Controls de-emphasis of 50 Ω Driver
0000: DE Disabled
0001: 0.2 dB
0010: 1.8 dB
0111: 11 dB
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH1218 is a single channel SDI and 10GbE Cable Driver with Integrated Reclocker that supports different
application spaces. The following sections describe the typical use cases and common implementation practices.
8.1.1 General Guidance for All Applications
The LMH1218 supports two modes of configuration: SPI Mode, and SMBus Mode. Once one of these two control
mechanism is chosen, pay attention to the PCB layout for the high speed signals. SMPTE specifies the
requirements for the Serial Digital Interface to transport digital video at SD, HD, 3Gb/s and higher data rates over
coaxial cables. One of the requirements is meeting the required Return Loss. This requirement specifies how
closely the port resembles 75-Ω impedance across a specified frequency band. The SMPTE specifications also
defines the use of AC coupling capacitors for transporting uncompressed serial data streams with heavy low
frequency content. This specification requires the use of a 4.7µF AC coupling capacitors to avoid low frequency
DC wander. The 75-Ω signal is also required to meet certain rise/fall timing to facilitate highest eye opening for
the receiving device. The LMH1218 built-in 75-Ω termination minimizes parasitic, improving overall signal
integrity. Note: When the FPGA is not transmitting valid SMPTE data, the FPGA output should be muted (P=N).
8.2 Typical Application
VDD
MODE_SEL
0.1 mF
0.01 mF
ENABLE
6
1
7
21
4.7 mF
4.7 mF
4.7 mF
OUT
OUT
11
IN0+
OUT0+
OUT0-
20
LMH1218
75W T-Line
FPGA
FPGA
100W Differential T-Line
100W Differential T-Line
12
19
IN0-
DAP
VSS
75W
24
10
VSS
4.7 mF
8
OUT
OUT
IN1+
IN1-
IN+
IN-
OUT1+
23
Optical Module
9
100W Differential T-Line
OUT1-
22
2
3
4
13
15
16
SS_N
SCK
MOSI
LOS_INT_N
MISO
LOCK
图 23. LMH1218 SPI Mode Configuration
44
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Typical Application (接下页)
The LMH1218 has strong equalization capabilities that allow it to recover data over lossy channel up to 27 dB at
6 GHz. As a result, the optimal placement for the LMH1218 is with the higher loss channel at its input and lower
loss channel segment at the output in order to meet the various SMPTE requirements. To meet SMPTE
requirements, it is strongly recommended to put the LMH1218 as close as possible to the BNC (within 1 inch).
The LMH1218 can be used as a cable driver with integrated reclocker or as reclocker only.
8.2.1 Design Requirements
For the LMH1218 design example, the requirements noted in 表 9 apply.
表 9. LMH1218 Design Parameters
DESIGN PARAMETER
Input AC coupling capacitors
REQUIREMENT
Required. 4.7 µF AC coupling capacitors are recommended.
Capacitors may be implemented on the PCB or in the connector.
Required. Both OUT0 and OUT1 require AC coupling capacitors.
OUT0 AC Coupling capacitors is expected to be 4.7 µF to comply
with SMPTE wander requirement. It is assumed that Optical Module
has AC coupling capacitors on its input within the module
Output AC coupling capacitors
To minimize power supply noise, use 0.01 µF capacitors as close to
the device VDD pins as possible
DC Power Supply Coupling Capacitors
Distance from Device to BNC
Keep this distance within 1 inch to meet Proposed ST-2081 and ST-
2082 requirements
Design differential trace impedance of IN0, IN1, and OUT1 with 100-
Ω ± 5%, single-end trace impedance for OUT0 with 75 Ω ± 5%
High Speed IN0, IN1, OUT0, and OUT1 trace impedance
VDD
MODE_SEL
0.01 mF
0.01 mF
ENABLE
6
1
7
21
4.7 mF
OUT
OUT
11
12
OUT0+
OUT0-
IN0+
20
19
LMH1218
75W T-Line
4.7 mF
100W Differential T-Line
4.7 mF
FPGA
IN0-
DAP
VSS
75W
24
10
DAP = GND
VSS
8
9
OUT
OUT
IN1+
IN1-
IN+
IN-
OUT1+
FPGA
4.7 mF
100W Differential T-Line
23
22
Optical Module
100W Differential T-Line
OUT1-
2
15
3
4
13
16
ADDR0
ADDR1
SCL
SDA
LOS_INT_N
LOCK
图 24. LMH1218 SMBus Mode Configuration
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8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
1. Maximum power draw for PCB regulator selection. In this case, use the transient CDR power (during
acquisition) specified in the datasheet, multiplied by the number of channels.
2. Maximum operational power for thermal calculation. For thermal calculation, use the locked power number.
Transient power consumption is only observed during lock acquisition, which typically lasts for <5ms.
Additional margin can be applied in case of unsupported data rates being applied which extend the lock time.
Note that the CDR should operate in bypass mode for any unsupported data rates.
3. Consult the BNC vendor for optimum BNC landing pattern.
4. Use IBIS-AMI model for simple channel simulation before PCB layout.
5. Closely compare schematic against typical connection diagram in the data sheet.
6. Plan out the PCB layout and component placement to minimize parasitic.
8.2.3 Application Curves
图 25 and 图 27 depict the differential output eye diagrams for OUT1 at 10.3125 Gbps and 11.88 Gbps. 图 26
depicts the single-end eye diagram for OUT0 at 11.88 Gbps. Measurements were done at default operating
conditions.
图 26. 11.88 Gbps 75 Ω OUT0
图 25. 10.3125 Gbps 50 Ω OUT1
图 27. 11.88 Gbps 50 Ω OUT1
46
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8.3 Do's and Don'ts
In order to meet SMPTE standard requirements for jitter, AC timing, and return loss use the following guidelines:
1. Do place BNC within 1 inch of the device.
2. Do consult BNC vendor to provide optimum landing pad for the BNC to comply with the required
specifications.
3. Do pay attention to the recommended solder paste to ensure reliable GND connection to DAP.
4. Do use control impedance for both 100 Ω and 75 Ω for IN0/1 and OUT0/1.
8.4 Initialization Set Up
After power up or register reset write the initialization sequences in 表 10.
表 10. LMH1218 Register Initialization
DESCRIPTION
ADDRESS [Hex]
0xFF
VALUE [Hex]
0x04
Enable Channel Registers
Enable Full Temperature Range
0x16
0x25
0x3E
0x00
Initialize CDR State Machine Control
0x55
0x02
0x6A
0x00
Restore media CTLE setting(1)
Reset CDR
0x03
xx
0x0A
0x5C
0x50
Release Reset
0x0A
(1) Refer to LMH1218 Programming Guide (SNLU174) on how to quickly select the most appropriate CTLE boost setting.
8.4.1 Selective Data Rate Lock
The LMH1218 is configured to automatically lock to all SMPTE data rates. The LMH1218 can be configured to
restrict the dividers to lock to certain data rates. This enables faster lock time. To disable 270 Mbps data rate
lock, additional registers need to be programmed. Refer to LMH1218 Programming Guide (SNLU174) for details.
9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the recommended operating conditions in terms of DC
voltage, AC noise, and start-up ramp time.
2. The maximum current draw for the LMH1218 is provided in the data sheet. This figure can be used to
calculate the maximum current the supply must provide. Current consumption can be derived from the typical
power consumption specification in the data sheet.
3. The LMH1218 does not require any special power supply filtering, provided the recommended operating
conditions are met. Only standard supply decoupling is required.
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10 Layout
10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Set trace impedances to 75-Ω ± 5% single ended, 100-Ω ± 5% differential.
2. Maintain the same signal reference plane for 75-Ω single-end trace, and reference plane for 100-Ω
differential traces.
3. Use the smallest size surface mount components.
4. Use solid planes. Provide GND or VDD relief under the component pads to minimize parasitic capacitance.
5. Select trace widths that minimize the impedance mismatch along the signal path.
6. Select a board stack-up that supports 75-Ω or 50-Ω single-end trace, 100-Ω coupled differential traces.
7. Use surface mount ceramic capacitors.
8. Place BNC component within 1 inches of the LMH1218 device.
9. Maintain symmetry on the complimentary signals.
10. Route 100-Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
11. Avoid sharp bends; use 45-degree or radial bends.
12. Walk along the signal path, identify geometry changes and estimate their impedance changes.
13. Maintain 75-Ω impedance with a well-designed connectors’ footprint.
14. Consult a 3-D simulation tool to guide layout decisions.
15. Use the shortest path for VDD and Ground hook-ups; connect pin to planes with vias to minimize or
eliminate trace.
16. When a high speed trace changes layer, provide at least 2 return vias to improve current return path.
10.2 Layout Example
The following example layout demonstrates how the thermal pad should be laid out using standard WQFN board
routing guidelines.
Note: Thermal pad is divided into 4 squares with solder paste
图 28. LMH1218 Recommended Four Squares Solder Paste
48
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ZHCSDJ6E –FEBRUARY 2015–REVISED JUNE 2018
Layout Example (接下页)
5 Vias without solder paste are located between 4 squares solder paste
图 29. LMH1218 Recommended Solder Paste Mask and Vias
Top etch plus traces
图 30. Example Layout
10.3 Solder Profile
The LMH1218 RTW024A Package solder profile and solder paste material can be found in AN-1187 Leadless
Leadframe Package (LLP) (SNOA401).
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
如需支持,请访问以下网站:
•
•
TI 工程师 (E2E) 社区:http://e2echina.ti.com/
E2E 社区高速接口论坛:http://e2e.ti.com/support/interface/high_speed_interface/
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档:
•
•
《LMH1218 编程指南》(SNLU174)
《LMH1218EVM 用户指南》(SNLU173)
11.3 接收文档更新通知
如需接收文档更新通知,请访问 ti.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本,请参阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH1218RTWR
LMH1218RTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
L1218A1
L1218A1
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH1218RTWR
LMH1218RTWT
WQFN
WQFN
RTW
RTW
24
24
1000
250
178.0
178.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH1218RTWR
LMH1218RTWT
WQFN
WQFN
RTW
RTW
24
24
1000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RTW0024A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.1) TYP
EXPOSED
THERMAL PAD
7
12
20X 0.5
6
13
2X
25
2.5
2.6 0.1
1
18
0.3
24X
0.2
24
19
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
24X
4222815/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(1.05)
SYMM
25
(3.8)
20X (0.5)
(R0.05)
TYP
6
13
(
0.2) TYP
VIA
7
12
(1.05)
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222815/A 03/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
(0.675) TYP
19
(R0.05) TYP
24
24X (0.6)
1
18
24X (0.25)
(0.675)
TYP
SYMM
20X (0.5)
25
(3.8)
6
13
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222815/A 03/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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