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LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

LMH1226 低功耗双路输出 12G 超高清时钟恢复器

1 特性

3 说明

1

•

支持 ST-2082-1(12G)、ST-2081-1(6G)、ST-424

LMH1226 是一款低功耗双路输出 12G 超高清时钟恢

(3G)、ST-292(HD) 和 ST-259(SD)

复器。该器件支持高达 11.88Gbps 的 SMPTE 视频速

率以及基于 IP 传输的 10GbE 视频，能够应用于

4K/8K 超高清 (UHD) 应用至 RTN。IN1 上的自适应电

路板走线均衡器与 SFF-8431 兼容，并且支持 SMPTE

和 10GbE 数据速率。

•

支持适用于 SMPTE 2022-5/6 的 SFF8431 (SFP+)

兼容 DVB-ASI 和 AES10 (MADI)

无基准的时钟恢复器锁定至 SMPTE 和 10GbE 速

率：11.88Gbps、5.94Gbps、2.97Gbps、

1.485Gbps 或经 1.001 分频的子速率、270Mbps

和 10.3125Gbps

该时钟恢复器可削弱高频抖动并且提供出色的信号完整

性。该器件的高输入抖动容差改善了时序裕度。该时钟

恢复器内置有环路滤波器，运行时无需精准的输入基准

时钟。非破坏性眼图监视器支持实时测量串行数据，从

而简化系统调试并加速电路板调通。

•

无基准，锁定迅速

输入 1 (IN1) 上具有自适应电路板走线均衡器

低功耗：214mW（典型值）

省电模式：16mW

集成 1:2 扇出输出，具有去加重功能

片上环路滤波器和眼图监视器

凭借集成的 1:2 扇出，该器件能够灵活输出多种视频信

号。输出驱动器提供可编程的去加重功能，用于补偿其

输出端的电路板走线损失。LMH1226 的功耗典型值为

214mW。无输入信号时，功耗会进一步降至 16mW。

由 2.5V 单电源或片上 1.8V 稳压器供电

可通过控制引脚、SPI 或者 SMBus 接口进行配置

4mm × 4mm 24 引脚 QFN 封装

工作温度范围：-40°C 至 +85°C

LMH1226 与 LMH1219 （带有集成时钟恢复器的 12G

超高清电缆均衡器）引脚兼容。

2 应用

器件信息⁽¹⁾

•

兼容 SMPTE 的串行数字接口 (SDI)

器件型号

LMH1226

封装

QFN (24)

封装尺寸（标称值）

UHDTV/4K/8K/HDTV/SDTV 视频

广播视频路由器、交换机和监视器

数字视频处理和编辑

4.00mm × 4.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

10GbE - SDI 媒体网关

简化框图

2

100-Ω

Driver

OUT0±

OUT1±

Reclocker

with

Integrated

LoopFilter,

EyeMon

Data

2

Diff 100 Ω

Term

PCB

EQ

IN1±

Clock

100-Ω

Driver

OUT_MUX

Power

Management

Serial

Interface

LDO

Control Logic

VDD_LDO Single 2.5 V

or

Control

Pins

Lock

Indicator

SPI

or

Dual 2.5 V and 1.8 V

SMBus

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS534

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 20

7.5 LMH1226 Register Map .......................................... 25

Application and Implementation ........................ 37

8.1 Application Information............................................ 37

8.2 Typical Application ................................................. 37

Power Supply Recommendations...................... 41

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

8

9

10 Layout................................................................... 41

10.1 PCB Layout Guidelines......................................... 41

10.2 Layout Example .................................................... 42

11 器件和文档支持 ..................................................... 43

11.1 接收文档更新通知 ................................................. 43

11.2 社区资源................................................................ 43

11.3 商标....................................................................... 43

11.4 静电放电警告......................................................... 43

11.5 术语表 ................................................................... 43

12 机械、封装和可订购信息....................................... 43

6.6 Recommended SMBus Interface AC Timing

Specifications .......................................................... 11

6.7 Serial Parallel Interface (SPI) AC Timing

Specifications........................................................... 11

6.8 Typical Characteristics............................................ 12

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (October 2017) to Revision D

Page

•

首次公开发布的完整生产版产品说明书 .................................................................................................................................. 1

Changes from Revision B (February 2017) to Revision C

Page

•

已添加封装图 ...................................................................................................................................................................... 43

Changes from Revision A (May 2016) to Revision B

Page

•

Changed eq_en_bypass bit description from "Gain Stages 3 and 4" to "Gain Stages 2 and 3" ........................................ 27

Changed bit location of IN1 Carrier Detect Power Down Control from Reg 0x13[5] to Reg 0x15[6] .................................. 27

Changes from Original (April 2016) to Revision A

Page

•

Deleted min and max VOD_DE amplitude specification when VOD_DE = Level F ............................................................. 8

Changed typical VOD_DE amplitude specifications for Levels F, R, and L .......................................................................... 8

Changed DEM value and DEM register settings in Table 5 to match correct VOD_DE pin logic levels ............................. 18

已添加 new row for VOD = 5, DEM = 5 setting in 表 10 ..................................................................................................... 39

2

LMH1226

www.ti.com.cn

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

5 Pin Configuration and Functions

RTW Package

24-Pin QFN

Top View

RSV1

RSV2

1

2

3

4

5

6

18 OUT0+

17 OUT0-

16 VSS

VSS

LMH1226

IN1+

15 OUT1+

14 OUT1-

13 VDD_CDR

IN1-

EP = VSS

MODE_SEL

Pin Functions

(1)

I/O

DESCRIPTION

NAME

NO.

High-Speed Differential I/Os

IN1+

4

5

I, Analog

O, Analog

Differential complementary inputs with internal 100-Ω termination. Requires external

4.7-µF AC coupling capacitors for SMPTE and 10 GbE.

IN1-

OUT0+

18

Differential complementary outputs with 100-Ω internal termination. Requires external

4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user

control.

OUT0-

OUT1+

OUT1-

17

15

14

O, Analog

Differential complementary outputs with 100 Ω internal termination. Requires external

4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user

control.

RSV1

1

2

Reserved pins.

Do not connect.

RSV2

Control Pins

LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW

when the reclocker has acquired locking condition. LOCK_N is an open drain output,

LOCK_N

12

O, LVCMOS, OD 3.3 V tolerant, and requires an external 2-kΩ to 5-kΩ pull-up resistor to logic supply.

LOCK_N pin can be re-configured to indicate INT_N (Interrupt) through register

programming.

IN_OUT_SEL selects the signal flow at input ports to output ports. See Table 2 for

I, 4-LEVEL

IN_OUT_SEL

OUT_CTRL

8

details. This pin setting can be overridden by register control.

OUT_CTRL selects the signal flow from IN1± to OUT1± and OUT0±. It selects

reclocked data, reclocked data and clock, bypassed reclocker data (equalized data to

output driver), or bypassed equalizer and reclocker data. See Table 4 for details. This

19

I, 4-LEVEL

pin setting can be overridden by register control.

(1) I = Input, O = Output, IO = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic

3

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

Pin Functions (continued)

(1)

I/O

DESCRIPTION

NAME

VOD_DE

MODE_SEL

NO.

11

6

VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0±

and OUT1±. See Table 5 for details. This pin setting can be overridden by register

control.

I, 4-LEVEL

MODE_SEL enables SPI or SMBus serial control interface. See Table 6 for details.

Serial Control Interface (SPI Mode), MODE_SEL = F (Float)

SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the

LMH1226 slave device. SS_N is a LVCMOS input reference to VDDIO.

SS_N

MISO

MOSI

SCK

7

I, LVCMOS

O, LVCMOS

I, LVCMOS

MISO is the SPI control serial data output from the LMH1226 slave device. MISO is a

LVCMOS output reference to VDDIO.

20

10

21

MOSI is used as the SPI control serial data input to the LMH1226 slave device. MOSI

is LVCMOS input reference to VDDIO.

SCK is the SPI serial input clock to the LMH1226 slave device. SCK is LVCMOS

reference to VDDIO.

Serial Control Interface (SMBus Mode) , MODE_SEL = L (1 kΩ to VSS)

ADDR0

ADDR1

7

Strap, 4-LEVEL

ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus

addresses. ADDR[1:0] are 4-level straps and are read into the device at power up.

20

SDA is the SMBus bi-directional open drain SDA data line to or from the LMH1226

SDA

SCL

10

21

IO, LVCMOS, OD slave device. SDA is an open drain IO and tolerant to 3.3 V. SDA requires an external

2-kΩ to 5-kΩ pull-up resistor to the SMBus termination voltage.

SCL is the SMBus input clock to the LMH1226 slave device. It is driven by a

I, LVCMOS, OD

LVCMOS open drain driver from the SMBus master. SCL is tolerant to 3.3 V and

requires an external 2-kΩ to 5-kΩ pull up resistor to the SMBus termination voltage.

Power

VSS

3, 9, 16

24

I, Ground

I, Power

Ground reference.

VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ±

5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO

regulator. For lower power operation, both VIN and VDD_LDO should be connected

to a 1.8 V supply.

VIN

VDDIO powers the LVCMOS IO and 4-level input logic and connects to 2.5 V ± 5%

supply.

VDDIO

22

I, Power

VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to

a 2.5 V supply. VDD_LDO output requires external 1-μF and 0.1-μF bypass

capacitors to VSS. The internal LDO is designed to power internal circuitry only.

VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation.

When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be

connected to a 1.8 V supply.

VDD_LDO

23

13

IO, Power

VDD_CDR

EP

I, Power

VDD_CDR powers the reclocker circuitry and connects to 2.5 V ± 5% supply.

EP is the exposed pad at the bottom of the QFN package. The exposed pad must be

connected to the ground plane through a via array. See 图 29 for details.

I, Ground

4

LMH1226

www.ti.com.cn

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

2.75

2.0

UNIT

V

Supply Voltage for 2.5 V Mode (VDD_CDR, VIN, VDDIO)

Supply Voltage for 1.8 V Mode (VIN, VDD_LDO)

V

4-Level Input/Output Voltage (IN_OUT_SEL, OUT_CTRL, VOD_DE,

MODE_SEL, ADDR0, ADDR1)

–0.5

2.75

V

SMBus Input/Output Voltage (SDA, SCL)

SPI Input/Output Voltage (SS_N, MISO, MOSI, and SCK)

Input Voltage (IN1±)

–0.5

–30

4.0

2.75

30

V

Input Current (IN1±)

mA

°C

Operating Junction Temperature

Storage temperature

125

150

-65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500 V HBM is possible with the necessary precautions. Pins listed as ±4500 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250 V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.375

1.71

NOM

2.5

MAX

2.625

1.89

UNIT

(1)

Single Supply Mode

VIN, VDDIO, VDD_CDR to VSS

V

VIN, VDD_LDO to VSS

1.8

(2)(3)

Dual Supply Mode

VDD_SMBUS

VDD_CDR, VDDIO to VSS

2.375

300

2.5

2.625

3.6

SMBus: SDA, SCL Open Drain Termination Voltage

Source Differential Launch Amplitude Before 5-Inch Board Trace

Source Differential Launch Amplitude Before 20-Inch Board Trace

Operating Junction Temperature

850 mVp-p

1000 mVp-p

V_{IN1_LAUNCH}

650

T_JUNCTION

T_AMBIENT

100

85

°C

Ambient Temperature

–40

25

Maximum Supply Noise

50 Hz to 1 MHz, Sinusoidal

Tolerance

<20

mVp-p

(4)

NTps_max

Maximum Supply Noise

1.1 MHz to 6 GHz, Sinusoidal

Tolerance

<10

(1) In Single Supply Mode, the VIN, VDDIO and VDD_CDR supplies are 2.5 V. The VDD_LDO is the 1.8 V LDO output of an internal LDO

regulator, the VDD_LDO pin should not be connected to any external supply voltage.

(2) In Dual Supply Mode, the VIN and VDD_LDO are connected to a 1.8 V supply, while the VDD_CDR and VDDIO supplies are 2.5 V.

(3) In Dual Supply Mode, the VDDIO supply should be powered before or at the same time as VIN and VDD_LDO = 1.8 V.

(4) The sum of the DC supply voltage and AC supply noise should not exceed the recommended supply voltage range.

5

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

6.4 Thermal Information

LMH1226

RTW (QFN)

24 PINS

33.2

THERMAL METRIC⁽¹⁾⁽²⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

28.8

11.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

11.3

R_θJC(bot)

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient

temperature (< 85°C) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

Power Dissipation, Dual Measured with PRBS-10, Locked

PD_DUAL

214

16

mW

Supply Mode

to 11.88 Gbps, only OUT1 enabled

Power Dissipation, Dual

Supply Mode

PD_{Z_DUAL}

PD_SINGLE

PD_{Z_SINGLE}

Power Save Mode, no input signal

Power Dissipation,

Single Supply Mode

Measured with PRBS-10, Locked

to 11.88 Gbps, only OUT1 enabled

227

27

Power Dissipation,

Single Supply Mode

Power Save Mode, no input signal

Measured at 2.5 V supply with

PRBS-10, Locked to 11.88 Gbps,

VOD = Default, only OUT1

enabled

73

17

80

25

Current Consumption,

Dual Supply Mode

IDD_DUAL

mA

Measured at 1.8 V supply with

PRBS-10, Locked to 11.88 Gbps,

VOD = Default, only OUT1

enabled

Forced Power Save Mode,

MODE_SEL = LEVEL-H,

measured at 2.5 V supply

4

3

5

9

Current Consumption,

Dual Supply Mode

IDD_{Z_DUAL}

Forced Power Save Mode,

MODE_SEL = LEVEL-H,

measured at 1.8 V supply

Measured at 2.5 V supply with

PRBS-10, Acquiring Lock, VOD =

Default, OUT0 and OUT1 enabled

Current Consumption,

Dual Supply Mode,

IDD_{TRANS_DUAL}Acquiring Lock,

HEO/VEO Lock Monitor

90

101

mA

V

Measured at 1.8 V supply with

PRBS-10, Acquiring Lock, VOD =

Default, OUT0 and OUT1 enabled

30

37

Disabled

LDO 1.8 V Output

Voltage

VDD_LDO

VIN = 2.5 V, Single Supply Mode

1.71

1.8

1.89

6

LMH1226

www.ti.com.cn

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVCMOS DC SPECIFICATIONS

2-Level Input (SS_N, SCK, MOSI),

VDDIO = 2.5 V

0.7 x VDDIO

VDDIO + 0.3

3.6

V_IH

High Level Input Voltage

V

2-Level Input (SCL, SDA), VDDIO

= 2.5 V

0.7 x VDDIO

2-Level Input (SS_N, SCK, MOSI),

VDDIO = 2.5 V

-0.3

0.3 x VDDIO

VDDIO

V_IL

Low Level Input Voltage

V

2-Level Input (SCL, SDA), VDDIO

= 2.5 V

0

High Level Output

Voltage

IOH = -2 mA, (MISO), VDDIO =

2.5 V

V_OH

0.8 x VDDIO

IOL = 2 mA, (MISO), VDDIO = 2.5

V

0

0.2 x VDDIO

0.4

Low Level Output

Voltage

V_OL

IOL = 3 mA, (LOCK_N, SCL,

SDA), VDDIO = 2.5 V

SPI Mode: LVCMOS (SS_N, SCK,

MOSI), Vinput = VDDIO

15

Input High Leakage

Current

I_IH

µA

SMBus Mode: LVCMOS

(LOCK_N, SCL, SDA), Vinput =

VDDIO

10

SPI: LVCMOS (SS_N), Vinput =

VSS

-40

-15

-10

Input Low Leakage

Current

SPI: LVCMOS (SCK, MOSI),

Vinput = VSS

I_IL

SMBus: LVCMOS (CD_N, SCL,

SDA), Vinput = VSS

4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)

V_{4_LVL_H}

V_{4_LVL_F}

LEVEL-H Input Voltage

Pull-up 1 kΩ to VDDIO

VDDIO

V

LEVEL-F Default Voltage Float, VDDIO = 2.5 V

2/3 x VDDIO

External Pull-down 20 kΩ to VSS,

VDDIO = 2.5 V

V_{4_LVL_R}

V_{4_LVL_L}

LEVEL-R Input Voltage

LEVEL-L Input Voltage

1/3 x VDDIO

0

V

External Pull-down 1 kΩ to VSS

4-Levels (IN_OUT_SEL,

OUT_CTRL, VOD_DE,

MODE_SEL); Vinput = VDDIO

20

45

80

Input High Leakage

Current

I_{4_LVL_IH}

µA

SMBus Mode: 4-Levels (ADDR0,

ADDR1), Vinput = VDDIO

4-Levels (IN_OUT_SEL,

OUT_CTRL, VOD_DE,

MODE_SEL), Vinput = VSS

-160

-93

-40

Input Low Leakage

Current

I_{4_LVL_IL}

SMBus Mode: 4-Levels (ADDR0,

ADDR1), Vinput = VSS

7

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ω

RECEIVER SPECIFICATIONS (IN1±)

DC Input Differential

R_{IN1_TERM}

Measured across IN1+ to IN1-

80

100

120

Termination

SDD11, 10 MHz - 2.8 GHz

SDD11, 2.8 GHz - 6 GHz

SDD11, 6 GHz - 11.1 GHz

-21

-17

-8

Input Differential Return

Loss

RL_{IN1_SDD11}

dB

(1)

Differential to common

mode Conversion

RL_{IN1_SCD11}

SCD11, 10 MHz to 11.1 GHz

-23

15

dB

mV (rms)

V

(1)

Input AC Common Mode

V_{IN1_CM_TOL}

Voltage Tolerance

DC Common Mode

Input common mode voltage at

IN1+ or IN1- to VSS

V_{IN1_CM}

Voltage

2.06

10.3125 Gbps, 1010 Clock Pattern

10.3125 Gbps, PRBS-31 Pattern

39

25

CD_N = LOW, Signal

Detect (default), Assert

ON Threshold Level

CD_{ON_IN1}

mVp-p

11.88 Gbps, EQ and PLL

Pathological Pattern

20

10.3125 Gbps, 1010 Clock Pattern

10.3125 Gbps, PRBS-31 Pattern

15

CD_N = HIGH, Signal

Detect (default), De-

assert OFF Threshold

Level for

CD_{OFF_IN1}

11.88 Gbps, EQ and PLL

Pathological Pattern

18

TRANSMITTER OUTPUT (OUT0± AND OUT1±)

8T pattern, VOD_DE = LEVEL-H,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

410

560

635

810

410

500

480

8T pattern, VOD_DE = LEVEL-F,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

485

620

Output Differential

Voltage⁽²⁾

V_OD

mVp-p

8T pattern, VOD_DE = LEVEL-R,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

8T pattern, VOD_DE = LEVEL-L,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

8T pattern, VOD_DE = LEVEL-H,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

8T pattern, VOD_DE = LEVEL-F,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

De-emphasized Output

Differential Voltage⁽²⁾

VOD_DE

mVp-p

8T pattern, VOD_DE = LEVEL-R,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

8T pattern, VOD_DE = LEVEL-L,

see Figure 13

SD, HD, 3G, 6G, 12G, and 10

GbE

(1) This parameter was measured with an LMH1219EVM.

(2) ATE production tested with DC method.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC Output Differential

Termination

Measured across OUTn+ and

OUTn-

R_{OUT_TERM}

80

100

120

Ω

20% - 80% using 8T Pattern

SMPTE SD, HD, 3G, 6G, 12G,

and 10 GbE, measured after 1

inch trace

t_R/t_F

Output Rise/Fall Time⁽¹⁾

45

ps

Output Differential

SDD22, 10 MHz - 2.8 GHz

SDD22, 2.8 GHz - 6 GHz

-17

-15

Return Loss, Measured

with the device powered

up and outputs a 10

MHz clock signal.⁽¹⁾

RL_TX-SDD22

dB

SDD22, 6 GHz - 11.1 GHz

SCC22, 10 MHz - 4.75 GHz

-15

-12

Output Common Mode

Return Loss, measured

with the device powered

up and outputs a 10

RL_TX-SCC22

dB

SCC22, 4.75 GHz - 11.1 GHz

-12

5

MHz clock signal.⁽³⁾

AC Common Mode

Voltage⁽³⁾

Default Setting, PRBS-31, 10.3125

Gbps

V_{TX_CM}

mV (rms)

OUTPUT JITTER

11.88 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

0.11

0.106

0.075

0.07

0.15

UI

5.94 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

2.97 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

Total Jitter (BER≤1e-12),

T_J

Reclocked Output⁽⁴⁾

1.485 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

270 Mbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

0.07

10.3125 Gbps, PRBS-10, 500

mVp-p and 1000 mVp-p launch

amplitude, 20 inch FR4 board

trace at IN1±

0.09

5

0.15

UI

11.88 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

mUI (rms)

mUI

Random Jitter,

Reclocked Output

R_J

10.3125 Gbps, PRBS-10, 500

mVp-p and 1000 mVp-p launch

amplitude, 20 inch FR4 board

trace at IN1±

4.1

40

34

11.88 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

Deterministic Jitter,

Reclocked Output

D_J

10.3125 Gbps, PRBS-10, 500

mVp-p and 1000 mVp-p launch

amplitude, 20 inch FR4 board

trace at IN1±

mUI

(3) This parameter was measured with an LMH1219EVM.

(4) These limits are ensured by bench characterization and are not production tested.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

125 Mbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

0.17

Total Jitter (BER≤1e-12),

RAW (Reclocker

Bypassed)

TJ_RAW

UI

1.25 Gbps, PRBS-10, 500 mVp-p

and 1000 mVp-p launch amplitude,

20 inch FR4 board trace at IN1±

0.17

CLOCK AND DATA RECOVERY

SMPTE 12G, /1

SMPTE 12G, /1.001

SMPTE 6G, /1

SMPTE 6G, /1.001

SMPTE 3G, /1

SMPTE 3G, /1.001

SMPTE HD, /1

SMPTE HD, /1.001

SMPTE SD, /1

10 GbE

11.88

11.868

5.94

Gbps

Mbps

Gbps

Mbps

Gbps

5.934

2.97

Reclocker Lock Data

LOCK_RATE

Rates

2.967

1.485

1.4835

270

10.3125

125

MADI

Bypass reclocker data

BYPASS_RATE

rate

1 GbE

1.25

Measured with 0.2 UI SJ at -3 dB,

10.3125 Gbps

8

13

7

Measured with 0.2 UI SJ at -3 dB,

11.88 Gbps

Measured with 0.2 UI SJ at -3 dB,

5.94 Gbps

BW_PLL

PLL Bandwidth

MHz

Measured with 0.2 UI SJ at -3 dB,

2.97 Gbps

5

Measured with 0.2 UI SJ at -3 dB,

1.485 Gbps

3

Measured with 0.2 UI SJ at -3 dB,

270 Mbps

1

SD, HD, 3G, 6G, 12G, and 10

GbE

J_PEAKING

PLL Jitter Peaking

IN1 Input Jitter

0.3

dB

UI

Total jitter tolerance combination

Tolerance per SFF-8431 of Dj, Pj, and Rj at 10 GbE, with

J_{TOL_IN1}

>0.7

Appendix D.11

RX stress eye mask Y1, Y2 limits

Sinusoidal jitter, tested at 3G, 6G

and 12G; SJ amplitude low to high

sweep, tested at BER ≤ 1e-12

IN1 Input Jitter

Tolerance with SJ

J_TOL

0.65

5

UI

ms

°C

All supported data rates, disable

HEO/VEO monitor

T_LOCK

Reclocker lock time

Lock Temperature Range (5 °C

per min, ramp up and down),

-40°C to 85°C operating range

VCO Lock with Temp

Ramp

TEMP_LOCK

125

T_LATENCY

T_PD-RAW

Reclocker Latency⁽⁵⁾

Propagation Delay

IN1, all supported data rates

1.5 UI + 190

190

ps

Raw Data (reclocker bypassed),

IN1± EQ = default

(5) This parameter is data rate dependent. For example, at 11.88 Gbps, 1.5 UI = 1.5 x 84.17 ps = 126.25 ps. Therefore, T_Latency= (126.25 +

190) ps = 316.25 ps.

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Operating at 11.88 Gbps

Operating at 5.94 Gbps

Operating at 2.97 Gbps

Operating at 1.485 Gbps

Operating at 270 Mbps

MIN

TYP

297

MAX

UNIT

MHz

GHz

MHz

297

Output Clock Frequency

OUT1 Programmed to

Output Recovered Clock

FCLK_OUT

2.97

1.485

270

(1)(2)(3)

6.6 Recommended SMBus Interface AC Timing Specifications

PARAMETER

TEST CONDITIONS

MIN

10

NOM

MAX

UNIT

kHz

µs

F_SCL

T_BUF

SMBus SCL Frequency

400

Bus Free Time Between Stop and

Start Condition

1.3

Hold time after (Repeated) Start

Condition.

After this period, the first clock is

generated.

0.6

µs

T_HD:STA

T_SU:STA

T_SU:STO

T_HD:DAT

T_SU:DAT

T_LOW

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time

0.6

0

µs

ns

µs

ns

Data Setup Time

100

1.3

0.6

Clock Low Period

T_HIGH

T_R

Clock High Period

Clock/Data Rise Time

Clock/Data Fall Time

300

T_F

(1) These parameters support SMBus 2.0 specifications.

(2) These parameters are not production tested.

(3) See Figure 1 for timing diagrams.

6.7 Serial Parallel Interface (SPI) AC Timing Specifications⁽¹⁾

PARAMETER

SPI SCK Frequency

SCK Period

TEST CONDITIONS

MIN

NOM

MAX

UNIT

MHz

ns

F_SCK

T_SCK

T_PH

10

20

50

SCK Pulse Width High

SCK Pulse Width Low

MOSI Setup Time

0.40 x T_SCK

ns

T_PL

0.40 x T_SCK

ns

T_SU

4

ns

T_H

MOSI Hold Time

ns

T_SSSU

T_SSH

T_SSOF

T_ODZ

T_OZD

T_OD

SS_N Setup Time

14

4

ns

SS_N Hold Time

ns

SS_N Off Time

1

µs

MISO Driven-to-Tristate Time

MISO Tristate-to-Driven Time

MISO Output Delay Time

20

10

15

ns

(1) See Figure 2 for timing diagrams.

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tt_LOW

t

t_R

t_HIGH

SCL

tt_HD:STA

t

t_HD:DAT

t_SU:STA

t_F

t_SU:STO

tt_BUF

t

t_SU:DAT

SDA

SP

ST

SP

Figure 1. SMBUS Timing Parameters

t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

1

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

1

Don‘t Care

Figure 2. SPI Timing Parameters

6.8 Typical Characteristics

T_A= 25°C and VDD = 2.5 V (unless otherwise noted)

Figure 3. 10.3125 Gbps, Input: 20 in. FR4 Trace

Figure 4. 11.88 Gbps, Input: 20 in. FR4 Trace

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Typical Characteristics (continued)

T_A= 25°C and VDD = 2.5 V (unless otherwise noted)

Figure 5. 5.94 Gbps, Input: 20 in. FR4 Trace

Figure 6. 2.97 Gbps, Input: 20 in. FR4 Trace

Figure 7. 1.485 Gbps, Input: 20 in. FR4 Trace

Figure 8. 270 Mbps, Input: 20 in. FR4 Trace

1.0

0

œ2

DE = 0

DE = 1

DE = 2

DE = 3

DE = 4

DE = 5

DE = 6

DE = 7

0.9

0.8

0.7

0.6

0.5

0.4

œ4

œ6

œ8

œ10

œ12

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

VOD Register Settings

C001

C002

Figure 9. VOD vs. VOD and DEM Register Settings

Figure 10. De-Emphasis vs. VOD and DEM Register Settings

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7 Detailed Description

7.1 Overview

The LMH1226 is a SMPTE and 10 GbE compatible multi-rate serial digital video reclocker for SMPTE ST-2081/2,

ST-424, ST-292, ST-259, and 10 GbE SFF-8431 requirements. The LMH1226 has a 100-Ω PCB (printed circuit

board) equalizer at IN1. The 100-Ω PCB equalizer input supports high speed signals across differential PCB

traces that connect to an external SFF-8431 optical module or on-board FPGA. The input then passes through a

multi-rate reclocker with a built-in loop-filter. The multi-rate reclocker is compatible with SMPTE data rates (11.88,

5.94, 2.97, 1.485 Gbps, 270 Mbps) and their divide-by-1.001 sub-rates. It is also compatible with the 10 GbE

data rate (10.3125 Gbps). After the reclocker, an internal 1:2 fan-out mux allows users to select the data or clock

content for each output. At both outputs, the LMH1226 has 100-Ω drivers with de-emphasis. The de-emphasis

feature of the drivers is designed to compensate for insertion loss caused by output PCB traces.

The operating mode of the LMH1226 can be set by 4-level control pins, SPI, or SMBus serial control interface.

The LMH1226 can be powered from a single 2.5 V supply or dual 2.5 V/1.8 V supplies for lower power

consumption. The LMH1226 is offered in a small 4 mm x 4 mm 24-lead QFN package.

7.2 Functional Block Diagram

VOD SEL

CDR Bypass

DE SEL

2

EQ Sel

100-Ω

OUT0±

Driver

LOS1

Data

Reclocker with

2

VOD SEL

DE SEL

To FPGA

or ASIC

Diff 100 Ω

Term

Integrated

LoopFilter,

EyeMon

PCB EQ

IN1±

Clock

2

100-Ω

OUT1±

Driver

OUT_MUX

LOS1

Power

Management

Serial

Interface

LDO

Control Logic

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7.3 Feature Description

The LMH1226 consists of several key blocks:

•

4-Level Input Configuration Pins

Input Carrier Detect

Continuous Time Linear Equalizer (CTLE)

Input-Output Mux Selection

Clock and Data Recovery (CDR) Reclocker

Internal Eye Opening Monitor (EOM)

Output Function Control

Output Driver Amplitude and De-Emphasis Control

Status Indicators and Interrupts

7.3.1 4-Level Input Configuration Pins

The 4-level input configuration pins use a resistor divider to provide four logic states for each control pin. There is

an internal 30-kΩ pull-up and a 60-kΩ pull-down connected to the control pin that sets the default voltage at 2/3 x

VDDIO. These resistors, together with the external resistor, combine to achieve the desired voltage level. By

using the 1-kΩ pull-down, 20-kΩ pull-down, no connect, and 1-kΩ pull-up, the optimal voltage levels for each of

the four input states are achieved as shown in Table 1.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTING

RESULTING PIN VOLTAGE

H

F

R

L

Tie 1 kΩ to VDDIO

Float (leave pin open)

Tie 20 kΩ to VSS

Tie 1 kΩ to VSS

VDDIO

2/3 × VDDIO

1/3 × VDDIO

0

Typical 4-Level Input Thresholds:

•

Internal Threshold between L and R = 0.2 × VDDIO

Internal Threshold between R and F = 0.5 × VDDIO

Internal Threshold between F and H = 0.8 × VDDIO

7.3.2 Input Carrier Detect

The LMH1226 has a Carrier Detect circuit to monitor the presence or absence of the input signal. When the input

signal amplitude surpasses the Carrier Detect assert threshold, the LMH1226 operates in normal mode.

In the absence of an input signal, the LMH1226 automatically goes into Power Save Mode to conserve power

consumption. When a valid signal is detected, the LMH1226 automatically exits Power Save Mode and returns to

the normal operating mode.

7.3.3 Continuous Time Linear Equalizer (CTLE)

The LMH1226 has a Continuous Time Linear Equalizer (CTLE) block for IN1. The CTLE compensates for

frequency-dependent loss due to the transmission media prior to the device input. The CTLE accomplishes this

by applying variable gain to the input signal, thereby boosting higher frequencies more than lower frequencies.

The CTLE can be bypassed either by using the OUT_CTRL pin or via register control.

7.3.3.1 Adaptive PCB Trace Equalizer (IN1±)

The IN1 PCB equalizer has an on-chip 100-Ω termination and is designed for AC coupling, requiring a 4.7-μF AC

coupling capacitor for minimizing base-line wander due to the rare-occurring pathological bit pattern. The PCB

equalizer can compensate up to 20 inches of board trace at data rates up to 11.88 Gbps. There are two adapt

modes for IN1: AM0 manual mode and AM1 adaptive mode. In AM0 manual mode, fixed EQ boost settings are

applied through user-programmable register control, whereas in AM1 adaptive mode, state machines

automatically find the optimal equalization setting from a set of 16 pre-determined settings defined in Registers

0x40-0x4F.

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By default, AM1 adaptive mode is enabled at the data rate determined by the IN_OUT_SEL pin. The PCB

equalizer is able to adapt at 10.3125 Gbps (10 GbE) and 2.97 Gbps, 5.94 Gbps, and 11.88 Gbps (SMPTE) data

rates. At 1.485 Gbps and 270 Mbps data rates, the equalization is fixed at 0x00 (minimum EQ boost). This fixed

EQ value can be changed via register control. For more details, refer to the LMH1226 Register Map.

7.3.4 Input-Output Mux Selection

By default, the LMH1226 input-to-output signal flow and data rate selection are configured by the IN_OUT_SEL

pin logic settings shown in Table 2. These settings can be overridden via register control by applying the

appropriate override bit values. For more information, refer to the LMH1226 Register Map.

Table 2. IN_OUT_SEL Pin Settings

LEVEL

DEFINITION

SMPTE Data Rates: IN1 to OUT0 and OUT1

SMPTE Data Rates: IN1 to OUT1 (OUT0 disabled)

10 GbE Data Rate: IN1 to OUT1 (OUT0 disabled)

10 GbE Data Rate: IN1 to OUT0 and OUT1

H

F

R

L

7.3.5 Clock and Data Recovery (CDR) Reclocker

After the input signal passes through the CTLE, the equalized data is fed into the clock and data recovery (CDR)

block. Using an internal PLL, the CDR locks to the incoming equalized data and recovers a clean internal clock

to re-sample the equalized data. The LMH1226 CDR is able to tolerate high input jitter, tracking low frequency

input jitter below the PLL bandwidth while reducing high frequency input jitter above the PLL bandwidth.

The supported data rates are listed in Table 3. IN1 locks to either SMPTE or 10 GbE data rates according to the

IN_OUT_SEL pin logic shown previously in Table 2. When locked to SMPTE data rates according to

IN_OUT_SEL pin logic, IN1 can be programmed to lock to the 10 GbE data rate, and vice versa, via register

control by applying the appropriate override bit values. For more information, refer to the LMH1226 Register

Map.

Table 3. Supported Data Rates

IN_OUT_SEL

DATA RATE

RECLOCKER MODE

Reclocker Enabled

LEVEL

11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps,

270 Mbps⁽¹⁾

H, F

125 Mbps

Reclocker Disabled (CDR Bypassed)

Reclocker Enabled

10.3125 Gbps

1.25 Gbps

R, L

Reclocker Disabled (CDR Bypassed)

(1) Divide-by-1.001 lock rates available only for 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, and 1.485 Gbps.

NOTE

If the selected data rate (SMPTE or 10 GbE) is changed while the device is operating with

active data, a CDR reset and release is required for the CDR to re-acquire lock. If the

input data signal is toggled off and on after the selected data rate is changed, the Carrier

Detect circuit will reset the CDR. In this case, no register write is needed for the CDR to

re-acquire lock.

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7.3.6 Internal Eye Opening Monitor (EOM)

The LMH1226 has an on-chip eye opening monitor (EOM) that can be used to analyze, monitor, and diagnose

the post-equalized waveform, just prior to the CDR reclocker. The EOM is operational for 2.97 Gbps and higher

data rates.

The EOM monitors the post-equalized waveform in a time window that spans one unit interval and a configurable

voltage range that spans up to ±400 mV differential. The time window and voltage range are divided into 64

steps, so the result of the eye capture is a 64 × 64 matrix of hits, where each point represents a specific voltage

and phase offset relative to the main data sampler. The number of hits registered at each point needs to be

taken in context with the total number of bits observed at that voltage and phase offset in order to determine the

corresponding probability for that point. The number of bits observed at each point is configurable.

The resulting 64 × 64 matrix produced by the EOM can be processed by software and visualized in a number of

ways. Two common ways to visualize this data are shown in Figure 11 and Figure 12. These diagrams depict

examples of eye monitor plots implemented by software. The first plot is an example using the EOM data to plot

a basic eye using ASCII characters, which can be useful for simple diagnostic software. The second plot shows

the first derivative of the EOM data, revealing the density of hits and the actual waveforms and crossings that

comprise the eye.

Figure 11. Internal Input Eye Monitor Plot

Figure 12. Internal Eye Monitor Hit Density Plot

A common measurement performed by the EOM is the horizontal and vertical eye opening. The horizontal eye

opening (HEO) represents the width of the post-equalized eye at 0-V differential amplitude, measured in unit

intervals or picoseconds (ps). The vertical eye opening (VEO) represents the height of the post-equalized eye,

measured midway between the mean zero crossing of the eye. This position in time approximates the CDR

sampling phase.

7.3.7 Output Function Control

By default, the LMH1226 output function control for OUT0 and OUT1 is configured by the OUT_CTRL pin logic

settings shown in Table 4. These settings can be overridden via register control by applying the appropriate

override bit values. For more information, refer to the LMH1226 Register Map.

Table 4. OUT_CTRL Pin Settings

LEVEL

DEFINITION

H

F

OUT0 and OUT1: Raw Data, Both EQ and Reclocker Bypassed

OUT0 and OUT1: Recovered Data, Both EQ and Reclocker Enabled

OUT0: Recovered Data, EQ and Reclocker Enabled

OUT1: Full-Rate Recovered Clock if Data Rate ≤ 3 Gbps. 297 MHz Recovered

Clock if Data Rate > 3 Gbps⁽¹⁾

R

L

OUT0 and OUT1: Equalized Data, EQ Enabled, Reclocker Bypassed

(1) This setting is only valid for SMPTE data rates. It is not supported for the 10 GbE data rate.

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7.3.8 Output Driver Amplitude and De-Emphasis Control

The VOD_DE control pin selects the output amplitude and de-emphasis settings for both OUT0 and OUT1. It

offers users the capability to select higher output amplitude and de-emphasis levels for longer board trace that

connects the drivers to their downstream receivers. Driver de-emphasis provides transmitter equalization to

reduce the ISI caused by the board trace.

By default, the output driver VOD and de-emphasis settings are configured by the VOD_DE pin logic settings

shown in Table 5. These settings can be overridden via register control by applying the appropriate override bit

values. When these parameters are controlled by registers, the VOD and de-emphasis levels for each channel

can be programmed independently. For more information, refer to the LMH1226 Register Map.

Table 5. Recommended VOD_DE Pin and Register Settings for Different FR4 Trace Lengths⁽¹⁾

VOD REG SETTING

OUT0±: 0x30[5]=1, 0x30[2:0]

OUT1±: 0x32[5]=1, 0x32[2:0]

DEM REG SETTING

OUT0±: 0x31[6]=1, 0x31[2:0]

OUT1±: 0x33[6]=1, 0x33[2:0]

FR4 TRACE

LENGTH

(inches)

VOD_DE

LEVEL

VOD

VOD_DE

DEM (dB)

(mVpp)⁽²⁾

H

F

R

L

0

2

3

5

0

2

3

5

410

560

635

810

410

500

480

0

0 – 1

2 – 4

5 – 6

7 – 8

-0.9

-2.4

-6.1

(1) The output drivers are capable of providing higher VOD and DEM levels (max settings are 7). For more VOD and de-emphasis levels,

refer to 表 10.

(2) See Figure 13.

VOD

VODDE

Figure 13. VOD and VOD_DELevels

7.3.9 Status Indicators and Interrupts

7.3.9.1 LOCK_N (Lock Indicator)

The LOCK_N pin is a 3.3 V tolerant, active-low open drain output. An external resistor to the logic supply is

required. By default, LOCK_N is the reclocker lock indicator, and this pin asserts low when the LMH1226

achieves lock to a valid SMPTE or 10 GbE data rate. The LOCK_N pin functionality can also be configured via

register control to indicate CD_N (Carrier Detect) or INT_N (Interrupt) events. For more information about how to

reconfigure the LOCK_N pin functionality, refer to the LMH1226 Register Map.

7.3.9.2 CD_N (Carrier Detect)

The LOCK_N pin can be reconfigured via register control to indicate a CD_N (Carrier Detect) event. When

configured as a CD_N output, the pin asserts low at the end of adaptation after a valid signal is detected by the

Carrier Detect circuit. Under register control, this pin can be reconfigured to indicate CD_N. For more information

about how to configure the LOCK_N pin for CD_N functionality, refer to the LMH1226 Register Map.

7.3.9.3 INT_N (Interrupt)

The LOCK_N pin can be configured to indicate an INT_N (Interrupt) event. When configured as an INT_N output,

the pin asserts low when an interrupt occurs, according to the programmed interrupt masks. Five separate masks

can be programmed via register control as interrupt sources:

•

If there is a Loss of Signal (LOS) event on IN1 (2 separate masks).

If HEO or VEO falls below a certain threshold after CDR is locked (1 mask).

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•

If a CDR Lock event has occurred (2 separate masks).

INT_N is a sticky bit, meaning that it will flag after an interrupt event occurs and will not clear until read back.

Once the Interrupt Status Register is read, the INT_N pin will assert high again. For more information about how

to configure the LOCK_N pin for INT_N functionality, refer to the LMH1226 Register Map.

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7.4 Device Functional Modes

The LMH1226 operates in one of two modes: System Management Bus (SMBus) or Serial Peripheral Interface

(SPI) mode. In order to determine the mode of operation, the proper setting must be applied to the MODE_SEL

pin at power-up, as detailed in Table 6.

Table 6. MODE_SEL Pin Settings

LEVEL

DEFINITION

Forced Power Save Mode, only SPI is enabled (all other circuitry powered down)

Select SPI Interface for register access

H

F

R

L

Reserved for factory testing – do not use

Select SMBus Interface for register access

NOTE

Changing logic states between LEVEL-L and LEVEL-H after power up is not allowed.

7.4.1 System Management Bus (SMBus) Mode

If MODE_SEL = L, the LMH1226 is in SMBus mode. In SMBus mode, Pins 10 and 21 are configured as SDA

and SCL. Pins 7 and 20 act as 4-level address straps for ADDR0 and ADDR1 at power up to determine the 7-bit

slave address of the LMH1226, as shown in Table 7.

Table 7. SMBus Device Slave Addresses⁽¹⁾

ADDR0

ADDR1

7-BIT SLAVE

8-BIT WRITE

(LEVEL)

ADDRESS [HEX]

COMMAND [HEX]

L

R

F

H

L

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

3A

3C

3E

40

42

44

46

48

4A

4C

4E

50

52

54

56

58

L

R

F

H

R

F

H

L

R

F

H

L

R

F

H

(1) The 8-bit write command consists of the 7-bit slave address (Bits 7:1) with 0 appended to the LSB to

indicate an SMBus write. For example, if the 7-bit slave address is 0x1D (001 1101'b), the 8-bit write

command is 0x3A (0011 1010'b).

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7.4.1.1 SMBus Read and Write Transactions

SMBus is a two-wire serial interface through which various system component chips can communicate with the

master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of

SCL and SDA signals. SCL is a clock output from the master to all of the slave devices on the bus. SDA is a

bidirectional data signal between the master and slave devices. The LMH1226 SMBus SCL and SDA signals are

open drain and require external pull-up resistors.

Start and Stop:

The master generates start and stop patterns at the beginning and end of each transaction.

•

Start: High to low transition (falling edge) of SDA while SCL is high.

Stop: Low to high transition (rising edge) of SDA while SCL is high.

SDA

SCL

S

P

Start

Stop

Condition

Figure 14. Start and Stop Conditions

The master generates nine clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle.

The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is recorded when the device

pulls SDA low, while a NACK is recorded if the line remains high.

ACK Signal

from Receiver

SDA

MSB

SCL

1

2

3 - 6

7

8

9

1

2

3 - 8

9

S

P

ACK

Start

Stop

Condition

Byte Complete

Interrupt Within

Receiver

Clock Line Held Low

by Receiver While

Interrupt Serviced

Figure 15. Acknowledge (ACK)

7.4.1.1.1 SMBus Write Operation Format

Writing data to a slave device consists of three parts, as illustrated in Figure 16:

1. The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the 8-bit data is written, followed by a stop condition.

Device

Address

Word Address

Data

SDA

Line

Figure 16. SMBus Write Operation

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7.4.1.1.2 SMBus Read Operation Format

Reading data from a slave device consists of four parts, as illustrated in Figure 17:

1. The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the master initiates a re-start condition, followed by the slave address

with the R/W bit set to 1'b.

4. After an ACK from the slave device, the 8-bit data is read back. The last ACK is high if there are no more

bytes to read, and the last read is followed by a stop condition.

Device

Address

Word Address (n)

Address

Data (n)

SDA

Line

Set word address in the device

that will be read following restart

and repeat of device address

Figure 17. SMBus Read Operation

7.4.2 Serial Peripheral Interface (SPI) Mode

If MODE_SEL = F or H, the LMH1226 is in SPI mode. In SPI mode, the following pins are used for SPI bus

communication:

•

MOSI (pin 10): Master Output Slave Input

MISO (pin 20): Master Input Slave Output

SS_N (pin 7): Slave Select (active low)

SCK (pin 21): Serial clock (input to the LMH1226 slave device)

7.4.2.1 SPI Read and Write Transactions

Each SPI transaction to a single device is 17 bits long and is framed by SS_N when asserted low. The MOSI

input is ignored, and the MISO output is floated whenever SS_N is de-asserted (high).

The bits are shifted in left-to-right. The first bit is R/W, which is 1'b for "read" and 0'b for "write." Bits A7-A0 are

the 8-bit register address, and bits D7-D0 are the 8-bit read or write data. The previous SPI command, address,

and data are shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI

transactions, the MISO output signal is enabled asynchronously when SS_N asserts low. The contents of a

single MOSI or MISO transaction frame are shown in Table 8.

Table 8. 17-Bit Single SPI Transaction Frame

R/W

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

7.4.2.1.1 SPI Write Transaction Format

For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on

the rising edge of SS_N. The SPI transaction always starts on the rising edge of the clock.

The signal timing for a SPI Write transaction is shown in Figure 18. The "prime" values on MISO (for example,

A7') reflect the contents of the shift register from the previous SPI transaction and are don’t-care for the current

transaction.

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t_SSOF

t_SSH

SS_N

t_PL

t_SSSU

t_PH

SCK

t_H

t_SU

HiZ

MOSI

0

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

t_ODZ

HiZ

MISO

R/W

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

Figure 18. Signal Timing for a SPI Write Transaction

7.4.2.1.2 SPI Read Transaction Format

A SPI read transaction is 34 bits per device and consists of two 17-bit frames. The first 17-bit read transaction

frame shifts in the address to be read, followed by a dummy transaction second frame to shift out 17-bit read

data. The R/W bit is 1'b for the read transaction, as shown in Figure 19.

The first 17 bits from the read transaction specifies 1-bit of R/W and 8-bits of address A7-A0 in the first 8 bits.

The eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on

address 0xFF and needs to be ignored. However, the transaction is necessary in order to shift out the read data

D7-D0 in the last 8 bits of the MISO output. As with the SPI Write, the “prime” values on MISO during the first 16

clocks are don’t-care for this portion of the transaction. The values shifted out on MISO during the last 17 clocks

reflect the read address and 8-bit read data for the current transaction.

t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

1

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

1

Don‘t Care

Figure 19. Signal Timing for a SPI Read Transaction

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7.4.2.2 SPI Daisy Chain

The LMH1226 supports SPI daisy-chaining among multiple devices, as shown in Figure 20.

MISO

Device 1

Device 2

Device 3

Device N

Host

LMH1226

. . .

MOSI

MISO

MOSI

MISO

MOSI

MISO

MOSI

MISO

SCK

SS

Figure 20. Daisy-Chain Configuration

Each LMH1226 device is directly connected to the SCK and SS_N pins of the host. The first LMH1226 device in

the chain is connected to the host’s MOSI pin, and the last device in the chain is connected to the host’s MISO

pin. The MOSI pin of each intermediate LMH1226 device in the chain is connected to the MISO pin of the

previous LMH1226 device, thereby creating a serial shift register. In a daisy-chain configuration of N x LMH1226

devices, the host conceptually sees a shift register of length 17 x N for a basic SPI transaction, during which

SS_N is asserted low for 17 x N clock cycles.

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7.5 LMH1226 Register Map

The LMH1226 register map is divided into three register pages. These register pages are used to control

different aspects of the LMH1226 functionality. A brief summary of the pages is shown below:

1. Share Register Page: This page corresponds to global parameters, such as LMH1226 device ID and

LOCK_N status configuration. This is the default page at start-up.

2. CTLE/CDR Register Page: This page corresponds to IN1 PCB CTLE, input and output mux settings,

internal CDR settings, and output interrupt overrides. Access this page by setting Reg 0xFF[2:0] = 100’b.

3. Drivers Register Page: This page corresponds to both OUT0 and OUT1 driver output settings. Access this

page by setting Reg 0xFF[2:0] = 101’b.

Please note the following about the LMH1226 default register values in the register map:

•

Default register values were read after power-up with no active inputs applied to IN1.

Default register values for Reserved "Read-Only" bits may vary dynamically from part to part.

7.5.1 Share Register Page

Address Register Name

Bit

7:0

7:5

Field

Default Type

Description

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Reserved

0x00

0x40

0x02

0x00

0x01

0x00

0x04

0x11

0x00

R

Reserved

RW Reserved

R

Reserved

0 = Internal state machine register initialization not done.

1 = Internal state machine register initialization done.

4

3:1

0

reset_done

Reserved

reset_init

R

Reset

Share/Channel

Regs

0xE2

0x10

RW Reserved

1 = Initialize internal state machine register settings. Refer to

the LMH1219 Programming Guide for details.

RW

0xF0

0xF1

Device Revision

Device ID

7:0

7:6

Version

Device_ID

Reserved

0x02

0x86

R

Device Revision

For LMH1226, Device ID = 0x86

RW Reserved

Controls the output on LOCK_N pin

00 = Default behavior (LOCK_N outputs lock status from

reclocker)

5:4

los_int_bus_sel

RW 01 = Reserved

10 = LOS of IN1

11 = Interrupts are output on LOCK_N pin, as determined by

CTLE/CDR Page Reg 0x56[6:0]

Register

Communication

Control

0xFF

0x00

3

2

Reserved

RW Reserved

0 = The shared registers are enabled.

RW 1 = Enables communication access to the Register Page

specified in Reg 0xFF[1:0].

page_select_enable

Enable communication access to a specific Register Page

00 = CTLE/CDR Register Page

01 = Drivers Register Page

1:0

page_select

RW

Other settings are invalid.

7.5.2 CTLE/CDR Register Page

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Address Register Name

Bit

Field

Default Type

RW Reserved

Reset registers (self-clearing)

0 = Normal Operation

Description

7:3

Reserved

Reset CTLE/CDR

0x00

2

rst_CTLE/CDR_regs

0x00

RW

Registers

1 = Reset CTLE/CDR Registers. Register re-initialization

procedure required after resetting the CTLE/CDR Registers.

1:0

7:2

Reserved

RW Reserved

0 = Signal Present on IN1

1 = Loss of Signal on IN1

0x01

0x02

LOS Status

CDR_Status

1

0

LOS1

0x03

0x41

R

Reserved

CDR status indicator. See "Lock Data Rate Indication"

subsection in the LMH1219 Programming Guide for more

information.

7:0

CDR_Status

R

7:6

5:4

3:2

eq_BST0

eq_BST1

eq_BST2

RW Used for setting manual EQ value for IN1 when Reg 0x2D[3]

= 1. EQ boost value can be read back on CTLE/CDR Page

Reg 0x52.

[7:6]: 2-bit control for Stage 0 of the CTLE.

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

IN1 Manual EQ

Boost

RW

0x03

0x80

1:0

eq_BST3

RW

0x04

0x05

0x06

0x07

0x08

Reserved

7:0

7:6

Reserved

0x00

RW Reserved

Output Mux Override Control

0 = Reg 0x1C[3:2] determines the output selection for both

RW OUT0 and OUT1

5

reg_out_control_ov

Output Mux

Override Control

0x09

0x00

1 = Enable individual output mux control based on values

from Reg 0x1C[7:5] and Reg 0x1E[7:5]

4:3

2:0

7:4

Reserved

RW Reserved

0 = Disables CDR Reset (Normal Operating Mode)

1 = Enables Reg 0x0A[2] to control CDR Reset

3

2

reg_cdr_reset_ov

reg_cdr_reset

RW

CDR Reset

Control

0x0A

0x50

0 = No CDR Reset if Reg 0x0A[3] = 1

1 = CDR Reset if Reg 0x0A[3] = 1

1:0

7:0

Reserved

RW Reserved

0x0B

0x0C

Reserved

0x1F

0x08

Value determines what CDR status outputs are displayed in

CTLE/CDR Page Reg 0x02. See "Lock Data Rate Indication"

subsection in the LMH1219 Programming Guide for more

information.

7:4 reg_sh_status_control

RW

CDR Output

Status Control

3:0

7:0

Reserved

RW Reserved

0x0D

0x0E

0x0F

0x10

Reserved

0x00

0x93

0x69

0x27

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Address Register Name

Bit

Field

Default Type

Description

Sets the expected incoming eye diagram vertical eye

opening interval if Reg 0x2C[6] = 0

00 = 3.125 mV (3.125 mV x 64 = 200 mV; ±100 mV range)

01 = 6.25 mV (6.25 mV x 64 = 400 mV; ±200 mV range)

10 = 9.375 mV (9.375 mV x 64 = 600 mV; ±300 mV range)

11 = 12.5 mV (12.5 mV x 64 = 800 mV; ±400 mV range)

7:6

eom_sel_vrange

RW

EOM Voltage

0x11

0xE0

Range Control

0 = EOM is always powered up

1 = Power down EOM when not in use

5

eom_PD

RW

4:0

7:0

7:4

Reserved

RW Reserved

IN1 CTLE Power-Down Control

0x12

0x13

0x14

Reserved

0xA0

0x90

0 = Powers up EQ of IN1

1 = Powers down EQ of IN1

3

eq_PD_EQ

RW

IN1 Carrier

Detect and CTLE

Control

Note: The un-selected channel is always powered-down.

2

1

Reserved

RW Reserved

0 = Enable Gain Stages 2 and 3 of IN1 CTLE

1 = Bypass Gain Stages 2 and 3 of IN1 CTLE

eq_en_bypass

RW

0

7:0

7

Reserved

RW Reserved

Reserved

0x00

IN1 Carrier Detect Power Down Control

RW 0 = Power Up IN1 Carrier Detect

1 = Power Down IN1 Carrier Detect

6

cd_1_PD

IN1 Carrier

Detect Threshold

Setting

5:4

cd_1_refa_sel

RW Controls IN1 Carrier Detect Assert and De-Assert Thresholds

0000 = Default levels (nominal)

0x15

0101 = Nominal - 2 mV

1010 = Nominal + 5 mV

3:2

cd_1_refd_sel

RW

1111 = Nominal + 3 mV

1:0

7:0

Reserved

RW Reserved

0x16

0x17

0x18

0x19

0x1A

0x1B

Reserved

0x25

0x40

0x00

0xA0

0x03

RW Reserved

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Address Register Name

Bit

Field

Default Type

Description

In normal operating mode, Reg 0x1C[7:5] returns the mux

select value applied at OUT0.

When Reg 0x09[5] = 1, OUT0 mux selection is controlled by

Reg 0x1C[7:5] as follows:

7:5

out_sel0_data_mux

RW 000 = Mute

001 = 10 MHz Clock

010 = Raw Data (EQ Only)

100 = Retimed Data

Other Settings are invalid.

When Reg 0x09[5] = 1 and Reg 0x1E[7:5] = 101'b, OUT1

clock selection can be controlled by Reg 0x1C[4] as follows:

0 = OUT1 outputs 10 MHz clock

4

VCO_Div40

drv_out_ctrl

RW

OUT Mux

0x1C

1 = OUT1 outputs VCO divide-by-40

0x58

Select_0

Controls output mux selection for both OUT0 and OUT1 if

Reg 0x3F[3] = 1 to override the OUT_CTRL pin

00 = Mute both OUT0 and OUT1

01 = When CDR is locked, output reclocked data on OUT0

and output clock on OUT1. If locked data rate is ≤ 3G, OUT1

3:2

RW = VCO. If locked data rate is > 3G, OUT1 = VCO/40. When

unlocked, output raw data on OUT0 and mute OUT1.

10 = When locked, output retimed data on both OUT0 and

OUT1. When unlocked, output raw data on both OUT0 and

OUT1. This is the default setting.

11 = Output raw data on both OUT0 and OUT1.

1:0

7:0

Reserved

RW Reserved

0x1D

0x1E

Reserved

0x00

0x09

In normal operating mode, Reg 0x1E[7:5] returns the mux

select value applied at OUT1.

When Reg 0x09[5] = 1, OUT1 mux selection is controlled by

Reg 0x1E[7:5] as follows:

000 = Raw Data (EQ Only)

7:5

out_sel1_data_mux

RW 001 = Retimed Data

OUT Mux

Select_1

010 = Full Rate VCO clock

101 = 10 MHz Clock if Reg 0x1C[4] = 0 and VCO/40 clock if

Reg 0x1C[4] = 1

111 = Mute

Other Settings are invalid

4:0

7

Reserved

RW Reserved

0 = OUT1 normal polarity

RW 1 = Inverts OUT1 driver polarity

Note: No polarity inversion for OUT0

sel_inv_out1

0x1F

OUT1 Polarity

0x10

6:0

7:0

Reserved

RW Reserved

0x20

0x21

0x22

Reserved

0x00

0 = Disable HEO/VEO Acquisition override.

1 = Enable HEO/VEO Acquisition override. Value determined

by Reg 0x24[1].

eom_get_heo_

veo_ov

7

0x23

HEO_VEO_OV

0x40

RW

6:0

7

Reserved

fast_eom

Reserved

0 = Disable Fast EOM mode

RW

1 = Enable Fast EOM mode

6

R

Reserved

Zero Crossing Error Detector Status

0 = Zero crossing errors in the eye diagram observed

1 = No zero crossing errors in the eye diagram observed

get_heo_veo_error_

no_hits

5

4

0x24

EOM Control

0x40

Vertical Eye Closure Detector Status

0 = Open eye diagram detected

1 = Eye diagram completely closed

get_heo_veo_error_

no_opening

R

3:2

1

Reserved

eom_get_heo_veo

eom_start

Reserved

RW 1 = Acquire HEO and VEO (self-clearing) if Reg 0x23[7] = 1

RW 1 = Start EOM counter (self-clearing)

0

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Address Register Name

Bit

7:0

Field

Default Type

Description

0x25

0x26

EOM_MSB

EOM_LSB

eom_count_msb

eom_count_lsb

0x00

R

MSBs of EOM counter

LSBs of EOM counter

HEO value. This is measured in 0-63 phase settings. To get

HEO in UI, read HEO, convert hex to dec, then divide by 64.

0x27

HEO

7:0

heo

0x00

R

VEO value. This is measured in 0-63 vertical steps. To get

VEO in mV, convert hex to dec, then multiply by the EOM

Voltage Range defined in Reg 0x29[6:5].

0x28

VEO

7:0

7

veo

0x00

R

Reserved

RW Reserved

Readback of automatic EOM Voltage Range granularity.

00 = 3.125 mV

01 = 6.25 mV

10 = 9.375 mV

11 = 12.5 mV

Auto EOM

Voltage Range

0x29

6:5

eom_vrange_setting

0x00

R

4:0

7:0

7

Reserved

eom_timer_thr

Reserved

RW Reserved

0x2A

0x2B

EOM_timer_thr

Reserved

0x30

0x00

RW EOM timer for how long to check each phase/voltage setting.

RW Reserved

Reserved

0 = VEO scaling based on manual Voltage Range settings

RW (see Reg 0x11[7:6])

0x2C

VEO Scale

6

veo_scale

0x72

1 = Enable Auto VEO scaling

5:0

7:4

Reserved

RW Reserved

IN1 EQ Boost Override Control

CTLE Boost

Override

0 = Disable IN1 EQ boost override

1 = Override the internal IN1 EQ boost settings with values in

0x2D

3

reg_eq_bst_ov

0x00

RW

Reg 0x03[7:0]

2:0

7:0

Reserved

RW Reserved

0x2E

0x2F

0x30

Reserved

Rate Overrides

Reserved

0x24

0x06

0x00

RW Reserved

Reference Rate Selection for CDR Lock if Reg 0x3F[2] = 1

00 = Select SMPTE rates

01 = Select 10G Ethernet rate

7:6

refn_rate

RW

Other settings are Invalid

5:0

7:0

7

Reserved

R

Reserved

RW Reserved

Adapt Mode Override Value if Reg 0x3F[5] = 1

00 = Manual CTLE for IN1. Set CTLE/CDR Page Reg

RW 0x2D[3] = 1 to enable IN1 EQ boost settings with values in

Reg 0x03[7:0].

6:5

4:2

1:0

adapt_mode

Reserved

IN1 Adaptation

Mode and Input

Mux Select

01 = Automatic CTLE Adaptation for IN1.

0x31

0x00

RW Reserved

Input Mux Selection if Reg 0x3F[4] = 1 to override

IN_OUT_SEL pin

RW 10 = IN1 to OUT1 only

11 = IN1 to OUT0 and OUT1

Other settings are Invalid

input_mux_ch_sel

Compares HEO value, Reg 0x27[7:0] vs. threshold from Reg

0x32[7:4] x 4.

7:4

3:0

heo_int_thresh

veo_int_thresh

RW

HEO/VEO

Interrupt

Threshold

0x32

0x11

Compares VEO value. Reg 0x28[7:0] vs. threshold from Reg

0x32[3:0] x 4.

RW

0x33

0x34

0x35

0x36

0x37

0x38

Reserved

7:0

Reserved

0x88

0x3F

0x1F

0x11

0x00

RW Reserved

R

Reserved

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Address Register Name

Bit

7:0

7:6

5:4

3:2

Field

Default Type

Description

0x39

0x3A

Reserved

0x00

R

Reserved

fixed_eq_BST0

fixed_eq_BST1

fixed_eq_BST2

RW Fixed IN1 CTLE setting for 270M and 1.5G SMPTE rates. If

Reg 0x3F[0] = 0, Reg 0x3A fixed IN1 CTLE setting is also

RW

used for 3G rate.

Low Data Rate

IN1 EQ Boost

RW

0x00

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

1:0

fixed_eq_BST3

RW

0x3B

0x3C

0x3D

Reserved

7:0

Reserved

0x96

0x90

0x00

R

Reserved

RW Reserved

Enable HEO/VEO lock monitoring. Once the lock and

adaptation processes are complete, HEO/VEO monitoring is

performed once per the interval determined by Reg

0x69[3:0].

7

heo_veo_lockmon_en

RW

HEO_VEO Lock

Monitor Enable

0x3E

0x80

6:0

7:6

Reserved

RW Reserved

0 = Normal Behavior (Automatic Adaptation when IN1 is

selected)

5

mr_adapt_mode_ov

RW

1 = Override Automatic Adaptation for IN1. Adaptation

behavior is controlled by Reg 0x31[6:5].

0 = Input channel selection determined by IN_OUT_SEL pin

4

3

mr_in_out_sel_ov

mr_out_ctrl_ov

RW 1 = Override input channel selection pin settings. Input

selection is controlled by Reg 0x31[1:0].

0 = Output mux settings determined by OUT_CTRL pin

RW 1 = Override output mux pin settings. Output mux is

controlled by Reg 0x1C[3:2].

Pin Override

Register Control

0x3F

0x01

0 = SMPTE or 10 GbE reference rates determined by

IN_OUT_SEL pin

1 = Override reference rate pin settings. Reference rates for

2

mr_refn_rate_ov

RW

CDR lock are controlled by Reg 0x2F[7:6].

0 = IN1 EQ boost Bypass is controlled by OUT_CTRL pin

behavior

1

0

mr_eqbst_pin_ov

RW 1 = Override IN1 EQ boost pin control. IN1 EQ boost bypass

characteristics are controlled by settings in Reg 0x2D[3] and

Reg 0x03[7:0].

0 = Disables IN1 EQ Adaptation for 3G data rate

RW

mr_en_3G_divsel_eq

1 = Enables IN1 EQ Adaptation for 3G data rate

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

EQ_index_0_BST0

EQ_index_0_BST1

EQ_index_0_BST2

EQ_index_0_BST3

EQ_index_1_BST0

EQ_index_1_BST1

EQ_index_1_BST2

EQ_index_1_BST3

EQ_index_2_BST0

EQ_index_2_BST1

EQ_index_2_BST2

EQ_index_2_BST3

EQ_index_3_BST0

EQ_index_3_BST1

EQ_index_3_BST2

EQ_index_3_BST3

RW

Index 0 Boost

IN1 Index 0

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

0x40

0x41

0x42

0x43

0x00

0x40

0x80

0x50

Index 1 Boost

IN1 Index 1

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

Index 2 Boost

IN1 Index 2

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

Index 3 Boost

IN1 Index 3

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

Address Register Name

Bit

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:6

5:4

3:2

1:0

7:0

Field

Default Type

Description

EQ_index_4_BST0

EQ_index_4_BST1

EQ_index_4_BST2

EQ_index_4_BST3

EQ_index_5_BST0

EQ_index_5_BST1

EQ_index_5_BST2

EQ_index_5_BST3

EQ_index_6_BST0

EQ_index_6_BST1

EQ_index_6_BST2

EQ_index_6_BST3

EQ_index_7_BST0

EQ_index_7_BST1

EQ_index_7_BST2

EQ_index_7_BST3

EQ_index_8_BST0

EQ_index_8_BST1

EQ_index_8_BST2

EQ_index_8_BST3

EQ_index_9_BST0

EQ_index_9_BST1

EQ_index_9_BST2

EQ_index_9_BST3

EQ_index_10_BST0

EQ_index_10_BST1

EQ_index_10_BST2

EQ_index_10_BST3

EQ_index_11_BST0

EQ_index_11_BST1

EQ_index_11_BST2

EQ_index_11_BST3

EQ_index_12_BST0

EQ_index_12_BST1

EQ_index_12_BST2

EQ_index_12_BST3

EQ_index_13_BST0

EQ_index_13_BST1

EQ_index_13_BST2

EQ_index_13_BST3

EQ_index_14_BST0

EQ_index_14_BST1

EQ_index_14_BST2

EQ_index_14_BST3

EQ_index_15_BST0

EQ_index_15_BST1

EQ_index_15_BST2

EQ_index_15_BST3

Reserved

RW

Index 4 Boost

IN1 Index 4

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xC0

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

Boost for

Adaptation

RW

Index 5 Boost

IN1 Index 5

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0x90

RW

Index 6 Boost

IN1 Index 6

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0x54

RW

Index 7 Boost

IN1 Index 7

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xA0

RW

Index 8 Boost

IN1 Index 8

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xB0

RW

Index 9 Boost

IN1 Index 9

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0x95

RW

Index 10 Boost

IN1 Index 10

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0x69

RW

Index 11 Boost

IN1 Index 11

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xD5

RW

Index 12 Boost

IN1 Index 12

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0x99

RW

Index 13 Boost

IN1 Index 13

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xA5

RW

Index 14 Boost

IN1 Index 14

Boost for

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xE6

RW

Adaptation

RW

Index 15 Boost

IN1 Index 15

Boost for

Adaptation

[7:6]: 2-bit control for Stage 0 of the CTLE

[5:4]: 2-bit control for Stage 1 of the CTLE.

[3:2]: 2-bit control for Stage 2 of the CTLE.

[1:0]: 2-bit control for Stage 3 of the CTLE.

RW

0xF9

0x4F

0x50

RW

Reserved

0x00

RW Reserved

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

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Address Register Name

Bit

Field

Default Type

Description

0x51

0x52

0x53

Reserved

7:0

Reserved

0x00

RW Reserved

IN1 Active EQ

Readback

IN1 CTLE boost setting readback from Active CTLE

Adaptation.

7:0

eq_bst_to_ana

Reserved

R

Reserved

0 = Carrier Detect from the selected input de-asserted

1 = Carrier Detect from the selected input asserted

Note: Clears when Reg 0x54 is read-back.

7

6

cardet

R

0 = No interrupt from CDR Lock

1 = CDR Lock Interrupt

cdr_lock_int

Note: Clears when Reg 0x54 is read-back.

0 = No interrupt from IN1 Carrier Detect

1 = IN1 Carrier Detect Interrupt

Note: Clears when Reg 0x54 is read-back.

5

4

3

carrier_det1_int

Reserved

R

Reserved

Interrupt Status

Register

0x54

0x00

0 = No interrupt from HEO/VEO

1 = HEO/VEO Threshold Reached Interrupt

Note: Clears when Reg 0x54 is read-back.

heo_veo_int

0 = No interrupt from CDR Lock

2

1

cdr_lock_loss_int

R

1 = CDR Loss of Lock Interrupt

Note: Clears when Reg 0x54 is read-back.

0 = No interrupt from IN1 Carrier Detect

1 = IN1 Carrier Detect Loss Interrupt

Note: Clears when Reg 0x54 is read-back.

carrier_det1_loss_int

0

7:0

7

Reserved

R

Reserved

0x55

Reserved

0x02

RW Reserved

0 = Disable interrupt if CDR lock is achieved

1 = Enable interrupt if CDR lock is achieved

6

cdr_lock_int_en

RW

0 = Disable interrupt if IN1 Carrier Detect is asserted

1 = Enable interrupt if IN1 Carrier Detect is asserted

5

4

3

carrier_det1_int_en

Reserved

RW Reserved

Interrupt Control

Register

0x56

0x00

0 = Disable interrupt if HEO/VEO threshold is reached

1 = Enable interrupt if HEO/VEO threshold is reached

heo_veo_int_en

RW

0 = Disable interrupt if CDR loses lock

1 = Enable interrupt if CDR loses lock

2

1

cdr_lock_loss_int_en

carrier_det1_loss_int_

en

0 = Disable interrupt if there is loss of signal (LOS) on IN1

1 = Enable interrupt if there is loss of signal (LOS) on IN1

0

Reserved

RW Reserved

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

Reserved

7:0

7:4

0x26

0x31

0x70

0x3D

0xFF

0x00

While monitoring lock, these bits set the amount of interval

HEO_VEO Lock

Monitor

0x69

0x0A

times to monitor HEO or VEO lock. Each interval is 6.5 ms.

Therefore, by default, Reg 0x69[3:0] = 1010'b causes

HEO_VEO lock monitor to occur once every 65 ms.

3:0

hv_lckmon_cnt_ms

RW

7:4

3:0

7:0

veo_lck_thrsh

heo_lck_thrsh

Reserved

RW

HEO and VEO

Lock Threshold

HEO/VEO lock thresholds. Lock will not be declared until

HEO ≥ (heo_lck_thrsh x 4) and VEO ≥ (veo_lck_thrsh x 4).

0x6A

0x6B

0x44

0x40

Reserved

RW Reserved

32

LMH1226

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

Address Register Name

Bit

7:0

7:5

Field

Default Type

RW Reserved

Description

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x77

0x80

0x81

0x82

0x83

0x84

0x85

0x87

0x90

0x91

0x92

0x93

0x94

0x95

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

Reserved

0x00

0x03

0x20

0x00

0x50

0x00

0x80

0x70

0x04

0x00

0xA5

0x23

0x2C

0x32

0x37

0x3E

0x3F

0x04

0x06

0x04

RW Reserved

R

Reserved

RW Reserved

0 = Disable CDR Lock to 270 Mbps

1 = Enable CDR Lock to 270 Mbps

4

3

2

1

0

dvb_enable

hd_enable

3G_enable

6G_enable

12G_enable

RW

0 = Disable CDR Lock to 1.485/1.4835 Gbps

1 = Enable CDR Lock to 1.485/1.4835 Gbps

SMPTE Data

Rate Lock Enable

0xA0

0x1F

0 = Disable CDR Lock to 2.97/2.967 Gbps

1 = Enable CDR Lock to 2.97/2.967 Gbps

0 = Disable CDR Lock to 5.94/5.934 Gbps

1 = Enable CDR Lock to 5.94/5.934 Gbps

0 = Disable CDR Lock to 11.88/11.868 Gbps

1 = Enable CDR Lock to 11.88/11.868 Gbps

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7.5.3 Drivers Register Page

Address Register Name

Bit

7:0

7:6

7:0

Field

Default Type

RW Reserved

Description

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

Reserved

0x08

0x80

0x07

0x3F

0x00

0xA0

0x24

0x27

0x01

0x05

0x37

0x01

0x25

0x37

0x02

0x0A

0x02

0x08

0x04

0x3C

0x00

0x08

0x01

0x08

0x01

0xA7

0x00

0xC0

0x00

0x05

0x00

0x20

0x40

0x89

0x0B

0x20

0x00

RW Reserved

R

Reserved

RW Reserved

R

Reserved

RW Reserved

R

Reserved

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

Address Register Name

Bit

Field

Default Type

Description

0x2F

Reserved

7:0

Reserved

0x00

RW Reserved

OUT0 Mute Override Control

0 = Disable OUT0 Mute Override Control

1 = Enable OUT0 Mute Override Control by value in Reg

0x30[6].

7

6

5

tx0_mute_ov

tx0_mute_val

tx0_vod_ov

RW

0 = Normal Operation

1 = Mute OUT0 if Reg 0x30[7] = 1

OUT0 Output

Control

0x30

0x0A

OUT0 VOD Override Control

0 = VOD settings for OUT0 determined by VOD_DE pin

1 = Override VOD pin settings for OUT0. VOD settings for

OUT0 are controlled by Reg 0x30[2:0]

4:3

2:0

7

Reserved

tx0_vod

RW Reserved

VOD settings with DE = 0 for OUT0 if Reg 0x30[5] = 1. See

Figure 9.

RW Reserved

OUT0 De-Emphasis Override Control

RW

Reserved

0 = De-emphasis for OUT0 determined by VOD_DE pin

1 = Override De-emphasis settings for OUT0. De-emphasis

settings for OUT0 are controlled by Reg 0x31[2:0]

6

5

tx0_dem_ov

tx0_PD_ov

RW

OUT0 Power Down Override Control

0 = Disable OUT0 Power Down Override Control

1 = Enable OUT0 Power Down Override Control by value in

Reg 0x31[4].

OUT0

De-Emphasis

Control

RW

0x31

0x32

0x33

0x01

0x0A

0x11

0 = Normal Operation

1 = Power Down OUT0 if Reg 0x31[5] = 1

4

3

tx0_PD

Reserved

tx0_dem

RW Reserved

De-emphasis settings for OUT0 if Reg 0x31[6] = 1. See

Figure 10.

2:0

RW

OUT1 Mute Override Control

0 = Disable OUT1 Mute Override Control

1 = Enable OUT1 Mute Override Control by value in Reg

0x32[6].

7

6

5

tx1_mute_ov

tx1_mute_val

tx1_vod_ov

0 = Normal Operation

1 = Mute OUT1 if Reg 0x32[7] = 1

OUT1 Output

Control

OUT1 VOD Override Control

0 = VOD settings for OUT1 determined by VOD_DE pin

1 = Override VOD pin settings for OUT1. VOD settings for

OUT1 are controlled by Reg 0x32[2:0]

4:3

2:0

7

Reserved

tx1_vod

RW Reserved

VOD settings with DE = 0 for OUT1 if Reg 0x32[5] = 1. See

Figure 9.

RW Reserved

OUT1 De-Emphasis Override Control

RW

Reserved

0 = De-emphasis for OUT1 determined by VOD_DE pin

1 = Override De-emphasis settings for OUT1. De-emphasis

settings for OUT1 are controlled by Reg 0x33[2:0]

6

5

tx1_dem_ov

tx1_PD_ov

RW

OUT1 Power Down Override Control

0 = Disable OUT1 Power Down Override Control

1 = Enable OUT1 Power Down Override Control by value in

Reg 0x33[4].

OUT1

De-Emphasis

Control

RW

0 = Normal Operation

1 = Power Down OUT1 if Reg 0x33[5] = 1

4

3

tx1_PD

Reserved

tx1_dem

RW Reserved

De-emphasis settings for OUT1 if Reg 0x33[6] = 1. See

Figure 10.

2:0

RW

0x34

0x35

0x36

0x37

Reserved

7:0

Reserved

0x17

0x61

0x02

0x00

RW Reserved

35

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

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Address Register Name

Bit

7:0

Field

Default Type

RW Reserved

Description

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

Reserved

0x00

0x7F

0x00

0x01

0x00

0x0F

RW Reserved

R

Reserved

RW Reserved

R

Reserved

36

LMH1226

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ZHCSID0D –APRIL 2016–REVISED JUNE 2018

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 General Guidance for SMPTE and 10 GbE Applications

SMPTE specifications define the use of AC coupling capacitors for transporting uncompressed serial data

streams with heavy low frequency content. The use of 4.7-μF AC coupling capacitors is recommended to avoid

low frequency DC wander. SFF-8431 (SFP+) requires the 100-Ω signal to meet the electrical, return loss, jitter,

and eye mask specifications. It is recommended to place the LMH1226 as close as possible to the 100-Ω SFP+

optical module in order to meet the specifications for SFF-8431. Refer to 表 9 for design guidelines.

8.1.2 LMH1219 and LMH1226 Compatibility

The LMH1226 is pin compatible with LMH1219 (12G UHD cable equalizer with integrated reclocker). Both

LMH1219 and LMH1226 devices support Single Supply Mode and Dual Supply Mode as shown in 图 27 and 图

28, respectively.

8.2 Typical Application

The LMH1226 is a multi-rate reclocker that supports SDI data rates up to 11.88 Gbps and 10 GbE. 图 21 shows

a typical implementation of the LMH1226 as a SDI reclocker. Signal from a FPGA or optical module is connected

to the input port at IN1±. Equalized and reclocked data is output at OUT0± and OUT1± to a downstream video

processor.

2.5 V (Single Supply)

0.1-µF Capacitor close to each supply pin

10 µF

1 µF

0.1 µF

100-ꢀ Coupled Trace

VDD_CDR VDDIO

VIN

RX+

OUT0+

OUT0-

RSV1

RSV2

RSV1 and RSV2: No Connect

RX-

4.7 µF

EP

VSS

VDD_LDO

(1.8 V)

FPGA/Video

Processor

LMH1226

1 µF 0.1 µF

100-ꢀ Coupled Trace

100 ꢀ Coupled Trace

RX+

TX+

TX-

OUT1+

OUT1-

IN1+

IN1-

FPGA/Optical

Module

RX-

4.7 µF

VDDIO

220 ꢀ

VDDIO

LED

1 kꢀ

FLOAT for SPI Mode

1 kꢀ

or

20 kꢀ

1 kꢀ

or

20 kꢀ

1 kꢀ

or

20 kꢀ

Optional pullup or

pulldown resistors for

strap configuration

图 21. LMH1226 SPI Mode Connection Diagram

37

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

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Typical Application (接下页)

8.2.1 Design Requirements

表 9. LMH1226 Design Requirements

DESIGN PARAMETER

REQUIREMENTS

AC Coupling capacitors at IN1± should be 4.7-μF capacitors. Choose small 0402 surface

mount ceramic capacitors. This allows both SMPTE and 10 GbE data traffic.

IN1± Input AC coupling capacitors

Both OUT0± and OUT1± require AC coupling capacitors. Choose small 0402 surface mount

ceramic capacitors. 4.7-μF AC coupling capacitors are recommended.

Output AC coupling Capacitors

Decoupling capacitors are required to minimize power supply noise. Place 10-μF and 1-μF

bulk capacitors close to each device. Place a 0.1-μF capacitor close to each supply pin.

DC power supply decoupling capacitors

VDD_LDO decoupling capacitors

Place 1-μF and 0.1-μF surface mount ceramic capacitors as close as possible to the device

VDD_LDO pin.

High Speed IN1, OUT0, and OUT1 trace

impedance

IN1±, OUT0± and OUT1± should be routed with coupled board traces with 100-Ω differential

impedance.

SFP+ (SFF-8431) return loss

Place SFP module within 1-2 inches of the LMH1226 to minimize insertion and return loss.

Set MODE_SEL to Level-F (pin unconnected) for SPI. Set MODE_SEL to Level-L (connect 1

kΩ to VSS) for SMBus. SMBus is 3.3 V tolerant.

Use of SPI or SMBus interface

8.2.2 Detailed Design Procedure

The following general design procedure is recommended:

1. Select a suitable power supply voltage for the LMH1226. See Power Supply Recommendations for details.

2. Check that the power supply meets the DC and AC requirements in Recommended Operating Conditions.

3. Select the proper pull-high or pull-low resistors for IN_OUT_SEL and OUT_CTRL for setting the signal path.

4. Depending on the length and insertion loss of the output traces for OUT0± and OUT1±, select the proper

pull-high or pull-low resistors for VOD_DE to set the output amplitude and de-emphasis settings. Refer to

Table 5 for details.

5. Follow all design requirements detailed in 表 9 to optimize LMH1226 performance.

6. For additional layout recommendations, refer to PCB Layout Guidelines.

8.2.3 Recommended VOD and DEM Register Settings

表 10 shows recommended output amplitude and de-emphasis register settings for most applications.

表 10. VOD and DEM Register Settings

VOD REG SETTING

DEM REG SETTING

OUT0±: 0x30[5]=1, 0x30[2:0]

OUT1±: 0x32[5]=1, 0x32[2:0]

OUT0±: 0x31[6]=1, 0x31[2:0]

OUT1±: 0x33[6]=1, 0x33[2:0]

VOD (mVpp)

DEM (dB)

0

1

2

3

4

5

0

1

2

1

2

3

1

2

3

4

1

2

3

4

410

486

560

635

716

810

0

-0.1

-0.9

-0.3

-1.3

-2.4

-0.5

-1.8

-3.0

-4.0

-0.8

-2.4

-3.6

-4.6

38

LMH1226

www.ti.com.cn

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

表 10. VOD and DEM Register Settings (接下页)

VOD REG SETTING

DEM REG SETTING

OUT0±: 0x30[5]=1, 0x30[2:0]

OUT1±: 0x32[5]=1, 0x32[2:0]

OUT0±: 0x31[6]=1, 0x31[2:0]

OUT1±: 0x33[6]=1, 0x33[2:0]

VOD (mVpp)

DEM (dB)

5

6

7

5

1

2

3

4

5

1

2

3

4

5

810

880

973

-6.1

-1.0

-2.7

-4.0

-5.0

-6.5

-1.2

-3.1

-4.6

-5.7

-7.1

8.2.4 Application Performance Plots

The LMH1226 performance was measured with the test setup shown in 图 22.

Pattern

TL

Generator

V_OD= 800 mVp-p,

PRBS10

Differential 100 Ω

FR4 Channel

IN1±

LMH1226 OUT0±

Oscilloscope

图 22. Test Setup for LMH1226 PCB Equalizer (IN1±)

The eye diagrams in this subsection show how the LMH1226 improves overall signal integrity in the data path for

100-Ω differential FR4 PCB trace at IN1.

Time (30 ps/DIV)

VOD_DE = H, IN_OUT_SEL = L, OUT_CTRL = F

图 24. 10.3125 Gbps, TL = 20 in. 5-Mil FR4, Reclocked

Time (30 ps/DIV)

VOD_DE = H, IN_OUT_SEL = L, OUT_CTRL = L

图 23. 10.3125 Gbps, TL = 20 in. 5-Mil FR4, EQ Only

39

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

Time (20 ps/DIV)

VOD_DE = H, IN_OUT_SEL = H, OUT_CTRL = L

图 25. 11.88 Gbps, TL = 20 in. 5-Mil FR4, EQ Only

VOD_DE = H, IN_OUT_SEL = H, OUT_CTRL = F

图 26. 11.88 Gbps, TL = 20 in. 5-Mil FR4, Reclocked

40

LMH1226

www.ti.com.cn

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

9 Power Supply Recommendations

The LMH1226 is designed to provide flexibility in supply rails. There are two ways to power the LMH1226:

•

Single Supply Mode (2.5 V): This mode offers ease of use, with the internal circuitry receiving power from

the on-chip 1.8 V regulator. In this mode, 2.5 V is applied to VDD_CDR, VIN, and VDDIO. See 图 27 for more

details.

Dual Supply Mode (2.5 V and 1.8 V): This mode provides lower power consumption. In this mode, 1.8 V is

connected to both VIN and VDD_LDO. VDD_CDR, and VDDIO are powered from a 2.5 V supply. See 图 28

for more details.

When Dual Supply Mode is used, the 2.5 V supply for VDD_CDR and VDDIO should be powered before or at

the same time as the 1.8 V supply that powers VIN and VDD_LDO.

2.5 V

1 µF

10 µF

0.1 µF

VDD_CDR

VDDIO

VIN

Internal LDO

2.5 V to 1.8 V

EP

VSS

VDD_LDO (1.8 V)

1 µF

0.1 µF

图 27. Typical Connection for Single 2.5 V Supply

2.5 V

10 µF

0.1 µF

1 µF

0.1 µF

1.8 V

VDD_CDR

VDDIO

VIN

1 µF

EP

0.1 µF

VSS

VDD_LDO

0.1 µF

图 28. Typical Connection for Dual 2.5 V and 1.8 V Supply

For power supply de-coupling, 0.1-μF surface-mount ceramic capacitors are recommended to be placed close to

each VDD_CDR, VIN, VDD_LDO, and VDDIO supply pin to VSS. Larger bulk capacitors (for example, 10 µF and

1 µF) are recommended for VDD_CDR and VIN. Good supply bypassing requires low inductance capacitors.

This can be achieved through an array of multiple small body size surface-mount bypass capacitors in order to

keep low supply impedance. Better results can be achieved through the use of a buried capacitor formed by a

VDD and VSS plane separated by 2-4 mil dielectric in a printed circuit board.

10 Layout

10.1 PCB Layout Guidelines

The following guidelines are recommended for designing the board layout for the LMH1226:

1. Choose a suitable board stack-up that supports 100-Ω differential trace routing on the board's top layer. This

is typically done with a Layer 2 ground plane reference for the 100-Ω differential traces.

41

LMH1226

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

www.ti.com.cn

PCB Layout Guidelines (接下页)

2. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-µF AC coupling

capacitor and IC landing pads to minimize parasitic capacitance. The size of the anti-pad depends on the

board stack-up and can be determined by a 3-dimension electromagnetic simulation tool.

3. Keep trace length within 1-2 inches between the SFP module and IN1±. This minimizes insertion loss and

return loss.

4. Use coupled differential traces with 100-Ω impedance for signal routing to IN1±, OUT0± and OUT1±. They

are usually 5-8 mil trace width reference to a ground plane at Layer 2.

5. The exposed pad EP of the package should be connected to the ground plane through an array of vias.

These vias are solder-masked to avoid solder flowing into the plated-through holes during the board

manufacturing process.

6. Connect each supply pin (VDD_CDR, VIN, VDDIO, VDD_LDO) to the power or ground planes with a short

via. The via is usually placed tangent to the supply pins' landing pads with the shortest trace possible.

7. Power supply bypass capacitors should be placed close to the supply pins. They are commonly placed at the

bottom layer and share the ground of the EP.

10.2 Layout Example

The following example demonstrates the high speed signal trace routing to the LMH1226.

1. Anti-pad under passive components.

2. 100-Ω coupled trace.

3. Vias with solder mask.

2

1

2

3

1

2

图 29. LMH1226 PCB Layout Example

42

LMH1226

www.ti.com.cn

ZHCSID0D –APRIL 2016–REVISED JUNE 2018

11 器件和文档支持

11.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

43

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

4.1

3.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

7

12

20X 0.5

6

13

2X

25

2.5

2.6 0.1

1

18

0.3

24X

0.2

24

19

PIN 1 ID

(OPTIONAL)

0.1

C A B

C

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(1.05)

SYMM

25

(3.8)

20X (0.5)

(R0.05)

TYP

6

13

(

0.2) TYP

VIA

7

12

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

19

(R0.05) TYP

24

24X (0.6)

1

18

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

25

(3.8)

6

13

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMH1226RTWR
厂家：	TEXAS INSTRUMENTS
描述：	12G SDI 双路输出时钟恢复器 \| RTW \| 24 \| -40 to 85 时钟
文件：	总51页 (文件大小：1840K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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