LMH1228RTVR [TI]

具有集成时钟恢复器的 12G 超高清 SDI 双路电缆驱动器 | RTV | 32 | -40 to 85;


型号：	LMH1228RTVR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成时钟恢复器的 12G 超高清 SDI 双路电缆驱动器 \| RTV \| 32 \| -40 to 85 时钟驱动电视驱动器
文件：	总47页 (文件大小：2485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

带集成时钟恢复器的 LMH1228 12G UHD-SDI 双路输出电缆驱动器

1 特性

3 说明

•

支持 ST-2082-1 (12G)、ST-2081-1 (6G)、ST-424

(3G)、ST-292 (HD) 和 ST-259 (SD)

LMH1228 器件是一款带有时钟恢复器的 12G UHD-

SDI 低功耗双路输出电缆驱动器。它支持高达

11.88Gbps 的 SMPTE 视频速率，因此可为 4K/8K 应

用实现超高清视频的高度集成和高性能解决方案。时钟

和数据恢复 (CDR) 电路多种多样，因此片上时钟恢复

器可自动检测并锁定到高达 11.88Gbps 的各种

SMPTE 视频速率。主机端上的其他时钟恢复型 100Ω

驱动器输出可用于监控或信号分配用途。

•

兼容 DVB-ASI 和 AES10 (MADI)

集成时钟恢复器锁定为 11.88Gbps、5.94Gbps、

2.97Gbps、1.485Gbps 或 1.001 分频子速率和

270Mbps 的 SMPTE 速率

•

集成眼图张开度监视器 (EOM)

双路差分输出电缆驱动器

片上 75Ω 终端和回损补偿网络

自适应 PCB 输入均衡器

片上时钟恢复器可减弱高频抖动并使用纯净的低抖动时

钟完全重新生成数据。此时钟恢复器具有内置环路滤波

器，且不需要任何输入参考时钟。LMH1228 还具有内

部眼图张开度监视器和可编程引脚，可实现 CDR 锁定

指示、输入信号检测或硬件干扰，从而为系统诊断和板

启动提供支持。

时钟恢复型 100Ω 环回输出

75Ω 输出端的自动压摆率控制

75Ω 输出端的自动预加重和输出振幅

100Ω 输出端的可编程去加重功能和输出振幅

75Ω 和 100Ω 输出端的极性反转

没有输入信号时自动进入省电工作模式

LMH1228 由 2.5V 单电源供电运行。它采用小尺寸

5mm × 5mm 32 引脚 WQFN 封装。LMH1228 与

LMH1208（12G 双路电缆驱动器）引脚兼容。

–

功耗：25mW（典型值）

•

通过使能引脚进行断电控制

2.5V 单电源

器件信息⁽¹⁾

–

功耗：305mW（典型值）

器件型号

LMH1228

封装

WQFN (32)

封装尺寸（标称值）

•

可通过引脚、SPI 或 SMBus 接口进行编程

工作温度范围：-40°C 至 +85°C

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

5mm × 5mm 32 引脚 WQFN 封装

2 应用

简化方框图

•

SMPTE 兼容串行数字接口

100-Ω

Driver

UHDTV/4K/8K/HDTV/SDTV 视频

广播视频路由器、交换机、分配放大器和监视器

数字视频处理和编辑

OUT0

Cable

Driver

SDI_OUT1

SDI_OUT2

CDR

PCB

Cable

Driver

IN0

Control

Power

Management

Serial

Interface

LDO

Control Logic

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS568

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 21

7.5 Register Maps ........................................................ 25

Application and Implementation ........................ 26

8.1 Application Information............................................ 26

8.2 Typical Applications ................................................ 27

Power Supply Recommendations...................... 34

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

10 Layout................................................................... 34

10.1 Layout Guidelines ................................................. 34

10.2 Layout Example .................................................... 36

11 器件和文档支持 ..................................................... 37

11.1 文档支持................................................................ 37

11.2 接收文档更新通知 ................................................. 37

11.3 支持资源................................................................ 37

11.4 商标....................................................................... 37

11.5 静电放电警告......................................................... 37

11.6 出口管制提示......................................................... 37

11.7 Glossary................................................................ 37

12 机械、封装和可订购信息....................................... 37

12.1 Package Option Addendum .................................. 38

6.6 Recommended SMBus Interface Timing

Specifications........................................................... 11

6.7 Serial Parallel Interface (SPI) Timing

Specifications........................................................... 12

6.8 Typical Characteristics............................................ 14

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 16

4 修订历史记录

Changes from Revision B (September 2017) to Revision C

Page

•

首次公开发布 .......................................................................................................................................................................... 1

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

5 Pin Configuration and Functions

RTV Package

32-Pin WQFN

Top View

SDI_OUT1+

SDI_VOD

OUT0+

OUT0-

VDD_CDR

VSS

SDI_OUT1-

VSS

OUT0_SEL

LMH1228

RSV6

IN0+

VSS

IN0-

SDI_OUT2-

SDI_OUT2+

EP = VSS

OUT_CTRL

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

HIGH-SPEED DIFFERENTIAL I/OS

SDI_OUT1+

SDI_OUT1–

SDI_OUT2+

SDI_OUT2–

I/O, Analog

Single-ended complementary outputs with on-chip 75-Ω termination at SDI_OUT1+ and SDI_OUT1–.

SDI_OUT1± include integrated return loss networks designed to meet the SMPTE output return loss

requirements. Connect SDI_OUT1+ to a BNC through a 4.7-µF, AC-coupling capacitor. SDI_OUT1–

should be similarly AC-coupled and terminated with an external 4.7-µF capacitor and 75-Ω resistor to

GND.

I/O, Analog

O, Analog

Single-ended complementary outputs with on-chip 75-Ω termination at SDI_OUT2+ and SDI_OUT2–.

SDI_OUT2± include integrated return loss networks designed to meet the SMPTE output return loss

requirements. SDI_OUT2± is used as a second cable driver. Connect SDI_OUT2+ to a BNC through a

4.7-µF, AC-coupling capacitor. SDI_OUT2– should be similarly AC-coupled and terminated with an

external 4.7-µF capacitor and 75-Ω resistor to GND.

IN0+

I, Analog

O, Analog

Differential inputs from host video processor. On-chip 100-Ω differential termination. Requires external

4.7-µF, AC-coupling capacitors for SMPTE applications.

IN0–

OUT0+

Differential outputs to host video processor. On-chip 100-Ω differential termination. Requires external 4.7-

µF, AC-coupling capacitors for SMPTE applications.

OUT0–

CONTROL PINS

OUT0_SEL enables the use of the 100-Ω host-side output driver at OUT0±.

See Table 2 for details.

OUT0_SEL

I, LVCMOS

OUT0_SEL is internally pulled high by default (OUT0 disabled).

HOST_EQ0 selects the equalizer setting for IN0±.

See Table 4 for details.

HOST_EQ0

MODE_SEL

I, 4-LEVEL

MODE_SEL enables the SPI or SMBus serial control interface.

See Table 9 for details.

SDI_OUT2_SEL enables the use of the 75-Ω output driver at SDI_OUT2±.

See Table 2 for details.

SDI_OUT2_SEL

I, LVCMOS

SDI_OUT2_SEL is internally pulled high by default (SDI_OUT2 disabled).

(1) I = Input, O = Output, I/O = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

OUT_CTRL selects the signal being routed to the output. It is used to enable or bypass the reclocker.

See Table 6 for details.

OUT_CTRL

I, 4-LEVEL

SDI_VOD selects one of four output amplitudes for the cable drivers at SDI_OUT1± and SDI_OUT2±.

See Table 7 for details.

SDI_VOD

LOCK_N

LOCK_N is the reclocker lock indicator. LOCK_N is pulled low when the reclocker has acquired lock

condition. LOCK_N is a 3.3-V tolerant, open-drain output. It requires an external resistor to a logic supply.

LOCK_N can be reconfigured to indicate Signal Detector (SD_N) or Interrupt (INT_N) through register

programming. See Status Indicators and Interrupts.

O, LVCMOS,

A logic-high at ENABLE enables normal operation for the LMH1228. A logic-low at ENABLE places the

LMH1228 in Power-Down Mode.

ENABLE

I, LVCMOS

ENABLE is internally pulled high by default.

SPI SERIAL CONTROL INTERFACE, MODE_SEL = F (FLOAT)

SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH1228 slave

SS_N

I, LVCMOS

device.

SS_N is a 2.5-V LVCMOS input and is internally pulled high by default.

MOSI is the SPI serial control data input to the LMH1228 slave device when the SPI bus is enabled.

MOSI is a 2.5-V LVCMOS input.

An external pullup resistor is recommended.

MOSI

MISO

SCK

I, LVCMOS

O, LVCMOS

I, LVCMOS

MISO is the SPI serial control data output from the LMH1228 slave device.

MISO is a 2.5-V LVCMOS output.

SCK is the SPI serial input clock to the LMH1228 slave device when the SPI interface is enabled. SCK is

a 2.5-V LVCMOS input.

An external pullup resistor is recommended.

SMBUS SERIAL CONTROL INTERFACE, MODE_SEL = L (1 KΩ TO VSS)

ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16

supported SMBus addresses when SMBus is enabled. See Table 10 for details.

ADDR0

SDA

Strap, 4-LEVEL

SDA is the SMBus bidirectional data line to or from the LMH1228 slave device when SMBus is enabled.

SDA is an open-drain I/O and requires an external pullup resistor to the SMBus termination voltage. SDA

is 3.3-V tolerant.

I/O, LVCMOS,

ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16

supported SMBus addresses when SMBus is enabled. See Table 10 for details.

ADDR1

Strap, 4-LEVEL

SCL is the SMBus input clock to the LMH1228 slave device when SMBus is enabled. It is driven by a

LVCMOS open-drain driver from the SMBus master. SCL requires an external pullup resistor to the

SMBus termination voltage. SCL is 3.3-V tolerant.

I/O, LVCMOS,

SCL

RESERVED

RSV1

RSV2

RSV3

RSV4

RSV5

—

Reserved pins. Do not connect.

Reserved pin. This input must be tied high with 1-kΩ resistor to VIN. Alternatively, this pin setting can be

overridden by register control. Refer to the LMH1228 and LMH1208 Programming Guide (SNAU206) for

more details.

RSV6

I, LVCMOS

POWER

VSS

3, 6, 20

I, Ground

I, Power

Ground reference.

VDD_CDR

VIN

VDD_CDR powers the reclocker circuitry. It is connected to the same 2.5-V ± 5% supply as VIN.

VIN is connected to an external 2.5-V ± 5% power supply.

VDD_LDO is the output of the internal 1.8-V LDO regulator. VDD_LDO output requires an external 1-µF

and 0.1-µF bypass capacitor to VSS. The internal LDO is designed to power internal circuitry only.

VDD_LDO

—

O, Power

I, Ground

EP is the exposed pad at the bottom of the RTV package. The exposed pad should be connected to the

VSS plane through a 3 × 3 via array.

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–30

MAX

2.75

UNIT

Supply voltage (VIN, VDD_CDR)

Input voltage for 4-level pins

Input/output voltage for 2-level control pins

SMBus input/output voltage (SDA, SCL)

SPI input/output voltage (SS_N, MISO, MOSI, and SCK)

High-speed input/output voltage (IN0±, SDI_OUT1±, OUT0±, SDI_OUT2±)

Input current (IN0±)

2.75

°C

Operating junction temperature

125

150

Storage temperature, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±6000

±5500

±1500

UNIT

All pins except 13 and 29

Pins 13 and 29

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.375

300

NOM

MAX

2.625

3.6

UNIT

Supply voltage

VIN, VDD_CDR to VSS

2.5

VDD_SMBUS

SMBus: SDA, SCL open-drain termination voltage

Before 5-inch board trace to IN0±

850

Source differential launch

amplitude

V_{IN0_LAUNCH}

mVp-p

Before 20-inch board trace to IN0±

650

1000

110

T_JUNCTION

T_AMBIENT

Operating junction temperature

Ambient temperature

°C

–40

< 20

< 10

50 Hz to 1 MHz, sinusoidal

NTps_max

Maximum supply noise⁽¹⁾

mVp-p

1.1 MHz to 50 MHz, sinusoidal

(1) The sum of the DC supply voltage and AC supply noise should not exceed the recommended supply voltage range.

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

6.4 Thermal Information

LMH1228

RTV (WQFN)

32 PINS

32.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

15.0

6.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

6.5

R_θJC(bot)

1.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

SDI_OUT1± enabled

SDI_OUT2± disabled

OUT0± disabled

305

350

442

SDI_OUT1± enabled

SDI_OUT2± disabled

OUT0± enabled

Power dissipation,

Measured with PRBS10,

CDR Locked to 11.88 Gbps,

VOD = default,

SDI_OUT1± enabled

SDI_OUT2± enabled

OUT0± disabled

HEO/VEO lock monitor disabled

SDI_OUT1± enabled

SDI_OUT2± enabled

OUT0± enabled

485

Power dissipation,

Power Save Mode

Power Save Mode,

ENABLE = H, no signal applied at IN0±

PD_Z

SDI_OUT1± enabled

SDI_OUT2± disabled

OUT0± disabled

122

146

166

211

230

SDI_OUT1± enabled

SDI_OUT2± disabled

OUT0± enabled

Current consumption,

140

177

194

Measured with PRBS10,

CDR Locked to 11.88 Gbps,

VOD = default,

IDD

SDI_OUT1± enabled

SDI_OUT2± enabled

OUT0± disabled

HEO/VEO lock monitor disabled

SDI_OUT1± enabled

SDI_OUT2± enabled

OUT0± enabled

Current consumption,

Power Save Mode

Power Save Mode,

ENABLE = H, no signal applied at IN0±

IDD_Z

Current consumption,

Power-Down Mode

Power-Down Mode,

ENABLE = L, no signal applied at IN0±

IDD_{Z_PD}

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SDI_OUT1± enabled

SDI_OUT2± disabled

OUT0± disabled

200

SDI_OUT1± enabled

SDI_OUT2± disabled

OUT0± enabled

Current consumption,

CDR acquiring lock to 11.88

Gbps,

VOD = default,

HEO/VEO lock monitor enabled

225

271

290

IDD_TRANS

SDI_OUT1± enabled

SDI_OUT2± enabled

OUT0± disabled

SDI_OUT1± enabled

SDI_OUT2± enabled

OUT0± enabled

LVCMOS DC SPECIFICATIONS

2-level input (SS_N, SCK, MOSI,

SDI_OUT2_SEL, OUT0_SEL, ENABLE)

0.72 ×

VIN

VIN +

0.3

V_IH

Logic high input voltage

0.7 ×

VIN

2-level input (SCL, SDA)

3.6

2-level input (SS_N, SCK, MOSI,

SDI_OUT2_SEL, OUT0_SEL, ENABLE,

SCL, SDA)

0.3 ×

VIN

V_IL

Logic low input voltage

Logic high output voltage

0.8 ×

VIN

V_OH

IOH = –2 mA, (MISO)

IOL = 2 mA, (MISO)

VIN

0.2 ×

VIN

V_OL

Logic low output voltage

IOL = 3 mA, (LOCK_N, SDA)

LVCMOS (SDI_OUT2_SEL, ENABLE)

LVCMOS (OUT0_SEL)

0.4

µA

Input high leakage current

(Vinput = VIN)

I_IH

LVCMOS (LOCK_N)

SPI mode: LVCMOS (SS_N, SCK, MOSI)

SMBus mode: LVCMOS (SCL, SDA)

LVCMOS (SDI_OUT2_SEL, ENABLE)

LVCMOS (OUT0_SEL)

–50

–15

–10

–15

–50

–10

LVCMOS (LOCK_N)

Input low leakage current

(Vinput = GND)

I_IL

SPI mode: LVCMOS (SCK, MOSI)

SPI mode: LVCMOS (SS_N)

SMBus mode: LVCMOS (SCL, SDA)

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)

Measured voltage at 4-level pin with

V_{LVL_H}

V_{LVL_F}

V _{LVL_R}

V_{LVL_L}

LEVEL-H input voltage

LEVEL-F default voltage

LEVEL-R input voltage

LEVEL-L input voltage

VIN

external 1 kΩ to VIN

2/3 ×

VIN

Measured voltage 4-level pin at default

Measured voltage at 4-level pin with

external 20 kΩ to VSS

1/3 ×

VIN

Measured voltage at 4-level pin with

external 1 kΩ to VSS

4-levels (HOST_EQ0, MODE_SEL,

OUT_CTRL, SDI_VOD)

µA

Input high leakage current

(Vinput = VIN)

I_IH

SMBus mode: 4-levels (ADDR0, ADDR1)

4-levels (HOST_EQ0, MODE_SEL,

OUT_CTRL, SDI_VOD)

–160

–93

–40

Input low leakage current

(Vinput = GND)

I_IL

SMBus mode: 4-levels (ADDR0, ADDR1)

RECEIVER SPECIFICATIONS (IN0±)

R_{IN0_TERM}

DC input differential termination Measured across IN0+ to IN0–

100

–22

–16

–10

120

SDD11, 10 MHz – 2.8 GHz

SDD11, 2.8 GHz – 6 GHz

SDD11, 6 GHz – 11.1 GHz

RL_{IN0_SDD11}

Input differential return loss⁽¹⁾

Differential to common-mode

input conversion⁽¹⁾

RL_{IN0_SCD11}

V_{IN0_CM}

SCD11, 10 MHz to 11.1 GHz

–21

Input common-mode voltage at IN0+ or

IN0– to GND

DC common-mode voltage

2.06

Signal detect (default)

Assert ON threshold level for

IN0±

11.88 Gbps, EQ and PLL pathological

pattern

CD_{ON_IN0}

mVp-p

Signal detect (default)

Deassert OFF threshold level

for IN0±

11.88 Gbps, EQ and PLL pathological

pattern

CD_{OFF_IN0}

DRIVER OUTPUT (SDI_OUT1+ AND SDI_OUT2+)

SDI_OUT1+ and SDI_OUT1–,

SDI_OUT2+ and SDI_OUT2– to VIN

DC output single-ended

R_{OUT_TERM}

termination

Measure AC signal at SDI_OUT1+ and

SDI_OUT2+, with SDI_OUT1– and

SDI_OUT2– AC terminated with 75 Ω

SDI_VOD = H

840

mVp-p

Output single-ended output

VOD_{CD_OUTP}

voltage

SDI_VOD = F

SDI_VOD = R

SDI_VOD = L

720

800

880

760

880

mVp-p

Measure AC signal at SDI_OUT1– and

SDI_OUT2-, with SDI_OUT1+ and

SDI_OUT2+ AC terminated with 75 Ω

SDI_VOD = H

840

mVp-p

Output single-ended output

VOD_{CD_OUTN}

voltage

SDI_VOD = F

SDI_VOD = R

SDI_VOD = L

720

800

880

760

880

mVp-p

Output pre-emphasis boost amplitude at

SDI_OUT1+ and SDI_OUT2+, programmed

to maximum setting through register,

measured at SDI_VOD = F

PRE_{CD_OUTP}

Output pre-emphasis

(1) This parameter is measured with the LMH1297EVM (Evaluation board for LMH1228).

LMH1228

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ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output pre-emphasis boost amplitude at

SDI_OUT1– and SDI_OUT2–, programmed

to maximum setting through register,

measured at SDI_VOD = F

PRE_{CD_OUTN}

Output pre-emphasis

Measured with PRBS10 pattern, default

VOD at 20% – 80% amplitude, default pre-

emphasis enabled

11.88 Gbps

t_{R_F_SDI}

Output rise and fall time⁽¹⁾

5.94 Gbps

2.97 Gbps

1.485 Gbps

270 Mbps

400

550

700

Measured with PRBS10 pattern, default

VOD at 20% – 80% amplitude, default pre-

emphasis enabled

11.88 Gbps

Output rise and fall time

mismatch⁽¹⁾

t_{R_F_DELTA}

5.94 Gbps

2.97 Gbps

1.485 Gbps

270 Mbps

2.7

0.8

150

Measured with PRBS10 pattern, default

VOD, default pre-emphasis enabled⁽²⁾

12G/6G/3G/HD/SD

Output overshoot or undershoot

V_OVERSHOOT

(1)

V_{DC_OFFSET}

V_{DC_WANDER}

DC offset

12G/6G/3G/HD/SD

±0.2

12G/6G/3G/HD/SD with EQ pathological

pattern

DC wander

S22, 5 MHz to 1.485 GHz

S22, 1.485 GHz to 3 GHz

S22, 3 GHz to 6 GHz

–25

–22

–12

–8

Output return loss at

RL_{CD_S22}

SDI_OUT1+ and SDI_OUT2+

reference to 75 Ω⁽¹⁾

S22, 6 GHz to 12 GHz

(2) V_OVERSHOOTovershoot/undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The

maximum value specified in Electrical Characteristics for V_OVERSHOOTis based on bench evaluation across temperature and supply

voltages with the LMH1297EVM.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

DRIVER OUTPUT (OUT0±)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC output differential

termination

R_{OUT0_TERM}

Measured across OUT0+ and OUT0–

100

410

120

620

Measured with 8T pattern

HOST_EQ0 = H

mVp-p

Output differential voltage at

OUT0±

HOST_EQ0 = F

HOST_EQ0 = R

HOST_EQ0 = L

485

560

635

810

mVp-p

VOD_OUT0

Measured with 8T pattern

HOST_EQ0 = H

410

mVp-p

De-emphasized output

differential voltage at OUT0±

HOST_EQ0 = F

HOST_EQ0 = R

HOST_EQ0 = L

550

545

532

mVp-p

VOD_{OUT0_DE}

Measured with 8T Pattern, 20% – 80%

amplitude

t_R/t_F

Output rise and fall time

Measured with the device powered up and

outputs a 10-MHz clock signal

–24

SDD22, 10 MHz – 2.8 GHz

RL_OUT0-SDD22

Output differential return loss⁽¹⁾

SDD22, 2.8 GHz – 6 GHz

SDD22, 6 GHz – 11.1 GHz

–16

–15

Measured with the device powered up and

outputs a 10-MHz clock signal.

SCC22, 10 MHz – 4.75 GHz

–12

Output common-mode return

loss⁽¹⁾

RL_OUT0-SCC22

SCC22, 4.75 GHz – 11.1 GHz

–9

AC common-mode voltage on

OUT0±⁽¹⁾

V_{OUT0_CM}

Default setting, PRBS31, 11.88 Gbps

mV (rms)

RECLOCKER OUTPUT JITTER

Measured at SDI_OUT1+ and SDI_OUT2+,

OUT0± disabled

PRBS10, 3G/HD/SD12G/6G/3G/HD/SD

AJ_CD

Alignment jitter⁽¹⁾

Timing jitter⁽¹⁾

0.1

0.14

Measured at SDI_OUT1+ and SDI_OUT2+,

OUT0± disabled

TMJ_CD

0.45

PRBS10, 12G/6G/3G/HD/SD

RECLOCKER SPECIFICATIONS

SMPTE 12G, /1

SMPTE 12G, /1.001

SMPTE 6G, /1

11.88

11.868

5.94

Gbps

Mbps

SMPTE 6G, /1.001

SMPTE 3G, /1

5.934

2.97

LOCK_RATE

Reclocker lock data rates

SMPTE 3G, /1.001

SMPTE HD, /1

2.967

1.485

1.4835

270

SMPTE HD, /1.001

SMPTE SD, /1

Reclocker automatically goes to

bypass

BYPASS_RATE

MADI

125

Mbps

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Applied 0.2 UI input sinusoidal jitter,

measure –3-dB bandwidth on input-to-

output jitter transfer

MHz

11.88 Gbps

BW_PLL

PLL bandwidth

5.94 Gbps

2.97 Gbps

1.485 Gbps

270 Mbps

MHz

11.88 Gbps, 5.94 Gbps, 2.97 Gbps,

1.485 Gbps, 270 Mbps

J_PEAKING

PLL jitter peaking

Lock time

<0.3

SMPTE supported data rates, disable

HEO/VEO monitor, CTLE in AM0 Manual

Mode

T_LOCK

Measured with temperature ramp of 5°C

per min, ramp up and down, –40°C to 85°C

operating range at 11.88 Gbps

TEMP_LOCK

TLAT

VCO temperature lock range

Reclocker latency

125

°C

Measured from IN0± to SDI_OUT1+, 11.88

Gbps

1.5 UI +

175

Measured from IN0± to SDI_OUT2+, 11.88

Gbps

1.6 UI +

130

6.6 Recommended SMBus Interface Timing Specifications

over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

F_SCL

T_BUF

SMBUS SCL frequency

400

kHz

Bus free time between stop and start

condition

See Figure 1.

1.3

µs

T_HD:STA

T_SU:STA

T_SU:STO

T_HD:DAT

T_SU:DAT

T_LOW

Hold time after (repeated) start condition.

Repeated start condition setup time

Stop condition setup time

Data hold time

After this period, the first clock is generated.

See Figure 1.

0.6

µs

See Figure 1.

Data setup time

See Figure 1.

100

1.3

0.6

Clock low period

See Figure 1.

T_HIGH

T_R

Clock high period

See Figure 1.

Clock and data rise time

Clock and data fall time

See Figure 1.

300

T_F

See Figure 1.

Time from minimum VDDIO to SMBus valid

write or read access

T_POR

SMBus ready time after POR

(1) These parameters support SMBus 2.0 specifications.

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6.7 Serial Parallel Interface (SPI) Timing Specifications

over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

F_SCK

T_PH

SPI SCK frequency

MHz

% SCK

period

SCK pulse width high

SCK pulse width low

See Figure 17 and Figure 18

% SCK

period

T_PL

T_SU

MOSI setup time

µs

See Figure 17 and Figure 18

T_H

MOSI hold time

T_SSSU

T_SSH

T_SSOF

T_ODZ

T_OZD

T_OD

SS setup time

SS hold time

SS off time

MISO driven-to-tristate time

MISO tristate-to-driven time

MISO output delay time

See Figure 17 and Figure 18

(1) Typical SPI load capacitance is 2 pF.

tt_LOW

t_R

t_HIGH

SCL

tt_HD:STA

t_HD:DAT

t_SU:STA

t_F

t_SU:STO

tt_BUF

t_SU:DAT

SDA

Figure 1. SMBus Timing Parameters

t_SSOF

t_SSH

SS_N

SCK

t_PL

t_SSSU

t_PH

t_H

t_SU

HiZ

MOSI

MISO

t_ODZ

HiZ

R/W

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

Figure 2. SPI Timing Parameters (Write Operation)

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t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

Don‘t Care

Figure 3. SPI Timing Parameters (Read Operation)

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6.8 Typical Characteristics

T_A= 25°C and VIN = VDD_CDR = 2.5 V (unless otherwise noted)

Figure 4. Output at 11.88 Gbps, Measured at SDI_OUT1+,

20-in. FR4 Before IN0±

Figure 5. Output at 11.88 Gbps, Measured at SDI_OUT2+,

20-in. FR4 Before IN0±

1.0

DE = 0

DE = 1

0.9

0.8

0.7

0.6

0.5

0.4

œ2

œ4

DE = 2

DE = 3

DE = 4

DE = 5

DE = 6

DE = 7

œ6

œ8

œ10

œ12

VOD Register Settings

C001

C002

Figure 6. OUT0 VOD vs. OUT0 VOD and DE

Figure 7. OUT0 De-Emphasis vs. OUT0 VOD and DE

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

SDI_OUT1+

SDI_OUT2+

SMPTE RL Specification Limit

Frequency (GHz)

C001

Measured with LMH1297EVM

Figure 8. Return Loss (RL) vs Frequency

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7 Detailed Description

7.1 Overview

The LMH1228 is a 12G UHD-SDI dual output cable driver with integrated reclocker. From the host-side input at

IN0±, the signal is equalized, reclocked, and routed to 75-Ω cable driver outputs at SDI_OUT1+ and

SDI_OUT2+. The 100-Ω driver at OUT0± can be used as a host-side loop-back output for monitoring purposes.

7.2 Functional Block Diagram

100-Ω

Driver

OUT0

Cable

Driver

SDI_OUT1

SDI_OUT2

CDR

PCB

Cable

Driver

IN0

Control

Power

Management

Serial

Interface

LDO

Control Logic

Figure 9. LMH1228 Block Diagram Overview

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7.3 Feature Description

The LMH1228 data path consists of several key blocks as shown in the functional block diagram. These key

blocks are:

•

4-Level Input Pins and Thresholds

OUT0_SEL and SDI_OUT2_SEL Control

Input Signal Detect

Continuous Time Linear Equalizer (CTLE)

Clock and Data (CDR) Recovery

Internal Eye Opening Monitor (EOM)

Output Function Control

Output Driver Control

Status Indicators and Interrupts

7.3.1 4-Level Input Pins and Thresholds

The 4-level input configuration pins use a resistor divider to provide four logic states for each control pin. There is

an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the control pin that sets the default voltage at 2/3 ×

VIN. These resistors, together with the external resistor, combine to achieve the desired voltage level. By using

the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage levels for each of the four

input states are achieved as shown in Table 1.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTING

Tie 1 kΩ to VIN

NOMINAL PIN VOLTAGE

VIN

2/3 × VIN

1/3 × VIN

Float (leave pin open)

Tie 20 kΩ to VSS

Tie 1 kΩ to VSS

Typical 4-Level Input Thresholds:

•

Internal Threshold between L and R = 0.2 × VIN

Internal Threshold between R and F = 0.5 × VIN

Internal Threshold between F and H = 0.8 × VIN

7.3.2 OUT0_SEL and SDI_OUT2_SEL Control

The OUT0_SEL and SDI_OUT2_SEL pins select the LMH1228 data-path routes. Table 2 shows all possible

signal path combinations and typical use cases for each configuration.

Table 2. LMH1228 Signal Path Combinations

LINE SIDE

SECONDARY

OUTPUT

HOST SIDE

LOOP-BACK TYPICAL APPLICATION

OUTPUT

MAIN

OUTPUT

OUT0_SEL

SDI_OUT2_SEL

INPUT

IN0±

SDI_OUT1±

Single cable driver

Dual cable drivers

SDI_OUT2±

OUT0±

Single cable driver with host-side loop-back enabled

Dual cable drivers with host-side loop-back enabled

7.3.3 Input Signal Detect

IN0 has a signal detect circuit to monitor the presence or absence of an input signal. When the input signal

amplitude for the selected input exceeds the signal detect assert threshold, the LMH1228 operates in normal

operation mode.

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In the absence of an input signal, the LMH1228 automatically goes into Power Save Mode to conserve power

dissipation. When a valid signal is detected, the LMH1228 automatically exits Power Save Mode and returns to

the normal operation mode. If the ENABLE pin is pulled low, the LMH1228 is forced into Power-Down Mode. In

Power Save Mode, both the signal detect circuit and the serial interface remain active. In Power-Down Mode,

only the serial interface remains active.

Users can monitor the status of the signal detect through register programming. This can be done either by

configuring the LOCK_N pin to output the SD_N status or by monitoring the signal detect status register.

Table 3. Input Signal Detect Modes of Operation

ENABLE

SIGNAL INPUT

OPERATING MODE

Normal operation

100-Ω signal input at IN0±

Signal Detector at IN0±

Serial interface active

Power Save Mode

No signal at IN0±

Signal Detector at IN0±

Serial interface active

Power-Down Mode

Forced device power down

Serial interface active

Input signal ignored

7.3.4 Continuous Time Linear Equalizer (CTLE)

The LMH1228 has a continuous time linear equalizer (CTLE) block for IN0. The CTLE compensates for

frequency-dependent loss due to the transmission media prior to the device input. The CTLE accomplishes this

by applying variable gain to the input signal, thereby boosting higher frequencies more than lower frequencies.

The CTLE block extends the signal bandwidth, restores the signal amplitude, and reduces ISI caused by the

transmission medium.

IN0 has an on-chip 100-Ω termination and is designed for AC coupling, requiring a 4.7-μF, AC-coupling capacitor

for minimizing base-line wander. The PCB equalizer can compensate up to 20 inches of board trace at data rates

up to 11.88 Gbps. There are two adapt modes for IN0: AM0 manual mode and AM1 adaptive mode. In AM0

manual mode, fixed EQ boost settings are applied through user-programmable control. In AM1 adaptive mode,

state machines automatically find the optimal EQ boost from a set of 16 predetermined settings defined in

Registers 0x40-0x4F.

The HOST_EQ0 pin determines the IN0 adapt mode and EQ boost level. For normal operation, HOST_EQ0 = F

is recommended. HOST_EQ0 pin logic settings are shown in Table 4. These HOST_EQ0 pin settings can be

overridden by register control. For more information, refer to the LMH1228 and LMH1208 Programming Guide

(SNAU206).

Table 4. HOST_EQ0 Pin EQ Settings

RECOMMENDED BOARD

HOST_EQ0⁽¹⁾IN0± EQ BOOST

TRACE IN0±⁽²⁾

All Rates: AM0 Manual Mode, EQ=0x00

< 1 inch

Normal Operation

12G to 3G Rates: AM1 Adaptive Mode

1.5G, 270M Rates: AM0 Manual Mode, EQ= 0x00

0-20 inches

All Rates: AM0 Manual Mode, EQ=0x80

All Rates: AM0 Manual Mode, EQ=0x90

10-15 inches

20 inches

(1) The HOST_EQ0 pin is also used to set OUT0 VOD and de-emphasis values. See Host-Side 100-Ω

Output Driver (OUT0±) for more information.

(2) Recommended board trace at 11.88 Gbps.

7.3.5 Clock and Data (CDR) Recovery

After the input signal passes through the CTLE, the equalized data is fed into the clock and data recovery (CDR)

block. Using an internal PLL, the CDR locks to the incoming equalized data and recovers a clean internal clock

to re-sample the equalized data. The LMH1228 CDR is able to tolerate high input jitter, tracking low-frequency

input jitter below the PLL bandwidth while reducing high-frequency input jitter above the PLL bandwidth. The

supported data rates are listed in Table 5.

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Table 5. Supported Data Rates

INPUT

DATA RATE

RECLOCKER

Enable

11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, 270 Mbps⁽¹⁾

IN0±

125 Mbps

Bypass

(1) The LMH1228 supports divide-by-1.001 lock rates for 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, and 1.485

Gbps.

7.3.6 Internal Eye Opening Monitor (EOM)

The LMH1228 has an on-chip eye opening monitor (EOM) that can be used to analyze, monitor, and diagnose

the post-equalized waveform, just prior to the CDR reclocker. The EOM is operational for 2.97 Gbps and higher

data rates.

The EOM monitors the post-equalized waveform in a time window that spans one unit interval and a configurable

voltage range that spans up to ±400 mV. The time window and voltage range are divided into 64 steps, so the

result of the eye capture is a 64 × 64 matrix of hits, where each point represents a specific voltage and phase

offset relative to the main data sampler. The number of hits registered at each point needs to be taken in context

with the total number of bits observed at that voltage and phase offset to determine the corresponding probability

for that point.

The resulting 64 × 64 matrix produced by the EOM can be processed by software and visualized in a number of

ways. Two common ways to visualize this data are shown in Figure 10 and Figure 11. These diagrams depict

examples of eye monitor plots implemented by software. The first plot is an example using the EOM data to plot

a basic eye using ASCII characters, which can be useful for diagnostic software. The second plot shows the first

derivative of the EOM data, revealing the density of hits and the actual waveforms and crossings that comprise

the eye.

Figure 10. Internal Input Eye Monitor Plot

Figure 11. Internal Eye Monitor Hit Density Plot

A common measurement performed by the EOM is the horizontal and vertical eye opening. The horizontal eye

opening (HEO) represents the width of the post-equalized eye at 0-V differential amplitude, measured in unit

intervals or picoseconds (ps). The vertical eye opening (VEO) represents the height of the post-equalized eye,

measured midway between the mean zero crossing of the eye. This position in time approximates the CDR

sampling phase. HEO and VEO measurements can be read back through register control.

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7.3.7 Output Function Control

The LMH1228 output function control for data routed to outputs SDI_OUT1, SDI_OUT2, and OUT0 is configured

by the OUT_CTRL pin. The OUT_CTRL pin determines whether to bypass the reclocker. In normal operation

(OUT_CTRL = F), the reclocker is enabled.

OUT_CTRL pin logic settings are shown in Table 6. These settings can be overridden through register control by

applying the appropriate override bit values. For more information, refer to the LMH1228 and LMH1208

Programming Guide (SNAU206).

Table 6. OUT_CTRL Settings for Bypass Modes⁽¹⁾

IN0± PCB

EQUALIZER

OUT_CTRL

RECLOCKER SUMMARY

Normal operation

H, F

Enable

Bypass

Input IN0 equalizer enabled

Reclocker enabled

Input IN0 equalizer enabled in AM0 manual mode.

IN0 EQ settings configurable by HOST_EQ0 pin.

Reclocker bypassed

R, L

Enable

(1) Regardless of OUT_CTRL pin setting, IN0 CTLE is always enabled.

7.3.8 Output Driver Control

7.3.8.1 Line-Side Output Cable Driver (SDI_OUT1+, SDI_OUT2+)

The LMH1228 has two output cable driver (CD) blocks, one for SDI_OUT1 and another for SDI_OUT2. These

SDI outputs are designed to drive 75-Ω single-ended coaxial cables at data rates up to 11.88 Gbps. Both

SDI_OUT1 and SDI_OUT2 feature an integrated 75-Ω termination and return loss compensation network for

meeting stringent SMPTE return loss requirements (see Figure 8). The cable drivers are designed for AC

coupling, requiring a 4.7-μF, AC-coupling capacitor for minimizing base-line wander due to the rare-occurring

pathological bit pattern.

7.3.8.1.1 Output Amplitude (VOD)

SDI_OUT1 and SDI_OUT2 are designed for transmission across 75-Ω single-ended impedance. The nominal

SDI cable driver output amplitude (VOD) is 800 mVp-p single-ended. In the presence of long output cable lengths

or crosstalk, the SDI_VOD pin can be used to optimize the cable driver output with respect to the nominal

amplitude. Table 7 details VOD settings that can be applied to both SDI_OUT1 and SDI_OUT2. The SDI_VOD

pin can be overridden through register control. In addition, the nominal VOD amplitude can be changed by

Table 7. SDI_VOD Settings for Line-Side Output Amplitude

SDI_VOD

DESCRIPTION

about +5% of nominal

800 mVp-p (nominal)

about +10% of nominal

about –5% of nominal

7.3.8.1.2 Output Pre-Emphasis

In addition to SDI cable driver VOD control, the LMH1228 can add pre-emphasis on the cable driver output to

improve output signal integrity when the reclocker recovers a UHD (12G, 6G) or HD (3G, 1.5G) input data rate.

By default, the LMH1228 automatically enables pre-emphasis on SDI_OUT1 and SDI_OUT2 at UHD (12G, 6G)

rates, and pre-emphasis is disabled for all other data rates. When enabled, the amount of pre-emphasis applied

to the cable driver outputs is determined by register control. If the reclocker is bypassed or if the user desires to

disable automatic pre-emphasis, pre-emphasis can be enabled manually through register control. For more

information, refer to the LMH1228 and LMH1208 Programming Guide (SNAU206).

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7.3.8.1.3 Output Slew Rate

SMPTE specifications require different output driver rise and fall times depending on the operating data rate. To

meet these requirements, the output edge rate of SDI_OUT1 and SDI_OUT2 is automatically programmed

according to the signal recovered by the reclocker. Typical edge rates at the cable driver output are shown in

Table 8.

Table 8. SDI_OUT1 and SDI_OUT2 Output Edge Rate

CABLE DRIVER OUTPUT

DETECTED DATA RATE

EDGE RATE (TYP)

11.88 Gbps

5.94 Gbps

2.97 Gbps

1.485 Gbps

270 Mbps

34 ps

36 ps

59 ps

60 ps

550 ps

If the reclocker is bypassed, users must program the desired edge rate manually through register control. For

more information, refer to the LMH1228 and LMH1208 Programming Guide (SNAU206).

7.3.8.1.4 Output Polarity Inversion

Polarity inversion is supported on both SDI_OUT1 and SDI_OUT2 outputs through register control.

7.3.8.2 Host-Side 100-Ω Output Driver (OUT0±)

OUT0 is a 100-Ω driver output. OUT0 serves as a host-side loop-back output. OUT0 also supports polarity

inversion.

The driver offers users the capability to select higher output amplitude and de-emphasis levels for longer board

trace that connects the drivers to their downstream receivers. Driver de-emphasis provides transmitter

equalization to reduce the ISI caused by the board trace.

The VOD and de-emphasis levels for OUT0 are set by default to 570 mVp-p and –0.4 dB, and these values are

recommended for driving 1-2 inches of board trace from OUT0± at 11.88 Gbps. These settings can be changed

through register control if desired. When these parameters are controlled by registers, the VOD and de-emphasis

levels can be programmed independently. For more information, refer to the LMH1228 and LMH1208

Programming Guide (SNAU206).

7.3.9 Status Indicators and Interrupts

The LOCK_N pin is a 3.3-V tolerant, active-low, open-drain output. An external resistor to the logic supply is

required. The LOCK_N pin can be configured to indicate reclocker lock, input signal detect, or an interrupt event.

7.3.9.1 LOCK_N (Lock Indicator)

By default, LOCK_N is the reclocker lock indicator, and this pin asserts low when the LMH1228 achieves lock to

a valid SMPTE data rate. The LOCK_N pin functionality can also be configured through register control to

indicate SD_N (signal detect) or INT_N (interrupt) events. For more information about how to reconfigure the

LOCK_N pin functionality, refer to the LMH1228 and LMH1208 Programming Guide (SNAU206).

7.3.9.2 SD_N (Signal Detect)

The LOCK_N pin can be reconfigured through register control to indicate a SD_N (signal detect) event. When

configured as a SD_N output, the pin asserts low at the end of adaptation after a valid signal is detected by the

IN0 signal detect circuit. For more information about how to configure the LOCK_N pin for SD_N functionality,

refer to the LMH1228 and LMH1208 Programming Guide (SNAU206).

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7.3.9.3 INT_N (Interrupt)

The LOCK_N pin can be configured to indicate an INT_N (interrupt) event. When configured as an INT_N output,

the pin asserts low when an interrupt occurs, according to the programmed interrupt masks. Five separate masks

can be programmed through register control as interrupt sources:

•

If there is a loss of signal (LOS) event on IN0 (2 separate masks).

If HEO or VEO falls below a certain threshold after CDR is locked (1 mask).

If a CDR Lock event has occurred (2 separate masks).

INT_N is a sticky bit, meaning that it will flag after an interrupt occurs and will not clear until read-back. Once the

Interrupt Status Register is read, the INT_N pin will assert high again. For more information about how to

configure the LOCK_N pin for INT_N functionality, refer to the LMH1228 and LMH1208 Programming Guide

(SNAU206).

7.4 Device Functional Modes

The LMH1228 operates in one of two modes: System Management Bus (SMBus) or Serial Peripheral Interface

(SPI) mode. To determine the mode of operation, the proper setting must be applied to the MODE_SEL pin at

power up, as detailed in Table 9.

Table 9. MODE_SEL Pin Settings

LEVEL

DESCRIPTION

Reserved for factory testing – do not use

Selects SPI Interface for register access

Reserved for factory testing – do not use

Selects SMBus Interface for register access

7.4.1 System Management Bus (SMBus) Mode

The SMBus interface can also be used to control the device. If MODE_SEL = Low (1 kΩ to VSS), Pins 13 and 29

are configured as SDA and SCL. Pins 11 and 28 are address straps ADDR0 and ADDR1 during power up. The

maximum operating speed supported on the SMBUS pins is 400 kHz.

Table 10. SMBus Device Slave Addresses⁽¹⁾

ADDR0

ADDR1

7-BIT SLAVE

8-BIT WRITE

(LEVEL)

ADDRESS [HEX]

COMMAND [HEX]

(1) The 8-bit write command consists of the 7-bit slave address (Bits 7:1) with 0 appended to the LSB to

indicate an SMBus write. For example, if the 7-bit slave address is 0x2D (010 1101'b), the 8-bit write

command is 0x5A (0101 1010'b).

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7.4.1.1 SMBus Read and Write Transaction

SMBus is a two-wire serial interface through which various system component chips can communicate with the

master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of

SCL and SDA signals. SCL is a clock output from the master to all of the slave devices on the bus. SDA is a

bidirectional data signal between the master and slave devices. The LMH1228 SMBus SCL and SDA signals are

open-drain and require external pullup resistors.

Start and Stop:

The master generates Start and Stop patterns at the beginning and end of each transaction.

•

Start: High-to-low transition (falling edge) of SDA while SCL is high.

SDA

SCL

Start

Condition

Stop

Condition

Figure 12. Start and Stop Conditions

The master generates nine clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle.

The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is recorded when the device

pulls SDA low, while a NACK is recorded if the line remains high.

ACK Signal

from Receiver

SDA

MSB

SCL

3 - 6

3 - 8

ACK

Start

Condition

Stop

Condition

Byte Complete

Interrupt Within

Receiver

Clock Line Held Low

by Receiver While

Interrupt Serviced

Figure 13. Acknowledge (ACK)

7.4.1.1.1 SMBus Write Operation Format

Writing data to a slave device consists of three parts, as illustrated in Figure 14:

1. The master begins with a start condition followed by the slave device address with the R/W bit set to 0’b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the 8-bit data is written, followed by a stop condition.

Device

Address

Word Address

Data

SDA

Line

Figure 14. SMBus Write Operation

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7.4.1.1.2 SMBus Read Operation Format

SMBus read operation consists of four parts, as illustrated in Figure 15:

1. The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.

2. After an ACK from the slave device, the 8-bit register word address is written.

3. After an ACK from the slave device, the master initiates a restart condition, followed by the slave address

with the R/W bit set to 1'b.

4. After an ACK from the slave device, the 8-bit data is read-back. The last ACK is high if there are no more

bytes to read, and the last read is followed by a stop condition.

Device

Address

Device

Address

Word Address (n)

Data (n)

SDA

Line

Set word address in the device

that will be read following restart

and repeat of device address

Figure 15. SMBus Read Operation

7.4.2 Serial Peripheral Interface (SPI) Mode

If MODE_SEL = F or H, the LMH1228 is in SPI mode. In SPI mode, the following pins are used for SPI bus

communication:

•

MOSI (Pin 13): Master Output Slave Input

MISO (Pin 28): Master Input Slave Output

SS_N (Pin 11): Slave Select (Active Low)

SCK (Pin 29): Serial Clock (Input to the LMH1228 Slave Device)

7.4.2.1 SPI Read and Write Transactions

Each SPI transaction to a single device is 17 bits long and is framed by SS_N when asserted low. The MOSI

input is ignored, and the MISO output is floated whenever SS_N is deasserted (high).

The bits are shifted in left-to-right. The first bit is R/W, which is 1'b for read and 0'b for write. Bits A7-A0 are the

8-bit register address, and bits D7-D0 are the 8-bit read or write data. The previous SPI command, address, and

data are shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI

transactions, the MISO output signal is enabled asynchronously when SS_N asserts low. The contents of a

single MOSI or MISO transaction frame are shown in Figure 16.

Figure 16. 17-Bit Single SPI Transaction Frame

R/W

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7.4.2.2 SPI Write Transaction Format

For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on

the rising edge of SS_N. The SPI transaction always starts on the rising edge of the clock.

The signal timing for a SPI Write transaction is shown in Figure 17. The prime values on MISO (for example, A7')

reflect the contents of the shift register from the previous SPI transaction and are listed as don’t-care for the

current transaction.

t_SSOF

t_SSH

SS_N

SCK

t_PL

t_SSSU

t_PH

t_H

t_SU

HiZ

MOSI

t_ODZ

HiZ

MISO

R/W

A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

Figure 17. Signal Timing for a SPI Write Transaction

7.4.2.3 SPI Read Transaction Format

A SPI read transaction is 34 bits per device and consists of two 17-bit frames. The first 17-bit read transaction

frame shifts in the address to be read, followed by a dummy transaction second frame to shift out 17-bit read

data. The R/W bit is 1'b for the read transaction, as shown in Figure 18.

The first 17 bits from the read transaction specifies 1-bit of R/W and 8-bits of address A7-A0 in the first 8 bits.

The eight 1’s following the address are ignored. The second dummy transaction acts like a read operation on

address 0xFF and needs to be ignored. However, the transaction is necessary to shift out the read data D7-D0 in

the last 8 bits of the MISO output. As with the SPI Write, the prime values on MISO during the first 16 clocks are

listed as don’t care for this portion of the transaction. The values shifted out on MISO during the last 17 clocks

reflect the read address and 8-bit read data for the current transaction.

t_SSOF

SS_N

(host)

t_SSOF

t_SSSU

t_PH

t_PL

t_SSH

SCK

(host)

t_H

—8X1“

—17X1“

t_SU

MOSI

(host)

A7 A6 A5 A4 A3 A2 A1 A0

t_OD

t_ODZ

t_OZD

MISO

(device)

A7' A6' A5' A4' A3' A2' A1' A0' D7' D6' D5' D4' D3' D2' D1' D0'

Don‘t Care

Figure 18. Signal Timing for a SPI Read Transaction

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7.4.2.4 SPI Daisy Chain

The LMH1228 supports SPI daisy-chaining among multiple devices, as shown in Figure 19.

MISO

Device 1

Device 2

Device 3

Device N

Host

LMH1228

. . .

MOSI

MISO

MOSI

MISO

MOSI

MISO

MOSI

MISO

SCK

Figure 19. Daisy-Chain Configuration

Each LMH1228 device is directly connected to the SCK and SS_N pins of the host. The first LMH1228 device in

the chain is connected to the host’s MOSI pin, and the last device in the chain is connected to the host’s MISO

pin. The MOSI pin of each intermediate LMH1228 device in the chain is connected to the MISO pin of the

previous LMH1228 device, thereby creating a serial shift register. In a daisy-chain configuration of N × LMH1228

devices, the host conceptually sees a shift register of length 17 × N for a basic SPI transaction, during which

SS_N is asserted low for 17 × N clock cycles.

7.5 Register Maps

The LMH1228 register map is divided into three register pages. These register pages are used to control

different aspects of the LMH1228 functionality. A brief summary of the pages is shown below:

1. Share Register Page: This page corresponds to global parameters, such as LMH1228 device ID and

LOCK_N status configuration. This is the default page at start-up. Access this page by setting Reg 0xFF[2:0]

= 000’b.

2. CTLE/CDR Register Page: This page corresponds to IN0 PCB CTLE, output mux settings, CDR settings,

and output interrupt overrides. Access this page by setting Reg 0xFF[2:0] = 100’b.

3. Driver Register Page: This page corresponds to OUT0, SDI_OUT1, and SDI_OUT2 driver output settings.

Access this page by setting Reg 0xFF[2:0] = 101’b.

For the complete register map, typical device configurations, and proper register reset sequencing, refer to the

LMH1228 and LMH1208 Programming Guide (SNAU206).

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 SMPTE Requirements and Specifications

SMPTE specifies several key requirements for the Serial Digital Interface to transport digital video over coaxial

cables. Such requirements include return loss, AC coupling, and data rate dependency with rise and fall times.

1. Return Loss: This specification details how closely the port resembles 75-Ω impedance across a specified

frequency band. The LMH1228 features a built-in 75-Ω return-loss network on SDI_OUT1 and SDI_OUT2 to

minimize parasitics and improve overall signal integrity.

2. AC Coupling: AC-coupling capacitors are required for transporting uncompressed serial data streams with

heavy low-frequency content. The use of 4.7-μF, AC-coupling capacitors is recommended to avoid low-

frequency DC wander.

3. Rise/Fall Time: Output 75-Ω signals are required to meet certain rise and fall timing depending on the data

rate. This improves the eye opening observed for the receiving device. The LMH1228 SDI_OUT1 and

SDI_OUT2 cable drivers feature automatic edge rate adjustment to meet SMPTE rise and fall time

requirements.

TI recommends placing the LMH1228 as close as possible to the 75-Ω BNC ports to meet SMPTE specifications.

8.1.2 Low-Power Optimization

The LMH1228 IN0 CTLE operates in either AM1 Adaptive Mode or AM0 Manual Mode. When operating in AM1,

the LMH1228 uses HEO/VEO Lock Monitoring as a key parameter to achieve lock. HEO/VEO Lock Monitoring

determines the CTLE boost setting that produces the best horizontal and vertical eye opening after the CTLE.

Once AM1 adaptation is complete and the LMH1228 asserts CDR lock at the optimal IN0 CTLE setting,

HEO/VEO Lock Monitoring is no longer required to maintain lock. Therefore, HEO/VEO Lock Monitoring can be

disabled by setting CTLE/CDR Reg 0x3E[7] = 0'b after lock is declared. Disabling HEO/VEO Lock Monitoring

optimizes power dissipation, reducing the overall power by approximately 25 mW.

When operating in AM0, the LMH1228 does not use HEO/VEO Lock Monitoring, because the IN0 CTLE setting

is set manually by the user. In AM0, HEO/VEO Lock Monitoring can be disabled at any time.

8.1.3 Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications

The LMH1228 default loop bandwidth setting is optimized for a wide variety of applications. For applications

using the Intel Arria 10 FPGA, further optimization of the loop bandwidth may be required. Refer to the LMH1228

and LMH1208 Programming Guide (SNAU206) for detailed register settings when using the LMH1228 with an

Arria 10 FPGA.

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8.2 Typical Applications

The LMH1228 is a dual cable driver with integrated reclocker that supports SDI data rates up to 11.88 Gbps.

Figure 20 shows a typical application circuit for the LMH1228.

Specific examples of typical applications for the LMH1228 as a dual cable driver and distribution amplifier are

detailed in the following subsections.

2.5 V

Place 0.1-µF Capacitors

close to each supply pin

4.7 µF

100-ꢀ Coupled Trace

VDD_CDR

SDI_OUT1+

VIN

VDD_LDO

(1.8 V) OUT0+

Line-Side Output

RX+

RX-

75-ꢀ BNC

SDI_OUT1-

SS_N

OUT0-

4.7 µF

RSV1

RSV2

RSV3

RSV4

RSV5

VIN

75 Ω

SCK

1 kꢀ

Host-Side FPGA/

Video Processor

MOSI

VIN

MISO

LMH1228

RSV6**

VSS

200 Ω

MODE_SEL

Level F (SPI Mode)

LED

LOCK_N

100-ꢀ Coupled Trace

Line-Side Output

SDI_OUT2+

SDI_OUT2-

TX+

TX-

IN0+

IN0-

75-ꢀ BNC

4.7 µF

75 Ω

VIN

Optional pullup or pulldown

resistors for 4-Level Strap

Configuration Pins

Optional pullup or pulldown

resistors for 2-Level Strap

Configuration Pins

1 kꢀ

Level H = 1 kΩ to VIN

Level F = No Connect

Level R = 20 kΩ to VSS

Level L = 1 kΩ to VSS

Level H = 1 kΩ to VIN

Level L = 1 kΩ to VSS

1 kꢀ

20 kꢀ

*Internally pulled high

**Internally pulled low

Figure 20. LMH1228 Typical Application Circuit

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Typical Applications (continued)

8.2.1 Dual Cable Driver

The LMH1228 can be configured as a dual cable driver to route the same SDI output signal to multiple receivers.

In this configuration, the LMH1228 adaptively equalizes 100-Ω SDI input data at IN0 and uses the dual cable

drivers at SDI_OUT1 and SDI_OUT2 to drive out the SDI signal.

Figure 21 shows a typical application of an LMH1228 as a dual cable driver output. In this example, the

LMH1219 Cable EQ with Integrated Reclocker provides an SDI input to the SDI FPGA. The FPGA then sends

post-processed SDI data to the IN0 of the LMH1228, which drives the data on cable driver outputs SDI_OUT1

and SDI_OUT2.

IN0

OUT0

75-Ω SDI

Input

LMH1219

EQ +

Reclocker

SerDes Rx

SDI FPGA

SDI_OUT1

SDI_OUT2

IN0

75-Ω SDI

Output 1

SerDes Tx

LMH1228

Dual Cable

Driver

75-Ω SDI

Output 2

Figure 21. LMH1228 Dual Cable Driver Application

8.2.1.1 Design Requirements

For general LMH1228 design requirements, reference the guidelines in Table 11.

For dual cable driver application-specific requirements, reference the guidelines in Table 12.

Table 11. LMH1228 General Design Requirements

DESIGN PARAMETER

REQUIREMENTS

SDI_OUT1+, SDI_OUT2+ AC-coupling capacitors 4.7-μF capacitors recommended

SDI_OUT1–, SDI_OUT2– AC-coupling capacitors 4.7-μF capacitors recommended, AC terminated with 75 Ω to VSS.

IN0± and OUT0± AC-coupling capacitors

Input and Output Terminations

4.7-μF capacitors recommended

Input and output terminations provided internally. Do not add external terminations.

10-μF and 1-μF bulk capacitors; place close to each device.

0.1-μF capacitor; place close to each supply pin.

DC power supply decoupling capacitors

VDD_LDO decoupling capacitors

MODE_SEL Pin

1-μF and 0.1-μF capacitors; place as close as possible to the device VDD_LDO pin.

SPI: Leave MODE_SEL unconnected (Level F)

SMBus: Connect 1 kΩ to VSS (Level L)

11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, or Divide-by-1.001 sub-rates and 270

Mbps.

Input Reclocked Data Rate

For all other input data rates, the reclocker is automatically bypassed.

Table 12. LMH1228 Dual Cable Driver Requirements

DESIGN PARAMETER

REQUIREMENTS

OUT0_SEL Pin

1 kΩ to VIN (Level H) to disable the OUT0 loop-back output

1 kΩ to VSS (Level L) to enable SDI_OUT2 as secondary cable output

SDI_OUT2_SEL Pin

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8.2.1.2 Detailed Design Procedure

The design procedure for dual cable driver applications is as follows:

1. Select a power supply that meets the DC and AC requirements in Recommended Operating Conditions.

2. Choose a small 0402 surface mount ceramic capacitor for AC-coupling capacitors to maintain characteristic

impedance.

3. Choose a high-quality, 75-Ω BNC connector that is capable of supporting 11.88-Gbps applications. Consult a

BNC supplier regarding insertion loss, impedance specifications, and recommended footprint for meeting

SMPTE return loss.

4. Follow detailed high-speed layout recommendations provided in Layout Guidelines to ensure optimal signal

quality when interconnecting 75-Ω and 100-Ω signals to the LMH1228.

5. Determine whether SPI or SMBus communication is necessary. If the LMH1228 must be programmed with

settings other than what is offered by pin control, users must use SPI or SMBus Mode for additional

programming.

6. Configure OUT0_SEL and SDI_OUT2_SEL pins according to the desired default use case.

7. Tune the SDI_VOD output amplitude control pin for optimal signal quality depending on the cable length

attached at SDI_OUT1+ and SDI_OUT2+. Use register control for more tuning options if necessary.

8.2.1.3 Application Curves

The LMH1228 performance on SDI_OUT1+ and SDI_OUT2+ was measured with the test setups shown in

Figure 22 and Figure 23.

LMH1228

Pattern

Generator

Differential 100 Ω

IN0

Oscilloscope

SDI_OUT1+

V_OD= 800 mVp-p,

PRBS10

FR4 Channel

Figure 22. Test Setup for LMH1228 to SDI_OUT1+

LMH1228

SDI_OUT2+

Pattern

Generator

Differential 100 Ω

FR4 Channel

IN0

Oscilloscope

V_OD= 800 mVp-p,

PRBS10

Figure 23. Test Setup for LMH1228 to SDI_OUT2+

The eye diagrams in this subsection show how the LMH1228 improves overall signal integrity in the data path for

100-Ω differential FR4 PCB trace at IN0±.

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Measured at SDI_OUT1+

Measured at SDI_OUT2+

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 24. 11.88 Gbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 25. 11.88 Gbps, TL = 20" FR4, Reclocked

Measured at SDI_OUT1+

Measured at SDI_OUT2+

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 26. 5.94 Gbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 27. 5.94 Gbps, TL = 20" FR4, Reclocked

Measured at SDI_OUT1+

Measured at SDI_OUT2+

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 28. 2.97 Gbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 29. 2.97 Gbps, TL = 20" FR4, Reclocked

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Measured at SDI_OUT1+

Measured at SDI_OUT2+

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 30. 1.485 Gbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 31. 1.485 Gbps, TL = 20" FR4, Reclocked

Measured at SDI_OUT1+

Measured at SDI_OUT2+

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 32. 270 Mbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 33. 270 Mbps, TL = 20" FR4, Reclocked

8.2.2 Distribution Amplifier

The LMH1228 can be configured as a distribution amplifier to distribute the same SDI input signal to multiple

cable driver outputs. In this configuration, the LMH1228 uses the dual cable drivers at SDI_OUT1 and

SDI_OUT2 to drive out the SDI signal seen at IN0. Meanwhile, the loop-back output on OUT0 is daisy-chained

as a duplicate input to IN0 of the next LMH1228.

Figure 34 shows a typical application where four LMH1228s are used in combination with an LMH1219 Cable EQ

with Integrated Reclocker to form a 1:8 distribution amplifier network.

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IN0

OUT0 IN0

OUT0

SDI_OUT1

SDI_OUT2

75-Ω SDI

Output 1

75-Ω SDI

Input

LMH1219

EQ +

Reclocker

LMH1228

Dual Cable

Driver

75-Ω SDI

Output 2

IN0

SDI_OUT1

SDI_OUT2

75-Ω SDI

Output 3

LMH1228

Dual Cable

Driver

OUT0

75-Ω SDI

Output 4

IN0

SDI_OUT1

SDI_OUT2

75-Ω SDI

Output 5

LMH1228

Dual Cable

Driver

OUT0

75-Ω SDI

Output 6

IN0

SDI_OUT1

SDI_OUT2

75-Ω SDI

Output 7

LMH1228

Dual Cable

Driver

75-Ω SDI

Output 8

Figure 34. LMH1228 Distribution Amplifier Application

8.2.2.1 Design Requirements

See Table 11 in Dual Cable Driver Design Requirements for general LMH1228 design requirements.

For distribution amplifier application-specific requirements, reference the guidelines in Table 13.

Table 13. LMH1228 Distribution Amplifier Requirements

DESIGN PARAMETER

REQUIREMENTS

1 kΩ to VSS (Level L) to enable OUT0 as a loop-back output to the next LMH1228

IN0 input

OUT0_SEL Pin

SDI_OUT2_SEL Pin

1 kΩ to VSS (Level L) to enable SDI_OUT2 as secondary cable output

8.2.2.2 Detailed Design Procedure

See Dual Cable Driver Detailed Design Procedure and follow Steps 1 through 5. Refer to the additional steps

below for distribution amplifier applications.

1. Configure OUT0_SEL and SDI_OUT2_SEL pins according to the desired default use case.

2. Tune the output VOD and de-emphasis level for the 100-Ω driver prior to each LMH1228 IN0±. In the

distribution amplifier example shown in Figure 34, this step applies to the LMH1219 OUT0± driver and all

LMH1228 OUT0± drivers that are daisy-chained to a subsequent LMH1228 IN0±. If OUT0± is located within

1-2 inches of IN0±, then use a lower VOD setting and no de-emphasis. If the OUT0± is located many inches

away from IN0±, some VOD gain and de-emphasis may be required at OUT0± for the IN0 CTLE to equalize

optimally. Use register control for more tuning options if necessary.

3. Tune the SDI_VOD output amplitude control pin for optimal signal quality depending on the cable length

attached at SDI_OUT1+ and SDI_OUT2+ for each LMH1228. Use register control for more tuning options if

necessary.

8.2.2.3 Application Curves

The LMH1228 performance on OUT0± was measured with the test setup shown in Figure 22.

LMH1228

Pattern

Generator

Differential 100 Ω

IN0

Oscilloscope

OUT0

V_OD= 800 mVp-p,

PRBS10

FR4 Channel

Figure 35. Test Setup for LMH1228 to OUT0±

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The eye diagrams in this subsection show how the LMH1228 improves overall signal integrity in the data path for

100-Ω differential FR4 PCB trace at IN0±.

Measured at OUT0±

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 36. 11.88 Gbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 37. 5.94 Gbps, TL = 20" FR4, Reclocked

Measured at OUT0±

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 38. 2.97 Gbps, TL = 20" FR4, Reclocked

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 39. 1.485 Gbps, TL = 20" FR4, Reclocked

Measured at OUT0±

HOST_EQ0 = F, SDI_OUT2_SEL = L, OUT_CTRL = F

Figure 40. 270 Mbps, TL = 20" FR4, Reclocked

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9 Power Supply Recommendations

The LMH1228 requires decoupling capacitors to ensure a stable power supply. For power supply decoupling,

0.1-μF surface-mount ceramic capacitors must be placed close to each VDD_CDR, VDD_LDO, and VIN supply

pin to VSS. Larger bulk capacitors (for example, 10 μF and 1 μF) are recommended for VDD_CDR and VIN.

2.5 V

10 µF

1 µF

0.1 µF

VDD_CDR

VIN

VDD_LDO

(1.8 V)

VSS

LMH1228

1 µF

0.1 µF

Figure 41. Recommended Power Supply Decoupling

Good supply bypassing requires low inductance capacitors. This can be achieved through an array of multiple

small body size surface-mount bypass capacitors to keep low supply impedance. Better results can be achieved

through the use of a buried capacitor formed by a VDD and VSS plane separated by 2 to 4 mil dielectric in a

printed-circuit board.

10 Layout

10.1 Layout Guidelines

The following guidelines are recommended to optimize the board layout for the LMH1228.

10.1.1 Board Stack-Up and Ground References

•

Choose a suitable board stack-up that supports 75-Ω single-ended trace and 100-Ω differential trace routing

on the top layer of the board. This is typically done with a Layer-2 ground plane reference for the 100-Ω

differential traces and a Layer-3 ground plane reference for the 75-Ω single-end traces.

•

Maintain a distance of at least 5 times the trace width between signal trace and ground reference if they are

on the same layer. This prevents unwanted changes in the characteristic impedance.

Maintain a consistent ground plane reference for each high-speed trace from source to end-point. Ground

reference discontinuities lead to characteristic impedance mismatch.

10.1.2 High-Speed PCB Trace Routing and Coupling

Observe the following general high-speed recommendations for high-speed trace routing:

•

For differential pairs, maintain a uniform width and gap for each differential pair where possible. When traces

must diverge (for example, due to AC-coupling capacitors), ensure that the traces branch out or merge

uniformly.

•

To prevent reflections due to trace routing, ensure that trace bends are at most 45°. Right angle bends should

be implemented with at least two 45° corners. Radial bends are ideal.

Avoid using signal vias. If signal vias must be used, a return path (GND) via must be placed near the signal

via to provide a consistent ground reference and minimize impedance discontinuities.

Avoid via stubs by back-drilling as necessary.

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Layout Guidelines (continued)

10.1.2.1 SDI_OUT1± and SDI_OUT2±:

•

Use an uncoupled trace with 75-Ω single-ended impedance for signal routing to SDI_OUT1± and

SDI_OUT2±.

•

The trace width is typically 8 to 10 mils with reference to a Layer-3 ground plane.

10.1.2.2 IN0± and OUT0±:

•

Use coupled traces with 100-Ω differential impedance for signal routing to IN0± and OUT0±.

The trace width is typically 5 to 8 mils with reference to a Layer-2 ground plane.

10.1.3 Anti-Pads

•

Place anti-pads (ground relief) on the power and ground planes directly under the 4.7-μF, AC-coupling

capacitor and IC landing pads to minimize parasitic capacitance. The size of the anti-pad and the number of

layers to use the anti-pad depend on the board stack-up and can be determined by a 3-dimension

electromagnetic simulation tool.

10.1.4 BNC Connector Layout and Routing

•

Use a well-designed BNC footprint to ensure the BNC's signal landing pad achieves 75-Ω characteristic

impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.

•

Keep trace length short between the BNC and SDI_OUT1±. The trace routing for SDI_OUT1+ and

SDI_OUT1– should be as symmetrical as possible, with approximately equal lengths and equal loading. The

same is true for SDI_OUT2+ and SDI_OUT2–.

10.1.5 Power Supply and Ground Connections

•

Connect each supply pin (VDD_CDR, VIN, VDD_LDO) directly to the power or ground planes with a short via.

The via is usually placed tangent to the supply pins' landing pads with the shortest trace possible.

•

Power supply decoupling capacitors should be a small physical size (0402 or smaller) and placed close to the

supply pins to minimize inductance. The capacitors are commonly placed on the bottom layer and share the

ground of the EP (Exposed Pad).

10.1.6 Footprint Recommendations

•

Stencil parameters for the EP (Exposed Pad) such as aperture area ratio and the fabrication process have a

significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is

highly recommended to improve board assembly yields. If the via and aperture openings are not carefully

monitored, the solder may flow unevenly through the EP. Stencil parameters for aperture opening and via

locations are shown in the RTV package drawing in 机械、封装和可订购信息.

•

The EP of the package must be connected to the ground plane through a 3 × 3 via array. These vias are

solder-masked to avoid solder flowing into the plated-through holes during the board manufacturing process.

Details about via dimensions are also shown in the RTV package drawing in 机械、封装和可订购信息.

More information on the WQFN style package is provided in WQFN/SON PCB Attachment Application Report

(SLUA271).

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

10.2 Layout Example

The example shown in Figure 42 demonstrates the LMH1228 layout guidelines highlighted in Layout Guidelines.

Larger bulk capacitors (10 µF, 1 µF)

for VIN and VDD_CDR can be

placed farther from IC.

BNC Footprint

Anti-pad

Zo = 75 ꢀ

W = 10 mils

Via to

VDD_LDO

Pour

4.7 µF

Place 0.1-µF decoupling caps on

Bottom Layer close to pins. Connect

to Pour and EP with vias.

Via to VIN

Pour

4.7 µF

100-ꢀ coupled

trace

4.7 µF

75 ꢀ

W = 8 mils

S = 10 mils

W = 8 mils

Solder

Paste

Mask

(Stencil)

4.7 µF

VSS Via to

GND

Via to

VDD_CDR

Pour

W = 8 mils

S = 10 mils

W = 8 mils

4.7 µF

75 ꢀ

(Exposed Pad)

Via Array on Bottom

Layer shared with VSS

pins and decoupling caps

where applicable

100-ꢀ coupled

trace

4.7 µF

W = 10 mils

> 5W

Zo = 75 ꢀ

Layer 3 GND Reference for

75-Ω Single-Ended Traces

Layer 2 GND Reference for

100-Ω Differential Traces

Note: All high speed signal traces are assumed to be on Layer 1 (Top Layer).

Figure 42. LMH1228 High-Speed Trace Layout Example

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

《QFN/SON PCB 连接应用报告》(SLUA271)

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 出口管制提示

接收方同意：如果美国或其他适用法律限制或禁止将通过本协议的披露方获得的任何产品或技术数据（其中包括软

件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制产品或此项技术的任

何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政府机构授权的情况下，接收

方不得在知情的情况下，以直接或间接的方式将其出口。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

12.1 Package Option Addendum

12.1.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

Lead/Ball

Finish⁽³⁾

(1)

(2)

(4)

Orderable Device

LMH1228RTVR

LMH1228RTVT

Status

Pins

Eco Plan

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking⁽⁵⁾⁽⁶⁾

Green (RoHS

& no Sb/Br)

Level-3-260C-168

ACTIVE

WQFN

RTV

1000

250

CU NIPDAU

L1228

Green (RoHS

& no Sb/Br)

Level-3-260C-168

WQFN

-40 to 85

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the

finish value exceeds the maximum column width.

space

(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(6) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

12.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

LMH1228RTVR

LMH1228RTVT

WQFN

RTV

1000

250

178.0

12.4

5.3

1.1

8.0

12.0

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

WQFN

Package Drawing Pins

SPQ

1000

250

Length (mm) Width (mm)

Height (mm)

35.0

LMH1228RTVR

LMH1228RTVT

RTV

210.0

185.0

WQFN

35.0

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

LMH1228

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

www.ti.com.cn

LMH1228

www.ti.com.cn

ZHCSKF4C –MARCH 2017–REVISED OCTOBER 2019

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMH1228RTVR

LMH1228RTVT

ACTIVE

WQFN

RTV

1000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 85

L1228

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMH1228RTVR [TI]

相关型号：

LMH1228RTVT

LMH1251

LMH1251

LMH1251MT

LMH1251MT

LMH1251MT-NOPB

LMH1251MT/NOPB

LMH1251MTX

LMH1251MTX

LMH1297

LMH1297RTVR

LMH1297RTVT