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LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

LMH1983 3G/HD/SD Video Clock Generator with Audio Clock

1 Features

3 Description

The LMH1983 is a highly-integrated programmable

1

•

Four PLLs for Simultaneous A/V Clock Generation

audio/video (A/V) clock generator intended for

broadcast and professional applications. It can

replace multiple PLLs and VCXOs used in

applications supporting SMPTE serial digital video

(SDI) and digital audio AES3/EBU standards. It offers

low-jitter reference clocks for any SDI transmitter to

meet stringent output jitter specifications without

additional clock cleaning circuits.

–

PLL1: 27 or 13.5 MHz

PLL2: 148.5 or 74.25 MHz

PLL3: 148.5/1.001 or 74.25/1.001 MHz

PLL4: 98.304 MHz / 2^X(X = 0 to 15)

•

3 x 2 Video Clock Crosspoint

Flexible PLL Bandwidth to Optimize Jitter

Performance and Lock Time

The LMH1983 features automatic input format

detection, simple programming of multiple A/V output

formats, genlock or digital free-run modes, and

override programmability of various automatic

functions. The recognized input formats include HVF

syncs for the major video standards, 27 MHz, 10

MHz, and 32/44.1/48/96 kHz audio word clocks.

•

Soft Resynchronization to New Reference

Digital Holdover or Free-run on Loss of Reference

Status Flags for Loss of Reference and Loss of

PLL Lock

•

3.3 V Single Supply Operation

I²C Interface with Address Select Pin (3 States)

The dual-stage PLL architecture integrates four PLLs

with three on-chip VCOs. The first stage (PLL1) uses

an external low-noise 27 MHz VCXO with narrow

loop bandwidth to provide a clean reference clock for

the next stage. The second stage (PLL2, 3, 4)

consists of three parallel VCO PLLs for simultaneous

generation of the major digital A/V clock fundamental

rates, including 148.5 MHz, 148.5/1.001 MHz, and

98.304 MHz (4 × 24.576 MHz). Each PLL can

generate a clock and a timing pulse to indicate top of

frame (TOF).

2 Applications

•

Triple Rate (3G/HD/SD) SDI SerDes

FPGA Reference Clock Generation/Cleaning

Audio Embed or De-embed

Video Cameras

Frame Synchronizers (Genlock, DARS)

A-D or D-A Conversion, Editing, Processing Cards

Keyers and Logo Inserters

Device Information⁽¹⁾

Format or Standards Converters

Video Displays and Projectors

PART NUMBER

PACKAGE

BODY SIZE (NOM)

LMH1983

WQFN (40)

6.00 mm × 6.00 mm

A/V Test and Measurement Equipment

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Block Diagram

LOOP

FILTER

27 MHz

VCXO

27 MHz (PLL1)

525i

Analog

ref. in

H sync

V sync

F sync

CLKout1

29.97 Hz (TOF1)

525i/29.97 SDI out

+ embedded audio

LMH1981

Sync

Separator

Hin

Vin

Fin

148.5 MHz (PLL2)

29.97 Hz (TOF2)

CLKout2

CLKout3

FPGA

1080p/59.94 SDI out

+ embedded audio

A/V Frame Sync with

Downconverter,

LMH1983

148.35 MHz (PLL3)

59.94 Hz (TOF3)

Audio Embedder and

De-embedder

1080p/59.94 SDI in

+ embedded audio

24.576 MHz (PLL4)

5.994 Hz

CLKout4

Genlocked to video ref. in

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

Table of Contents

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 20

8.5 Programming........................................................... 24

8.6 Register Map........................................................... 26

Applications and Implementation ...................... 35

9.1 Application Information............................................ 35

9.2 Typical Applications ................................................ 35

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 3

Pin Configurations and Functions....................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Frame Timing Outputs Timing Requirements........... 8

7.7 Frame Timing Outputs Switching Characteristics..... 8

7.8 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 12

9

10 Power Supply Recommendations ..................... 43

11 Layout................................................................... 43

11.1 Layout Guidelines ................................................. 43

11.2 Layout Example .................................................... 44

12 Device and Documentation Support ................. 47

12.1 Documentation Support ........................................ 47

12.2 Trademarks........................................................... 47

12.3 Electrostatic Discharge Caution............................ 47

12.4 Glossary................................................................ 47

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 47

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (October 2014) to Revision I

Page

•

Updated ESD Ratings table.................................................................................................................................................... 5

Updated formatting for Typical Characteristics graphs ......................................................................................................... 9

Changes from Revision G (Nov 2012) to Revision H

Page

•

Added Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and

Functions, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation

Support; Mechanical, Packaging, and Ordering Information ................................................................................................. 1

Changed typical value of low output sink current to match simulation value of 1.25 mA. .................................................... 6

Added clarification about PLL4 behavior. ............................................................................................................................ 15

Added clarification section for LOR Determination .............................................................................................................. 17

Changed appearance of Reg 0x11 mode description for clarity. ......................................................................................... 18

Changed register initialization procedure to prevent device from exhibiting poor duty cycle performance on CLKout3 .... 19

Added clarification note about 480i/29.97, 480p/59.94, 576i/25 and 576p/50 resolutions................................................... 23

Changed default value for Reg 0x11[3:2] bits. .................................................................................................................... 28

Changed Reg 0x11[3:2] description for clarification of TOF1_Sync behavior dependent on LOA window ......................... 28

•

2

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5 Description (continued)

When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of

reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output

accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize

to a previous reference with glitch-less operation.

6 Pin Configurations and Functions

RTA40A Package

40-Pin WQFN Package with Exposed Thermal Pad

Top View

VDD

Hin

1

2

3

4

5

6

7

30 Fout2

29

CLKout2-

28 CLKout2+

27 Cbyp2

Vin

Fin

26

25

Cbyp4

Cbyp3

Die Attach Pad (DAP)

INIT

Connect to GND on PCB

ADDR

24 CLKout3-

23 CLKout3+

22 Fout3

8

9

SDA

SCL

VDD

21 GND

10

Pin Functions

SIGNAL

LEVEL

I/O

DESCRIPTION

NO.

1

NAME

VDD

–

Power

3.3-V supply for PLL1

3.3-V supply for logic I/O

2

VDD

Horizontal sync reference signal

3

Hin

I

LVCMOS

Auto polarity correction for HVF will be based off Hin polarity.

Recognized clock inputs can be applied to Hin.

4

5

6

Vin

Fin

I

LVCMOS

Vertical sync reference signal

Field sync (odd/even) reference signal

INIT

Reset signal for audio-video phase alignment (rising edge triggered)

I²C address select

Pin settings:

7

ADDR

I

LVCMOS

– Tie low: 0x65 (7-bit slave address in hex)

– Float: 0x66

– Tie high: 0x67

8

SDA⁽¹⁾

SCL⁽¹⁾

I/O

I

I²C

I²C Data signal

I²C Clock signal

9

10

11

12

VDD

NO_LOCK⁽²⁾

–

Power

LVCMOS

3.3-V supply for logic I/O

O

Loss of lock status flag for PLLs 1-4 (active high)

Loss of alignment status flag for OUTs 1–4 (active high)

NO_ALIGN

(1) SDA and SCL pins each require a pull-up resistor of 4.7 kΩ to the VDD supply.

(2) The NO_LOCK status flag is derived from the Lock Status register bits (LOCK1-4) for each PLL. Each lock status bit can be masked

from the NO_LOCK flag by setting their respective mask bits.

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Pin Functions (continued)

SIGNAL

LEVEL

I/O

DESCRIPTION

NO.

NAME

13

NO_REF

O

–

LVCMOS

LVDS

Loss of reference status flag (active high)

14

15

CLKout4–

CLKout4+

Audio clock from PLL4 (fundamental rate is 98.304 MHz).

The output is 24.576 MHz by default and is selectable via the host.

16

17

VDD

Power

3.3 V supply for CLKout4

Audio frame timing signal for OUT4 (active low.) Timing Generator

fixed to PLL4 clock. The output is the audio-video-frame (AVF) pulse

by default and is programmable via the host. Optional OSCin function

can be used to apply a 27 MHz external clock for PLL4 to generate an

audio clock independent of the video input reference; this function

must be enabled via the host.

Fout4 (OSCin)

I/O

LVCMOS

18

19

20

21

GND

VDD

GND

–

GND

Power

GND

Ground

3.3 V supply for PLL3 and PLL4

3.3 V supply for CLKout3

Ground

Video frame timing signal for OUT3 (active low). Timing generator

assignable to PLL1, PLL2, or PLL3. OUT3 format is selectable via the

host.

22

Fout3

O

LVCMOS

LVDS

Video clock from PLL1, PLL2, or PLL3 depending on output

crosspoint mode. The output is 148.35 MHz by default and is

selectable via the host.

23

24

CLKout3+

CLKout3–

Bias bypass for on-chip LDO for PLL3

Connect to 1.0 µF and 0.1 µF bypass capacitors.

25

26

27

Cbyp3

Cbyp4

Cbyp2

–

Analog

Bias bypass for on-chip LDO for PLL4

Connect to 1.0 µF and 0.1 µF bypass capacitors.

Bias bypass for on-chip LDO for PLL2

Connect to 1.0 µF and 0.1 µF bypass capacitors.

Video clock from PLL1, PLL2, or PLL3 depending on output

crosspoint mode. The output is 148.5 MHz by default and is selectable

via the host.

28

29

CLKout2+

CLKout2–

O

LVDS

Video frame timing signal for OUT2 (active low). Timing generator

assignable to PLL1, PLL2, or PLL3. OUT2 format is selectable via the

host.

30

Fout2

LVCMOS

31

32

VDD

–

Power

3.3-V supply for CLKout2

3.3-V supply for PLL2

27 MHz VCXO clock signal for PLL1.

33

34

XOin–⁽³⁾

XOin+

– LVCMOS: Directly connect clock signal to XOin+ and bias XOin- to

mid-supply with 0.1µF bypass capacitor.

I

LVCMOS/LVDS

– LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.⁽⁴⁾

35

36

CLKout1–

CLKout1+

Video clock from PLL1.

The output is 27 MHz by default and is selectable via the host.

O

LVDS

Reference frame timing signal for OUT1 (active Low). Timing

generator fixed to PLL1 OUT1 Format follows the reference input

format.

37

Fout1

LVCMOS

38

39

VDD

GND

–

Power

GND

3.3 V supply for CLKout1

Ground

Loop filter for PLL1 charge pump output with VCXO Voltage Control

(VC) sensing.

If free-run and holdover mode, PLL1 is disabled and an internal DAC

outputs a control voltage to the VCXO.

40

–

VC_LPF

DAP

O

–

Analog

GND

Die Attach Pad (Connect to ground on PCB)

(3) XOin must be driven by a 27 MHz clock in order to read or write registers via I²C.

(4) A TCXO or other clean 27 MHz oscillator can be applied for standalone clock generation using PLLs 2-4 (bypass PLL1).

4

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)(3)

MIN

MAX

3.6

UNIT

V

V_DD

V_I

Supply voltage

Input voltage (any input)

Output voltage (any output)

Junction temperature

Storage temperature range

-0.3

V_DD+ 0.3

150

V

V_O

V

T_JMAX

T_stg

°C

-65

150

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering information, see SNOA549.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

7.2 ESD Ratings

VALUE

2500

250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Machine model (MM)⁽²⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽³⁾

750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2500 V may actually have higher performance.

(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC).

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0

NOM

MAX

V_DD

85

UNIT

V

Input Voltage

Temperature Range, T_A

-40

°C

7.4 Thermal Information

RTA

THERMAL METRIC⁽¹⁾

UNIT

40 PINS

3.3 ± 5%

33

T_JMAX

R_θJA

Junction Temperature, V_DD

Thermal Resistance⁽²⁾

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The maximum power dissipation is a function of T_J(MAX), R_θJA. The maximum allowable power dissipation at any ambient temperature is

PD = (T_J(MAX)– T_A)/ R_θJA. All numbers apply for packages soldered directly onto a PC Board.

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7.5 Electrical Characteristics⁽¹⁾

Unless otherwise specified, all limits are specified for T_A= 25°C, V_DD= 3.3 V, R_{L_CLK}= 100 Ω (CLKout differential load).

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP⁽³⁾MAX⁽²⁾UNIT

Default register settings, no load on logic outputs.

V_DD= 3.465 V

I_DD

Total supply current

170

60

212

100

mA

PLL2, PLL3 and PLL4 disabled, no load on logic

outputs. V_DD= 3.465 V

Total supply current

REFERENCE INPUTS (Hin, Vin, Fin)

V_IL

V_IH

Low input voltage

High input voltage

I_IN= ±10 μA

0

0.3 V_DD

V_DD

V

I_IN= ±10 µA

0.7 V_DD

Time from when reference input first presented to

when detected as indicated by NO_REF going low.

Reference timing must be stable and accurate (no

missing pulses).

Input

Frames

T_AFD

Auto-format detection time

2

4

OSCin LOGIC INPUTS

V_IL

V_IH

Low input voltage

High input voltage

I_IN= ±10 µA

0

0.3 V_DD

V_DD

V

0.7 V_DD

I²C INTERFACE (SDA, SCL)

V_IL

V_IH

I_IN

Low input voltage

High input voltage

Input current

0

0.7 V_DD

−10

0.3 V_DD

V_DD

V

V_INbetween 0.1 V_DDand 0.9 V_DD

V_OL= 0V or 0.4V

+10

μA

mA

I_OL

Low output sink current

1.25

STATUS FLAG OUTPUTS (NO_REF, NO_ALIGN,NO_LOCK)

V_OL

V_OH

Low output voltage

High output voltage

I_OUT= +10 mA

0.4

10

V

I_OUT= −10 mA

V_DD-0.4V

FRAME TIMING OUTPUTS

I_OUT= +10 mA

V_OL

V_OH

I_OZ

Low output voltage

High output voltage

Fout1, Fout2, Fout3⁽⁴⁾

I_OUT= -10mA

V_DD-0.4 V

Fout1, Fout2, Fout3⁽⁴⁾

Output shutdown leakage

current

Output buffer shutdown, pin connected to V_DDor

GND V_DD= 3.465V

0.4

|μA|

VIDEO and AUDIO CLOCK OUTPUTS (CLKout1, CLKout2 and CLKout3)

Measured at CLKout1 all other CLKouts shutdown

250

8

fs

27 MHz TIE deterministic

Jitter

Measured at CLKout1, other CLKouts output default

PLL

Measured at CLKout2 all other CLKouts shutdown

ps

148.5 MHz TIE

deterministic Jitter

Measured at CLKout2, other CLKouts output default

PLL

8

t_DJ

Measured at CLKout3 all other CLKouts shutdown

4

148.35 MHz TIE

deterministic Jitter

Measured at CLKout3, other CLKouts output default

PLL

4

Measured at CLKout4 all other CLKouts shutdown

15

24.576 MHz TIE

deterministic Jitter

Measured at CLKout4, other CLKouts output default

PLL

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance

is indicated in the electrical tables under conditions different than those tested.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

statistical analysis methods.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(4) t_Dfor FoutX is measured from the positive clock edge of CLKout to the negative edge of FoutX at the 50% levels.

6

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Electrical Characteristics⁽¹⁾(continued)

Unless otherwise specified, all limits are specified for T_A= 25°C, V_DD= 3.3 V, R_{L_CLK}= 100 Ω (CLKout differential load).

PARAMETER

TEST CONDITIONS

MIN⁽²⁾

TYP⁽³⁾MAX⁽²⁾UNIT

Measured at CLKout1, other CLKouts shutdown

2.7

3.0

3.5

3.4

ps

27 MHz TIE random Output

Jitter⁽⁵⁾

Measured at CLKout1, other CLKouts output default

PLL

Measured at CLKout2, other CLKouts shutdown

148.5 MHz TIE Random

Output Jitter⁽⁵⁾

Measured at CLKout2, other CLKouts output default

PLL

t_RJ

Measured at CLKout3, other CLKouts shutdown

148.35 MHz TIE Random

(5)

Measured at CLKout3, other CLKouts output default

PLL

Output Jitter

Measured at CLKout4, other CLKouts shutdown

24.576 MHz TIE Random

Output Jitter⁽⁵⁾

Measured at CLKout4, other CLKouts output default

PLL

Measured at 50% level of clock amplitude, any

output clock

T_D

t_R

Duty cycle

50%

400

350

1.25

Rise time

20% to 80%

15 pF load

ps

mV

V

Fall time

80% to 20%

t_F

Differential signal output

voltage

100 Ω differential load, CLKout1, CLKout2 or

V_OD

V_OS

247

454

CLKout3⁽⁶⁾

Common signal output

voltage

100 Ω differential load, CLKout1, CLKout2 or

1.125

1.375

CLKout3⁽⁶⁾

|Change to V_OD| for

complementary output

states

100 Ω differential load, CLKout1, CLKout2 or

|V_OD

|

50

|mV|

CLKout3⁽⁶⁾

|Change to V_OS| for

complementary output

states

100 Ω differential load, CLKout1, CLKout2 or

|V_OS

|

CLKout3⁽⁶⁾

Differential clock output pins connected to GND for

CLKout1, CLKout2, or CLKout3

I_OS

I_OZ

Output short circuit current

24

10

|mA|

|µA|

Output shutdown leakage

current

Output buffer in shutdown mode, differential clock

output pins connected to V_DDor GND

1

VCXO INPUT (XOin)

Maximum relative frequency

offset between VCXO input Assumes H input jitter of ±15 ns

f_OFF

±150

ppm

and H input

Single-ended signal input

voltage range

V_{XOin_SE}

Single-ended input buffer mode

0

V_DD

454

V

Differential signal input

voltage range

V_{XOin_DIFF}

Differential input buffer mode, V_CM= 1.2 V

247

350

mV

DIGITAL HOLDOVER and FREE-RUN SPECIFICATIONS

V_{VCout_RNG}DAC output voltage range Digital Free-run Mode

V_DD

0.5V

-

0.5

V

(5) The SD and HD clock output jitter is based on XO input clock with 20 ps peak-to-peak using a time interval error (TIE) jitter

measurement. The typical TIE peak-to-peak jitter was measured on the LMH1983 evaluation bench board using TDSJIT3 jitter analysis

software on a Tektronix DSA71604 oscilloscope and 1 GHz active differential probe. TDSJIT3 Clock TIE Measurement Setup: 10^-12bit

error rate (BER), >100K samples recorded using multiple acquisitions. Oscilloscope Setup: 20 mV/div vertical scale, 10 µs/div horizontal

scale, and 25 GS/s sampling rate

(6) The differential output swing and common mode voltage may be adjusted via the I²C interface. Testing is done with a value of 0x3E

loaded into Register 0x3A.

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7.6 Frame Timing Outputs Timing Requirements

MIN

NOM

MAX UNIT

t_R

t_F

Rise time 20% to 80%

Fall time 20% to 80%

15 pF load

1

ns

7.7 Frame Timing Outputs Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TOF1 delay measured from the CLKout1 clock reset

edge. Delay spec applies for all output clock and format

supported by the output pair following output initialization.

15 pF load.

ns

(1)

t_D1

t_D2

t_D3

t_D4

Timing output delay time

22

TOF2 delay measured from the CLKout2 clock reset

edge. Delay spec applies for all output clock and format

supported by the output pair following output initialization.

15 pF load.

ns

Timing output delay time

2

TOF3 delay measured from the CLKout3 clock reset

edge. Delay spec applies for all output clock and format

supported by the output pair following output initialization.

15 pF load.

TOF4 delay measured from the CLKout4 clock reset

edge. Delay spec applies for all output clock and format

supported by the output pair following output initialization.

15 pF load.

22

(1) t_Dfor CLKoutX is measured from the positive clock edge of XOin to the positive clock edge of CLKoutX using 50% levels. The

measurement is taken at the clock cycle where the input and output clocks are phase aligned.

8

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7.8 Typical Characteristics

Horizontal Scale: 2.6ps / Division

Figure 1. CLKout1 Jitter Histogram

Figure 2. CLKout1 Phase Noise

Figure 4. CLKout2 Phase Noise

Figure 6. CLKout3 Phase Noise

Horizontal Scale: 4.4ps / Division

Figure 3. CLKout2 Jitter Histogram

Horizontal Scale: 4.4ps / Div

Figure 5. CLKout3 Jitter Histogram

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Typical Characteristics (continued)

Horizontal Scale: 7 ps / Div

Figure 7. CLKout4 Jitter Histogram

Figure 8. CLKout4 Phase Noise

10

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8 Detailed Description

8.1 Overview

The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at a

variety of video and audio rates, synchronized or “genlocked” to Hsync and Vsync input reference timing. The

LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with

programmable timing that can also be synchronized to the reference frame. The clock generator uses a two-

stage PLL architecture. The first stage is a VCXO-based PLL (PLL1) that requires an external 27 MHz VCXO

and loop filter. In Genlock mode, PLL1 can phase lock a low loop bandwidth VCXO clock to the input reference.

The VCXO provides a low phase noise clock source to attenuate input timing jitter for minimum jitter transfer.

The combination of the external VCXO, external loop filter, and programmable PLL parameters provide flexibility

for the system designer to optimize the loop bandwidth and loop response for the application.

The second stage consists of three PLLs (PLL2, PLL3, PLL4) with integrated VCOs and loop filters. These PLLs

continually track the reference VCXO clock phase from PLL1 regardless of the device mode. The PLL2 and PLL3

have pre-configured divider ratios to provide frequency multiplication or translation from the VCXO clock

frequency to generate the two common HD clock rates (148.5 MHz and 148.35 MHz). PLL4 is pre-configured to

generate an audio clock that defaults to a 24.576 MHz output, although PLL4 has several registers that allow it to

be re-configured for a variety of applications.

The VCO PLLs use a high loop bandwidth to assure PLL stability, so the VCXO of PLL1 must provide a stable

low-jitter clock reference to ensure optimal output jitter performance. Any unused clock or TOF output can be

placed in Hi-Z mode. This may be useful for reducing power dissipation as well as reducing jitter or phase noise

on the active clock output. The TOF pulse can be programmed to indicate the start (top) of frame and even

provide format cross-locking. The output format registers should be programmed to specify the output timing

(output clocks and TOF pulse), the output timing offset relative to the reference, and the output initialization

(alignment) to the reference frame.

When a loss of reference occurs during genlock, PLL1 can default to either Free-run or Holdover operation.

When Free-run is selected, the output frequency accuracy will be determined by the external bias on the free-run

control voltage input pin, VC_LPF. When Holdover is selected, the loop filter can hold the control voltage to

maintain short-term output phase accuracy for a brief period in order to allow the application to select the

secondary input reference and re-lock the outputs. These options in combination with a proper PLL1 loop

response design can provide flexibility to manage output clock behavior during loss and re-acquisition of the

reference. The reference status and PLL lock status flags can provide real-time status indication to the

application system. The loss of reference and lock detection thresholds can also be configured.

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8.2 Functional Block Diagram

External Loop Filter and VCXO

27 MHz

VCXO

V

DD

/2

= Device pins

VC_LPF

XOin+

XOin-

10-Bit SAR

ADC

CLKout1+

CLKout1-

Vc(Freerun)

DAC

27.0

(13.5)

MHz

Vc(Genlock)

Fout1

Hin

Vin

Fin

Ref

Input Format

and Polarity

Detection

PLL1

TOF1

In1

In2

Genlock PLL

CLKout2+

CLKout2-

Fbk

148.5

(74.25)

MHz

Out2

PLL2

3G(HD)

Video Clock

3x2

Video Clock

Crosspoint

148.35,

(74.176)

MHz

CLKout3+

CLKout3-

Out3

PLL3

3G(HD)/1.001

Video Clock

NO_REF

Device

Control and

Registers

In3

ADDR

NO_ALIGN

NO_LOCK

Fout2

Fout3

SDA

SCL

2

I C Interface

2

I C Address Options: 0x65h-67h

98.304 MHz,

others*

CLKout4+

CLKout4-

PLL4

Audio Clock

MUX

AFS/Word

Fout4

(Osc In)

27 MHz_Osc

X

* Audio Clock PLL supports 98.304/2 MHz, where X=0-15

8.3 Feature Description

The following subsections provide information about the various control mechanisms and features that are

fundamental to the LMH1983 clock generator.

8.3.1 Control of PLL1

PLL1 generates a 27 MHz reference that is used as the primary frequency reference for all of the other PLLs in

the device. PLL1 has a dual loop architecture with the primary loop locking the external 27 MHz VCXO to a

harmonic of the H_INsignal. In addition to this loop, there is a secondary loop that may be used in genlock

operations. This second loop compares the phase of the TOF1 output signal from the LMH1983 to the F_INsignal.

In order to bring the frame alignment of the output signals into sync with the input reference, the second loop

may override the primary loop. Detailed information about controlling this functionality is described in TOF1

Alignment.

To illustrate the dual loop architecture of PLL1, refer to the PLL1 block diagram in Figure 9. The primary loop

takes the reference applied to the H_INinput and divides that by R (stored in Registers 0x29 and 0x2A). The

dividend is then compared in phase and frequency to the output of the external 27 MHz VCXO divided by N

(stored in Registers 0x2B and 0x2C). The PFD (phase frequency detector) then generates output pulses that are

integrated via an external loop filter that drives the control voltage of the external VCXO.

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Feature Description (continued)

V in

PFD

TOF1

SAR

DAC

MUX

CP

H in

÷ R

Current

Source

VCXO

(ext)

÷ N

Loop Filter

(ext)

÷ 1 or ÷ 2

CLK1 Out

Figure 9. PLL1 Block Diagram

Since PLL2, PLL3, and PLL4 all use PLL1 as their input reference, the performance of PLL1 affects the

performance of all four clock outputs. The loop filters for the other three PLLs are internal, and the bandwidths

are set significantly higher than that of PLL1, so the low frequency jitter characteristics of all four clock outputs

are determined by the loop response of PLL1. Accordingly, special attention should be paid to the PLL1's loop

bandwidth and damping factor.

8.3.2 PLL1 Loop Response Design Equations

The loop response is primarily determined by the loop filter components and the loop gain. A passive second

order loop filter consisting of R_S, C_S, and C_Pcomponents can provide sufficient input jitter attenuation for most

applications. In some cases, a higher order filter may be used to shape the low frequency response of PLL1

further. Assuming a topology for the loop filter similar to that shown in the Figure 9, the bandwidth of the PLL is

determined by:

BW_PLL1= R_Sx K_VCOx I_CP1/(2*π*FB_DIV)

where

•

R_Sis the series resistor value in the external loop filter.

K_VCOis the nominal 27 MHz VCXO gain in Hz/V. K_VCO= Pull_range*27 MHz/Vin_Range. For the VCXO used in

the typical interface circuit (Mfgr: CTS, P/N 357LB3C027M0000): L_VCO=100 ppm*27 MHz / (3.0V-0.3V) = 1000

Hz/V

•

I_CP1is the current from the PLL1 charge pump.

FB_DIV is the divide ratio of the PLL, which is set by the R and N register values, this will be equal to the

number of 27 MHz clock pulses in one H_INperiod. For NTSC, this value will be 1716.

(1)

Under normal operation, several of these parameters are set by the device automatically, for example the charge

pump current and the value of 'FB_DIV'. When the input reference format changes, both N and the charge pump

current are updated, N is changed to allow for lock to the new reference, and the charge pump current is

adjusted to maintain constant loop bandwidth.

It should be noted that this bandwidth calculation is an approximation and does not take into account the effects

of the damping factor or the second pole introduced by C_P.

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Feature Description (continued)

VC_LPF

CS

RS

CP

Figure 10. External Loop Filter Schematic Detail

At frequencies far above the –3dB loop bandwidth, the closed-loop frequency response of PLL1 will roll off at

about –40dB/decade, which is useful for attenuating input jitter at frequencies above the loop bandwidth. Near

the –3dB corner frequency, the roll-off characteristic depends on other factors, such as damping factor and filter

order.

To prevent output jitter due to the modulation of the VCXO by the PLL's phase comparison frequency, the

bandwidth needs to meet the following criterion:

BW ≤ (27 MHz / FB_DIV ) / 20

(2)

PLL1's damping factor can be approximated by:

DF = (R_S/2)√(I_CP1x C_Sx K_VCO/FB_DIV)

where

•

C_Sis the value of the series capacitor (in Farads)

(3)

Typically, DF is targeted to be between 1/√2 and 1, which will yield a good trade-off between lock time and

reference spur attenuation. DF is related to the phase margin, a measure of the PLL stability.

There is a second parallel capacitor, C_P, which is needed to filter the reference spurs introduced by the PLL. The

spurs may modulate the VCXO control voltage, leading to jitter. The following relationship should be used to

determine C_P:

C_P≈ C_S/20

(4)

The PLL loop gain, K, can be calculated as:

K = I_CP1x K_VCO/FB_DIV

(5)

Therefore, Bandwidth and Damping Factor can be expressed in terms of K:

BW = R_Sx K

(6)

(7)

DF = (R_S/2) x √(C_Sx K)

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Feature Description (continued)

8.3.3 Control of PLL2 and PLL3

PLL2 and PLL3 have the least amount of flexibility of the four PLLs in the LMH1983. They are pre-programmed

to run at 148.5 MHz and 148.35 MHz respectively. There is a divide-by-two option available to allow the output to

be 74.25 MHz or 74.18 MHz, should these frequencies be required. These two PLLs can also be disabled –

disabling PLL2 or PLL3 can save significant amounts of power if that particular clock is not required. Figure 11

shows a simplified functional block diagram of PLL2 and PLL3.

CP

÷ R

PFD

Current

Source

27 MHz In

þ

÷ N

VCO

CLK Out

Figure 11. PLL2 / PLL3 Block Diagram

8.3.4 Control of PLL4

Although originally intended to generate only a clock for audio use, PLL4 features much greater versatility.

Several registers may be used to configure PLL4 to generate a broad selection of frequencies. The default state

for PLL4 is to generate 24.576 MHz (48 kHz x 512) on the output of CLK4 and a 5.996 Hz output from TOF4.

This is done by taking CLK1 (27 MHz), and dividing by 75, resulting in a signal of 360 kHz. This frequency is

compared to the internal PLL4 VCO, nominally 1.2 GHz, divided by 4096. The VCO frequency is adjusted via

register control until the resulting frequency yields 360 kHz. The final VCO frequency is then divided by 12 to

generate a 98.304 MHz signal (48 kHz x 2048). Any power of two multiple of 48 kHz can be generated by

changing the contents of the PLL4_DIV component of Register 0x34. Note that the divider here is in powers of 2,

so the default value of 2 results in the 98.304 MHz signal being divided by 2²or 4. The final CLKout4 frequency

is therefore 24.576 MHz. PLL4_DIV is a 4-bit value, so values up to 15 may be programmed, resulting in a divide

by 2¹⁵or 32,768. If audio clocks based on a 44.1 kHz sampling clock are desired, refer to Application Note

AN–2108, Generating 44.1 kHz Based Clocks with the LMH1983, (SNLA129) for detailed instructions.

TOF4 has two different operation modes. When the AFS_mode bit (Register 0x09) is set to a 0, then TOF4 is

derived by dividing CLKout4 by a value of 2^TOF4_ACLK(Register 0x4A). if the AFS_mode bit is set to 1, then TOF4

is derived from TOF1 — divided by AFS_div (Register 0x49). When AutoFormatDetect is true, then the AFS_div

register is read only and is internally set depending upon the format detected.

Phase/

Frequency

Detector

27ꢀMHz In

Current

Source

÷ꢀR

Loop Filter

VCO

(~1.3545GHz)

÷ꢀ(N x 8)

CLKout4

PLL4_DIV

÷ 4 or 5

(is125M)

÷ꢀ3

÷ꢀ2

TOF4_ACLK

÷ꢀ2

TOF4

MUX

Frame_in

AFS_mode

AFS_div

Figure 12. PLL4 Block Diagram

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Feature Description (continued)

8.3.5 Clock Output Jitter

Many circuits that require video clocks, such as the embedded Serializers and Deserializers found in FPGAs, are

sensitive to jitter. In all real world applications, jitter has a random component, so it is best specified in statistical

terms. The SMPTE serial standards (SMPTE 259M, SMPTE 292M and SMPTE 424M) use a frequency domain

method of specifying jitter where they refer to the peak-to-peak jitter of a signal after the jitter has been bandpass

filtered. Jitter at frequencies below 10 Hz is ignored, and the jitter in a band from 10 Hz to an intermediate

frequency (1 kHz for the 270 Mbps standard, 100 kHz for the 1.5 Gbps and 3 Gbps standards) is referred to as

timing jitter. Jitter from the intermediate frequency up to 1/10 of the serial rate is referred to as alignment jitter.

The limits that the SMPTE standards place are peak-to-peak limits, but especially at the higher rates, random

processes have a significant impact, and it is not possible to consider peak-to-peak jitter without a corresponding

confidence level. The methodology used to specify the jitter on the LMH1983 decomposes the jitter into a

deterministic component (t_DJ) plus a random component (t_RJ). This is the methodology used by the jitter analysis

tools supported on high bandwidth oscilloscopes and timing analysis tools from major instrumentation

manufacturers.

To convert between RMS jitter and peak-to-peak jitter, the Bit Error Rate (BER) must be specified. Since jitter is

a random event, without a known BER, the peak-to-peak jitter will be dependent upon the observation time and

can be arbitrarily large. The equation that links peak-to-peak jitter to RMS jitter is:

t_P-P= t_DJ+α*t_RJ

(8)

where α is determined by the BER according to the equation:

1/2erfc(√2*α) = BER

(9)

The erfc (error function) can be found in several mathematics references and is also a function in both Excel and

MATLAB. A fairly common BER used for these calculations is 10^-12, which yields a value of α = 14.

Another common method for evaluating the jitter of a clock output is to look at the phase noise as a function of

frequency. Plots showing the phase noise for each of the four CLKout outputs can be found in Figure 1 through

Figure 8.

8.3.6 Lock Determination

There are four bits in Register 0x02 that indicate the lock status of the four PLLs. Lock determination for PLL1

can be controlled through two registers: LockStepSize (Register 0x2D) and Loss of Lock Threshold (Register

0x1C). The LockStepSize register sets the amount of variation that is permitted on the VC_LPF pin while still

considering the device to be locked. If the reference to the LMH1983 has a large amount of jitter, then the device

may be unable to declare lock because the LockStepSize is set too low. The second register, the Loss of Lock

Threshold register, controls the lock state declaration of PLL1. This register sets a number of cycles on the H_IN

input that must be seen before loss of lock is declared. For some reference signals, there can be several missing

H_INpulses during vertical refresh. Therefore, it is suggested that this register be loaded with a value greater than

six (Loss of Lock Threshold > 6). Pin 11, NO_LOCK, gives the lock status of the LMH1983. Note that the status

of the NO_LOCK pin can also be read from Register 0x01, and it is a logical OR of the four individual NO_LOCK

status bits of the four PLLs. The NO_LOCK status pin is masked by the bits in the PLL Lock mask (Register

0x1D), and the status is also masked if an individual PLL is powered down.

8.3.7 Lock Time Considerations

The lock time of the LMH1983 is dominated by the lock time of PLL1. The other PLLs have much higher loop

bandwidths, and as a result, they lock more quickly than PLL1 does. Therefore, lock time considerations mainly

rely on PLL1. The lock time for a PLL is dependent upon the loop bandwidth (see Equation 1). A small loop

bandwidth typically increases the time required to achieve lock. To counter this issue, the LMH1983 also allows a

Fastlock mode. In this mode, the bandwidth is increased by increasing the charge pump current when the loop is

unlocked. Then, at a time programmed by the user after lock is declared, I_CP1is throttled back to drop the

bandwidth to the desired set point. The result is both fast lock time and very low residual jitter.

Another factor when considering lock time is whether 'drift lock' has been enabled or not (see TOF1 Alignment).

If drift lock is enabled and there is a significant difference in the phase of TOF1 relative to the F_INsignal, the

VCXO is slewed to ramp the clock rate up or down until the two framing signals are brought into alignment. It is

possible that this process may take a long time (tens of seconds).

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Feature Description (continued)

Aside from the time required for the PLL to lock, there is a circuit that determines how to set the NO_LOCK

output pin. The LMH1983 PLL operates by adjusting the voltage that is applied to the VCXO control pin to lock

the VCXO to a harmonic of the incoming reference. When the device is not locked, the PLL pulls the VCXO

control voltage to one extreme of its range to slew the voltage into lock. Once the phase differences between the

VCXO and the reference are small, the device begins to nudge the control voltage back and forth to maintain the

phase difference. An adjustment might be necessary either due to VCXO drift or due to jitter on the reference. To

determine the status of NO_LOCK, the LMH1983 establishes a window to view the amount of adjustment that is

required over a period of time. Two parameters are set via register control to determine NO_LOCK status.

LockStepSize (Register 0x2D) sets the amount of time in which to observe the signal, and Loss of Lock

Threshold (Register 0x1C) sets the amount of variation in the control voltage that can be seen over this time

frame while still considering the device to be locked.

To minimize the amount of time necessary to assert lock, load LockStepSize (Register 0x2D) with a value of

0x01 and the Loss of Lock Threshold (Register 0x1C) with a value of 0x1F. The effect of this change can be

seen in Figure 13:

reference

(input)

NOREF

(output)

LOCK ~ 4.4s

NOLOCK

(output)

reference

(input)

NOREF

(output)

LOCK ~ 760 ms

NOLOCK

(output)

Figure 13. Faster NO_LOCK Reaction Mode Timing

8.3.8 LOR Determination

When the PLL is not locked, there is an internal counter that counts the number of 27 MHz clock pulses between

consecutive HSync pulses divide-by-two. This counter saturates at 0x7FFF (or 32767 decimal). Once this

counter saturates, LOR is declared. Given this is a divide-by-two counter, the time to declare LOR is: (2 x 32767)

/ (27E6) = 2.4 ms. On the other hand, when the PLL is locked and there are missing HSync pulses, LOR is set

when the internal counter is greater than the following: (Number of 27 MHz clocks in one Hsync pulse + 3) x

(LOR_THRES + 1).

8.3.9 Output Driver Adjustments

The LVDS output drivers can be adjusted via the I²C interface to change the differential output voltage swing, the

common mode voltage, and the amount of pre-emphasis applied to the LVDS output:

•

Register 0x3A, Bit 7 turns on the pre-emphasis, which may be used to extend the reach between the

LMH1983 and the load. It is recommended that the trace length is kept short, as longer traces have more

opportunity to couple with hostile signals and degrade jitter performance.

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Feature Description (continued)

•

The differential output swing of the CLKout pins is adjusted through Register 0x3A, Bits [6:4]. A larger value

loaded into Bits [6:4] correspond to an increase in the output swing.

•

The common mode output voltage can be adjusted via Register 0x3A, Bits [3:0].

8.3.10 TOF1 Alignment

Each of the four clock outputs has a corresponding Top Of Frame (TOF) output signal. The LMH1983 is

programmed with a video format for each of the three video clocks (CLKout 1-3), and the TOF signal provides a

digital indication when the start of a new frame occurs for that particular format. As an example, if PLL1 is

programmed with a video format corresponding to NTSC, CLK1 is 27 MHz, and TOF1 outputs a pulse once per

frame, or once every 900,900 clock cycles. In its default state, the LMH1983 detects the input reference format

and programs this format as the output format for CLKout1. Therefore, if the input reference is an NTSC

reference, then TOF1 will default to a 29.97 Hz signal.

If the H_IN, V_IN, and F_INinputs to the LMH1983 are coming from the LMH1981 Sync Separator, then the rising

edge of the F_INinput will come in the middle of a line (between H_INpulses). The TOF pulse, if aligned, will be a

pulse with a width of 1 x H period and transitions aligned with the leading edges of the H_INpulses. When set for

zero offset, the TOF pulse will be high during the H period where the F_INinput transitions, as seen in Figure 14.

TOF1

H

IN

F

IN

Figure 14. TOF1 Timing

The alignment between the incoming F_INand the TOF1 output may be controlled in a number of ways. There are

three different alignment modes in which TOF1 may operate as selected via Register 0x11:

1. 11'b (default): PLL1 never attempts to align.

2. 10'b: PLL1 always forces alignment to F_IN.

3. 00'b: Automatically force alignment to F_INwhen they are misaligned.

Misalignment can be defined by the user via Register 0x15. In Register 0x15, a time window is defined to specify

the amount of mismatch permitted between F_INand TOF1 while still considering them to be aligned. If the input

reference signal has a significant amount of low frequency jitter or wander, it may be possible for the relative

alignment between TOF1 and F_INto vary over time. Selecting "Always Align" mode may lead to undesirable

timing jumps on the output of CLKout1/TOF1.

Once the device decides that it needs to align TOF1 and F_IN, there are two ways that it can be done. Crash lock

involves simply resetting the counter that keeps track of where the TOF1 output transition happens, resulting in

an instantaneous shift of TOF1 to align with F_IN. Drift lock involves using the second loop in PLL1 and skewing

the VCXO to make the frequency of CLKout1 either speed up or slow down. The VCXO skewing slowly pulls

TOF1 and F_INinto alignment. If a new reference is applied that is not in alignment with TOF1, but the output is

currently in use, it may be better to slew TOF1 into alignment rather than to cause a major disruption in the

timing with a crash lock. The LMH1983 allows the user to select either crash lock or drift lock, controllable via

Register 0x11. The option of crash lock or drift lock is available when the difference in phase is small (Output <

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Feature Description (continued)

2^LOA_windowx 27 MHz Clock) and when the difference in phase is large (Output > 2^LOA_windowx 27 MHz Clock).

Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or

retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock

may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input

H_IN.

8.3.11 TOF2 and TOF3 Alignment

Similar to TOF1, CLKout2 and CLKout3 have associated video formats. The format is determined by

programming Register 0x07 and 0x08, respectively. Once the format is programmed and the TOF outputs are

enabled, a TOF pulse is generated at the appropriate rate for each of the outputs. There are four different

alignment modes that may be selected for TOF2 and TOF3:

Table 1. TOF2/TOF3 Alignment Modes

TOF2/TOF3 ALIGNMENT MODE

DESCRIPTION

Auto Align when Misaligned

One Shot Manual Align

Always Align

0

1

2

3

Never Align

TOF2 and TOF3 are generally aligned with TOF1. The alignment status bit will only be set if the frame rates are

the same as one another. Another option for alignment is via software, where the TOFX_INIT bit is set. For

example, the LSB of Register 0x12 is the TOF2_INIT bit. Writing a 1 to this bit while also setting TOF2 alignment

mode to anything other than 3 (Never Align) will cause TOF2 to reset its phase immediately. Note that this bit is

a self-clearing bit, so it will always return a zero.

8.3.11.1 TOF3 Initialization Set Up

Under some circumstances, it is possible for an LMH1983 to power up in an anomalous state in which the output

of PLL3 exhibits a large amount of cycle-to-cycle jitter. A simple register write after power up will prevent the

device from remaining in this state. Writing to Register 0x13[5:4] = 10'b to force Always Align Mode ensures that

the device will not exhibit poor duty cycle performance on CLKout3.

8.3.12 TOF4 Alignment

CLKout4 of the LMH1983 is most often used to generate an audio clock. The default base audio clock rate is 48

kHz, and this sample clock is synchronous in phase with the video frame only once every 5 frames for 29.97 and

30 Hz frame rate standards, or once every ten frames for 60 Hz and 59.94 Hz systems. The LMH1983 can

generate a TOF4 pulse that occurs at this rate, allowing audio frames to be synchronized with the video frames.

TOF4 may be aligned either to TOF1 or to the F_INinput. Additionally, there is an external INIT input that can be

used to set TOF4 alignment.

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10ns / div

Top 200mV / div

Bottom 1V / div

4 ns / div

Top 200 mV / div

Bottom 1V / div

Figure 15. TOF1 Timing

Top Trace CLKout1, Bottom Trace TOF1

Figure 16. TOF2 Timing

Top Trace CLKout2, Bottom Trace TOF2

4ns / div

Top 200mV / div

Bottom 1V / div

10 ns / div

Top 200 mV / div

Bottom 1V / div

Figure 17. TOF3 Timing

Top Trace CLKout3, Bottom Trace TOF3

Figure 18. TOF4 Timing

Top Trace CLKout4, Bottom Trace TOF4

8.4 Device Functional Modes

8.4.1 Reference Detection

The device uses Auto Format Detect as the default mode, as the device determines the reference format among

those shown in Auto Format Detection Codes, and initiates the internal configurations accordingly. There are 31

pre-defined formats plus one format that the user can define. The device recognizes a format by measuring the

H_INinput frequency and looking at the V_INand F_INinputs. The device then determines if the reference input

format is an interlaced or progressive input. For some formats such as a 10 MHz or 27 MHz Hsync reference, if

H_INand V_INcreate a spurious input, the device will not properly recognize the reference input and will not lock

properly to the reference. Because of this, if H_INhas one of these 'special' signals on it, V_INand F_INshould be

muted.

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Device Functional Modes (continued)

8.4.2 User Defined Formats

There are several registers in the LMH1983 that are loaded automatically based on the format of the reference

that is detected. The LMH1983 allows the user to define a non-standard format and a corresponding set of

values to load into the appropriate registers if that format is detected. In order to identify the format, the

LMH1983 measures the frequency of the Hsync input, counts the number of lines per frame in the format, and

detects if the particular format is interlaced or progressive. The Hsync frequency is measured by counting the

number of 27 MHz clock edges that occur in a period of time equal to 20 horizontal sync times. To implement a

user defined format, the following registers are configured:

•

The minimum and maximum permissible count must be set, thereby establishing a window of frequency for

Hsync. Registers 0x51 and 0x52 define the 16-bit value for the low end of the frequency range, while

Registers 0x53 and 0x54 define the high end of the frequency range.

•

Registers 0x5A and 0x5B define the number of lines per frame for the format.

Register 0x5D, Bit 4 indicates whether the user defined format is interlaced or not.

Register 0x5D, Bit 7 enables the detection of a user-defined format.

Once the user-defined format is detected, the contents of Registers 0x55 through 0x59 configure PLL1 to lock

to 27MHz, which is then used as the reference for PLL2, PLL3, and PLL4.

Table 2 lists the supported standard timing formats. Table 2 includes the relevant parameters used to configure

the LMH1983 for the input and output formats. Auto-detection of the input is supported for the formats listed in

Table 2. The input format can also be programmed manually by the host via I²C if it is necessary to override the

auto-detection feature.

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8.4.3 Auto Format Detection Codes

The Auto Format Detection Codes apply to Registers 0x07 (Output Mode – PLL2 Format), 0x08 (Output Mode –

PLL3 Format), and 0x20 (Input Format).

FORMAT CODE

DESCRIPTION

Hsync PERIOD

(in 27 MHz CLOCKS)

INTERLACED (I) /

PROGRESSIVE (P)

0

525I29.97⁽¹⁾

625I25⁽²⁾

1716

1728

I

1

I

2

525P59.94⁽¹⁾

625P50⁽²⁾

720P60

858

P

3

864

P

4

600

P

5

720P59.94

720P50

600.6

720

P

6

P

7

720P30

1200

P

8

720P29.97

720P25

1201.2

1440

P

9

P

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

63

720P24

1500

P

720P23.98

1080P60

1501.5

400

P

1080P59.94

1080P50

400.4

480

P

1080P30

800

P

1080P29.97

1080P25

800.8

960

P

1080P24

1000

P

1080P23.98

1080I30

1001

P

800

I

1080I29.97

1080I25

800.8

960

I

1080I24

1000

I

1080I23.98

48 kHz Audio

96 kHz Audio

44.1 kHz Audio

32 kHz Audio

27 MHz Hsync

10 MHz Hsync

User Defined

Unknown

1001

I

562.5

281.25

612.244898

843.75

1

—

2.7

User Defined

All Others

User Defined

(1) NTSC, 525i and 525p formats are also commonly known as 480I29.97 and 480P59.94, respectively,

since the visible screen resolution consists of 480 pixels.

(2) PAL, 625i and 625p formats are also commonly known as 576I25 and 576P50, respectively, since the

visible screen resolution consists of 576 pixels.

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8.4.4 Free-Run, Genlock, and Holdover Modes

The LMH1983 primary PLL can operate in three different modes, selected via Register 0x05. These modes are

Free-run, Genlock, and Holdover Mode:

•

Free-run mode: H_IN, V_IN, and F_INare not used, and the VCXO control voltage is set by the contents of

Registers 0x18 and 0x19. By writing to these registers, the VCXO voltage can be trimmed up or down. The

slave PLLs will remain locked to the primary PLL.

Genlock mode: The VCXO control voltage is actively controlled to maintain lock between H_INand the VCXO

output frequency. In addition, there is a second PLL loop that may take over to assert a lock between TOF1

and F_IN. See TOF1 Alignment for more details.

Holdover mode: In the event that the reference is lost, there is an A/D — D/A pair that is able to take over for

the PLL control loop and hold the VCXO control voltage constant. For this to work properly, the device must

realize that it has lost its reference shortly after the reference is actually lost. Some sync separators, when the

analog input is lost, will output random pulses from the H, V, and F outputs. This can confuse the device.

Therefore if Holdover mode is to be used in conjunction with an analog sync separator, it is best to gate the

H, V, and F signals with a signal that indicates if there is a valid reference input.

8.5 Programming

8.5.1 I²C Interface Protocol

The protocol of the I²C interface begins with the start pulse, followed by a byte which consists of a seven-bit

slave device address and a Read/Write bit as an LSB. The default address of the LMH1983 for write sequences

is 0xCC (11001100'b) and for read sequences is 0xCD (11001101'b). The base address can be changed with the

ADDR pin. When ADDR is left open, the base address is 0x66 (which, when left shifted for a write sequence

becomes 0xCC). When ADDR is connected to GND, the base address is 0x65, and when ADDR is connected to

V_DD, the base address is 0x67.

Please note: The I2C interface of the LMH1983 requires the 27 MHz VCXO clock input to be running in order to

read I2C data packets into the 27 MHz clock domain. If the 27 MHz clock is not running, the I2C interface should

still respond (ACK), but Write commands may be ignored and Read commands may return invalid data.

8.5.2 Write Sequence

The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is high.

The slave address is sent next. The slave address is a seven-bit address followed by the Read/Write bit (Read =

1'b and Write = 0'b). For the default base address of 0x66 (1100110'b), the 0 is appended to the end, and the net

address is 0xCC. Each byte sent after the address is followed by an ACK bit. When SCL is high, the master will

release the SDA line, and the slave pulls SDA low to acknowledge. Once the device address has been sent, the

next byte sent is the register address. Following the register address and the ACK, the data byte is sent. When

more than one data byte is sent, the register address is automatically incremented so that the data is written into

the next address location. The Write Sequence Timing Diagram is shown in Figure 19. Note that there is an ACK

bit following each data byte.

SCL

SDA

A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

S

t

S

t

a

r

t

o

p

A

C

K

A

C

K

A

C

K

A

C

K

R

e

a

d

2

Address

Data Byte 1

Data Byte n

I C

Slave

Address

$CD

Figure 19. Write Sequence Timing Diagram

24

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Programming (continued)

8.5.3 Read Sequence

Read sequences consist of two I²C transfers. The first is the address access transfer, which consists of a write

sequence that transfers only the address to be accessed. The second is the data read transfer which starts at

the address indicated in the first transfer and increments to the next address, continuing to read addresses until

a stop condition is encountered. The timing diagram of the address access transfer is shown in Figure 20. A read

sequence begins with a start pulse, the slave device address including the Read/Write bit (Read = 1'b and Write

= 0'b), and then its ACK bit. The next byte is the address to be read, followed by the ACK bit and the stop bit to

indicate the end of the address access transfer. The subsequent read data transfer shown consists of the start

pulse, the slave device address including the Read/Write bit (this time a R/W Bit = 1'b, indicating that the data is

to be read) and the ACK bit. The next byte is the data read from the initial access address. After each data byte

is read, the address is incremented, thereby allowing the next byte of data to be read from the subsequent

address of the device. Each byte is separated from the previous byte by an ACK bit, and the end of the read

sequence is indicated with a STOP bit. The timing diagram for a read data transfer is shown in Figure 21 for

additional timing details.

SCL

SDA

A7 A6 A5 A4 A3 A2 A1 A0

1

0

1

0

S

t

S

t

a

r

t

o

p

A

C

K

A

C

K

W

r

I

t

e

2

Address

I C

Slave

Address

$CC

Figure 20. Read Sequence — Address Access Transfer

SCL

SDA

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

1

0

S

t

S

t

a

r

t

o

p

A

C

K

A

C

K

A

C

K

R

e

a

d

2

Data Byte 1

Data Byte n

I C

Slave

Address

$CD

Figure 21. Read Sequence — Data Read Transfer

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8.6 Register Map

The following table provides details on the device's configuration registers. Default value for fields that are seven

bits or less are expressed in binary, and default values for fields that are 8 bits (Byte) are expressed in hex. Do

not write to Reserved (RSVD) fields.

Table 3. LMH1983 Register Map

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

7

INTERLACED

R

—

Indicates if the input reference format is an interlaced format

This bit is set depending on if the sync detection circuit had

determined if the reference is an analog or digital derived

signal

6

ANALOG_REF

R

—

Returns the value of the input polarity determined by the sync

detector for HSYNC — 0 indicates an active low sync

5

4

INPUT_POLARITY

HSYNC_STATUS

R

—

Device Status

— Input Reference

This bit is set if the Hsync During Vsync detector will set

NO_H_DURING_V on the next rising edge of VSYNC

0x00

3

2

H_ONLY

R

—

This is set by the Interlaced detector

LOR_STATUS

Returns the inverse of the NO_REF output pin state

Set if HSYNC_MISSING is high wile no_h_during_v is low.

Remains set until read, then self-clears

1

LOST_HSYNC

R

—

0

Reserved

R

0

Reserved — always returns '0'

7

Lock_Status

Align_Status

Wrong_Format

Holdover

1

0

Returns lock status for all unmasked and enabled PLLs

Returns the Align Status for all enabled TOFs

Returns the value of the Wrong_Format bit.

Returns the value of the PLL Holdover Bit

Reserved

6

0x01 Device Status

5

1

4

0

3:0

RSVD

0000

[7] indicates the lock status of PLL4.

[6] indicates the lock status of PLL3.

[5] indicates the lock status of PLL2.

[4] indicates the lock status of PLL1.

0 = PLL Not Locked

7:4

3:0

Lock_Detect

Align_Detect

R

—

1 = PLL Locked

PLL Lock and Output

Alignment Status

0x02

[3] indicates the lock status of TOF4.

[2] indicates the lock status of TOF3.

[1] indicates the lock status of TOF2.

[0] indicates the lock status of TOF1.

0 = TOF Alignment not detected

1 = TOF alignment detected

R

0x03 Revision ID

0x04 Reserved

7:0

0xC0

0x00

Returns device revision code

Reserved

RSVD

Writing a ‘1’ will reset all registers to their default values. This

bit is self-clearing and always returns ‘0’ when read.

7

6

Soft_Reset

Powerdown

R/W

0

Controls the power down function.

Enables Auto Format Detection (AFD).

0 = Auto Format Detect disabled

1 = Auto Format Detect enabled

5

EN_AFD

R/W

1

Sets PLL1 operating mode:

00 = Force Free-run

01 = Genlock

4:3

PLL1_Mode

R/W

01

10 = Force Holdover

11 = Reserved

0x05 Device Control

Sets default mode of operation on Loss of Reference (LOR)

condition:

0 = Holdover on LOR

1 = Free-run on LOR

2

LOR Mode

R/W

0

When this bit is set, it forces the PLL2 and PLL3 clock rates to

148.xx MHz regardless of chosen output format. Otherwise,

the native clock rate of the chosen output format will be used.

0 = Uses the native clock rates

1 = Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz clock

rate

1

0

Force_148

GOE

R/W

1

Global Output Enable

0 = Disables all CLKout and Fout output buffers (Hi-Z)

1 = Enable active outputs

26

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

7:4

RSVD

0000

Reserved

Enables Auto Polarity Detection and Correction. The proper

polarity needs to be set to synchronize the output timing

signals to the leading edges of the H and V inputs.

0 = The polarities of HVF inputs are manually set by their

respective polarity override registers.

3

EN_AUTOPOL

R/W

1

1 = The polarity of the H input is auto-detected. The polarity

correction applied to the H input will also be applied to V and

F inputs.

0x06 Input Polarity

Used to manually set the H input Polarity.

0 = Active Low (Negative polarity)

1 = Active High (Positive polarity)

2

1

0

HIN_POL_OVR

VIN_POL_OVR

FIN_POL_OVR

R/W

0

Used to manually set the V input Polarity.

0 = Active Low (Negative polarity)

1 = Active High (Positive polarity)

Used to manually set the F input Polarity.

0 = Active Low (Negative polarity)

1 = Active High (Positive polarity)

7:6

5:0

7:6

5:0

7:5

RSVD

00

001110

00

Reserved

0x07 Output Mode – PLL2 Format

0x08 Output Mode – PLL3 Format

PLL2_Format

RSVD

R/W

Sets the video format output timing for PLL2.

Reserved

PLL3_Format

RSVD

001101

000

Sets the video format output timing for PLL3.

Reserved

Sets the TOF4 output timing mode.

4

AFS Mode

XPT_Mode

R/W

0

0 = Secondary Audio Clock Output (derived from PLL4 clock)

1 = Audio Frame Sync (derived from TOF1)

0x09 Output Mode – Misc

Sets the PLL crosspoint mode for Out2 and Out3.

Refer to Table 4.

3:0

0000

[3] sets CLKout4 output buffer mode.

[2] sets CLKout3 output buffer mode.

[1] sets CLKout2 output buffer mode.

[0] sets CLKout1 output buffer mode.

0 = CLKoutx enabled

7:4

3:0

CLK_HIZ

R/W

0000

1111

1 = CLKoutx Hi-Z

0x0A Output Buffer Control

[3] sets Fout4 output buffer mode.

[2] sets Fout3 output buffer mode.

[1] sets Fout2 output buffer mode.

[0] sets Fout1 output buffer mode.

0 = Foutx enabled

FOUT_HIZ

1 = Foutx Hi-Z

7:5

4:0

RSVD

000

Reserved

Output Frame Control –

Offset1_MSB

0x0B

TOF1 Offset MSB

R/W

00000

TOF1_Offset[12:0] sets number of lines to delay TOF1.

TOF1_Offset_MSB[4:0] sets TOF1_Offset[12:8]

TOF1_Offset_LSB[7:0] sets TOF1_Offset[7:0]

Output Frame Control –

Offset1_LSB

0x0C

7:0

TOF1 Offset LSB

0x00

7:5

4:0

RSVD

000

Reserved

Output Frame Control –

Offset2_MSB

0x0D

TOF2 Offset MSB

R/W

00000

TOF2_Offset[12:0] sets number of lines to delay TOF2.

TOF2_Offset_MSB[4:0] sets TOF2_Offset[12:8]

TOF2_Offset_LSB[7:0] sets TOF2_Offset[7:0]

Output Frame Control –

Offset2_LSB

0x0E

7:0

TOF2 Offset LSB

0x00

7:5

4:0

RSVD

000

Reserved

Output Frame Control –

Offset3_MSB

0x0F

TOF3 Offset MSB

R/W

00000

TOF3_Offset[12:0] sets number of lines to delay TOF3.

TOF3_Offset_MSB[4:0] sets TOF3_Offset[12:8]

TOF3_Offset_LSB[7:0] sets TOF3_Offset[7:0]

Output Frame Control –

Offset3_LSB

0x10

7:0

TOF3 Offset LSB

0x00

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

7:6

RSVD

00

Reserved

00 = Auto-align when misaligned

01 = Reserved

5:4

TOF1_Align_Mode

R/W

11

10 = Always Align

11 = Never Align⁽¹⁾

This bit sets the PLL1/TOF1 output synchronization behavior

when the same reference is reapplied following a momentary

LOR condition and TOF1 is within 2 lines of the expected

location.

00 = Always Drift Lock – ensures the outputs drift smoothly

back to frame alignment without excessive output phase

disturbances

01 = Drift Lock if output < (2^LOA_windowx 27 MHz Clock). Crash

Lock otherwise.

3:2

TOF1_Sync

R/W

01

0x11 Alignment Control – TOF1

1X = Always Crash Lock – achieves the fastest frame

alignment through PLL/TOF counter resets, which can result in

output phase disturbances

Sets the direction that TOF1 slews to achieve frame alignment

when a new reference is applied and TOF1 is outside of 2

lines of the expected location.

0 = TOF1 lags by railing the VCXO input low

1 = TOF1 advances by railing the VCXO input high

1

TOF1_Sync_Slew

R/W

0

RSVD

0

Reserved

7:6

00

00 = auto align when misaligned

01 = one shot manual align when writing TOF2_INIT=1

10 = always align

5:4

3:1

TOF2_Align_Mode

RSVD

11

11 = never align

000

Reserved

0x12 Alignment Control – TOF2

Writing one to this bit while also writing TOF2_Align_Mode =

3, will cause the TOF2_INIT output to go high for at least one

vframe period + one Hsync period and not more than one

vframe period + two Hsync periods. The assertion of

TOF2_INIT must happen immediately (it cannot wait for

Hsync). If TOF2_Align_Mode is being written to 3, this bit will

have no effect. This bit is self-clearing and will always read

zero.

0

TOF2_INIT

0

7:6

5:4

3:1

RSVD

00

11

Reserved

00 = auto align when misaligned

01 = one shot manual align when writing TOF3_INIT=1

10 = always align

TOF3_Align_Mode

RSVD

R/W

11= never align

000

Reserved

0x13 Alignment Control – TOF3

Writing one to this bit while also writing TOF3_Align_Mode ≠

3, will cause the TOF3_INIT output to go high for at least one

vframe period + one Hsync period and not more than one

vframe period + two Hsync periods. The assertion of

0

TOF3_INIT

0

TOF3_init must happen immediately (it cannot wait for Hsync).

If TOF3_Align_Mode is being written to 3, this bit will have no

effect. This bit is self-clearing and will always read zero.

(1) NOTE: When H_ONLY is 1, TOF1 align mode is forced to never align.

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

7:6

RSVD

00

Reserved

00 = auto align when misaligned

01 = one shot manual align. AFS_Init_Input reg determines if

done by pin (INIT) or register (AFS_INIT = 1)

10 = always align

5:4

AFS_Align_Mode

11

11= never align

0 = Rising edges on INIT (pin 6) trigger AFS one shot manual

align.

3

AFS_Init_Input

RSVD

0

1 = Writing ‘1’ to AFS_Init register triggers AFS one shot

manual align.

0x14 Alignment Control – AFS

2:1

00

Reserved

Writing one to this bit while also writing AFS_Align_Mode = 3

and AFS_Init_Input=1, or providing a rising edge on the init

input when AFS_Align_Mode ≠ 3 and AFS_Init_Input=0, will

cause the AFS_INIT output to go high for at least one vframe

period + one Hsync period and not more than one vframe

period + two Hsync periods. The assertion of AFS_INIT must

happen immediately (it cannot wait for Hsync). If

0

AFS_INIT

R/W

0

AFS_Align_Mode = 3, toggling the init input will have no effect.

This bit is self-clearing and will always read zero.

7:3

2:0

7:2

RSVD

00000

010

Reserved

Number of 27 MHz clocks between the TOF1 and Vsync

before Loss of Alignment is reported.

If the code loaded in this register is n, then Loss of Alignment

will be reported if the difference between TOF1 and Vsync

exceeds 2ⁿ27 MHz clock cycles

0x15 Loss of Alignment Control

LOA_Window

RSVD

R/W

000000

Reserved

The VC_Hold[9:0] input signal changes rather slowly. For

synchronization, it should be sampled on consecutive 27 MHz

clocks until two identical values are found. This value will be

saved as VC_Hold_sampled[9:0].

LOR Control – Holdover

0x16

Whenever the VC_Hold[9:8] register is read,

Sampled Voltage MSB

1:0

VC_Hold_MSB

R

10

VC_Hold_sampled[9:8] is returned, and VC_Hold[7:0] will

memorize the current value of VC_Hold_sampled[7:0] (to be

read at a later time).

This scheme allows a coherent 10-bit value to be read.

Returns a synchronized snapshot of the VC_Hold[9:8] (MSB).

The VC_Hold[9:0] input signal changes rather slowly. For

synchronization, it should be sampled on consecutive 27 MHz

clocks until two identical values are found. This value will be

saved as VC_Hold_sampled[9:0].

LOR Control – Holdover

0x17

Whenever the VC_Hold[9:8] register is read,

7:0

VC_Hold_LSB

R

—

Sampled Voltage LSB

VC_Hold_sampled[9:8] is returned, and VC_Hold[7:0] will

memorize the current value of VC_Hold_sampled[7:0] (to be

read at a later time).

This scheme allows a coherent 10-bit value to be read.

Returns a synchronized snapshot of the VC_Hold[7:0] (LSB)

7:2

1:0

RSVD

Reserved

LOR Control Free-run

0x18

Free-run Control Voltage (VC_Free[9:0]) is the voltage

asserted on VC_LPF pin in free-run mode.

Writing will change the MSB (VC_Free[9:8])

Control Voltage MSB

VC_Free_MSB

R/W

01

Free-run Control Voltage (VC_Free[9:0]) is the voltage

asserted on VC_LPF pin in free-run mode.

Writing will change the LSB (VC_Free[7:0])

LOR Control – Free-run

0x19

7:0

7:2

1

VC_Free_LSB

RSVD

0xFF

000000

0

Control Voltage LSB

Reserved

Directly controls the ADC_Disable output port.

0 = enable holdover ADC

1 = disable holdover ADC

ADC_Disable

R/W

LOR Control – ADC and

DAC Disable

0x1A

Directly controls the DAC_Disable output port.

0 = enable Free-run/Holdover DAC

0

DAC_Disable

0

1 = disable Free-run/Holdover DAC

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

7

RSVD

0

Reserved

HSYNC_Missing

Threshold

Sets the threshold for number of additional clocks to wait

before setting HSYNC_Missing.

6:4

3

R/W

00

0

Loss of Reference

Threshold

0x1B

RSVD

Reserved

Sets the number of Hsync periods to wait before setting loss

of reference. Since during blanking there can have up to 5

missing Hsync pulses, this value is usually set to 6.

2:0

7:5

4:0

LOR_Threshold

RSVD

R/W

001

000

Reserved

Sets the number of Hsync periods to wait before setting loss

of lock. Since during blanking there can have up to 5 missing

Hsync pulses, this value is usually set > 6.

0x1C Loss of Lock Threshold

LOCK1_Threshold

10000

Setting this bit masks the PLL4 lock status in the global

LOCK_STATUS bit.

7

6

5

4

3

2

1

0

MASK_LOCK4

R/W

0

Setting this bit masks the PLL3 lock status in the global

LOCK_STATUS bit.

MASK_LOCK3

Setting this bit masks the PLL2 lock status in the global

LOCK_STATUS bit.

MASK_LOCK2

Setting this bit masks the PLL1 lock status in the global

LOCK_STATUS bit.

MASK_LOCK1

Mask Control – PLL Lock

0x1D

and Output Align

Setting this bit masks the TOF4 align status in the global

ALIGN_STATUS bit.

MASK_TOF4_ALIGN

MASK_TOF3_ALIGN

MASK_TOF2_ALIGN

MASK_TOF1_ALIGN

Setting this bit masks the TOF3 align status in the global

ALIGN_STATUS bit.

Setting this bit masks the TOF2 align status in the global

ALIGN_STATUS bit.

Setting this bit masks the TOF1 align status in the global

ALIGN_STATUS bit.

0x1E Reserved

0x1F Reserved

7:0

7:6

RSVD

0x00

00

Reserved

When Auto Format Detection is enabled (EN_AFD, address

0x05), this register is read-only and controlled automatically.

When Auto Format Detection is disabled, this register is

writable via I²C.

All writes to this register (whether automatic or manual) will

update all the LUT1 (Lookup Table 1), LUT2_2, and LUT2_3

output registers based on the value written here. Writing to

any of the LUT1, LUT2_2, or LUT2_3 output registers will set

this field to 6’d62 (0x3E) indicating that custom changes have

been made.

0x20 Input Format

5:0

Input Format

000000

7:4

3:0

RSVD

00

Reserved

Writes to this register update the Vsync code which tells the

device what the Input frame rate is. There is a table which

correlates the Vsync codes to the actual frame rates. When

Auto Format Detection is enabled (EN_AFD, address 5), this

register is read-only, and is automatically loaded by the

device.

Output Frame Lookup –

0x21

Input Vsync Code

R/W

0011

7:4

3:0

7:4

3:0

7:0

RSVD

00

Reserved

Whenever PLL2_FORMAT (address 7) is written, this field is

updated with the appropriate Vsync code. If any custom

changes are made the device will set this field to 4’d14 (0x0E)

to so indicate.

Output Frame Lookup –

0x22

PLL2 Vsync Code

RSVD

R/W

0101

0000

0110

0x00

Reserved

Whenever PLL3_FORMAT (address 8) is written, this field is

updated with the appropriate Vsync code. If any custom

changes are made the device will set this field to 4’d14 (Ox0E)

to so indicate.

Output Frame Lookup –

0x23

PLL3 Vsync Code

RSVD

0x24 Reserved

Reserved

30

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

7:5

4

RSVD

000

Reserved

0 = Divide by 1 (Output is 27 MHz)

1 = Divide by 2 (Output is 13.5 MHz)

PLL1_DIV

RSVD

R/W

0

3

Reserved

Directly controls the mode of the PLL1 input buffer.

0 = Single Ended

1 = Differential

2

1

PLL1 Input Mode

RSVD

R/W

0

0x25 PLL1 Advanced Control

Reserved

This bit enables ICP1_FAST (address 0x27) to be used during

locking.

0 = FastLock disabled

1 = FastLock enabled

0

FastLock

RSVD

1

7:4

0000

Reserved

Sets the amount of time that PLL1_Lock must be asserted

before the PLL1 Charge pump current is reduced from the

ICP1_Fast value to the ICP1 value. The time delay is specified

in units of half seconds. Delay = FastlockDelay*0.5 Seconds.

Valid values are from 0 to 10. Values from 11 to 15 are

reserved.

PLL1 Advanced Control

0x26

FastLock Delay

3:0

FastLock Delay

R/W

0000

This field specifies the charge pump current to drive when

FastLock is active. Charge pump current is equal to 34.375 µA

* register value

PLL1 Advanced Control

0x27

FastLock Charge Pump

Current

4:0

R/W

11111

01000

Fastlock CP Current

This field defines the charge pump current used when

FastLock is not active. Charge pump current is equal to

34.375 µA * register value

PLL1 Advanced Control

0x28

PLL1 Charge Pump

Current

Charge Pump Current

7:2

1:0

RSVD

MSB

000000

00

Reserved

PLL1 Advanced Control

0x29

R Counter MSB

R/W

The two LSBs of Register 0x29 along with the eight bits of

Register 0x2A form a ten bit word which comprises the R

divider for PLL1. This register is internally written based on the

input format and when AutoFormatDetect is enabled, these

registers are read only.

PLL1 Advanced Control

0x2A

7:0

LSB

0x01

R Counter LSB

7

RSVD

MSB

0

Reserved

PLL1 Advanced Control

0x2B

N Counter MSB

6:0

R/W

0000110

The 7 LSBs of Register 0x2B along with the eight bits of

Register 0x2C comprise the fifteen bit word which is used for

the N divider of PLL1. These registers are internally controlled

based on the input format detected and when

PLL1 Advanced Control

0x2C

7:0

LSB

0xB4

N Counter LSB

AutoFormatDetect is enabled, these registers are read only.

7:5

4:0

7:5

RSVD

000

01000

000

Reserved

PLL1 Advanced Control

0x2D

Lock Step Size

RSVD

R/W

See Application Information section discussion on Lock Detect

Reserved

0 = divide by 1

1 = divide by 2

4

3

PLL2_DIV

R/W

0

PLL2 Advanced Control

0x2E

Main

0 = PLL2 disable is determined by XPT_MODE (Address

0x09)

PLL2_DISABLE

1 = PLL2 is disabled

2:0

7:4

3:0

RSVD

ICP2

000

0000

0010

Reserved

PLL2 Advanced Control

0x2F

Charge Pump Current

R/W

Controls PLL2 Charge Pump Current

PLL2 Advanced Control

VCO Range

0x30

7:0

7:5

4

VCO_RNG2

RSVD

0x0C

000

0

Controls the VCO range

Reserved

0 = divide by 1

1 = divide by 2

PLL3_DIV

R/W

PLL3 Advanced Control

0x31

Main

0 = PLL3 disable is determined by XPT_MODE (Address

0x09)

3

ICP3

0

1 = PLL3 is disabled

2:0

7:4

3:0

RSVD

ICP3

000

0000

0011

Reserved

PLL3 Advanced Control

0x32

Charge Pump Current

R/W

Controls PLL3 Charge Pump Current

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

DESCRIPTION

PLL3 Advanced Control

VCO Range

0x33

7:0

7:4

VCO_RNG3

R/W

0x05

Controls the VCO range

Controls the PLL4 output divider — PLL4 is divided by

2^PLL4_DIV

PLL4_DIV

R/W

0010

0 = PLL4 is enabled

1 = PLL4 is disabled

3

2

1

PLL4_Disable

RSVD

0

PLL4 Advanced Control

Main

0x34

Reserved

0 = 100 MHz clock

1 = 125 MHz clock

IS125M

R/W

0 = using 27 MHz Clock

1 = using external clock

0

PLL4_Mode

0

7:4

3:0

7

RSVD

0000

1000

0

Reserved

PLL4 Advanced Control

Charge Pump Current

0x35

0x36

0x37

ICP4

R/W

Controls PLL4 Charge Pump Current

Reserved

RSVD

PLL4 Advanced Control

R counter

6:0

7:2

1:0

DIV_R4

RSVD

1001011

000000

10

Sets the R divider in PLL4

Reserved

PLL4 Advanced Control

N counter MSB

DIV_N4_MSB

R/W

Two MSBs of the N divider in PLL4

PLL4 Advanced Control

N counter LSB

0x38

0x39

7:0

DIV_N4_LSB

VCO4 Range

0x00

0x16

8 LSBs of the N divider in PLL4

PLL4 Advanced Control

VCO Range

The value in the VCO4 Range register is used to adjust the

center frequency of PLL4.

R/W

7

LVDS Boost

LVDS_DIFF

LVDS_CM

RSVD

R/W

0

Applies pre-emphasis to LVDS output

Adjusts LVDS Differential output swing

Adjusts LVDS Common Mode output voltage

Reserved

0x3A LVDS Control

6:4

3:0

7:5

100

1001

000

TOF1 Adv Control

LPF MSB

5 MSBs of the TOF1 lines per Frame count. This is read-only

and loaded automatically when Auto Format Detection is

enabled

0x3B

4:0

TOF1_LPF_MSB

R

00010

8 LSBs of the TOF1 lines per Frame count. This is read-only

and loaded automatically when Auto Format Detection is

enabled

Together with Register 0x3B this is a 13 bit number which

number of lines per frame. TOF1 will be at a frequency of

Hsync divided by this value.

TOF1 Advanced Control

LPF_LSB

0x3C

7:0

TOF1_LPF_LSB

0x0D

7

RSVD

0

Reserved

TOF2 Advanced Control

CPL MSB

0x3D

0x3E

0x3F

6:0

TOF2_CPL_MSB

R

0001010

This 15 bit register gives the number of clock cycles per line to

calculate TOF2. It is loaded automatically based on the format

set with Register 0x07.

TOF2 Advanced Control

CPL LSB

7:0

TOF2_CPL_LSB

0x50

7:5

4:0

RSVD

000

Reserved

TOF2 Advanced Control

LPF MSB

TOF2_LPF_MSB

R

00010

This 13 bit register is loaded automatically based on the

format selected via Register 0x07. It sets the number of lines

per frame for the selected format to set the TOF2 rate

correctly.

TOF2 Advanced Control

LPF_LSB

0x40

7:0

TOF2_LPF_LSB

0x65

7:5

4:0

RSVD

000

Reserved

TOF2 Advanced Control

Frame Reset MSB

0x41

0x42

0x43

0x44

0x45

TOF2_RST_MSB

R

00010

Automatically loaded based on formats selected.

TOF2 Advanced Control

Frame Reset LSB

7:0

TOF2_RST_LSB

0x58

7

RSVD

0

Reserved

TOF3 Advanced Control

CPL_MSB

6:0

TOF3_CPL_MSB

R

0001000

This 15 bit register gives the number of clock cycles per line to

calculate TOF3. It is loaded automatically based on the format

set with Register 0x08.

TOF3 Advanced Control

CPL_LSB

7:0

TOF2_CPL_LSB

0x98

7:5

4:0

RSVD

000

Reserved

TOF3 Advanced Control

LPF_MSB

TOF3_LPF_MSB

R

00100

This 13 bit register is loaded automatically based on the

format selected via Register 0x08. It sets the number of lines

per frame for the selected format to set the TOF3 rate

correctly.

TOF3 Advanced Control

LPF_LSB

0x46

7:0

TOF3_LPF_LSB

0x65

32

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Register Map (continued)

Table 3. LMH1983 Register Map (continued)

ADD NAME

BITS FIELD

R/W

DEFAULT

000

DESCRIPTION

7:5

4:0

RSVD

Reserved

TOF3 Advanced Control

Frame Reset MSB

0x47

TOF3_RST_MSB

R

00000

Automatically loaded based on formats selected.

TOF3 Advanced Control

Frame Reset LSB

0x48

0x49

7:0

TOF3_RST_LSB

0x01

TOF4 Advanced Control

AFS

See Detailed Description section for details. See also PLL4

7:0

7:4

3:0

TOF4_AFS

RSVD

R/W

0x05

0000

1011

Block Diagram.

Reserved

TOF4 Advanced Control

ACLK

0x4A

See Detailed Description section for details. See also PLL4

TOF4_ACLK

Block Diagram.

0x4B

to

0x50

Reserved

7:0

RSVD

0x00

Reserved

User Auto Format

27M High Value MSB

User format detect is determined by looking at the frequency

of the Hsync input. This frequency is measured by counting

the number of 27 MHz clock cycles that occur in 20 Hsync

periods. This 16 bit register lists the maximum number of 27

MHz clock cycles in 20 Hsync periods that could be

0x51

0x52

0x53

0x54

USR_27M_High_MSB

R/W

User Auto Format

27M High Value LSB

7:0

USR_27M_High_LSB

USR_27M_Low_MSB

USR_27M_Low_LSB

0x00

considered to meet the criteria for the User Format

User Auto Format

27M Low Value MSB

User format detect is determined by looking at the frequency

of the Hysnc input. This frequency is measured by counting

the number of 27 MHz clock cycles that occur in 20 Hsync

periods. This 16 bit register lists the minimum number of 27

MHz clock cycles in 20 Hsync periods that could be

considered to meet the criteria for the User Format

User Auto Format

27M Low Value LSB

7:2

1:0

RSVD

000000

00

Reserved

User Auto Format

R divider MSB

0x55

0x56

0x57

USR_DIV_R1_MSB

R/W

See Detailed Description section for details.

User Auto Format

R Divider LSB

7:0

USR_DIV_R1_LSB

0x00

See Detailed Description section for details.

7

RSVD

0

Reserved

User Auto Format

N Divider MSB

6:0

USR_DIV_N1_MSB

R/W

0000000

See Detailed Description section for details.

User Auto Format

N Divider LSB

0x58

0x59

7:0

USR_DIV_N1_LSB

USR_ICP

0x00

See Detailed Description section for details.

User Auto Format

Charge Pump Current

R/W

7:5

4:0

RSVD

000

Reserved

User Auto Format

LPF MSB

0x5A

USR_TOF_LPF_MSB

R/W

00000

See Detailed Description section for details.

User Auto Format

LPF LSB

0x5B

0x5C

7:0

USR_TOF_LPF_MSB

USR_TOF4

0x00

See Detailed Description section for details.

User Auto Format

AFS

R/W

Enables the Auto Format Detection User Mode.

0 = disabled

1 = enabled

7

EN_USERMODE

RSVD

0

6:5

00

Reserved

User Auto Format

Misc

Sets the INTERLACED value to output from LUT1 if the

INPUT_FORMAT register is set to the user code. This bit also

specifies the value that the Auto Format Detection must see

on the interlaced signal to detect the user defined mode.

0x5D

4

USR_IINTERLACED

USR_IN_VS_CODE

R/W

0

Sets the INPUT_VS_CODE value to output from LUT1 if the

INPUT_FORMAT registers is set to the user code.

3:0

0000

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Table 4. Crosspoint Output Selection Table

REGISTER 0x09 [3:0]

PLL2_DISABLE⁽¹⁾

PLL3_DISABLE⁽¹⁾

OUT2 SOURCE

PLL2

OUT3 SOURCE

0000 (default)

0001

0

PLL3

PLL1

1

PLL1

0010

0

1

PLL2

0011

1

0

PLL3

0100

0

PLL3

PLL2

0101

1

0

PLL1

PLL3

0110

0

1

PLL2

PLL1

0111

0

1

PLL1

PLL2

1000

1

0

PLL3

PLL1

1001

Reserved

1010

1011

1100

1101

1110

1111

(1) PLL2_Disable and PLL3_Disable can be forced via register writes to the PLLx_DISABLE registers independently of the status of the

Crosspoint Mode bits.

Table 5. Vsync Codes

Vsync CODE

FRAME RATE (Hz)

NUMBER (BINARY)⁽¹⁾

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

23.98 Hz

24 Hz

25 Hz

29.97 Hz

30 Hz

50 Hz

59.94 Hz

60 Hz

(1) Vsync codes are used by Registers 0x21 (Output Frame Lookup –

Input Vsync Code), 0x22 (Output Frame Lookup – PLL2 Vsync

Code), and 0x23 (Output Frame Lookup – PLL3 Vsync Code).

34

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9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at a

variety of video and audio rates, synchronized or “genlocked” to Hsync and Vsync input reference timing. The

LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with

programmable timing that can also be synchronized to the reference frame. The clock generator uses a two-

stage PLL architecture to attenuate input timing jitter for minimum jitter transfer. The combination of the external

VCXO, external loop filter, and programmable PLL parameters provides flexibility to optimize the loop bandwidth

and loop response for design applications.

9.2 Typical Applications

9.2.1 Typical Genlock Timing Generation with NTSC 525i/29.97 High Speed Reference

The LMH1983 is commonly used with Hsync, Vsync, and Fsync timing signals as a reference for genlock. Once

these signals are provided, the LMH1983 can produce a specific set of clock output signals required by a

downstream endpoint. In some video applications, a multi-format video sync separator is used to derive the

Hsync, Vsync, and Fsync signals from a standard analog SD/ED/HD video signal. In Figure 22, a LMH1981

multi-format sync separator is used to provide H_IN, V_IN, and F_INfor the LMH1983. In this case, LMH1983 PLLs 1-

4 provide a 27 MHz/29.97 Hz, 148.5 MHz/29.97 Hz, 148.35 MHz/59.94 Hz, and 24.576 MHz/5.994 Hz output,

respectively, to an A/V Frame Synchronizer. Another example of this application can be seen in Figure 23, where

H_IN, V_IN, and F_INsignals are provided directly from an FPGA SDI RX without a sync separator. In the latter

example, the NTSC 525i/29.97 H_IN, V_IN, and F_INparameters are provided individually for the LMH1983, after

which the LMH1983 provides 3G, 3G/1.001, and Audio Clock Generation.

LOOP

FILTER

27 MHz

VCXO

27 MHz (PLL1)

525i

Analog

ref. in

H sync

V sync

F sync

CLKout1

29.97 Hz (TOF1)

525i/29.97 SDI out

+ embedded audio

LMH1981

Sync

Separator

Hin

Vin

Fin

148.5 MHz (PLL2)

29.97 Hz (TOF2)

CLKout2

CLKout3

FPGA

1080p/59.94 SDI out

+ embedded audio

A/V Frame Sync with

Downconverter,

Audio Embedder and

De-embedder

LMH1983

148.35 MHz (PLL3)

59.94 Hz (TOF3)

1080p/59.94 SDI in

+ embedded audio

24.576 MHz (PLL4)

5.994 Hz

CLKout4

Genlocked to video ref. in

Figure 22. LMH1983 Video Genlock Timing Generation for A/V Frame Synchronizer

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Typical Applications (continued)

LOOP

FILTER

27 MHz

VCXO

27 MHz

525i/29.97 SDI out

+ embedded audio

H blank

V blank

F blank

CLKout1

525i/29.97 digital

blanking pulse inputs

from FPGA SDI RX

Hin

Vin

Fin

1080i/29.97 SDI out

+ embedded audio

148.5 MHz (PLL2)

148.35 MHz (PLL3)

CLKout2

CLKout3

CLKout4

HD-SDI Upconverter

(HD/SD Simulcast)

with Audio Embedder

LMH1983

525i/29.97 SDI in

+ embedded audio

24.576 MHz

PLL1 Ref. In Format = 525i/29.97

PLL2 Video Format = 525i/29.97*

PLL3 Video Format = 1080i/29.97*

A/V clock signals

genlocked to SDI in

PLL4 Audio Format = 24.576 MHz with 48 kHz word clock

* GHQRWHVꢀ³3*ꢀ&/.´ꢀPRGHꢀ(148.5 or 148.35 MHz)

Figure 23. LMH1983 Video Timing Generation for HD-SDI Up-Conversion with Audio Embed/De-embed

9.2.1.1 Design Requirements

When designing for the LMH1983, it is essential to choose the correct VCXO and external loop filter capacitors.

The following subsections provide guidance regarding how to select these components to improve timing stability

and accuracy.

9.2.1.1.1 VCXO Selection Criteria

The recommended VCXO is CTS part number 357LB3C027M0000, which has an absolute pull range of ±50 ppm

and a temperature range of –20°C to +70°C. A VCXO with a smaller APR can provide better frequency stability

and slightly lower jitter, but the APR must be larger than the anticipated variation of the input frequency range.

9.2.1.1.2 Loop Filter Capacitors

The most common types of capacitors used in many circuits today are ferroelectric ceramic capacitors such as

X7R, Y5V, X5R, Y5U, and so on. These capacitors suffer from piezoelectric effects, which generate an electrical

signal in response to mechanical vibration, stress, and shock. This effect can adversely affect the jitter

performance when presented to the control input to the VCXO. The easiest way to eliminate this effect is to use

tantalum capacitors that do not exhibit the piezoelectric effect.

9.2.1.2 Detailed Design Procedure

Once the appropriate external VCXO and loop filter components are selected, the input timing signaling should

be referenced to Table 2 to determine whether NTSC 525i/29.97 sync format is supported. This video format is a

supported video format for automatic detection under Auto Format Detection Code 0, so it is not necessary to

override the input auto-detection feature.

Once PLL1 has genlocked to the chosen NTSC, 525i input reference signal, PLLs 2-3 can be set according to

the desired output signals specified in Figure 23. Refer to Table 6 and Table 7 for a list of possible input and

output formats available for auto-format detection in Figure 22 and Figure 23, respectively. The format code can

be applied as an expected input format for PLL1 (Register 0x20) or a programmed output format for PLL2

(Register 0x07) and PLL3 (Register 0x08).

Table 6. Relevant Auto-Format Detection Codes for Figure 22

PLLx

(INPUT/OUTPUT)

HSync PERIOD

(in 27 MHz CLOCKS)

FORMAT CODE

DESCRIPTION

PLL1 (Input)

PLL2 (Output)

PLL3 (Output)

0

525I29.97

1716

400.4

13

1080P59.94

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Table 7. Relevant Auto-Format Detection Codes for Figure 23

PLLx

(INPUT/OUTPUT)

HSync PERIOD

(in 27 MHz CLOCKS)

FORMAT CODE

DESCRIPTION

PLL1 (Input)

0

525I29.97

1080I29.97

1716

800.8

PLL2 (Output)

PLL3 (Output)

21

To ensure correct auto-detection and CLKout signaling desired in Figure 22 and Figure 23, the following SMBus

register values should be verified or changed from their default values.

Table 8. SMBus Register Settings for Figure 22

Register[Bit(s)]

0x05[5]

WRITE VALUE

1'b

COMMENTS

Auto Format Detect enabled

0x05[4:3]

0x05[1]

01'b

PLL1 operating in Genlock mode

1'b

Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz

Set PLL2 Output to Format Detection Code 0 (0x00)

Set PLL3 Output to Format Detection Code 13 (0x0D)

Set to always align when misaligned

0x07[5:0]

0x08[5:0]

0x11[5:4]

0x11[3:2]

0x12[5:4]

0x13[5:4]

0x14[5:4]

0x34[7:4]

000000'b

001101'b

10'b

01'b

Drift lock (small misalignment), crash lock (large misalignment)

Set TOF2 to always align when misaligned

10'b

Set TOF3 to always align when misaligned

10'b

Set AFS_Align_Mode to always align when misaligned

Set PLL4_DIV to divide-by-4 for 24.576 MHz

0010'b

Table 9. SMBus Register Settings for Figure 23

Register[Bit(s)]

0x05[5]

WRITE VALUE

1'b

COMMENTS

Auto Format Detect enabled

0x05[4:3]

0x05[1]

01'b

PLL1 operating in Genlock mode

1'b

Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz

Set PLL2 Output to Format Detection Code 0 (0x00)

Set PLL3 Output to Format Detection Code 21 (0x15)

Set to always align when misaligned

0x07[5:0]

0x08[5:0]

0x11[5:4]

0x11[3:2]

0x12[5:4]

0x13[5:4]

0x14[5:4]

0x34[7:4]

000000'b

010101'b

10'b

01'b

Drift lock (small misalignment), crash lock (large misalignment)

Set TOF2 to always align when misaligned

Set TOF3 to always align when misaligned

Set AFS_Align_Mode to always align when misaligned

Set PLL4_DIV to divide-by-4 for 24.576 MHz

10'b

0010'b

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9.2.1.3 Application Curves

10 ns / div

20 µs / div

Traces 1-4: 1V / div

Traces 1-3: 2V / div

Figure 24. CLKout 1-4 Signals after Genlock to 525i/29.97

Input Reference

Figure 25. TOF1 Falling Edge Alignment with HSync and

VSync Reference Timing

20 µs / div

Traces 1-3: 2 V / div

Traces 1-4: 2 V / div

Figure 26. TOF1 Alignment Comparison to HSync and

VSync Reference Timing

Figure 27. TOF1 and TOF3 Alignment on Rising Edge

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9.2.2 A/V Clock Generation with Recognized Clock-based Input Reference

The LMH1983 is shown in the following application example where the H_INinput reference timing signal is clock-

based. After achieving genlock, the LMH1983 can produce a specific set of clock output signals required

downstream. In this case, LMH1983 PLLs 1-4 provide a 27 MHz, 74.25 MHz, 74.176 MHz, and 98.304 MHz

output, respectively.

LOOP

FILTER

27 MHz

VCXO

27 MHz

CLKout1

Other clock inputs supported

32, 44.1, 48 or 96 kHz (Audio)

27 MHz (Video)

Hin

74.25 MHz (PLL2)

74.176 MHz (PLL3)

10 MHz (GPS)

CLKout2

CLKout3

CLKout4

A/V clock signals

genlocked to

clock ref. in

LMH1983

98.304 MHz

PLL1 Ref. In Format = Audio word, 27 MHz, or 10 MHz clock

PLL2 Video Format = 1080i/25

PLL3 Video Format = 1080i/29.97

PLL4 Audio Format = 98.304 MHz with 48 kHz word clock

Figure 28. LMH1983 A/V Clock Generation with Non-Format Specific Input Clock Reference

9.2.2.1 Design Requirements

When designing for the LMH1983, it is essential to ensure that the correct VCXO and external loop filter

capacitors are chosen. Refer to VCXO Selection Criteria and Loop Filter Capacitors for guidance regarding how

to select these components to improve timing stability and accuracy.

9.2.2.2 Detailed Design Procedure

Once the appropriate external VCXO and loop filter components are selected, the input timing signaling should

be referenced to the "Supported Formats Lookup Table (LUT)" (see Table 2) to determine whether the video

clock, GPS clock, and audio clock are supported by automatic format detection. From Table 2 and the Auto

Format Detection Codes, all of the reference clock inputs mentioned in this application are supported under the

auto format detection feature. Once PLL1 has genlocked to the chosen H_INsignal, PLLs 2-3 can be set

according to the desired output signals specified in Auto Format Detection Codes. Refer to Table 10 for a list of

possible input and output formats available for auto-format detection in this application. The format code can be

applied as an expected input format for PLL1 (Register 0x20) or a programmed output format for PLL2 (Register

0x07) and PLL3 (Register 0x08).

Table 10. Relevant Auto-Format Detection Codes for Figure 28

HSync PERIOD

(in 27 MHz CLOCKS)

PLLx (INPUT/OUTPUT)

FORMAT CODE

DESCRIPTION

PLL2 (Output)

PLL3 (Output)

PLL1 (Input)

22

21

25

26

27

28

29

30

1080I25

960

800.8

562.5

281.25

612.244898

843.75

1

1080I29.97

48 kHz Audio

96 kHz Audio

44.1 kHz Audio

32 kHz Audio

27 MHz HSync

10 MHz HSync

2.7

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To ensure correct auto-detection and the correct CLKout signaling desired in Figure 28, the following SMBus

register values should be verified or changed from their default values.

Table 11. SMBus Register Settings for Figure 28

REGISTER[Bit(s)]

0x05[5]

WRITE VALUE

1'b

COMMENTS

Auto Format Detect enabled

0x05[4:3]

0x05[1]

01'b

PLL1 operating in Genlock mode

0'b

Allow PLL2 and PLL3 to use the native clock rates

Set PLL2 Output to Format Detection Code 22 (0x16)

Set PLL3 Output to Format Detection Code 21 (0x15)

Set to always align when misaligned

0x07[5:0]

0x08[5:0]

0x11[5:4]

0x11[3:2]

0x12[5:4]

0x13[5:4]

0x14[5:4]

0x2E[4]

010110'b

010101'b

10'b

01'b

Drift lock (small misalignment), crash lock (large misalignment)

Set TOF2 to always align when misaligned

Set TOF3 to always align when misaligned

Set AFS_Align_Mode to always align when misaligned

Set PLL2_DIV to divide-by-2 for 74.25 MHz

Set PLL3_DIV to divide-by-2 for 74.176 MHz

Set PLL4_DIV to divide-by-1 for 98.304 MHz

10'b

1'b

0x31[4]

1'b

0x34[7:4]

0000'b

9.2.2.3 Application Curve

10ns / div

Traces 1-4: 1V / div

Figure 29. CLKout 1-4 Signals after Genlock to Clock-Based Reference

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9.2.3 A/V Clock Generation Using Free-Run Mode

The LMH1983 can be used in free-run mode, as shown in the following application example. No H_IN, V_IN, and F_IN

input reference timing signals are provided. Instead, the LMH1983 tracks a 27 MHz TCXO reference, which

replaces the external VCXO and loop filter mentioned in previous applications. The LMH1983 can still produce a

specific set of clock output signals required by a downstream endpoint. In this application, LMH1983 PLLs 1-4

provide a 27 MHz, 148.5 MHz, 148.35 MHz, and 98.304 MHz output, respectively.

TCXO

27 MHz

±1ppm

27 MHz

CLKout1

Hin

Vin

Fin

No input

148.5 MHz (PLL2)

148.35 MHz (PLL3)

98.304 MHz

CLKout2

CLKout3

CLKout4

A/V clock

signals will

track the TCXO

and have the

same accuracy

LMH1983

PLL1 Mode = Free run

PLL2 Video Format = 1080p/50

PLL3 Video Format = 1080p/59.94

PLL4 Audio Format = 98.304 MHz with 48 kHz word clock

Figure 30. High-Precision, Stable A/V Clock Generation Using a 27 MHz TCXO Reference

9.2.3.1 Design Requirements

This application requires less components than the previous applications mentioned in this section. This is

because there is no H_INreference, external VCXO, or loop filter. However, the PLL1 signal is still applied via the

27 MHz TCXO clock signal on the XOin± pins. Using a TCXO for reference allows a stable, standalone clock

generation for PLLs 2-4.

9.2.3.2 Detailed Design Procedure

Since no H_INinput timing signaling is provided, this application example cannot use the "Supported Formats

Lookup Table (LUT)" (see Table 2) for automatic format detection. However, PLLs 2-4 can still be manually

programmed to output the correct output format using Auto Format Detection Codes. To output the desired video

and audio formats from PLLs 2-3, the following output codes should be used:

Table 12. Auto-Format Detection Output Codes for Figure 30

PLLx

(INPUT/OUTPUT)

HSync PERIOD

(in 27 MHz CLOCKS)

FORMAT CODE

DESCRIPTION

PLL2 (Output)

PLL3 (Output)

14

13

1080P50

480

1080P59.94

400.4

To ensure correct auto-detection and the correct CLKout signaling desired in Figure 30, the following SMBus

register values should be verified or changed from their default values.

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Table 13. SMBus Register Settings for Figure 30

REGISTER[Bit(s)]

0x05[5]

WRITE VALUE

1'b

COMMENTS

Auto Format Detect enabled

0x05[4:3]

0x05[1]

00'b

PLL1 operating in Free-run mode

1'b

Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz

Set PLL2 Output to Format Detection Code 14 (0x0E)

Set PLL3 Output to Format Detection Code 13 (0x0D)

Set to always align when misaligned

0x07[5:0]

0x08[5:0]

0x11[5:4]

0x11[3:2]

0x12[5:4]

0x13[5:4]

0x34[7:4]

001110'b

001101'b

10'b

01'b

Drift lock (small misalignment), crash lock (large misalignment)

Set TOF2 to always align when misaligned

10'b

Set TOF3 to always align when misaligned

0000'b

Set PLL4_DIV to divide-by-1 for 98.304 MHz

9.2.3.3 Application Curve

10 ns / div

Traces 1-4: 1 V / div

Figure 31. CLKout 1-4 Signals after Tracking 27 MHz TCXO Reference

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10 Power Supply Recommendations

It is important to ensure that the LMH1983 is provided with an adequate power supply that provides the cleanest

voltage to the VDD_IO and VDD supply pins. One potential source of jitter on a multiple clock system such as

the LMH1983 is interference among the four PLLs on the chip. To help reduce this effect, each PLL is run from a

separate power supply internally on the LMH1983, and each supply has its own internal regulator. These

regulators each require their own external bypass as seen in Figure 32 with bypass capacitors.

Capacitors can be

either tantalum or an

ultra-low ESR ceramic.

3.3 V

VDD_IO

VDD

PLL1

(Pin 1)

(Pin 2, 10)

VDD

CLKout3

(Pin 20)

VDD

CLKout1

(Pin 38)

3.3 V

VDD

CLKout4

(Pin 16)

CLKout2

(Pin 31)

VDD

PLL2

(Pin 32)

Internal

LDO

regulator

Cbyp2

(Pin 27)

3.3 V

VDD

Internal

LDO

regulator

Cbyp3

(Pin 25)

PLL3,

PLL4

(Pin 19)

Internal

LDO

regulator

Cbyp4

(Pin 26)

Place 1 µF and 0.1 µF

bypass capacitors as close to

the Cbyp Pin as possible.

Figure 32. LMH1983 Power Supply Connection Diagram

11 Layout

11.1 Layout Guidelines

When designing the PCB layout for the LMH1983, it is important to follow these the guidelines:

•

Whenever possible, dedicate an entire layer to each power supply. This will reduce the inductance in the

supply plane.

•

Use surface mount components whenever possible.

Place bypass capacitors and filter components as close as possible to each power pin.

Place the loop filter components, including the buffer amplifier, and VCXO as close as possible to the

LMH1983.

•

Do not allow discontinuities in the ground planes – return currents follow the path of least resistance. For high

frequency signals this will be the path of least inductance.

•

Make sure to match the trace lengths of all differential traces.

Remember that vias have significant inductance — when using a via to connect to a power supply or ground

layer, two in parallel will reduce the inductance over a single via.

•

Connect the pad on the bottom of the package to a solid ground connection. This contact is used as a major

ground connection as well as providing a thermal conduit which helps to maintain a constant die temperature.

See Application Note: AN-1187, Leadless Leadframe Package (LLP) (SNOA401) for more Information on the

LLP (WQFN) style package.

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11.2 Layout Example

C1

C3

C6

VddCLK1

VddCLK2

VddCLK3

VddCLK4

1 µF

C2

C4

C7

Vdd3_3

C5

C8

VddPLL1

VddPLL2

VddPLL3

0.1 µF

1 µF

0.1 µF

GND

37

36

35

GND

Fout1

CLKout1+

CLKout1-

Fout1

CLK1_P

CLK1_N

Vdd3_3

R1

R2

3

4

5

6

30

29

28

Vin

Hin

Hsync

Fout2

CLKout2-

CLKout2+

Fout2

CLK2_P

CLK2_N

0

Vsync

Fsync

INIT

Do Not Load

Fin

INIT

GND

24

23

22

CLKout3-

CLKout3+

Fout3

CLK3_N

CLK3_P

Fout3

7

8

9

ADDR

SDA

SCL

SDA

SCL

U1

Vdd3_3

17

15

14

Fout4/OSCin

CLKout4+

CLKout4-

Fout4

CLK4_P

CLK4_N

LMH1983SQ

Vdd3_3

R4

R5

10.0k

13

12

11

NO_REF

NO_ALIGN

NO_LOCK

NOREF

NOALIGN

NOLOCK

3.0k

34

33

XOin+

XOin-

5

GND

U2

40

3

LMP7711MK

VC_LPF

R7

1.8k

1

V-

V+

CS

47 µF

4

CP

1 µF

VddVCXO

Vdd3_3

RS

17.4k

GND

C12

0.1 µF

5

GND

OUTA

OUT

GND

1

VC

R10

4

49.9

X1

GND

357LB3I027M0000

GND

Figure 33. LMH1983 Typical Interface Circuit

An example of a typical application circuit for the LMH1983 is shown in the Figure 33. When performing PCB

layout, key areas to consider regarding this circuit are the loop filter – which consists of R_S, C_S, C_Pand the

LM7711 Operational Amplifier which buffers the loop filter output prior to driving the control voltage input of the

VCXO. Care must be taken in the component selection for the loop filter components (see VCXO Selection

Criteria and Loop Filter Capacitors). The CLKout outputs are differential LVDS signals and should be treated as

differential signals. These signals may be laid out as fully differential lines, in which the characteristic impedance

between the two lines is nominally 100 Ω. Alternately, loosely coupled lines may be used, in which case the

characteristic impedance of each line should be 50 Ω referenced to GND. In either case, care should be taken to

match the lengths of the traces as closely as possible. Trace length mismatches on a differential line will add to

the jitter seen on that line. Jitter is also added to the clock outputs if other signals are allowed to interfere with the

signal traces. Therefore, to the greatest extent possible, the clock traces should be isolated from other signals.

Long parallel runs should also be avoided. In places where a hostile signal must cross a sensitive clock signal, it

should be routed such that it crosses as closely as possible to a 90° crossing.

When performing board layouts with the LMH1983, stencil parameters such as aperture area ratio and the

fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of

the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings

are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture

opening and via locations are shown in Figure 34.

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Layout Example (continued)

Figure 34. No Pullback LLP, Single Row Reference Diagram

Table 14. No Pullback LLP Stencil Aperture Summary for LMH1983

DEVICE

COUNT

MKT.

DWG.

PCB I/O

PAD SIZE PITCH

(mm)

PCB

DAP SIZE

(mm)

STENCIL

I/O

STENCIL

DAP

NUMBER of

DAP

GAP BETWEEN

DAP APERTURE

(DIM A mm)

(mm)

APERTURE APERTURE APERTURE

(mm)

OPENINGS

LMH1983

40

SNA40A 0.25 x 0.6

0.5

4.6 x 4.6

0.25 x 0.7

1.0 x 1.0

16

0.2

Figure 35. 40-Pin WQFN Stencil Example of Via and Opening Placement

The following PCB layout example is derived from the layout design of the LMH1983 in the SD1983EVK

Evaluation Module User's Guide (SNLU001). This graphic and additional layout board description demonstrates

both proper routing and solder techniques when designing in this clock generator.

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Figure 36. LMH1983 Example Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

•

Absolute Maximum Ratings for Soldering (SNOA549).

Generating 44.1 kHz Based Clocks with the LMH1983, Application Note AN–2108 (SNLA129).

Leadless Leadframe Package (LLP), Application Note AN-1187 (SNOA401).

SD1983EVK/LMH1983 Evaluation Kit User Guide (SNLU001).

Semiconductor and IC Package Thermal Metrics (SPRA953).

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RTA0040A

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

2

0

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

B

A

PIN 1 INDEX AREA

6.1

5.9

0.5

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

C

SEATING PLANE

0.08

0.05

0.00

(0.2) TYP

(0.1) TYP

4.6 0.1

EXPOSED

THERMAL PAD

20

11

36X 0.5

10

21

4X

4.5

SEE TERMINAL

DETAIL

1

30

0.3

40X

40

31

0.2

PIN 1 ID

(OPTIONAL)

0.5

0.3

0.1

C A B

40X

0.05

4214989/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTA0040A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.6)

SYMM

40

31

40X (0.6)

40X (0.25)

1

30

36X (0.5)

SYMM

(5.8)

(0.74)

TYP

(

0.2) TYP

VIA

(1.31)

TYP

10

21

(R0.05) TYP

11

20

(0.74) TYP

(1.31 TYP)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214989/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RTA0040A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.48) TYP

9X ( 1.28)

40

31

40X (0.6)

1

30

40X (0.25)

36X (0.5)

(1.48)

TYP

SYMM

(5.8)

METAL

TYP

10

21

(R0.05) TYP

11

20

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

70% PRINTED SOLDER COVERAGE BY AREA

SCALE:15X

4214989/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMH1983
厂家：	TEXAS INSTRUMENTS
描述：	具有音频时钟的 3G/高清/标清视频时钟发生器时钟时钟发生器
文件：	总55页 (文件大小：1943K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMH1983 [TI]

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