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LMH2832

ZHCSF77A –JULY 2016–REVISED JULY 2016

LMH2832 全差分双路 1.1GHz 数字可变增益放大器

1 特性

3 说明

1

•

由 SPI™单独控制的双通道数字可变增益放大器

LMH2832 是一款高线性度双通道数字可变增益放大器

(DVGA)

(DVGA)，适用于高速信号链和数据采集系统。

LMH2832 已经过优化，可实现高带宽、低失真和低噪

声等特性，因此非常适合用作双路 14 位模数转换器

(ADC) 的驱动器。此器件包含一个固定增益模块和一

个可变衰减器，总增益为 30dB，最大衰减为 39dB。

增益范围为 –9dB 到 30dB，增益步长为 1dB，增益精

度为 ±0.2dB。输入阻抗可分别使用 1:3Ω 或 1:2Ω 比率

平衡-非平衡转换器来轻松匹配 50Ω 或 75Ω 系统。

LMH2832 设计用于驱动通用 ADC，而且满足电缆数

据服务接口规范 (DOCSIS) 3.0 32 正交振幅调制

(QAM) 载波和 DOCSIS 3.1 宽带正交频分多路复用

(OFDM) 系统的要求。凭借优异的 NF (6.5dB) 和线性

度，LMH2832 可遵循 DOCSIS 规范执行。掉电状态

下的静态电流低于每通道 5mA，而运行期间的典型流

耗为每通道 105mA。

•

5V 单电源

–3dB 带宽：1.1GHz（最大增益）

平滑带宽响应：300MHz

通道间增益匹配：±0.05dB

通道间相位匹配：±0.1°

增益:

–

-9dB 至 30dB

1dB 步长 ±0.2dB

•

输出三阶截断点 (OIP3)：

–

300MHz 时为 43dBm

200MHz 时为 51dBm

•

噪声系数 (NF)：

300MHz、Z_IN= 150Ω 时为 6.5dB（最大增益）

可调功耗：

–

每通道 90mA 至 108mA

器件信息⁽¹⁾

节能、掉电特性：

器件型号

LMH2832

封装

VQFN (40)

封装尺寸（标称值）

–

每通道 I_Q< 4.5mA

6.00mm x 6.00mm

掉电引脚和 SPI 可编程性

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

•

300MHz 时的输入回波损耗：

17dB (R_S= 150Ω)

–

2 应用

•

DOCSIS 3.1 CMTS 上行直接采样接收器

CATV 调制解调器信号调节

可编程增益 IF 放大器

通用 RF、IF 增益级

ADC 驱动器

输出三阶截断点 (OIP3) 性能

60

55

50

45

40

35

30

25

Channel A

Channel B

0

50 100 150 200 250 300 350 400 450 500 550 600

Frequency (MHz)

D005

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBOS709

LMH2832

ZHCSF77A –JULY 2016–REVISED JULY 2016

www.ti.com.cn

9.1 Overview ................................................................. 19

9.2 Functional Block Diagram ....................................... 19

9.3 Feature Description................................................. 19

9.4 Device Functional Modes........................................ 21

9.5 Programming........................................................... 21

9.6 Register Maps......................................................... 24

10 Application and Implementation........................ 29

10.1 Application Information.......................................... 29

10.2 Typical Applications .............................................. 32

10.3 Do's and Don'ts..................................................... 35

11 Power Supply Recommendations ..................... 35

11.1 Split Supplies ........................................................ 35

11.2 Supply Decoupling ................................................ 35

12 Layout................................................................... 36

12.1 Layout Guidelines ................................................. 36

12.2 Layout Example .................................................... 36

13 器件和文档支持 ..................................................... 37

13.1 器件支持 ............................................................... 37

13.2 文档支持 ............................................................... 37

13.3 接收文档更新通知 ................................................. 37

13.4 社区资源................................................................ 37

13.5 商标....................................................................... 37

13.6 静电放电警告......................................................... 38

13.7 Glossary................................................................ 38

14 机械、封装和可订购信息....................................... 38

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements: SPI ........................................ 8

7.7 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 16

8.1 Setup Diagrams ...................................................... 16

8.2 ATE Testing and DC Measurements ...................... 17

8.3 Frequency Response.............................................. 17

8.4 Distortion................................................................. 17

8.5 Noise Figure............................................................ 17

8

8.6 Pulse Response, Slew Rate, and Overdrive

Recovery.................................................................. 18

8.7 Power-Down............................................................ 18

8.8 Crosstalk, Gain Matching, and Phase Matching..... 18

8.9 Output Measurement Reference Points.................. 18

Detailed Description ............................................ 19

9

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (July 2016) to Revision A

Page

•

已发布为量产数据................................................................................................................................................................... 1

2

LMH2832

www.ti.com.cn

ZHCSF77A –JULY 2016–REVISED JULY 2016

5 Device Comparison Table

Table 1. DVGA Device Comparison

DEVICE

LMH6401

LHM6517

LMH6521

LMH6881

MAX GAIN, BW

DISTORTION

NOISE FIGURE

26 dB, 4.5 GHz

22 dB, 1.2 GHz

26 dB, 1.2 GHz

26 dB, 2.4 GHz

43-dBm OIP3 at 200 MHz, –80-dBc HD3 at 200 MHz

43-dBm OIP3 at 200 MHz, –74-dBc HD3 at 200 MHz

49-dBm OIP3 at 200 MHz, –84-dBc HD3 at 200 MHz

42-dBm OIP3 at 200 MHz, –76-dBc HD3 at 200 MHz

7.7 dB

5.5 dB

7.3 dB

9.7 dB

6 Pin Configuration and Functions

RHA Package

40-Pin VQFN

Top View

INMA

1

2

3

4

5

6

7

8

9

10

30

29

28

27

OUTMA

GND

VCC

GND

VCC

CS

VCC

SCLK,Thermal_pad

26

VCC

Thermal

Pad

SDI

SDO

VCC

GND

INMB

25

24

23

22

21

VCC

GND

OUTMB

Not to scale

3

LMH2832

ZHCSF77A –JULY 2016–REVISED JULY 2016

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

CS

NO.

4

I

Serial interface enable, active low

Analog ground

GND

2, 9, 12, 19, 22, 29, 32, 39

INMA

INMB

INPA

INPB

OUTMA

OUTMB

OUTPA

OUTPB

PDB

1

I

Negative differential input, channel A

Negative differential input, channel B

Positive differential input, channel A

Positive differential input, channel B

Negative differential output, channel A

Negative differential output, channel B

Positive differential output, channel A

Positive differential output, channel B

Power-down control, channel B (logic high = power-down)

Power-down control, channel A (logic high = power-down)

Serial interface clock input

10

40

11

30

21

31

20

15

36

5

I

O

I

PDA

I

SCLK

SDI

I

6

I

Serial interface data input

SDO

7

O

Serial interface data output

3, 8, 13, 14, 16, 17, 18, 23, 24, 25,

26, 27, 28, 33, 34, 35, 37, 38

VCC

I

Analog voltage supply

Connected to ground

Thermal pad

—

4

LMH2832

www.ti.com.cn

ZHCSF77A –JULY 2016–REVISED JULY 2016

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–0.3

MAX

5.5

2

UNIT

V

Power supply

Input applied to analog inputs

Voltage applied to input pins

Digital input/output voltage range

Operating junction temperature, T_J

Storage temperature, T_stg

INPA, INMA, INPB, INMB

V

125

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.75

–40

NOM

MAX

UNIT

V_S

Power-supply voltage

5

5.25

85

V

Specified operating temperature range

°C

7.4 Thermal Information

LMH2832

THERMAL METRIC⁽¹⁾

RHA (VQFN)

40 PINS

29.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

20.4

6.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

6.5

R_θJC(bot)

2.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

5

LMH2832

ZHCSF77A –JULY 2016–REVISED JULY 2016

www.ti.com.cn

7.5 Electrical Characteristics

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with a transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

TEST

PARAMETER

AC PERFORMANCE

TEST CONDITIONS

MIN

TYP

MAX UNIT

LEVEL⁽¹⁾

G = 30 dB, V_O= 2 V_PP

1140

2350

300

–88

–76

–63

–58

–94

–90

–81

–75

C

Large-signal,

–3-dB bandwidth

LSBW

BW

MHz

G = 0 dB, V_O= 2 V_PP

Bandwidth for 0.1-dB flatness

f = 100 MHz, V_O= 2 V_PP

f = 200 MHz, V_O= 2 V_PP

f = 300 MHz, V_O= 2 V_PP

f = 450 MHz, V_O= 2 V_PP

f = 100 MHz, V_O= 2 V_PP

f = 200 MHz, V_O= 2 V_PP

f = 300 MHz, V_O= 2 V_PP

f = 450 MHz, V_O= 2 V_PP

Second-order harmonic

distortion

HD2

dBc

Third-order harmonic

distortion

HD3

dBc

f = 100 MHz, tone spacing = 2 MHz,

P_OUT⁽²⁾= 0 dBm per tone

–106

C

Third-order intermodulation

distortion

IMD3

f = 200 MHz, tone spacing = 2 MHz

f = 300 MHz, tone spacing = 2 MHz

–102

–86

C

f = 100 MHz, tone spacing = 2 MHz,

P_OUT= 0 dBm per tone

53

51

43

C

Output third-order intercept

point

f = 200 MHz, tone spacing = 2 MHz,

P_OUT= 0 dBm per tone

OIP3

dBm

f = 300 MHz, tone spacing = 2 MHz,

P_OUT= 0 dBm per tone

f = 100 MHz, R_L= 150 Ω

f = 200 MHz, R_L= 150 Ω

f = 300 MHz, R_L= 150 Ω

R_i= 150 Ω, f = 300 MHz, max gain

16

C

P1dB

NF

1-dB compression point

Noise figure

16.5

6.5

dB

nV/√Hz

dB

Output-referred voltage noise f = 300 MHz, max gain

47.7

17

S11

S22

Input return loss

Reverse Isolation

f = 300 MHz

Including input transformer, f < 300 MHz

f = 300 MHz, channel A to B

f = 300 MHz, channel B to A

53

dB

–77

–81

Channel-to-channel crosstalk

dB

C

Channel-to-channel phase

matching

f = 200 MHz

±0.1

°

C

Channel-to-channel gain

matching

±0.05

dB

GAIN PARAMETERS

Maximum voltage gain

f = dc, gain code = 00h

f = dc, gain code = 27h

29.5

–9.5

30

–9

39

1

30.5

–8.5

dB

ns

A

C

A

C

Minimum voltage gain

Gain range

Gain step size

Between any two adjacent gain settings

For any gain value

0.75

–0.5

–1

1.25

0.5

1

E_G

Gain error

0

Cumulative gain error

Gain step transition time

Referenced to max gain

6

(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value only for information.

(2) P_OUTis the signal tone power at the output of the device.

6

LMH2832

www.ti.com.cn

ZHCSF77A –JULY 2016–REVISED JULY 2016

Electrical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with a transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LEVEL⁽¹⁾

ANALOG INPUT CHARACTERISTICS

z_in

Input resistance

f = dc, differential

Differential

135

150

0.6

75

165

Ω

pF

Ω

A

C

A

C_in

Input capacitance

Single-ended input resistance f = dc

67.5

82.5

Single-ended input

capacitance

1.2

pF

C

V_ICM

V_IL

Input common-mode voltage

Internally biased to mid-supply

–0.2

0.2

V

A

C

Low-level input voltage range Differential gain shift < 1 dB

High-level input voltage range Differential gain shift < 1 dB

(V_S–) + 1.5

(V_S+) – 1.5

V_IH

ANALOG OUTPUT CHARACTERISTICS

z_o

Output resistance

Differential

20

Ω

C

A

Low-level output voltage

range

V_OL

V_S= 5 V, GND = 0 V

1.15

1.25

6.4

V

High-level output voltage

range

V_OH

V_S= 5 V, GND = 0 V

3.75

5

3.85

V

A

T_A= 25°C

5.4

56

A

B

C

Maximum output voltage

swing

V_OM

V

T_A= –40°C to +85°C

CMRR

Common-mode rejection ratio

dB

POWER SUPPLY

V_S

Supply voltage

4.75

102

5.0

105

90

5.25

108

V

A

C

Default current, default bias setting

Quiescent current per channel Min current, lowest power setting

Max current, highest bias setting

I_Q

mA

dB

108

–48

±PSRR

Power-supply rejection ratio⁽³⁾Gain = 30 dB

POWER-DOWN⁽⁴⁾

T_A= 25°C

2.5

6

A

B

A

Power-down quiescent current

(per channel)

mA

T_A= –40°C to +85°C

6.5

Power-down bias current

–2

–1

55

µA

ns

Time to V_O= 90% of final value,

gain = 0 dB, V_I= 2 V

Turn-on time delay

Turn-off time delay

C

Time to V_O= 10% of original value,

gain = 0 dB, V_I= 2 V

110

–67

ns

C

Forward isolation in PD mode f = 300 MHz

DIGITAL INPUTS/OUTPUTS

dB

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.4

–0.3

1.65

1.55

2

V

A

0.8

I_OH= –100 µA

I_OH= –2 mA

I_OL= 100 µA

I_OL= 2 mA

V_OH

High-level output voltage

Low-level output voltage

V

0.1

0.2

V_OL

(3) PSRR is defined with respect to a differential output.

(4) The device power-down function can be controlled by the PDx pins or by the power-down register accessible from the SPI interface.

7

LMH2832

ZHCSF77A –JULY 2016–REVISED JULY 2016

www.ti.com.cn

7.6 Timing Requirements: SPI

MIN

TYP

25

10

3

MAX

UNIT

MHz

ns

f_{S_C}

t_PH

SCLK frequency⁽¹⁾

SCLK pulse duration, high

SCLK pulse duration, low

SDI setup

0

50

t_PL

ns

t_SU

ns

t_H

SDO hold

3

ns

t_IZ

SDO tri-state

3

ns

t_ODZ

t_OZD

t_OD

t_CSS

t_CSH

t_IAG

SDO driven to tri-state⁽²⁾

SDO tri-state to driven

SDO output delay⁽²⁾

CS setup⁽³⁾

0

3

10

2

20

5

ns

10

5

12

ns

CS hold

3

ns

Inter-access gap

20

ns

(1) Tested on the automated test equipment (ATE) only up to 25 MHz.

(2) Referenced to the negative edge of SCLK.

(3) Referenced to the positive edge of SCLK.

8

LMH2832

www.ti.com.cn

ZHCSF77A –JULY 2016–REVISED JULY 2016

7.7 Typical Characteristics

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

32

28

24

20

16

12

8

31

30.8

30.6

30.4

30.2

30

f = 50 MHz

f = 100 MHz

f = 200 MHz

f = 300 MHz

f = 400 MHz

f = 500 MHz

29.8

29.6

29.4

29.2

29

4

0

-4

-8

-12

-16

28.8

1

10

100

1000

8000

-40

-20

0

20

40

60

80

100110

Frequency (MHz)

Temperature (°C)

D001

D025

V_O= 2 V_PP

Figure 1. Voltage Gain vs Frequency (1-dB Gain Steps)

Figure 2. Gain Flatness vs Temperature

0

0.1

0.2

Gain Matching Error (dB)

Phase Matching Error (°)

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

-55

-60

0.05

0

0.1

0

-0.05

-0.1

-0.2

1

10

100

1000

3000

-9 -6 -3

0

3

6

9

12 15 18 21 24 27 30

Frequency (MHz)

Voltage Gain (dB)

D008

D034

Differential input impedance (Z_IN) = 150 Ω, all gain settings

f = 200 MHz

Figure 3. Input Return Loss vs Frequency

Figure 4. Channel-to-Channel Mismatch Error

60

-40'C

27'C

90'C

A_v= 30 dB

A_v= 22 dB

A_v= 14 dB

A_v= 6 dB

A_v= 2 dB

A_v= -2 dB

55

50

45

40

35

30

25

55

105'C

50

45

40

35

30

25

0

50 100 150 200 250 300 350 400 450 500 550 600

Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500 550 600

Frequency (MHz)

D002

D004

P_OUT= 0 dBm per tone

Figure 5. OIP3 vs Frequency and Voltage Gain

Figure 6. OIP3 vs Frequency and Temperature

9

LMH2832

ZHCSF77A –JULY 2016–REVISED JULY 2016

www.ti.com.cn

Typical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

60

55

50

45

40

35

30

25

60

55

50

45

40

35

30

25

A_v= 30 dB

A_v= 22 dB

A_v= 14 dB

A_v= 6 dB

A_v= 2 dB

A_v= -2 dB

Channel A

Channel B

0

2

4

6

8

10

12

14

0

50 100 150 200 250 300 350 400 450 500 550 600

Frequency (MHz)

P_OUTper tone (dBm)

D003

D005

f = 200 MHz

P_OUT= 0 dBm per tone

Figure 7. OIP3 vs Output Power

Figure 8. OIP3 Channel Comparison

46

45

44

43

42

41

40

58

57

56

55

54

53

52

51

50

V_S= 4.5 V

V_S= 4.75 V

V_S= 5 V

V_S= 4.5 V

V_S= 4.75 V

V_S= 5 V

V_S= 5.25 V

-40

-20

0

20

40

60

80

100110

-40

-20

0

20

40

60

80

100110

Temperature (°C)

D006

D007

P_OUT= 0 dBm per tone

Figure 9. OIP3 vs Temperature and Supply Voltage

(f = 200 MHz)

Figure 10. OIP3 vs Temperature and Supply Voltage

(f = 300 MHz)

0

56

55

54

53

52

51

50

49

48

47

46

IMD2 (dBc)

IMD3 (dBc)

-10

-20

-30

-40

-50

-60

-70

-80

Bias Setting = 00h

Bias Setting = 02h

Bias Setting = 08h

Bias Setting = 20h

Bias Setting = 80h

-90

-100

-110

-120

-40

-20

0

20

40

60

80

100110

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

Temperature (°C)

D038

D039

P_OUT= 0 dBm per tone

Figure 11. OIP3 vs Temperature and Bias Setting

(f = 200 MHz)

Figure 12. Intermodulation Distortion vs Frequency

10

LMH2832

www.ti.com.cn

ZHCSF77A –JULY 2016–REVISED JULY 2016

Typical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

50

45

40

35

30

25

20

15

10

5

12

11

10

9

f = 50 MHz

f = 100 MHz

f = 200 MHz

f = 300 MHz

25°C

8

7

6

5

4

-9 -6 -3

0

3

6

9

12 15 18 21 24 27 30

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

Voltage Gain (dB)

D011

D022

Z_IN= 150 Ω

Figure 13. Noise Figure vs Voltage Gain

Figure 14. Noise Figure vs Frequency

0

Gain = 30 dB

Gain = 22 dB

Gain = 14 dB

Gain = 6 dB

Gain = 2 dB

Gain = -2 dB

Gain = 30 dB

Gain = 22 dB

Gain = 14 dB

Gain = 6 dB

Gain = 2 dB

Gain = -2 dB

-10

-20

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

D012

D013

V_O= 2 V_PP

Figure 15. HD2 vs Frequency and Gain Settings

Figure 16. HD3 vs Frequency and Gain Settings

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

-10

-40°C

25°C

90°C

-40°C

25°C

90°C

-20

105°C

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

D014

D015

V_O= 2 V_PP

Figure 17. HD2 vs Frequency and Temperature

Figure 18. HD3 vs Frequency and Temperature

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Typical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

0

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

Channel A (HD2)

Channel A (HD3)

Channel B (HD2)

Channel B (HD3)

V_S= 4.5 V (HD2)

V_S= 4.5 V (HD3)

V_S= 5 V (HD2)

V_S= 5 V (HD3)

V_S= 5.25 V (HD2)

V_S= 5.25 V (HD3)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

-40

-20

0

20

40

60

80

100110

Temperature (°C)

D040

D016

V_O= 2 V_PP

Figure 19. Harmonic Distortion Between Channels

Figure 20. Harmonic Distortion vs Temperature and

Supply Voltage (100 MHz)

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-40

V_S= 4.5 V (HD2)

V_S= 4.5 V (HD3)

V_S= 5 V (HD2)

V_S= 5 V (HD3)

V_S= 5.25 V (HD2)

V_S= 5.25 V (HD3)

Gain = 30 dB

Gain = 22 dB

Gain = 14 dB

Gain = 6 dB

Gain = 2 dB

-50

-60

-70

-80

-90

-100

-40

-20

0

20

40

60

80

100110

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

Temperature (°C)

Differential Output Swing (V_PP

)

D017

D018

V_O= 2 V_PP

Figure 21. Harmonic Distortion vs Temperature and

Supply Voltage (200 MHz)

Figure 22. HD2 vs Differential Output Swing (100 MHz)

-40

-30

Gain = 30 dB

Gain = 22 dB

Gain = 14 dB

Gain = 6 dB

Gain = 2 dB

Gain = 30 dB

Gain = 22 dB

Gain = 14 dB

Gain = 6 dB

Gain = 2 dB

-40

-50

-60

-50

-60

-70

-80

-90

-100

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

Differential Output Swing (V_PP

)

Differential Output Swing (V_PP

)

D019

D020

Figure 23. HD3 vs Differential Output Swing (100 MHz)

Figure 24. HD2 vs Differential Output Swing (200 MHz)

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Typical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

-30

22

20

18

16

14

12

10

Gain = 30 dB

Gain = 22 dB

Gain = 14 dB

Gain = 6 dB

Gain = 2 dB

V_S= 4.5 V

V_S= 5 V

V_S= 5.25 V

-40

-50

-60

-70

-80

-90

-100

-110

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

Differential Output Swing (V_PP

)

D021

D023

Figure 25. HD3 vs Differential Output Swing (200 MHz)

Figure 26. Output P1dB Compression vs Frequency

20

80

70

60

50

40

30

20

10

0

V_S= 4.5 V

V_S= 5 V

V_S= 5.25 V

19

18

17

16

15

14

-40

-20

0

20

40

60

80

100110

1

10

100

1000

8000

Temperature (°C)

Frequency (MHz)

D024

D033

Sdd21 / Scc21

Figure 27. Output P1dB Compression vs Temperature

Figure 28. CMRR vs Frequency

0

-40

-50

Channel A to B

Channel B to A

-10

-20

-30

-40

-50

-60

-70

-80

-60

-70

-80

-90

-100

-110

1

10

100

1000

8000

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

D035

D037

Scd21 / Sdd21

Figure 29. Output Balance Error vs Frequency

Figure 30. Channel-to-Channel Isolation vs Frequency

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Typical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

0.15

6

f = 100 MHz

f = 200 MHz

f = 300 MHz

f = 100 MHz

f = 200 MHz

f = 300 MHz

0.1

4

0.05

0

2

0

-0.05

-0.1

-0.15

-2

-4

-6

-9 -6 -3

0

3

6

9

12 15 18 21 24 27 30

-9 -6 -3

0

3

6

9

12 15 18 21 24 27 30

Voltage Gain (dB)

D009

D010

Figure 31. Cumulative Gain Step Error vs Voltage Gain

Figure 32. Cumulative Phase Step Error vs Voltage Gain

200

2.4

2.5

R (W)

jX (W)

|Z| (W)

Power Down Pin

Output

2

150

100

50

1.6

1.2

0.8

0.4

0

1.5

1

0.5

0

-50

-100

-0.5

-0.4

-1

1

10

100

1000 2000

Time (50 ns/div)

Frequency (MHz)

D036

D026

Figure 33. Output Impedance vs Frequency

Figure 34. Power-Down Transition Response

2.4

2

2.4

2

2.4

SCLK

Output

SCLK

Output

2

1.6

1.2

0.8

0.4

0

2

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

Time (10 ns/div)

D027

D028

Figure 35. Gain Switching Response (A_V= 30 dB to 22 dB)

Figure 36. Gain Switching Response (A_V= 22 dB to 30 dB)

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Typical Characteristics (continued)

at T_A= 25°C, V_S+= 5 V, R_i= 75 Ω, R_L= 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to

300 MHz, V_Oconverted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise

noted); upon power-up, gain is set to mid-range

2.4

SCLK

Output

SCLK

Output

2

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

Time (10 ns/div)

D029

D030

Figure 37. Gain Switching Response (A_V= 30 dB to 14 dB)

Figure 38. Gain Switching Response (A_V= 14 dB to 30 dB)

2.4

2

2.4

2

SCLK

Output

SCLK

Output

2

1.6

1.2

0.8

0.4

0

2

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

1.6

1.2

0.8

0.4

0

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

-0.4

-0.8

-1.2

Time (10 ns/div)

D031

D032

Figure 39. Gain Switching Response (A_V= 30 dB to 6 dB)

Figure 40. Gain Switching Response (A_V= 6 dB to 30 dB)

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8 Parameter Measurement Information

8.1 Setup Diagrams

Figure 41 to Figure 44 illustrate various test setup diagrams using the LMH2832 evaluation module (EVM).

LMH2832EVM-50

V_S+= 5 V

Vector Network

Analyzer

Vector Network

Analyzer

0.1 µF

50 ꢀ

10 ꢀ

50 ꢀ

15 ꢀ

Port 1

Port 3

SMA

Port 2

Port 4

INPx

INMx

OUTPx

OUTMx

+

-

+

-

½ LMH2832

OUT_AMP

10 ꢀ

OUT_LOAD

SMA

50 ꢀ

Test Equipment

with 50-Ω Inputs/Outputs

SPI

USB

GND

Figure 41. Frequency Response Differential Test Setup

LMH2832EVM-75

V_S+= 5 V

z_o= 50 Ω, 1:2

ETC1-1-13T

(1:1, z_o= 50 Ω)

F-Connector

BMP5075

0.1 µF

10-ꢀ

50 ꢀ

40 ꢀ

INPx

INMx

OUTPx

OUTMx

0º

50 ꢀ

+

SMA

½ LMH2832

OUT_AMP

-

180º

BMP5075

F-Connector

Spectrum Analyzer

10-ꢀ

with 50-Ω Inputs

Signal Generator

with 50-Ω Outputs

Band-Pass

Filter

ZFSCJ-2-1-S+

SPI

USB

75-Ω Reference

50-Ω Reference

GND

Figure 42. Single-Tone Harmonic Distortion Test Setup

LMH2832EVM-75

V_S+= 5 V

50 ꢀ

Signal Generator

with 50-Ω Outputs

MABA011033

F-Connector

ETC1-1-13T

(1:1, z_o= 50 Ω)

0.1 µF

(1:2, z_o= 75 Ω)

10 ꢀ

50 ꢀ

ZFSCJ-2-1

or

ZFSCJ-2-4

40 ꢀ

6-dB

Attenuation

Pads

INPx

INMx

OUTPx

OUTMx

Band-Pass

Filter

BMP5075

+

-

SMA

½ LMH2832

OUT_AMP

Spectrum Analyzer

with 50-Ω Inputs

10 ꢀ

50 ꢀ

50-Ω Reference

75-Ω Reference

SPI

USB

Signal Generator

GND

with 50-Ω Outputs

Figure 43. Two-Tone Linearity Test Setup (OIP3, OIP2)

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Setup Diagrams (continued)

LMH2832EVM-50

V_S+= 5 V

MABA011038

(1:3, z_o= 50 Ω)

ETC1-1-13T

(1:1, z_o= 50 Ω)

0.1 µF

10 ꢀ

50 ꢀ

40 ꢀ

INPx

INMx

OUTPx

OUTMx

346B

Noise Source

SMA

½ LMH2832

SMA

Agilent E4443A

with 50-Ω Outputs

Agilent E4443A

with 50-Ω Inputs

10 ꢀ

0.1 µF

SPI

USB

GND

Figure 44. Noise Figure Test Setup

8.2 ATE Testing and DC Measurements

All production testing and dc parameters are measured on automated test equipment (ATE) capable of dc

measurements only. Some measurements (such as voltage gain) are referenced to the output of the internal

amplifier and do not include losses attributed to the on-chip output resistors. The Electrical Characteristics values

specify these conditions. When the measurement is referred to the amplifier output, the output resistors are not

included in the measurement. If the measurement is referred to the device pins, then the output resistor loss is

included in the measurement.

8.3 Frequency Response

This test is done by running an S-parameter sweep on a 4-port differential network analyzer using the standard

EVM with no baluns; see Figure 41. The inputs and outputs of the EVM are connected to the network analyzer

using 75-Ω coaxial cables with the input ports set to a characteristic impedance of 75 Ω, and the output ports set

to a characteristic impedance of 50 Ω.

The frequency response test with capacitive load is done by soldering the capacitor across the LMH2832 output

pins. In this configuration, the on-chip, 10-Ω resistors on each output leg isolate the capacitive load from the

amplifier output pins.

8.4 Distortion

The standard EVM is used for measuring both the single-tone harmonic distortion and two-tone intermodulation

distortion; see Figure 42 and Figure 43, respectively. The distortion is measured with differential input signals to

the LMH2832. In order to interface with 50-Ω, single-ended test equipment, 50-Ω to 75-Ω impedance matching

pads followed by external baluns (1:2, z_o= 75 Ω) are required between the EVM output ports and the test

equipment. These baluns are used to combine two single tones in the two-tone test plots as well as to convert

the single-ended input to differential output for harmonic distortion tests. The use of 6-dB attenuator pads on both

the inputs and outputs is recommended to provide a balanced match between the external balun and the EVM.

8.5 Noise Figure

This test is done by matching the input of the LMH2832 to a 50-Ω noise source using a 50-Ω to 75-Ω impedance

transformation pad followed by a 1:2 balun (Figure 44), with the noise figure being referred to the input

impedance (R_S= 150 Ω). As noted in Figure 44, a Keysight Technologies™ E4443A with NF features is used for

the testing.

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8.6 Pulse Response, Slew Rate, and Overdrive Recovery

For time-domain measurements, the standard EVM is driven through an impedance transformation pad and a

balun again to convert a single-ended output from the test equipment to the differential inputs of the LMH2832.

The differential outputs are directly connected to the oscilloscope inputs, with the differential signal response

calculated using trace math from the two separate oscilloscope inputs.

8.7 Power-Down

The standard EVM is used for this test by completely removing the shorting block on jumper JPD. A high-speed,

50-Ω pulse generator is used to drive the PDx pin that toggles the output signal on or off depending upon the

PDx pin voltage.

8.8 Crosstalk, Gain Matching, and Phase Matching

The standard EVM is used for these tests with both channels enabled. For gain and phase matching, the

responses of both channels are measured on a network analyzer and the gain and phase values are compared.

For crosstalk, a single channel is driven with a signal on the network analyzer when the other channel is

measured.

8.9 Output Measurement Reference Points

The LMH2832 has two on-chip, 10-Ω output resistors on each channel. When matching the output to a 100-Ω

load, the evaluation module (EVM) uses an external 40-Ω resistor on each output leg to complete the output

matching. The inclusion of on-chip output resistors creates two potential reference points for measuring the

output voltage. The first reference point is at the internal amplifier output (OUT_AMP), and the second reference

point is at the externally-matched 100-Ω load (OUT_LOAD). The measurements in the Electrical Characteristics

table and in the Typical Characteristics section are referred to the (OUT_AMP) reference point unless otherwise

specified. The conversion between reference points is a straightforward correction of 3 dB for power and 6 dB for

voltage, as shown in Equation 1 and Equation 2. The measurements are referenced to OUT_AMP when not

specified.

VOUT_LOAD = (VOUT_AMP – 6 dB)

POUT_LOAD = (POUT_AMP – 3 dB)

(1)

(2)

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9 Detailed Description

9.1 Overview

Each channel of the LMH2832 consists of an input attenuator block followed by a fully differential amplifier that

has a gain of 30 dB. The attenuator has a range of 0 dB to –39 dB in 1-dB steps that is controlled by an SPI

interface. The two channels can be controlled independently using the digital interface including power-down and

bias settings. A separate analog power-down pin (PDA, PDB) is also included for each channel so that the

device can bet set to a low-power state without waiting for a serial write to a register. The internal registers also

include a power-on-reset (POR) that ensures the device starts in a known state after the power is reset.

9.2 Functional Block Diagram

1-dB Attenuator Steps:

0 dB to -39 dB

INPA

OUTPA

OUTMA

FDA

G = 30 dB

150 ꢀ

INMA

PDA

CS

SCLK

SDI

Channel A Control Logic

Channel B Control Logic

SPI

POR

SDO

PDB

INMB

OUTMB

OUTPB

FDA

G = 30 dB

150 ꢀ

INPB

1-dB Attenuator Steps:

0 dB to -39 dB

9.3 Feature Description

9.3.1 Analog Input Characteristics

The LMH2832 is a dual-channel device with two identical channels (A and B) that each have differential input

pins (INP and INM) that denote the positive and negative inputs, respectively. The inputs are expected to be ac-

coupled only, typically through a transformer or capacitor. The amplifier self-biases the input common-mode to

mid-supply for the maximum input voltage range. The inputs of the LMH2832 can only be driven differentially. For

single-ended input source applications, use a balun or fully differential amplifier (such as the LMH3401 or

LMH5401) that can convert single-ended to differential signals before the LMH2832.

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Feature Description (continued)

At maximum gain, the digital attenuator is set to 0 dB of attenuation, causing the input signal to be much larger

than the output signal and forcing the maximum output voltage swing to be limited by the outputs of the device.

However at minimum gain, the maximum voltage swing is limited by the inputs of the device because the

attenuator causes the output voltage to be 9 dB lower than the input voltage. In minimum gain, the input voltage

limits against the electrostatic discharge (ESD) devices before the output reaches the maximum swing limits. For

linear operation, the input voltage must be kept within the maximum input voltage ratings described in the

Electrical Characteristics table.

The input impedance of the LMH2832 is set by internal termination resistors to a nominal value of 150 Ω,

differential. Process variations result in a range of values, as described in the Electrical Characteristics table. The

input impedance is also affected by device parasitic effects at higher frequencies that cause the impedance to

shift away from the nominal value.

9.3.2 Analog Output Characteristics

The LMH2832 has series, 10-Ω, on-chip resistors on each output to provide isolation from board parasitics that

can cause instability. When designing a filter following the LMH2832, the filter source impedance calculation

must include the two 10-Ω, on-chip resistors. Table 2 shows the calculated external source impedance values

required for various matched filter loads.

Table 2. Output Resistor Values for Matched Loads

MATCHED FILTER IMPEDANCE (Ω)

EXTERNAL SERIES RESISTOR PER OUTPUT (Ω)

100

150

200

300

80

130

180

280

9.3.3 Driving Low Insertion-Loss Filters

When driving high-speed ADCs, a filter is commonly driven with a matched impedance to the ADC. This

impedance is matched by the amplifier by setting the combination of the output resistors to the same impedance

as the ADC inputs. Impedance matching is often done to minimize any transmission reflections caused by the

physical signal path. The drawback to using a matched impedance is that a voltage swing is required from the

amplifier outputs that is twice the desired ADC input voltage swing, which can cause output voltage limitation

issues.

To avoid using a matched impedance, a low insertion loss filter can be driven where there is little to no

resistance added at the amplifier outputs. The amplifier outputs then only must swing to the value of the ADC

full-scale input voltage, thus eliminating most of the potential amplifier output headroom issues. The requirements

of this technique are that the amplifier must be able to provide enough current to the load of the ADC and that

the path between the amplifier outputs and ADC inputs must be minimized to prevent any reflections.

9.3.4 Input Impedance Matching

The LMH2832 has a differential input impedance of 150 Ω that can be easily matched to single-ended, 50-Ω or

75-Ω systems using baluns. For a single-ended, 50-Ω input, a 1:3-Ω ratio balun can be used to create a 150-Ω

differential source impedance to the device with a balun gain of 4.8 dB. For a single-ended, 75-Ω input, a 1:2-Ω

ratio balun creates a 150-Ω differential source impedance to the device with a voltage gain of 3 dB.

9.3.5 Power-On Reset (POR)

The LMH2832 has a built-in, power-on-reset (POR) that sets the device registers to their default state (see the

Register Maps section) on power-up. Note that the LMH2832 register information is lost when power is removed.

When power is reapplied, the POR ensures that the device enters a default state. Power glitches (of sufficient

duration) can also initiate the POR and return the device to a default state.

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9.4 Device Functional Modes

9.4.1 Power-Down (PD)

The device supports power-down control using an external power-down (PDx) pin or by writing a logic high to bit

6 of SPI register 2h (see the Register Maps section). The external PDx pins are active high; when left floating,

the device defaults to an on condition resulting from the internal pulldown resistors that cause a logic low on the

PDx pins. The device PDx thresholds are noted in the Electrical Characteristics table. The device consumes

approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down

mode.

9.4.2 Gain Control

The LMH2832 gain can be controlled from 30-dB gain (0-dB attenuation) to –9-dB gain in 1-dB steps by digitally

programming the SPI register 2h; see the Register Maps section for more details.

9.5 Programming

9.5.1 Details of the Serial Interface

The LMH2832 has a set of internal registers that can be accessed by the serial interface formed by the CS

(serial interface enable), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface

read-back data) pins. Serially shifting bits into the device is enabled when CS is low. SDI serial data are latched

at every SCLK rising edge when CS is active (low). The serial data are loaded into the register at every 16th

SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are

ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form

the register address and the remaining eight bits are the register data. The interface can function with SCLK

frequencies from 25 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. A

summary of the LMH2832 SPI protocol is:

1. SPI-1.1 interface

2. Independent channel A, B attenuation programming (6-bit gain control)

3. SPI register contents are preserved in power-down mode

4. SPI-controlled power modes (3-bit control for eight options to step down the power)

5. Powered for the main 5-V power supply

6. 1.8-V logic

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Programming (continued)

9.5.2 Timing Diagrams

Figure 45 and Figure 46 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 47

shows an example timing diagram for a streaming write cycle and Figure 48 shows an example timing diagram

for a streaming read cycle. Figure 49, Figure 50, Figure 51, and Figure 52 illustrate timing diagrams and

requirements for the clock, data input, data output, and chip select, respectively. See the Timing Requirements:

SPI table for SPI timing requirements.

CS

1

2

3

4

5

6

7

8

9

10 11

12 13 14 15 16

SCLK

SDI

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 45. SPI Write Bus Cycle Timing Diagram

CS

1

2

3

4

5

6

7

8

9

10 11

12 13 14 15 16

SCLK

SDI

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 46. SPI Read Bus Cycle Timing Diagram

CS

1

2

3

4

5

6

7

8

9

10 11

12 13 14 15 16 17 18 19 20 21 22 23 24

SCLK

Addr N

Addr N+1

SDI

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 47. SPI Streaming Write Example Timing Diagram

CS

1

2

3

4

5

6

7

8

9

10 11

12 13 14 15 16 17 18 19 20 21 22 23 24

SCLK

Addr N+1

Addr N

A6 A5 A4 A3 A2 A1 A0

SDI

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 48. SPI Streaming Read Example Timing Diagram

t_PH

t_PL

SCLK

t_PL

Figure 49. SPI Clock Timing Diagram

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Programming (continued)

SCLK

t_SU

t_H

SDI

Figure 50. SPI Data Input Timing Diagram

CS

t_ODZ

t_OD

t_ODZ

SDO_en

SDO

a) Need Title

b) Need Title

c) Need Title

Figure 51. SPI Data Output Timing Diagrams

SCLK

t_CSS

t_CSH

t_IAG

CS

a) Need Title

b) Need Title

Figure 52. SPI Chip Select Timing Diagrams

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9.6.1 Register Descriptions

Exercising the SW reset function returns all registers to the default values of the respective channel.

9.6.1.1 SW Reset Register (address = 2)

Figure 53. SW Reset Register

7

6

5

4

3

2

1

0

Reserved

R-0h

Reset B

R/W-0h

Reserved

R-0h

Reset A

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. SW Reset Register Field Descriptions

Bit

7-5

4

Field

Type

R

Reset

0h

Description

Reserved

Reset B

Reserved.

R/W

0h

This bit is a self-clearing bit.

0 = No action

1 = Reset

3-1

0

Reserved

Reset A

R

0h

Reserved.

R/W

This bit is a self-clearing bit.

0 = No action

1 = Reset

9.6.2 Power-Down Control Register (address = 3)

Figure 54. Power-Down Control Register

7

6

5

4

3

2

1

0

Reserved

R-0h

PD B

R/W-0h

Reserved

R-0h

PD A

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. Power-Down Control Register Field Descriptions

Bit

7-5

4

Field

Type

R

Reset

0h

Description

Reserved

PD B

Reserved.

R/W

0h

0 = Active

1 = PD

3-1

0

Reserved

PD A

R

0h

Reserved.

R/W

0 = Active

1 = PD

9.6.3 Channel A RW0 Register (address = 4)

Figure 55. Channel A RW0 Register

7

6

5

4

3

2

1

0

Channel A RW0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Channel A RW0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Channel A RW0

R/W

0h

These bits drive the output CHA_RW0[7:0] and are reset by a

device reset or Reset A. Table 10 lists controls for this register.

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9.6.4 Channel A RW1 Register (address = 5)

Figure 56. Channel A RW1 Register

7

6

5

4

3

2

1

0

Channel A RW1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. Channel A RW1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Channel A RW1

R/W

0h

These bits drive the output CHA_RW1[7:0] and are reset by a

device reset or Reset A. Table 11 lists controls for this register.

9.6.5 Channel B RW0 Register (address = 6)

Figure 57. Channel B RW0 Register

7

6

5

4

3

2

1

0

Channel B RW0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Channel B RW0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Channel B RW0

R/W

0h

These bits drive the output CHB_RW0[7:0] and are reset by a

device reset or Reset B. Table 10 lists controls for this register.

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9.6.6 Channel B RW1 Register (address = 7)

Figure 58. Channel B RW1 Register

7

6

5

4

3

2

1

0

Channel B RW1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. Channel B RW1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Channel B RW1

R/W

0h

These bits drive the output CHB_RW1[7:0] and are reset by a

device reset or Reset B. Table 11 lists controls for this register.

Table 10. Bias Control Register Bit Settings (Channels A, B)⁽¹⁾

7

0

1

6

0

1

X

5

0

1

X

4

0

1

X

3

0

1

X

2

0

1

0

1

0

1

X

1

X

(1) Default value: 001xxxxx. Highest power: 1xxxxxxx. Lower power: 00000000.

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Table 11. Attenuator Control Register Bit Settings (Channels A, B)⁽¹⁾

7

6

5

0

1

4

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved, always read 0

(1) Default attenuation setting: xx001011. Maximum attenuation (lowest gain setting): xx100111. Minimum attenuation (highest gain setting):

xx000000.

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The LMH2832 is designed as a general-purpose, analog-to-digital converter (ADC) driver that also meets the

performance requirements for DOCSIS 3.X upstream CMTS solutions. This section describes various

requirements and considerations for using the LMH2832 and also some design examples.

10.1.1 Driving ADCs

When the amplifier is driving an ADC, the key points to consider for implementation are the signal-to-noise ratio

(SNR), spurious-free dynamic range (SFDR), and ADC input considerations, as described in this section.

A typical application of the LMH2832 involves driving a wideband, 14-bit ADC (such as the ADS54J40), as

shown in Figure 59. The LMH2832 can drive the full Nyquist bandwidth of ADCs with sampling rates up to

900 MSPS. If the front-end bandwidth of the ADC is more than 450 MHz, then use a simple noise filter to

improve SNR. Otherwise, the ADC can be connected directly to the amplifier output pins with appropriate

matching resistors to limit the full-scale input of the ADC. Note that the LMH2832 inputs must be driven

differentially using a balun or fully differential amplifiers (FDAs). For dc-coupled applications, an FDA (such as

the LMH3401 or LMH5401) that can convert a single-ended input to a differential output with low distortion is

preferred.

VS+ = 5V

10 ꢀ

R_O

Z_S= 50-Ω

OUTPx

OUTMx

1:3 ꢀ

INPx

INMx

+

-

½ LMH2832

ADC

OUT_AMP

LPF

10 ꢀ

R_O

SPI

GND

Figure 59. ADC Driver with a 50-Ω Source

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Application Information (continued)

10.1.1.1 SNR Considerations

When using the LMH2832 with a filter, the signal-to-noise ratio (SNR) of the amplifier and filter can be calculated

from the amplitude of the signal and the bandwidth of the filter. The noise from the amplifier is band-limited by

the filter with the equivalent brick-wall filter bandwidth. The amplifier and filter noise can be calculated using

Equation 3:

V²

V_O

O

SNR_AMP+FILTER= 10 × log

= 20 × log

e²

e_FILTEROUT

FILTEROUT

where:

•

e_FILTEROUT= e_NAMPOUT• √ENB

e_NAMPOUT= the output noise density of the LMH2832 (50.4 nV/√Hz) at A_V= 30 dB

ENB = the brick-wall equivalent noise bandwidth of the filter

V_O= the amplifier output signal

(3)

For example, with a first-order (N = 1) band-pass or low-pass filter with a 1000-MHz cutoff, ENB is 1.57 • f_–3dB

=

1.57 • 1000 MHz = 1570 MHz. For second-order (N = 2) filters, ENB is 1.22 • f_–3dB. When the filter order

increases, ENB approaches f_–3dB(N = 3 → ENB = 1.15 • f_–3dB; N = 4 → ENB = 1.13 • f_–3dB). Both V_Oand

e_FILTEROUTare in RMS voltages. For example, with a 2-V_PP(0.707 V_RMS) output signal and a 300-MHz, first-order,

low-pass filter, the SNR of the amplifier and filter is 56 dB with e_FILTEROUT= 50.4 nV/√Hz • √471 MHz = 1.09

mV_RMS

.

The SNR of the amplifier, filter, and ADC sum in RMS fashion, as shown in Equation 4 (SNR values in dB):

-SNR_AMP+FILTER

-SNR_ADC

10

SNR_SYSTEM= -20 × log

10

+ 10

(4)

This formula shows that if the SNR of the amplifier and filter equals the SNR of the ADC, then the combined

SNR is 3 dB lower (worse). Thus, for minimal degradation (< 1 dB) on the ADC SNR, the SNR of the amplifier

and filter must be 10 dB greater than the ADC SNR. The combined SNR calculated in this manner is usually

accurate to within ±1 dB of the actual implementation.

10.1.1.2 SFDR Considerations

The SFDR of the amplifier is usually set by the second- or third-order harmonic distortion for single-tone inputs,

and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and second-

order intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs cannot be

filtered. The ADC generates the same distortion products as the amplifier, but also generates additional spurs

(not harmonically related to the input signal) as a result of sampling and clock feed through.

When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same

spur from the ADC, as shown in Equation 5, to estimate the combined spur (spur amplitudes in dBc):

-HDx_AMP+FILTER

-HDx_ADC

20

HDx_SYSTEM= -20 × log

10

+ 10

(5)

This calculation assumes that the spurs are in phase, but usually provides a good estimate of the final combined

distortion.

For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB

higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier

and filter must be approximately 15 dB lower in amplitude than that of the converter. The combined spur

calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher

variations can be detected as a result of phase shift in the filter, especially in second-order harmonic

performance.

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Application Information (continued)

This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the

corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phase-

shift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the

expected performance calculated using Equation 5; one mechanism is the common-mode phase shift and the

other is the differential phase shift.

Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path

including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC

spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs

become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However,

there is a significant challenge in designing an amplifier-ADC interface circuit to take advantage of a common-

mode phase shift for cancellation: the phase characteristics of the ADC spur sources are unknown, thus the

necessary phase shift in the filter and signal path for cancellation is also unknown.

Differential phase shift is the difference in the phase response between the two branches of the differential filter

signal path. Differential phase shift in the filter is a result of mismatched components caused by nominal

tolerances and can severely degrade the even harmonic distortion of the amplifier-ADC chain. This effect has the

same result as mismatched path lengths for the two differential traces, and causes more phase shift in one path

than the other. Ideally, the phase responses over frequency through the two sides of a differential signal path are

identical, such that even harmonics remain optimally out of phase and cancel when the signal is taken

differentially. However, if one side has more phase shift than the other, then the even harmonic cancellation is

not as effective.

Single-order, resistor-capacitor (RC) filters cause very little differential phase shift with nominal tolerances of 5%

or less, but higher-order, inductor-capacitor (LC) filters are very sensitive to component mismatch. For instance,

a third-order Butterworth band-pass filter with a 100-MHz center frequency and a 20-MHz bandwidth displays as

much as 20° of differential phase imbalance in a SPICE Monte Carlo analysis with 2% component tolerances.

Therefore, although a prototype may work, production variance is unacceptable. For ac-coupled or dc-coupled

applications where a transformer or balun cannot be used, using first- or second-order filters is recommended to

minimize the effect of differential phase shift.

10.1.1.3 ADC Input Common-Mode Voltage Considerations (AC-Coupled Input)

When interfacing to an ADC, the input common-mode voltage range of the ADC must be taken into account for

proper operation. In an ac-coupled application between the amplifier and the ADC, the input common-mode

voltage bias of the ADC can be accomplished in different ways. Some ADCs use internal bias networks such that

the analog inputs are automatically biased to the required input common-mode voltage if the inputs are ac-

coupled with capacitors (or if the filter between the amplifier and ADC is a band-pass filter). Other ADCs supply

the required input common-mode voltage from a reference voltage output pin (often termed CM or V_CM). With

these ADCs, the ac-coupled input signal can be re-biased to the input common-mode voltage by connecting

resistors from each input to the CM output of the ADC, as shown in Figure 60. AC coupling provides dc common-

mode isolation between the amplifier and the ADC; thus, the output common-mode voltage of the amplifier is a

don’t care for the ADC.

R_O

R_CM

A_IN+

Amp

ADC

CM

A_IN-

R_CM

R_O

Figure 60. Biasing AC-Coupled ADC Inputs Using the ADC CM Output

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Application Information (continued)

10.1.1.4 ADC Input Common-Mode Voltage Considerations (DC-Coupled Input)

The LMH2832 is designed to primarily be used in ac-coupled applications only. However, the LMH2832 can be

dc-coupled if certain strict conditions are met. The LMH2832 has an internal common-mode bias equal to the

mid-supply voltage, so any dc coupling on the input or output must have a common-mode voltage that is also set

to mid-supply. To dc couple to an ADC input, the mid-supply voltage of the LMH2832 must be centered around

the ADC input common-mode. This common-mode matching can be accomplished by shifting the supplies to

center the mid-supply voltage around the ADC input common-mode voltage. However, shifting the supplies also

changes the ground reference for the digital inputs, which then likely requires a voltage-shifted interface as well.

The LMH2832 is not recommended to be operated as dc-coupled unless absolutely necessary.

10.2 Typical Applications

10.2.1 DOCSIS 3.X Driver

The LMH2832 is designed to perform best when driving differential input ADCs in high-speed applications.

Figure 61 shows an example diagram of the LMH2832 driving an ADC with a fifth-order, low-pass filter for a 75-Ω

impedance, data over cable service interface specification (DOCSIS) 3.X upstream receiver return path

application. The primary interface between the amplifier and the ADC is usually an antialiasing filter to suppress

high-frequency harmonics that otherwise alias back into the ADC FFT spectrum. Filters range from single-order

real RC poles to higher-order, resistor-inductor-capacitor (RLC) filters, depending on the application

requirements. Series output resistors (R_O) help isolate the amplifier from any capacitive load presented by the

filter, and can also be used to create a matched impedance to drive transmission lines.

VS+ = 5V

0.1 µF

24 nH

5.5 pF

24 nH

82 nH

5.5 pF

82 nH

24 nH

10 ꢀ

64.9 ꢀ

5.1 ꢀ

0.1 µF

Z_S= 75-Ω

1:2 O

INPx

INMx

OUTPx

OUTMx

100 ꢀ

+

-

½ LMH2832

½ ADS54J40

V_OCM

OUT_AMP

10 ꢀ

24 nH

SPI

GND

Figure 61. DOCSIS 3.X Driver with the ADS54J40 and a 300-MHz, 4th-Order, Butterworth, Low-Pass Filter

10.2.1.1 Design Requirements

Table 12 shows example design requirements for the LMH2832 in an upstream receiver application.

Table 12. Example Design Requirements

SPECIFICATION

Supply voltage

DESIGN REQUIREMENTS

4.75 to 5.25 V

Usable input frequency range

System voltage gain and range

Source impedance

300 MHz

33-dB voltage gain with 30-dB range

75 Ω, single-ended

> 50 dBFS

Signal path SNR at 175 MHz (measured at ADC)

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10.2.1.2 Detailed Design Procedure

To begin the design process, make sure that none of the following design parameters exceed the limits listed in

the Electrical Characteristics table, such as:

•

Supply voltage

Temperature range

Input voltage range across gain

Output current requirements

Digital I/O voltages and currents

10.2.1.2.1 Source Resistance Matching

Standard DOCSIS systems use a characteristic single-ended impedance of 75 Ω that must be properly matched

to the 150-Ω differential impedance of the LMH2832. The circuit in Figure 61 uses a transformer with a 1:2-Ω

ratio to convert the signal from single-ended to differential, and also to match the differential impedance. The

transformer also adds a signal gain of approximately 3 dB to the system with some insertion loss depending on

the chosen transformer.

10.2.1.2.2 Output Impedance Matching

For the circuit in Figure 61, the output impedance is matched to a 150-Ω characteristic impedance filter to

maximize the performance of the LMH2832. On the amplifier output side, the output impedance is matched to

150 Ω by including a 65-Ω series resistor on each output. Combined with the internal 10-Ω resistors on each

output, the total differential impedance becomes 150 Ω. The ADS54J40 has an input impedance of

approximately 600 Ω that is reduced to 150 Ω by using two 5-Ω series input resistors in parallel with two 100-Ω

series resistors. The 5-Ω series resistors are included to isolate the input capacitance of the ADC so that the

response of the filter is not affected. With both the amplifier and ADC impedances matched, any transmission

line effects of the connection are minimized.

If the ADC is physically located close enough to the amplifier, a matched impedance may not be needed; see

Driving Low Insertion-Loss Filters section for more information on driving non-matched filters.

10.2.1.2.3 Voltage Headroom Considerations

Because of the series resistors included on both the amplifier outputs and ADC inputs, the amplifier must drive a

voltage that is significantly higher than the ADC full-scale input. For the circuit in Figure 61, the ADS54J40 full-

scale input voltage is 1.9 V_PP, so the required voltage at the amplifier output pins is 3.6 V_PP. This voltage is less

than the specified output voltage of 5 V_PPfor the LMH2832, thus system performance is not limited. If the

required output voltage is higher than what the amplifier can support, then the matched resistance value can be

reduced. However, this reduction can have performance implications because more current output is required

from the amplifier.

The input voltage swing can be larger than the output voltage swing because the LMH2832 can operate as an

attenuator. To maintain the full-scale voltage of the ADS54J40 input in this application, the amplifier cannot

attenuate more than 1 dB from input to output; otherwise, the maximum input voltage swing is exceeded. If the

amplifier must be operated with more attenuation, then the output voltage must be reduced.

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10.2.1.3 Application Curve

-40

-50

-60

-70

-80

-90

Channel A to B

Channel B to A

-100

-110

0

50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

D037

Figure 62. Amplifier Dual Channel Isolation Presented to ADC Interface

10.2.2 IQ Receiver

The LMH2832 is a dual-channel device; therefore, the device has excellent gain and phase matching between

channels A and B. This matching makes the LMH2832 an excellent choice for systems that require two matched

channels (such as an IQ demodulation receiver), as shown in Figure 63. For an IQ system, both the gain and

phase must match for the real and imaginary channel. When using two single-channel amplifiers, the matching

characteristics are subject to process lot and packaging variations for two individual devices, and there is often

no way to make sure that the amplifiers match without testing each amplifier. However, the dual-channel

architecture of the LMH2832 allows for much tighter gain and phase matching with minimal crosstalk effects. For

more matching information, see the Electrical Characteristics table.

I Channel

RF IN

LPF

LMH2832

ADS54J60

LPF

Q Channel

Figure 63. IQ Receiver Block Diagram

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10.3 Do's and Don'ts

10.3.1 Do:

•

Include a thermal analysis at the beginning of the project

Use well-terminated transmission lines for all signals

Maintain symmetrical input and output trace layouts

Use solid metal layers for the power supplies

Keep signal lines as straight as possible

10.3.2 Don't:

•

Use a lower power-supply voltage than necessary

Forget about the common-mode response of filters and transmission lines

Rout digital line traces close to the analog signals and supply line traces

11 Power Supply Recommendations

The LMH2832 is designed to be used with a single supply with a range of 4.75 V to 5.25 V. The ideal supply

voltage is a 5.0-V total single-ended supply. If the supply is reduced to the minimum voltage, then the maximum

input and output voltage range is reduced by 0.25 V.

11.1 Split Supplies

Ideally, the LMH2832 uses a single-ended, 5-V supply, but the device can be operated on a split supply if

necessary. However, the digital logic is referenced to the GND pins, meaning that the logic reference shifts with

the GND supply if connected to a negative voltage and must be accounted for in the logic connections. In

general, the LMH2832 is not suggested to be operated with a split-supply configuration.

11.2 Supply Decoupling

Power-supply decoupling is critical to high-frequency performance. Onboard bypass capacitors are used on the

LMH2832EVM; however, the most important component of the supply bypassing is provided by the printed circuit

board (PCB). As illustrated in Figure 64, there are multiple vias connecting the LMH2832 power planes to the

power-supply traces. These vias connect the internal power planes to the LMH2832. Both V_CCand GND must be

connected to the internal power planes with several square centimeters of continuous plane in the immediate

vicinity of the amplifier. The capacitance between these power planes provides the bulk of the high-frequency

bypassing for the LMH2832.

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12 Layout

12.1 Layout Guidelines

With a small bandwidth greater than 1 GHz, layout for the LMH2832 is critical and nothing can be neglected. In

order to simplify board design, the LMH2832 has on-chip resistors that reduce the affect of off-chip capacitance.

For this reason, make sure that the ground layer below the LMH2832 is not cut. The recommendation to not cut

the ground plane under the amplifier input and output pins is different than many other high-speed amplifiers, but

the reason is that parasitic inductance is more harmful to the LMH2832 performance than parasitic capacitance.

By leaving the ground layer under the device intact, parasitic inductance of the output and power traces is

minimized. The DUT portion of the evaluation board layout is shown in Figure 64.

The EVM uses long-edge capacitors for the decoupling capacitors, which reduces series resistance and

increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors.

Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the

device.

The output-matching resistors are 0402 size and are placed very close to the amplifier output pins, which

reduces both parasitic inductance and capacitance. The use of 0603 output-matching resistors produces a

measurable decrease in bandwidth.

When the signal is on a 50-Ω or 75-Ω controlled impedance transmission line, the layout then becomes much

less critical. The transition from the 50-Ω or 75-Ω transmission line to the amplifier pins is the most critical area.

12.2 Layout Example

Figure 64. Layout Example

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ZHCSF77A –JULY 2016–REVISED JULY 2016

13 器件和文档支持

13.1 器件支持

13.1.1 器件命名规则

Legend:

= Pin 1 Designator

LMH2832

IRHA

LMH2832 = Device Name

TI = Texas Instruments

TI YMS

LLLL

YM = Year Month Date Code

S = Assembly Site Code

LLLL = Assembly Lot Code

图 65. 器件标识信息

13.2 文档支持

13.2.1 相关文档ꢀ


型号：	LMH2832
厂家：	TEXAS INSTRUMENTS
描述：	全差分、双路、1.1GHz 数字可变增益放大器放大器
文件：	总47页 (文件大小：2579K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMH2832 [TI]

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