LMH32404-Q1 [TI]
具有集成多路复用功能的汽车类四通道差分输出跨阻放大器;
| 型号： | LMH32404-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成多路复用功能的汽车类四通道差分输出跨阻放大器 放大器 |
| 文件： | 总39页 (文件大小：2331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH32404-Q1
ZHCSMW3A –DECEMBER 2020 –REVISED NOVEMBER 2021
LMH32404-Q1 具有集成式钳位和环境光消除功能的汽车类四通道、差分输
出、多路复用跨阻放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 增益：20kΩ
LMH32404-Q1 是一款四通道、单端输入转差分输出跨
阻放大器 (TIA)，适用于光探测和测距 (LIDAR) 应用和
激光测距系统。
• 性能，CPD = 1pF：
LMH32404-Q1 在每个通道上集成了一个 100mA 钳
位，可以为放大器提供保护并允许器件迅速从过载输入
状况中恢复。LMH32404-Q1 还在每个通道上提供一个
集成式环境光消除 (ALC) 电路，可取代光电二极管与
放大器之间的交流耦合，从而节省布板空间和系统成
本。测量直流和低频时，应禁用ALC 回路。
– 带宽：350 MHz
– 输入参考噪声：56nARMS
– 上升，下降时间：1.25ns
• 静态电流：28 mA/通道
• 待机模式：10 mA/通道
• 低功耗模式：2.5mA（4 个通道）
• 通道开关时间：10ns
• 集成式环境光消除
• 集成式100mA 保护钳位
• 4 个输入通道和4 个差分输出通道
• 集成的多路复用器可实现光学传感器和ADC/TDC
之间的灵活配置
每个 LMH32404-Q1 通道在输出端有集成的开关，用
于断开差分输出放大器与输出引脚的连接，并将通道置
于待机模式。在不同通道之间切换时，转换时间仅为
10ns。当不使用放大器时，可以使用 EN 引脚将
LMH32404-Q1 置于低功耗模式，以节省能源。
器件信息(1)
• 可以将多个LMH32404 并联组合，以实现更宽的视
野(FoV)
封装尺寸（标称值）
器件型号
封装
VQFN (28)
LMH32404-Q1
5.00mm × 4.00mm
2 应用
(1) 要了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 机械扫描激光雷达
• 固态扫描激光雷达
• 激光测距仪
.
.
• 安全区域扫描仪
VDD1x
EN
VDD2
M1-4
100mA
Clamp
10 kΩ
OUT1Þ
10 Ω
IN1
TIA
+
2x
œ
10 Ω
Ambient Light
Cancellation
OUT1+
100mA
Clamp
10 kΩ
OUT2Þ
10 Ω
10 Ω
TIA
+
2x
œ
IN2
Ambient Light
Cancellation
OUT2+
100mA
Clamp
10 kΩ
OUT3Þ
10 Ω
10 Ω
TIA
+
2x
œ
IN3
Ambient Light
Cancellation
OUT3+
100mA
Clamp
10 kΩ
OUT4Þ
10 Ω
10 Ω
TIA
+
2x
œ
IN4
Ambient Light
Cancellation
OUT4+
Output
Common-Mode
闭环带宽
VOD
Output Offset
GND
VOCM
IDC EN
简化版方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA63
LMH32404-Q1
ZHCSMW3A –DECEMBER 2020 –REVISED NOVEMBER 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 25
9 Power Supply Recommendations................................28
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Example...................................................... 29
11 Device and Documentation Support..........................30
11.1 Device Support........................................................30
11.2 Documentation Support.......................................... 30
11.3 Receiving Notification of Documentation Updates..30
11.4 支持资源..................................................................30
11.5 Trademarks............................................................. 30
11.6 Electrostatic Discharge Caution..............................30
11.7 术语表..................................................................... 30
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics.............................................6
6.6 Electrical Characteristics: Logic Threshold and
Switching Characteristics ............................................. 9
6.7 Typical Characteristics..............................................10
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................18
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2020) to Revision A (November 2021)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
IN1
VDD1
IN2
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
OUT1œ
OUT1+
OUT2œ
OUT2+
OUT3œ
OUT3+
OUT4œ
OUT4+
VDD1
VDD1
IN3
Thermal
Pad
VDD1
IN4
Not to scale
图5-1. RHF Package, 28-Pin VQFN, Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
NO.
9
I
I
Device enable pin. EN = logic low = normal operation (default); EN = logic high = low power mode.(1)
Amplifier ground.
GND
11,26
Ambient light cancellation loop enable. IDC_EN = logic low = enable DC cancellation (default);
IDC_EN = logic high = disable DC cancellation.(1)
IDC_EN
28
I
IN1
IN2
IN3
IN4
1
3
6
8
I
I
I
I
Transimpedance amplifier input - Channel 1.
Transimpedance amplifier input - Channel 2.
Transimpedance amplifier input - Channel 3.
Transimpedance amplifier input - Channel 4.
Select Channel 1. M1 = logic high = Channel 1 operational and output switches closed. M1 = logic low
(default) = Channel 1 in standby power mode and output switches open. (1)
M1
25
24
13
12
22
21
20
19
I
I
Select Channel 2. M2 = logic high = Channel 2 operational and output switches closed. M2 = logic low
(default) = Channel 2 in standby power mode and output switches open. (1)
M2
Select Channel 3. M3 = logic high = Channel 3 operational and output switches closed. M3 = logic low
(default) = Channel 3 in standby power mode and output switches open. (1)
M3
I
Select Channel 4. M4 = logic high = Channel 4 operational and output switches closed. M4 = logic low
(default) = Channel 4 in standby power mode and output switches open. (1)
M4
I
Channel 1 inverting amplifier output. When light is incident on the photodiode the output pin transitions
in a negative direction from the no light condition.
O
O
O
O
OUT1–
OUT1+
OUT2–
OUT2+
Channel 1 noninverting amplifier output. When light is incident on the photodiode the output pin
transitions in a positive direction from the no light condition.
Channel 2 inverting amplifier output. When light is incident on the photodiode the output pin transitions
in a negative direction from the no light condition.
Channel 2 noninverting amplifier output. When light is incident on the photodiode the output pin
transitions in a positive direction from the no light condition.
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Channel 3 inverting amplifier output. When light is incident on the photodiode the output pin transitions
in a negative direction from the no light condition.
18
O
O
O
O
I
OUT3–
Channel 3 noninverting amplifier output. When light is incident on the photodiode the output pin
transitions in a positive direction from the no light condition.
OUT3+
OUT4–
OUT4+
VDD1
17
16
Channel 4 inverting amplifier output. When light is incident on the photodiode the output pin transitions
in a negative direction from the no light condition.
Channel 4 noninverting amplifier output. When light is incident on the photodiode the output pin
transitions in a positive direction from the no light condition.
15
Positive power supply for the transimpedance amplifier stage. Each pin should be tied to the same
power supply with independent power-supply bypassing.
2, 4, 5, 7
14,23
Positive power supply for the differential amplifier stage. Tie VDD1 and VDD2 to the same power
supply with independent power-supply bypassing.
VDD2
I
VOCM
VOD
27
10
I
I
Differential amplifier common-mode output control.
Differential amplifier differential output offset control.
Thermal pad
Connect the thermal pad to the same potential as pin 11 and 26 (GND).
—
(1) TI recommends driving a digital pin with a low-impedance source rather than leaving the pin floating because fast-moving transients
can couple into the pin and inadvertently change the logic level.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.65
VDD
VDD
25
UNIT
V
(2)
VDD1, VDD2
Total supply voltage, (VDD
Voltage at Output pins
Voltage at Logic pins
)
0
V
V
–0.2
IIN
Continuous current into IN
Continuous output current
Junction temperature
mA
mA
°C
°C
°C
IOUT
TJ
35
150
125
150
TA
Operating free-air temperature
Storage temperature
–40
–65
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD1 and VDD2 should always be tied to the same supply and have separate power-supply bypass capacitors.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±1500
±1000
V(ESD) Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.45
125
UNIT
V
VDD
TA
Total supply voltage
3.3
Operating free-air temperature
°C
–40
6.4 Thermal Information
LMH32404-Q1
RHF (VQFN)
28 PINS
39.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
31.5
17.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ΨJT
17.8
ΨJB
RθJC(bot)
6.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω(differential load between OUT+
and OUT-), and TA = 25℃. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
tR, tF
Small-signal bandwidth
VOUT = 100 mVPP
350
300
1.25
750
12
MHz
MHz
ns
Large-signal bandwidth
VOUT = 1 VPP
Rise and fall time
VOUT = 100 mVPP, Pulse width = 10 ns
VOUT = 1 VPP, Pulse width = 10 ns
IIN = 100 mA, Pulse width = 10 ns
IIN = 100 mA, Pulse width = 10 ns
f = 250 MHz
Slew Rate(4)
V/µs
ns
Overload recovery time (1% settling)
Overload pulse width extension(5)
Integrated input current noise
Adjacent channel crosstalk
Non adjacent channel crosstalk
All hostile channels crosstalk
5
ns
iN
56
nARMS
dBc
dBc
dBc
f = 100 MHz
-49
-58
-39
f = 100 MHz
f = 100 MHz
DC PERFORMANCE
Z21
Small-signal transimpedance gain(6)
17
20
23
20
kΩ
Channel-to-channel gain matching
Differential output offset voltage
±0.1
%
VOD
±5
mV
–20
(VOUT– –VOUT+
)
Differential output offset voltage
drift, ΔVOD/ΔTA
±20
µV/°C
INPUT PERFORMANCE
VIN Default input bias voltage
Input pin floating
2.42
60
2.47
1.1
72
2.52
V
Input pin floating
mV/°C
µA
Default input bias voltage drift, ΔVIN/ΔTA
IIN
DC Input current range
Z21 < 3-dB degradation from IIN = 5 µA
OUTPUT PERFORMANCE
VOH
VOL
Single-sided output voltage swing(high)(2) TA = 25°C
Single-sided output voltage swing (low)(2) TA = 25°C
2.85
24
2.9
0.36
26.6
27.1
25.1
70
V
V
0.39
32
TA = 25°C, IIN = 50 µA , RL = 25 Ω
TA = –40°C, IIN = 50 µA , RL = 25 Ω
TA = 125°C, IIN = 50 µA , RL = 25 Ω
IOUT
Linear output drive (sink and source)
mA
ISC
Output short-circuit current (differential) (3)
DC differential output impedance
mA
Ω
MX = high
MX = low
18
21
24
ZOUT
1
MΩ
OUTPUT COMMON-MODE CONTROL (VOCM) PERFORMANCE
SSBW
LSBW
Small-signal bandwidth
Large-signal bandwidth
VOCM = 100 mVPP at VOCM pin
VOCM = 1 VPP at VOCM pin
375
120
MHz
MHz
f = 10 MHz, 1 nF capacitor to GND on VOCM
pin
eN
Output common-mode noise
15
nV/√Hz
IN floating, VOCM = 1.1 V (driven)
1
0.5%
±1%
17
V/V
Gain, (ΔVOCM/ΔVOCM)
AV
TA = 25°C, VOCM = 0.7 V to 2.3 V
2%
45
–2%
–25
Gain Error
TA = –40°C to 125°C, VOCM = 0.7 V to 2.3 V
Input impedance
kΩ
mV
V/A
VOCM
VOCM pin default offset from 1.1 V
VOCM error vs Input current, ΔVOCM/ΔIIN
VOCM floating, (VOCM - 1.1 V)
VOCM driven to 1.1 V
8
10
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6.5 Electrical Characteristics (continued)
VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω(differential load between OUT+
and OUT-), and TA = 25℃. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output common-mode voltage,
(VOUT+ + VOUT-)/2
VOCM
TA = 25°C, VOCM floating
1
1.1
1.2
V
Output common-mode voltage drift,
(ΔVOCM/ΔTA)
300
1.1
µV/°C
TA = –40°C to 125°C, VOCM floating
Output common-mode voltage,
(VOUT+ + VOUT-)/2
VOCM
TA = 25°C, VOCM driven to 1.1V
1.05
1.15
1.3
V
µV/°C
V
Output common-mode voltage drift,
(ΔVOCM/ΔTA)
TA = –40°C to 125°C,
VOCM driven to 1.1V
–10
1.2
TA = 25°C, VOCM offset shift from VOCM = 1.1
V (driven) < 10-mV
VOCM headroom to positive supply
voltage
TA = –40°C to 125°C, VOCM offset shift from
VOCM = 1.1 V (driven) < 10-mV
1
V
TA = 25°C, VOCM offset shift from VOCM = 1.1
V (driven) < 10-mV
0.2
0.65
V
VOCM headroom to negative supply
voltage
TA = –40°C to 125°C, VOCM offset shift from
VOCM = 1.1 V (driven) < 10-mV
0.25
V
OUTPUT DIFFERENTIAL OFFSET (VOD) PERFORMANCE
SSBW
LSBW
VOD
Small-signal bandwidth
Large-signal bandwidth
Default VOD pin voltage
Differential output offset,
VOD = 100 mVPP
VOD = 1 VPP
45
17
MHz
MHz
V
0.5
VOS_D
IN floating, VOD = 0.5 V
IN floating, VOD = 0.5 V
IN floating, VOD floating
IN floating, VOD floating
IN floating, VOCM = 1.1 V (driven)
470
470
500
0.03
500
530
530
mV
mV/℃
mV
VOUT = (VOUT– –VOUT+
)
Differential output offset drift, ΔVOS_D
ΔTA
/
/
Differential output offset,
VOS_D
VOUT = (VOUT– –VOUT+
)
Differential output offset drift, ΔVOS_D
ΔTA
0.05
-1.01
mV/℃
V/V
Gain, (ΔVOUT/ΔVOD),
where VOUT = (VOUT– –VOUT+
)
AV
±0.8%
±1.5%
2.5
5%
TA = 25℃, VOD = 0.3 V to 1.2 V
–5%
Gain Error
TA = –40℃to 125℃, VOD = 0.3 V to 1.2 V
Input impedance
kΩ
AMBIENT LIGHT CANCELLATION PERFORMANCE (IDC_EN = 0 V) (7)
20
60
IIN = 0 µA →10 µA
Settling time, 1% (2 mV) of settled VOS
IIN = 10 µA →0 µA
µs
Differential output offset (VOUT– –VOUT+
shift from IDC = 10 µA < 10 mV
)
Ambient light current cancellation range
POWER SUPPLY
1.8
2.5
mA
MX = 3.3 V, TA = 25°C
MX = 0 V, TA = 25°C
VDD1 = VDD2
22.8
8.5
54
27.7
10.4
74
32.5
13.4
Quiescent current, per channel,
(VDD1 + VDD2)
IQ
mA
dB
PSRR+ Positive power-supply rejection ratio
SHUTDOWN
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6.5 Electrical Characteristics (continued)
VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω(differential load between OUT+
and OUT-), and TA = 25℃. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.35
2.25
2.55
MAX
UNIT
TA = 25°C
3
Total disabled quiescent current
IQ
mA
TA = –40°C
TA = 125°C
(EN = VDD
)
(1) Input capacitance of photodiode.
(2) Output slammed to the rail and VOCM adjusted to achieve output swing.
(3) Device cannot withstand continuous short-circuit between the differential outputs.
(4) Average of rising and falling slew rate.
(5) Pulse width extension measured at 50% of pulse height of a square wave.
(6) Gain measured at the amplifier output pins when driving a 100-Ωresistive load. At higher resistor loads the gain will increase.
(7) Enabling the ambient light cancellation loop will add noise to the system.
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6.6 Electrical Characteristics: Logic Threshold and Switching Characteristics
VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω(differential load between OUT+
and OUT-), and TA = 25℃. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD PERFORMANCE
EN CONTROL TRANSIENT PERFORMANCE
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA
Enable transition-time (1% settling)
Disable transition-time (1% settling)
Enable transition-time (1% settling)
Disable transition-time (1% settling)
250
8
ns
ns
µs
ns
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA
Ambient loop enabled, fIN = 25 MHz, VOUT
1 VPP, IDC = 100 µA
=
=
4
Ambient loop enabled, fIN = 25 MHz, VOUT
1 VPP, IDC = 100 µA
3
MULTIPLEXER CONTROL TRANSIENT PERFORMANCE
Channel to Channel transition-time
(1% settling)
Ambient loop disabled, 0 →0.5V transition
at VOUT.
10
8
ns
ns
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA
Disable transition-time (1% settling)
(1) Input capacitance of photodiode.
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6.7 Typical Characteristics
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
89
86
83
80
77
74
71
89
86
83
80
77
74
71
PCB Only
0.5 pF
1 pF
2 pF
3 pF
25 °C
125 °C
-40 °C
4.7 pF
10 pF
10M
100M
1G
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
VOUT = 100 mVPP
VOUT = 100 mVPP
图6-1. Small Signal Response vs Input Capacitance
89
图6-2. Small Signal Response vs Ambient Temperature
89
86
83
80
77
74
71
86
83
80
77
Channel 1
Channel 2
Channel 3
Channel 4
VOUT = 0.1 Vpp
VOUT = 1.0 Vpp
VOUT = 1.5 Vpp
74
71
10M
100M
1G
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
VOUT = 100 mVPP
.
图6-3. Small Signal Response vs Channels
图6-4. Frequency Response vs Output Swing
1
0
Amplifier Disabled
Amplifier Enabled
10k
-1
-2
-3
-4
-5
1k
100
10
ALC Disabled
ALC Enabled
1M
10M
100M
Frequency (Hz)
1G
1M
10M
Frequency (Hz)
IDC_IN = 100 µA
IDC_IN = 100 µA
图6-6. Closed-Loop Output Impedance vs Frequency
图6-5. Low-Side Frequency Response vs Ambient Light
Cancellation
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6.7 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
30
10
40
CPD = none
CPD = 0.5 pF
CPD = 1 pF
CPD = 2 pF
CPD = 3 pF
CPD = 4.7 pF
CPD = 10 pF
IDC = 0 A
IDC = 10 A
IDC = 100 A
IDC = 1 mA
10
1
1
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
.
.
图6-7. Input Noise Density vs Input Capacitance
图6-8. Input Noise Density vs Ambient Light DC Current
200
TA = 25 °C
TA = -40 °C
TA = 125 °C
Differential Noise
Single-Ended Noise
10
100
1
10k
10
10k
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
.
.
图6-9. Input Noise Density vs Ambient Temperature
-20
图6-10. Output Noise Density vs Output Configuration
-20
-30
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
100 mVpp
1 Vpp
100 mVpp
1 Vpp
-90
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
.
.
图6-11. Adjacent Channel Crosstalk
图6-12. Non-Adjacent Channel Crosstalk
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6.7 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
.
.
图6-13. Pulse Response vs Output Swing
图6-14. Overloaded Pulse Response
.
.
图6-15. Turn-On Time
图6-16. Turn-Off Time
0 →0.5V transition at VOUT (1% settling)
图6-17. Channel Turn-On Response
.
图6-18. Channel Turn-Off Response
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6.7 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
IDC_IN = 0 µA →100 µA, VOD = 0.5 V
IDC_IN = 100 µA →0 µA, VOD = 0.5 V
图6-19. Ambient Loop Cancellation Settling Time (1)
图6-20. Ambient Loop Cancellation Settling Time (1)
40
40
Gain Channel 1
Gain Channel 2
Gain Channel 3
Gain Channel 4
125 °C
-40 °C
25 °C
30
20
30
20
10
9
10
9
8
8
-100 -80 -60 -40 -20
0
20
40
60
80 100
-100 -80 -60 -40 -20
0
20
40
60
80 100
Input Current (A)
Input Current (A)
.
.
图6-21. Transimpedance Gain vs Input Current
2.5
图6-22. Transimpedance Gain vs Ambient Temperature
2.6
2.25
2
2.55
2.5
1.75
1.5
1.25
1
0.75
0.5
0.25
0
2.45
Unit 1
Unit 2
Unit 3
Unit 1
Unit 2
Unit 3
2.4
-40
-20
0
20
40
60
80
100 120 140
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Supply Voltage (V)
3
3.3
Temperature (°C)
.
.
图6-24. Input Bias Voltage vs Ambient Temperature (2)
图6-23. Input Bias Voltage vs Supply Voltage (2)
1
2
Differential Output Voltage = (Vout+ - Vout-).
Typical units from different lots.
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6.7 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
30
29
28
27
26
35
30
25
20
15
10
5
Unit 1
Unit 2
Unit 3
125 °C
-40 °C
25 °C
0
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
3.5
Temperature (°C)
Supply Voltage (V)
.
.
图6-25. Quiescent Current (Per Channel) vs Ambient
图6-26. Quiescent Current (Per Channel) vs Supply Voltage
Temperature (2)
1.8
1.7
1.6
1.2
1.1
1
1.5
0.9
Vout- (V)
Vout+ (V)
Vout- (V)
Vout+ (V)
1.4
1.3
1.2
1.1
1
0.8
0.7
0.6
0.5
0.4
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Input Current (A)
Input Current (A)
VOD = 0.75 V, VOCM = 1.4 V
图6-27. High-Side Swing vs Input Current
VOD = 0.75 V, VOCM = 0.8 V
图6-28. Low-Side Swing vs Input Current
500
495
490
485
480
475
470
465
460
455
450
1.5
1.2
0.9
0.6
0.3
0
-40 °C
25 °C
125 °C
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
0
0.3
0.6
0.9
1.2
1.5
1.8
2
Input Current (mA)
Differential Output Offset Set (V)
VOD = open
.
图6-30. Ambient Light Cancellation Range vs Ambient
图6-29. Differential Output Offset Gain
Temperature
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6.7 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted)
35
30
25
20
15
10
5
2250
2000
1750
1500
1250
1000
750
125 °C
-40 °C
25 °C
500
250
0
0
24
25
26
27
28
29
30
31
32
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Enable Voltage (EN) (V)
3
3.3
Quiescent Current (mA)
µ = 27.2 mA, σ= 0.27 mA
图6-32. Quiescent Current Distribution
.
图6-31. Logic Threshold vs Ambient Temperature
1750
1750
1500
1250
1000
750
500
250
0
1500
1250
1000
750
500
250
0
1
1.05
1.1
1.15
1.2
1.25
17
18
19
20
21
22
23
Output Common-Mode Voltage (V)
Gain (k)
µ = 1.1 V, σ= 2 mV
µ = 20.5 kΩ, σ= 0.2 kΩ
图6-33. Transimpedance Gain Distribution
图6-34. Output Common-Mode Voltage (VOCM) Distribution
2500
2250
2000
1750
1500
1250
1000
750
2250
2000
1750
1500
1250
1000
750
500
500
250
250
0
0
450 460 470 480 490 500 510 520 530 540 550
Differential Output Voltage (mV)
17.5 18 18.5 19 19.5 20 20.5 21 21.5 22 22.5 23
Differential Output Impedance ()
µ = 493 mV, σ= 2.8 mV
µ = 19.9 Ω, σ= 0.14 Ω, Device Enabled
图6-35. Differential Output Offset Voltage (VOD) Distribution
图6-36. Differential Output Impedance (ZOUT) Distribution
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7 Detailed Description
7.1 Overview
The LMH32404-Q1 is a quad-channel, differential output, high-speed transimpedance amplifier (TIA) geared
towards light detection and ranging (LIDAR) and laser distance measurement systems. Each LMH32404-Q1
channel has integrated switches on the output to disconnect the differential output amplifier from the output pins.
This enables the LMH32404-Q1 to be highly configurable in a multi-channel LIDAR system. The LMH32404-Q1
device is designed to work with photodiodes (PDs), for example avalanche photodiodes (APDs), connected in
configurations that can source or sink the current. When the photodiode sinks the photocurrent (anode is biased
to a negative voltage and cathode is tied to the amplifier input) the fast recovery clamp activates when the
amplifier input is overloaded. When the photodiode sources the photocurrent (cathode is biased to a positive
voltage and anode is tied to the amplifier input) a soft clamp activates when the amplifier input is overloaded.
When the soft clamp activates the amplifier takes longer to recover. The recovery time depends on the level of
input overload. The LMH32404-Q1 is offered in a space-saving 5-mm × 4-mm, 28-pin VQFN package and is
rated over a temperature range from –40°C to +125°C.
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7.2 Functional Block Diagram
M1 M2
VDD2
VDD1
100mA
Clamp
10 k
Mid-scale
Level Shift
Buffer
IDC + ISIG
Differential Output ADC Driver
IN1
ISIG
R
R
2.4R
10
OUT1
TIA
IDC
+
–
Ambient Light
Cancellation
VBIAS
2.4R
10
VREF
OUT1+
100mA
Clamp
Mid-scale
Buffer
10 k
IDC + ISIG
IN2
ISIG
R
R
2.4R
2.4R
10
10
OUT2
TIA
IDC
+
–
Ambient Light
Cancellation
VBIAS
VREF
OUT2+
100mA
Clamp
10 k
IDC + ISIG
IN3
ISIG
R
R
2.4R
2.4R
10
10
OUT3
TIA
IDC
+
–
Ambient Light
Cancellation
VBIAS
VREF
OUT3+
100mA
Clamp
10 k
IDC + ISIG
IN4
ISIG
R
R
2.4R
2.4R
10
OUT4
TIA
IDC
+
–
Ambient Light
Cancellation
VBIAS
10
VDD
VREF
OUT4+
VOCM
VDD
Mid-scale
Buffer
Voltage to
Current
VOD
M4 M3
GND
EN
IDC EN
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7.3 Feature Description
7.3.1 Clamping and Input Protection
The LMH32404-Q1 device is optimized to work with photodiodes (PD) configurations that can source or sink
current; however, the LMH32404-Q1 is optimized for a sinking current configuration. It is assumed that the
LMH32404-Q1 device is being used with a PD that is configured with its cathode tied to the amplifier input and
the anode tied to a negative supply voltage, unless stated otherwise.
The LMH32404-Q1 features two internal clamps, a fast recovery clamp and a soft clamp. The fast recovery
clamp is the active clamp when the photodiode is sinking a photocurrent. The soft clamp is the active clamp
when the photodiode is sourcing a photocurrent. Stray reflections from nearby objects with high reflectivity can
produce large output current pulses from the PD. The linear input range of the LMH32404-Q1 is approximately
65 µA. Input currents in excess of the linear current range will cause the internal nodes of the amplifier to
saturate, which increases the amplifier recovery time. The end result broadens the output pulse, which leads to
blind zones.
To protect against this condition, the LMH32404-Q1 features an integrated fast recovery clamp that absorbs and
diverts the excess current to the positive supply (VDD1) when the amplifier detects its nodes entering a saturated
condition. The integrated clamp minimizes the pulse extension to less than a few nanoseconds for input pulses
up to 100 mA. The power-supply pins (VDD1 and VDD2) must have their own bypass capacitors to prevent large
input pulses from affecting the differential output stage. The clamp circuitry is active when the amplifier is in
standby mode and low-power mode, thereby protecting the TIA input.
7.3.2 ESD Protection
All LMH32404-Q1 IO pins (excluding VDD1, VDD2, and GND) have an internal electrostatic discharge (ESD)
protection diode to the positive and negative supply rails to protect the amplifier from ESD events.
7.3.3 Differential Output Stage
Each channel of the LMH32404-Q1 has a differential output stage that performs two functions that are common
across all differential amplifiers. This stage does the following:
1. Converts the single-ended output from the TIA stage to a differential output.
2. Performs a common-mode output shift to match the specified ADC input common-mode voltage.
The VOD pin is functional only when the LMH32404-Q1 device is used with a PD that sinks the photocurrent.
Set VOD = 0 V when the LMH32404-Q1 device is interfaced with a PD that sources the photocurrent. The
differential output stage has two 10-Ω series resistors on its output to isolate the amplifier output stage
transistors from the package bond-wire inductance and printed circuit board (PCB) capacitance. The net gain of
the LMH32404-Q1 (TIA plus the output stage) is 20 kΩ per channel when driving an external 100-Ω resistor.
When the external load resistor is increased above 100 Ω, the effective gain from the IN pin to the differential
output pin increases. Consequently, when the external load resistor is decreased to less than 100 Ω, the
effective gain from the IN pin to the differential output pin decreases as a result of the larger voltage drop across
the two internal 10-Ω resistors. The effective TIA gain is 24 kΩ when there is no load resistor between the
OUT+ and OUT–pins.
The output common-mode voltage of the LMH32404-Q1 can be set externally through the VOCM pin. A resistor
divider internal to the amplifier, between VDD2 and ground sets the default voltage to 1.1 V. The internal
resistors generate common-mode noise that is typically rejected by the CMRR of the subsequent ADC stage. To
maximize the amplifier SNR, place an external noise bypass capacitor to ground on the VOCM pin. In single-
ended signal chains, such as ToF systems that use time-to-digital converters (TDCs), only a single output per
channel of the LMH32404-Q1 is needed. In such situations, terminate the unused differential output in the same
manner as the used output to maintain balance and symmetry. The signal swing of the single-ended output is
half the available differential output swing. Additionally, the common-mode noise of the output stage, which is
typically rejected by the differential input ADC, is now added to the total noise, further degrading SNR.
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The output stage of the LMH32404-Q1 has an additional VOD input that sets the differential output between
OUT– and OUT+. 图 7-1 shows how each output pin of the LMH32404-Q1 is at the voltage set by the VOCM
pin (default = 1.1 V) when the photodiode output current is zero and the VOD input is set to 0 V. When the VOD
pin is driven to a voltage of X volts, the two output pins are separated by X volts when the photodiode current is
zero. The average voltage is still equal to VOCM. For example, 图 7-2 shows how if VOCM is set to 1.1 V and
VOD is set to 0.4 V, then OUT–= 1.1 V + 0.2 V = 1.3 V and OUT+ = 1.1 V –0.2 V = 0.9 V.
The VOD output offset feature is included in the LMH32404-Q1 because the output current of a photodiode is
unipolar. Depending on the reverse bias configuration, a photodiode can either sink or source current, but cannot
do both at the same time. With the anode connected to a negative bias and the cathode connected to the TIA
stage input, the photodiode can only sink current, which implies that the TIA stage output swings in a positive
direction above its default input bias voltage. Subsequently, OUT– only swings below VOCM and OUT+ only
swings above VOCM. 图 7-1 shows how the with VOD = 0 V, the LMH32404-Q1 only uses half its output swing
range (VOUT = VOUT+ – VOUT–), because one output never swings below VOCM and the other output never
goes above VOCM. The signal dynamic range in this case is 0.4 VPP –0 V = 0.4 VPP
.
图 7-2 shows how the VOD pin voltage allows OUT– to be level-shifted above VOCM, and OUT+ to be level-
shifted below VOCM to maximize the output swing capabilities of the amplifier. The signal dynamic range in this
case is 0.4 VPP − (-0.4 VPP) = 0.8 VPP
.
VOUT = 0.4 VPP
APD Excited
VOUT = 0.4 VPP
APD Excited
VOUTÞ
VOUT+
VOUTÞ
VOUT+
1.3 V
1.3 V
VOD = 0.4 V
VOCM = 1.1 V
VOD = 0 V
VOCM = 1.1 V
0.9 V
0.9 V
VOUT = Þ0.4 VPP
No output from APD
VOUT = 0 VPP
No output from APD
图7-2. Single-Ended Outputs With VOD = 0.4 V
图7-1. Single-Ended Outputs With VOD = 0 V
When the LMH32404-Q1 drives a 100-Ω load, the voltage set at the VOD pin is equal to the differential output
offset (VOUT = VOUT+ – VOUT–) when the input signal current is zero. Use 方程式 1 to calculate the differential
output offset under other load conditions.
RL
VOD = 1.2 × VOD ×
R
(
+ 20
)
L
(1)
where
• VOD = Voltage applied at pin 10
• VOD = (VOUT– –VOUT+
)
• RL = External load resistance
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7.4 Device Functional Modes
7.4.1 Ambient Light Cancellation (ALC) Mode
The LMH32404-Q1 has an integrated DC cancellation loop that cancels and voltage offsets from incidental
ambient light. The ALC mode only works when the PD is sinking the photocurrent. The DC cancellation loop is
enabled by setting IDC_EN low. Incident ambient light on a photodiode produces a DC current resulting in an
offset voltage at the output of the TIA stage.
If the photodiode produces a DC output current resulting from ambient light, the output of the level-shift buffer
stage is offset from the reference voltage VREF. The ALC loop detects this offset and produces an opposing DC
current to compensate for the differential offset voltage at its input. The loop has a high-pass cutoff frequency of
400 kHz. The ambient light cancellation loop is disabled when the amplifier is placed in low-power mode.
The shot noise current introduced by the DC cancellation loop increases the overall amplifier noise; so, if the
ambient light level is negligible, then disable the loop to improve SNR. The cancellation loop helps save PCB
space and system costs by eliminating the need for external AC coupling passive components. Additionally, the
extra trace inductance and PCB capacitance introduced by using external AC coupling components degrades
the LMH32404-Q1 dynamic performance.
The ambient light cancellation loop is active (depending on IDC_EN configuration) when a channel(s) is in
standby mode. The ambient light cancellation loop is disabled when the amplifier is placed in low-power mode.
When the LMH32404-Q1 is brought out of low-power operation the ambient light cancellation loop requires
several time constants to settle. The time constant is based on the 400-kHz cutoff frequency of the loop. When in
standby mode, the ALC loop is still active depending on IDC_EN configuration.
7.4.2 Channel Multiplexer Mode
The LMH32404-Q1 is a highly integrated transimpedance amplifier device with four independent channels. Each
channel has its own single-ended input, differential output stage and multiplexing switch. The integrated switch
can be used to disconnect the differential output amplifier from the output pin, thereby enabling high-impedance
output for the respective channel.
图 7-4 shows how this device feature can further save board space and cost by eliminating the need for discrete
high-speed multiplexer in a system that consists of several amplifier channels multiplexed to a single ADC
channel. When switching between different channels, the LMH32404-Q1 has a transition time of 10 ns (typical).
The disabled channel outputs are high-impedance so multiple amplifier outputs can be directly shorted to each
other. If one channel is enabled and other channels are disabled, the disabled channels will not load the enabled
channel. This further makes the LMH32404-Q1 easy to use in photodiode array applications.
Set Mx (M1, M2, M3, or M4) high for the corresponding channel to be enabled and output switches closed. Set
Mx to logic low (default state) for the corresponding channel to be disabled (standby mode) and output switches
open. When the channel is in its standby power mode, the clamp circuitry is still active thereby protecting the TIA
input. Also, when in standby mode, the ALC loop is still active depending on IDC_EN configuration.
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M1 = 3.3V M1,M2,M3 = 0V
RISO
OUT1
IN1
Channel 1
OUT1+
Closed
RISO
VBIAS
IN2
Disabled
RISO
OUT2
Channel 2
Hi-Z
OUT2+
RADC_IN
RISO
High-Speed
Differential Input
ADC
VOCM
RADC_IN
VBIAS
IN3
RISO
OUT3
Channel 3
Hi-Z
OUT3+
RISO
VBIAS
IN4
RISO
OUT4
Channel 4
Hi-Z
OUT4+
RISO
VBIAS
图7-3. Configuring LMH32404-Q1 in Channel Multiplexer Mode to Drive a Single ADC
7.4.3 Low-Power Mode
The LMH32404-Q1 can be placed in low-power mode by setting EN high, which helps in saving system power.
Enabling low-power mode puts the outputs of the internal amplifiers in the LMH32404-Q1, including the
differential outputs, in a high-impedance state.
If a system consists of high number of amplifier channels multiplexed to a few ADC channels. 图 7-4 shows how
this device feature can further save board space and cost by eliminating the need for a discrete high-speed
multiplexer. The disabled LMH32404-Q1 outputs are high-impedance so multiple LMH32404-Q1 device outputs
can be directly shorted to each other. If one LMH32404-Q1 device is enabled and others are disabled, the
disabled devices will not load the enabled device. This further makes the LMH32404-Q1 easy to use in
photodiode array applications.
When the amplifier is in its low-power mode, the clamp circuitry is still active thereby protecting the TIA input.
The ambient light cancellation loop is disabled when the amplifier is placed in low-power mode. When the
LMH32404-Q1 is brought out of low-power operation the ambient light cancellation loop requires several time
constants to settle. The time constant is based on the 400-kHz cutoff frequency of the loop.
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EN = 0V
LMH32404
Enabled
Photodiode Array
Outputs are differential
lines. Simplified here to
show configuration.
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
PD-1
Channel 1
Channel 2
Channel 3
Channel 4
PD-2
PD-3
PD-4
OUT4
High-Speed
Differential Input
ADC-1
EN = 3.3V
LMH32404
Disabled
Photodiode Array
High-Speed
Differential Input
ADC-2
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
PD-1
Channel 1
Channel 2
Channel 3
Channel 4
PD-2
PD-3
PD-4
High-Speed
Differential Input
ADC-3
OUT4
High-Speed
Differential Input
ADC-4
EN = 3.3V
LMH32404
Disabled
Photodiode Array
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
PD-1
Channel 1
Channel 2
Channel 3
Channel 4
PD-2
PD-3
PD-4
OUT4
图7-4. Configuring Three LMH32404-Q1 Devices to Drive Four ADC Channels
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
Each differential output pair of the LMH32404-Q1 can directly drive a high-speed differential input ADC. 图 8-1
shows how the effective signal the effective signal gain between the TIA input and the ADC input is 20 kΩwhen
driving an ADC with a 100-Ω differential input impedance (RADC_IN = 50 Ω). 方程式 2 gives the effective signal
gain between the TIA input and the ADC input when driving an ADC with any other value of differential input
impedance (RADC_IN ≠50 Ω).
VDD1
VDD2 Mx
100 mA
Clamp
10 k
IN
Differential Output
ADC Driver
OUT
TIA
10
RADC_IN
Ambient Light
Cancellation
VBIAS
+
–
VOCM
RADC_IN
ADC12QJ1600
IDC EN
VOD
10
Output Offset
GND
OUT+
EN
图8-1. LMH32404-Q1 (Single Channel) to ADC Interface
2 ì R ADC _IN
A V = 20 kꢀ ì 1.2 ì
2 ì R
+ 20 ꢀ
ADC _IN
(2)
where
• AV = Differential gain from the TIA input to the ADC input
• RADC_IN = Input resistance of the ADC
图 8-2 shows that in some designs a matching resistor network can be inserted between the LMH32404-Q1
output and the ADC inputs. 方程式 3 gives the effective gain from the TIA input to the ADC input when using a
matching resistor network.
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VDD1
VDD2 Mx
100 mA
Clamp
10 k
IN
Differential Output
ADC Driver
OUT
TIA
10
RISO
RADC_IN
Ambient Light
Cancellation
VBIAS
+
–
VOCM
RADC_IN
ADC12QJ1600
IDC EN
RISO
VOD
10
Output Offset
GND
OUT+
EN
图8-2. LMH32404-Q1 (Single Channel) to ADC Interface With a Matching Resistor Network
2 ì R ADC _IN
A V = 20 kꢀ ì 1.2 ì
2 ì R
+ 2 ì RISO + 20ꢀ
ADC _IN
(3)
where
• AV = Gain from the TIA input to the ADC input
• RADC_IN = Differential input resistance of the ADC
• RISO = Series resistance between the TIA and ADC
方程式 4 gives the voltage to be applied at the VOD pin (pin 10) if a certain differential offset voltage (VOD) is
needed at the ADC input for the circuit in 图8-2.
2 ì R
+ 2ìRISO + 20 ꢀ
(
ì
)
1
≈
’
ADC _IN
VOD = VOD
ì
∆
«
÷
◊
1.2
2ìR
ADC _IN
(4)
where
• VOD = Voltage applied at pin 10
• VOD = Desired differential offset voltage at the ADC input
• RADC_IN = Differential input resistance of the ADC
• RISO = Series resistance between the TIA and ADC
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8.2 Typical Application
8.2.1 Standard TIA Application
图8-3 and 图8-4 shows the circuit used to test the LMH32404-Q1 with a voltage source.
Mx
VDD1
VDD2
100mA
Clamp
10 k
2k
Differential Output ADC Driver
2.4 × R 10
IN
50 measurement
instrument
ISIG
R
OUT
TIA
25
1 μF
1 μF
IDC
+
+
–
CLOAD
2.47 V
Ambient Light
Cancellation
–
25
IDC EN
GND
R
2.4 × R
10
VDD
VREF
OUT+
VDD
Voltage to Current
17 k
3 k
50.4 k
25 k
VOD
VOCM
GND
EN
图8-3. LMH32404-Q1 Single Channel Test Circuit for Single-Ended Measurement
Mx
VDD1
VDD2
100mA
Clamp
50 measurement
instrument
10 k
2k
Differential Output ADC Driver
2.4 × R 10
IN
ISIG
R
OUT
TIA
50
50
1 μF
1 μF
IDC
+
+
–
2.47 V
Ambient Light
Cancellation
–
IDC EN
R
2.4 × R
10
VDD
VREF
OUT+
VDD
50 measurement
instrument
Voltage to Current
17 k
3 k
50.4 k
25 k
VOD
VOCM
GND
EN
图8-4. LMH32404-Q1 Single Channel Test Circuit for Differential Measurement
8.2.1.1 Design Requirements
The objective is to design a low-noise, wideband differential output transimpedance amplifier. The design
requirements are:
• Amplifier supply voltage: 3.3 V
• Transimpedance gain: 20 kΩ
• Photodiode capacitance: CAPD = 1 pF
• Target bandwidth: > 300 MHz
• Multiple channels for array applications
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8.2.1.2 Detailed Design Procedure
图 8-3 and 图 8-4 shows the LMH32404-Q1 test circuit used to measure its bandwidth, noise and transient
response. The voltage source is DC biased close to the input bias voltage of the LMH32404-Q1. The
LMH32404-Q1 internal design is optimized to only source current out of the input pin (INx). When testing the
LMH32404-Q1 with a network analyzer or sinusoidal source, set the DC bias such that sum of the input AC and
DC component does not result in a sourcing current into the amplifier input. Only use the LMH32404-Q1 with
avalanche photodiodes (APDs) that sink current. An anode-biased APD satisfies this requirement.
图8-5 shows the measured results for bandwidth of LMH32404-Q1 for all four channels.
图 8-6 shows the output noise spectral density of the LMH32404-Q1 with CAPD = 1 pF and no photodiode
capacitance.
图 8-7 shows the turn-on time of the LMH32404-Q1 channel when the Mx pin is toggled from logic low to high.
When the amplifier is off, the output is in a high-impedance state. When the amplifier turns on, the output settles
and starts tracking the input within a few nanoseconds.
图 8-8 shows the turn-off time of the LMH32404-Q1 channel when the Mx pin is toggled from logic high to low.
When the amplifier is off, the output is in a high-impedance state.
8.2.1.3 Application Curves
图8-5. Transimpedance Bandwidth
图8-6. Output Noise Spectral Density
3.5
3
2.5
2
MX
1.5
1
Differential Output
0.5
0
-0.5
Time (10ns/div)
图8-8. Channel Turn-Off Response
图8-7. Channel Turn-On Response
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8.2.2 Increase Channel Density for Optical Front-End Systems
Modern LiDAR systems are moving towards solid state configurations with multi-channel photodiode arrays. For
optical front-end designs it is impractical to have single transimpedance amplifiers (TIA) connected to each diode
output along with additional multiplexers or other switching solutions to connect to the digitizer. This approach
causes increased solution size, complexity and signal degradation.
The LMH32404-Q1 resolves this problem in two ways, by providing higher integration within the device and by
allowing user configured output multiplexing for independent output control.
图 8-9 shows a comparison of a non-integrated front end using individual amplifiers, a multiplexer, and fully-
differential amplifier (FDA) to connect to the differential input ADC. In comparison, the front end using the
LMH32404-Q1 is able to connect four channels per amplifier to each ADC or set of ADC differential inputs. 图
8-9 shows how the LMH32404-Q1 improves solution size and system complexity compared to a non-integrated
solution. With the additional features like input current clamps and ambient light cancellation, LMH32404-Q1 also
improves system design and eliminates need for additional circuitry.
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
1
2
1
2
MUX
MUX
MUX
MUX
ADC 1
ADC 2
ADC 3
ADC 4
LMH32404
LMH32404
LMH32404
LMH32404
ADC 1
ADC 2
ADC 3
ADC 4
FDA
FDA
FDA
FDA
3
3
4
4
5
5
Reduced
Area and
Complexity
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
Non-integrated Solution
图8-9. Solution Size Comparison
LMH32404 Based Solution
LMH32404-Q1 is a quad-channel device and each channel has an independent differential output stage and
multiplexing switch. 图 8-10 shows two common output configurations. In a four-to-four configuration the
LMH32404-Q1 operates with no output multiplexing with each input and corresponding differential output active.
This configuration is useful when the user needs to be able to capture data from four optical sensors
simultaneously. In a four-to-one configuration, the LMH32404-Q1 internally multiplexes all four differential
outputs into a single differential output. The LMH32404-Q1 outputs can be configured in any permutation such
as one channel operating in one-to-one mode with the other three channels multiplexed in a three-to-one
configuration. This independent control and multiplexing feature significantly increases channel density for
systems that do not need to record all inputs simultaneously.
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Differential Output 1
CH1
CH2
CH3
CH4
Differential Output 1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
Differential Output 2
Differential Output 2
Multi-Channel
ADC
Single-Channel
ADC
LMH32404
LMH32404
Differential Output 3
Differential Output 3
Differential Output 4
Differential Output 4
LMH32404 4-to-4 Configuration
LMH32404 4-to-1 Configuration
图8-10. LMH32404 Multiplexing Configuration Examples
To show the front-end design integration and multiplexing capability, the LMH32404-Q1 performance was
measured with the ADC12QJ1600-Q1 quad channel analog to digital converter. 图 8-11 shows the data
measured from the ADC12QJ1600-Q1 using a 10ns electrical input pulse on a single channel of the LMH32404-
Q1. These pulses are similar to outputs seen in a typical LiDAR application. 图 8-12 shows the data from the
ADC12QJ1600- Q1 when the LMH32404-Q1 outputs multiplex between different channels. The initial output
shows a 10ns duration pulse train on channel 1, followed by a 20 MHz sinusoidal signal on channel 2 and then
the output with all channels turned off but the input signals still present. Details on these measurements and
application are discussed in the application brief, How to Increase the Channel Density of LiDAR Systems with
the 4-Channel LMH32404 Transimpedance Amplifier.
8.2.2.1 Application Curves
0.8
100
75
50
25
0
0.8
0.6
0.4
0.2
0
Input
Output
0.6
0.4
0.2
Channel 2 Selected
All Channels
Disconnected
Channel 1 Selected
0.5
0
0
1
1.5
2
Time (5 ns/div)
Time (us)
图8-11. 10 ns Pulse Electrical Input
图8-12. Multiplexed Channel Switching
9 Power Supply Recommendations
The LMH32404-Q1 operates on 3.3-V supplies. The VDD1 and VDD2 pins must always be driven from the same
supply source and individually bypassed. Use multiple bypass capacitors in parallel, because a low power-
supply source impedance must be maintained across frequency. Place the bypass capacitors as close to the
supply pins as possible. Place the smallest capacitor on the same side of the PCB as the LMH32404-Q1.
Placing the larger valued bypass capacitors on the same side of the PCB is preferable as well; if there are space
constraints however, the capacitors can be moved to the opposite side of the PCB using multiple vias to reduce
the series inductance resulting from the vias. The LMH32404-Q1 can be run on bipolar supplies by connecting
pins 11 and 26 to the negative supply. The thermal pad must always be connected to the most negative supply.
The digital pin threshold voltages must be appropriately level shifted as they are referred to voltages at pins 11
and 26.
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10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the LMH32404-Q1 requires careful
attention to board layout parasitics and external component types. Recommendations that optimize performance
include:
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output pins can cause instability, whereas parasitic capacitance on the input pin reduces the amplifier
bandwidth. Cut out the power and ground traces under the signal input and output pins to reduce unwanted
capacitance. Otherwise, ground and power planes must be unbroken elsewhere on the board.
• Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use low
inductance ceramic capacitors as decoupling capacitors with voltage ratings at least three times greater than
the amplifiers maximum power supplies. Place a combination of 100 pf (or higher) and 33 nF (or higher)
capacitors on the same side as the DUT. If space constraints force the larger value bypass capacitors to be
placed on the opposite side of the PCB, use multiple vias on the supply and ground side of the capacitors.
This configuration makes sure that there is a low-impedance path to the amplifiers power-supply pins across
the amplifiers gain bandwidth specification. Avoid narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are
effective at lower frequency must be used on the supply pins. Place these decoupling capacitors further from
the device. Share the decoupling capacitors among several devices in the same area of the printed circuit
board (PCB).
• For more information on board design and layout, see the evaluation module user guide, LMH32404
Evaluation Module User's Guide.
10.2 Layout Example
Optional capacitor to reduce
VOCM noise from internal
resistors
Place bypass capacitors close to VDD
and GND pins on the same side as
DUT. Use multiple vias to connect to
power and GND planes
GND
28
IDC_EN
27
VOCM
26
GND
25
M1
24
M2
23
VDD2
OUT1–
IN1
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
OUT1+
VDD1
IN2
− VBIAS
OUT2–
OUT2+
VDD1
VDD1
IN3
To subsequent gain stage/
ADC/TDC
− VBIAS
Thermal Pad
OUT3–
OUT3+
OUT4–
OUT4+
VDD1
IN4
− VBIAS
GND
11
M4
12
M3
13
VDD2
14
EN
9
VOD
10
− VBIAS
Not to scale
Remove GND and Power plane
between IN and APD to minimize
parasitic capacitance
Remove GND and Power
plane near output pins to
minimize parasitic PCB
capacitance. Resistors to
further isolate parasitics
Optional capacitor to reduce
VOD noise from internal
resistors
Optional isolation resistor to dampen
resonance due to bond wire
inductances and component
capacitances
图10-1. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
• Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design design guide
• Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design: Using High-Speed Data Converters
design guide
• Texas Instruments, Optical Front-End System Reference Design design guide
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, LMH32404 Evaluation Module user's guide
• Texas Instruments, Training Video: High speed TIAs for optical time of flight and LIDAR systems
• Texas Instruments, Training Video: Multi-channel optical front-end reference design overview
• Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 1 blog
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 2 blog
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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1-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH32404QWRHFRQ1
ACTIVE
VQFN
RHF
28
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
32404Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMH32404-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2022
Catalog : LMH32404
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH32404QWRHFRQ1
VQFN
RHF
28
3000
330.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RHF 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMH32404QWRHFRQ1
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RHF0028B
VQFN - 1.0 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.13)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2.55 0.1
2X 2.5
(0.2) TYP
9
EXPOSED
14
THERMAL PAD
24X 0.5
15
8
(0.16)
TYP
3.55 0.1
A
SYMM
A
2X
29
3.5
1
22
0.30
28X
0.18
0.1
C A B
PIN 1 ID
28
23
SYMM
0.05
0.5
28X
0.3
4225972/A 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHF0028B
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.55)
SYMM
28
23
28X (0.6)
22
1
28X (0.24)
(3.55)
(1.525)
24X (0.5)
29
SYMM
(4.8)
(
0.2) TYP
VIA
8
15
(R0.05)
TYP
9
14
(1.025)
(3.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225972/A 06/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHF0028B
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.13)
(0.665) TYP
23
28
28X (0.6)
1
22
28X (0.24)
(0.865)
TYP
24X (0.5)
SYMM
(4.8)
29
4X (1.53)
(R0.05) TYP
8
15
METAL
TYP
14
9
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 29
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225972/A 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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