LMH5485-SEP [TI]
Radiation-tolerant 850-MHz fully differential amplifier;
| 型号： | LMH5485-SEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Radiation-tolerant 850-MHz fully differential amplifier |
| 文件： | 总30页 (文件大小：1665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH5485-SEP
ZHCSO08A –DECEMBER 2021 –REVISED NOVEMBER 2022
LMH5485-SEP 耐Tolerant 型负轨输入、轨到轨输出高精度850MHz 全差分放大
器
1 特性
3 说明
• 抗辐射
LMH5485-SEP 是一款抗辐射、低功耗、电压反馈、全
差分放大器 (FDA)。该器件能够实现 850MHz 的高增
益带宽积(GBWP)，从而能够在下图所示的宽频率范围
内保持出色的失真性能。此外，还可在10.1mA 的相对
较低功耗和 2.4nV/√Hz 的宽带电压噪声下实现此宽带
宽范围。由于具有这样的功耗、带宽和噪声组合，
LMH5485-SEP 非常适合频率大于 10MHz 且同时要求
出色信噪比 (SNR) 和无杂散动态范围 (SFDR) 的功耗
敏感型数据采集系统。
– 每个晶圆批次的保障TID 高达30krad (Si)
– 单粒子闩锁(SEL) 对于LET 的
抗扰度= 43MeV-cm2/mg
– 支持军用级温度范围：..-55°C 至125°C
• 增益带宽积（GBWP）：850MHz
• 压摆率：1300V/µs
• HD2、HD3：–118dBc、–147dBc（100kHz、
2VPP
）
• 输入电压噪声：2.4 nV/√Hz
• 低温漂：±0.5µV/°C（典型值）
• 负轨输入(NRI)、轨到轨输出(RRO)
• 电源：
LMH5485-SEP 具有所需的负电源轨输入，可用于连接
直流耦合、以接地为中心的源信号。此负电源轨输入搭
配轨到轨输出，只需使用一个 2.7V 至 5.4V 的电源，
即可轻松将单端接地基准双极信号源与各种逐次逼近寄
存器 (SAR)、Δ-Σ 或流水线 ADC 相连接。该器件还
具有 ±0.5 μV/°C 的低失调电压漂移，能够在 –55°C
至+125°C 的宽温度范围内保持出色的直流性能。
– 电源电压范围：2.7V 至5.4V
– 静态电流：10.1 mA
– 断电能力：2µA（典型值）
封装信息(1)(2)
2 应用
封装尺寸（标称值）
器件型号
封装
• 低功耗高性能ADC 驱动器：
LMH5485-SEP DGK（VSSOP，8）
3.00mm × 3.00mm
– SAR、ΔΣ和流水线
• 差分DAC 输出驱动器
• 命令和数据处理
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 请参阅器件信息表
• 运载火箭系统
• 空间成像系统：
– 光学成像有效载荷
– 雷达成像有效载荷
– 热成像摄像机
-60
LMH5485-SEP Wideband,
HD2, VO = 2 VPP
HD3, VO = 2 VPP
Fully-Differential Amplifier
50- Input Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
-70
Rf1
402
-80
-90
C1
100 nF
Vcc
Rg1
191
-100
-110
-120
-130
-140
-150
-160
50-
Source
–
Output
Measurement
Point
+
Rt
60.2
Rload
500
Vocm
FDA
–
+
PD
Rg2
221
Vcc
C2
100 nF
Rf2
402
0.01
0.1
Frequency (MHz)
1
10
谐波失真与频率间的关系
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA87
LMH5485-SEP
ZHCSO08A –DECEMBER 2021 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................16
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................18
10 Application and Implementation................................22
10.1 Application Information........................................... 22
10.2 Typical Applications................................................ 22
11 Power Supply Recommendations..............................26
12 Layout...........................................................................26
12.1 Layout Guidelines................................................... 26
13 Device and Documentation Support..........................27
13.1 Documentation Support.......................................... 27
13.2 Receiving Notification of Documentation Updates..27
13.3 支持资源..................................................................27
13.4 Trademarks.............................................................27
13.5 Electrostatic Discharge Caution..............................27
13.6 术语表..................................................................... 27
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics: Vs+ –Vs- = 5 V................6
7.6 Electrical Characteristics: Vs+ –Vs- = 3 V................8
7.7 Typical Characteristics: 5 V Single Supply................10
7.8 Typical Characteristics: 3 V Single Supply................11
7.9 Typical Characteristics: 3 V to 5 V Supply Range.....12
8 Parameter Measurement Information..........................15
8.1 Example Characterization Circuits............................15
9 Detailed Description......................................................16
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (September 2022)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Device Comparison Table
INPUT NOISE
(nV/√Hz)
GBWP
(MHz)
IQ
(mA)
HD2 / HD3 (dBc)
2 VPP at 10 MHz
DEVICE
RAD TOLERANCE
RAIL-TO-RAIL
100 kRad TID
30 kRad TID
150 kRad TID
100 kRad TID
LMH5485-SP
LMH5485-SEP
THS4513-SP
LMH5401-SP
850
850
10.1
10.1
37.7
60
2.4
2.4
NRI/Out
NRI/Out
No
–79 / –97
–90 / –102
–106 / –108
–99 / –100
3000
6500
2.2
1.25
No
6 Pin Configuration and Functions
IN-
8
7
6
5
IN+
1
2
3
4
VOCM
PD
VS-
VS+
OUT+
OUT-
图6-1. DGK Package, 8-Pin VSSOP (Top View)
表6-1. Pin Functions
PIN
NAME
IN+
NO.
8
TYPE(1)
DESCRIPTION
I
I
Noninverting (positive) amplifier input
Inverting (negative) amplifier input
Noninverted (positive) amplifier output
Inverted (negative) amplifier output
1
IN–
OUT+
OUT–
PD
4
O
O
I
5
7
Power down. PD = logic low = power-down mode; PD = logic high = normal operation.
Common-mode voltage input
VOCM
Vs+
2
I
3
P
P
Positive power-supply input
6
Negative power-supply input
Vs–
(1) I = input, O = output, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage (normal operation), (Vs+) –(Vs–), PD = logic
high
5.5
Voltage(2)
V
5.25
(Vs+) + 0.5
±1
Supply voltage (power-down), (Vs+) –(Vs–), PD = logic low
Input-output voltage range
(Vs–) –0.5
Differential input voltage
Continuous input current
±20
mA
Continuous output current
±80
Current
See Thermal Information table and Thermal Analysis
Continuous power dissipation
section
Maximum junction temperature
Operating free-air temperature range
Storage temperature, Tstg
150
125
150
Temperature
–55
–65
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) If the device is under continous operation with PD permanantly tied to VS+, absolute maximum supply voltage is 5.5V. If
PD functionality is toggled during operation, abs max supply voltage should be limited to 5.25V.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
5.4
UNIT
Single-supply voltage (normal operation), PD = logic high
Single-supply voltage (power-down), PD = logic low
Ambient temperature
Vs+
TA
V
2.7
5
5.1
25
125
°C
–55
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7.4 Thermal Information
LMH5485-SEP
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
171.8
63.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
93.4
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.2
ψJT
91.9
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: Vs+ –Vs- = 5 V
at TA = -55℃to 125℃, VOCM = open (defaults midsupply), Vout = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G =
2 V/V, single-ended input, differential output, and PD = Vs+, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-2 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
Vout = 100 mVPP, G = 1
Vout = 100 mVPP, G = 2
Vout = 100 mVPP, G = 5
Vout = 100 mVPP, G = 10
Vout = 100 mVPP, G = 20
Vout = 2 VPP
590
495
185
110
850
295
125
1300
1.3
SSBW
Small-signal bandwidth
MHz
GBWP
LSBW
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate(1)
Vout = 2 VPP
Vout = 2-VPP, FPBW
Vout = 2-V step, input ≤0.5 ns tr
V/µs
ns
Rise/fall time
To 1%
4
Vout = 2-V step,
tr = 2 ns
Settling time
To 0.1%
8
Overshoot and undershoot
100-kHz harmonic distortion
10%
Vout = 2-V step, input ≤0.3 ns tr
HD2
Vout = 2 VPP
–118
–147
–90
HD3
HD
HD2
Vout = 2 VPP
10-MHz harmonic distortion
dBc
HD3
–102
–90
f = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per
tone)
2nd-order intermodulation distortion
3rd-order intermodulation distortion
–85
en
in
Input voltage noise
f > 100 kHz
2.4
1.9
20
nV/√Hz
pA/√Hz
ns
Input current noise
f > 1 MHz
Overdrive recovery time
Closed-loop output impedance
2x output overdrive, either polarity
f = 10 MHz (differential)
ZOUT
0.1
Ω
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
97
–900
–2.5
1.7
119
±100
±0.5
10
dB
Input-referred offset voltage
Input offset voltage drift(2)
900
2.5 µV/°C
15 µA
15 nA/°C
µV
IB+, IB– Input bias current
Input bias current drift(2)
Input offset current
Positive out of node
6
IOS
±150
±0.3
650
nA
–650
–1.5
Input offset current drift(2)
1.5 nA/°C
INPUT
VICML
Common-mode input low
(Vs–) –0.2
(Vs+) –1.2
100
Vs–
< 3-dB degradation in CMRR from
midsupply
V
VICMH
CMRR
Common-mode input high
(Vs+) –1.3
Common-mode rejection ratio
Input impedance differential mode
Input pins at midsupply
Input pins at midsupply
82
dB
110 || 0.9
kΩ|| pF
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7.5 Electrical Characteristics: Vs+ –Vs- = 5 V (continued)
at TA = -55℃to 125℃, VOCM = open (defaults midsupply), Vout = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G =
2 V/V, single-ended input, differential output, and PD = Vs+, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-2 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT
Output voltage low
Output voltage high
Output current drive
(Vs–) + 0.2 (Vs–) + 0.25
(Vs+) –0.25 (Vs+) –0.2
V
±75
±100
mA
POWER SUPPLY
IQ
Quiescent operating current
Power-supply rejection ratio
9.2
82
10.1
100
11
mA
dB
Either supply pin to differential
Vout
PSRR
POWER DOWN
VEN
Enable voltage threshold
(Vs–) + 1.7
V
VDIS
Disable voltage threshold
Disable pin bias current
(Vs–) + 0.7
20
6
50
30
8
nA
µA
PD = Vs–→Vs+
PD = (Vs–) + 0.7 V
PD = Vs–
Power-down quiescent current
2
Time from PD = low to
Vout = 90% of final value
Turnon-time delay
Turnoff time delay
100
60
ns
Time from PD = low to
Vout = 10% of final value
OUTPUT COMMON-MODE VOLTAGE CONTROL(3)
Small-signal bandwidth
Slew rate(1)
VOCM = 100 mVPP
150
400
MHz
V/µs
V/V
µA
VOCM = 2-V step
Gain
0.975
0.982
0.1
0.995
0.8
Input bias current
Input impedance
Considered positive out of node
VOCM input driven to midsupply
–0.8
47 || 1.2
±8
kΩ|| pF
Default voltage offset from midsupply VOCM pin open
45
8
–45
–8
mV
Common-mode offset voltage
CM VOS drift(2)
VOCM input driven to midsupply
±2
VOCM input driven to midsupply
±4
+20 µV/°C
–20
Common-mode loop supply
headroom to negative supply
< ±15-mV shift from midsupply CM
VOS
0.94
1.2
V
Common-mode loop supply
headroom to positive supply
< ±15-mV shift from midsupply CM
VOS
(1) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) × 2π× f–3dB
.
(2) Input offset voltage drift, input bias current drift, input offset current drift, and VOCM drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.
(3) Specifications are from the input VOCM pin to the differential output average voltage.
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7.6 Electrical Characteristics: Vs+ –Vs- = 3 V
at TA = -55℃to 125℃, VOCM = open (defaults midsupply), Vout = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G =
2 V/V, single-ended input, differential output, and PD = Vs+, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-2 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
Vout = 100 mVPP, G = 1
Vout = 100 mVPP, G = 2
Vout = 100 mVPP, G = 5
Vout = 100 mVPP, G = 20
Vout = 2 VPP
585
490
180
850
275
120
1200
1.6
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Small-signal bandwidth
GBWP
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate(1)
Vout = 2 VPP
Vout = 2-V step, FPBW
Vout = 2-V step, input ≤0.5 ns tr
Rise/fall time
To 1%
5
ns
Vout = 2-V step,
tr = 2 ns
Settling time
To 0.1%
8
ns
Overshoot and undershoot
100-kHz harmonic distortion
11%
Vout = 2-V step, input ≤0.3 ns tr
HD2
Vout = 2 VPP
dBc
dBc
dBc
dBc
dBc
–118
–148
–90
HD3
HD2
Vout = 2 VPP
10-MHz harmonic distortion
HD3
–100
–89
f = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per
tone)
2nd-order intermodulation distortion
3rd-order intermodulation distortion
dBc
–87
en
in
Input voltage noise
f > 100 kHz
2.4
1.9
20
nV/√Hz
pA/√Hz
ns
Input current noise
f > 1 MHz
Overdrive recovery time
Closed-loop output impedance
2X output overdrive, either polarity
f = 10 MHz (differential)
0.1
Ω
DC PERFORMANCE
AOL
Open-loop voltage gain
97
–900
–2.5
1.7
119
±100
±0.5
9
dB
Input-referred offset voltage
Input offset voltage drift(2)
Input bias current
900
2.5 µV/°C
15 µA
15 nA/°C
µV
Positive out of node
Input bias current drift(2)
5
Input offset current
±150
±0.3
650
nA
–650
–1.5
Input offset current drift(2)
1.5 nA/°C
INPUT
< 3-dB degradation in CMRR from
midsupply
Common-mode input low
Common-mode input high
V
V
(Vs–) –0.2
(Vs+) –1.2
Vs–
< 3-dB degradation in CMRR from
midsupply
(Vs+) –1.3
Common-mode rejection ratio
Input pins at midsupply
Input pins at midsupply
82
100
dB
Input impedance differential mode
110 || 0.9
kΩ|| pF
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7.6 Electrical Characteristics: Vs+ –Vs- = 3 V (continued)
at TA = -55℃to 125℃, VOCM = open (defaults midsupply), Vout = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G =
2 V/V, single-ended input, differential output, and PD = Vs+, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-2 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT
Output voltage low
Output voltage high
Output current drive
V
V
(Vs–) + 0.2 (Vs–) + 0.25
(Vs+) –0.25 (Vs+) –0.2
±55
±60
mA
POWER SUPPLY
Specified operating voltage
2.7
9
3
5.1
V
Quiescent operating current
9.7
10.6
mA
Either supply pin to differential
Vout
±PSRR Power-supply rejection ratio
82
100
dB
POWER DOWN
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
V
(Vs–) + 1.7
V
(Vs–) + 0.7
20
2
50
30
8
nA
µA
µA
PD = Vs–→Vs+
PD = (Vs–) + 0.7 V
PD = Vs–
Power-down quiescent current
1
Time from PD = low to
Vout = 90% of final value
Turnon-time delay
Turnoff time delay
100
60
ns
ns
Time from PD = low to
Vout = 10% of final value
OUTPUT COMMON-MODE VOLTAGE CONTROL(3)
Small-signal bandwidth
Slew rate(1)
VOCM = 100 mVPP
140
350
MHz
V/µs
V/V
µA
VOCM = 1-V step
Gain
0.975
0.987
0.1
0.990
0.7
Input bias current
Input impedance
Considered positive out of node
VOCM input driven to midsupply
–0.7
47 || 1.2
±10
kΩ|| pF
mV
Default voltage offset from midsupply VOCM pin open
CM VOS Common-mode offset voltage VOCM input driven to midsupply
45
8
–45
–8
±2
mV
CM VOS drift(2)
VOCM input driven to midsupply
±4
20 µV/°C
V
–20
Common-mode loop supply
headroom to negative supply
< ±15-mV shift from midsupply CM
VOS
0.94
1.2
Common-mode loop supply
headroom to positive supply
< ±15-mV shift from midsupply CM
VOS
V
(1) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) × 2π× f–3dB
.
(2) Input offset voltage drift, input bias current drift, input offset current drift, and VOCM drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.
Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
(3) Specifications are from input VOCM pin to differential output average voltage.
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7.7 Typical Characteristics: 5 V Single Supply
at Vs+ = 5 V, Vs– = GND, RF= 402 Ω, VOCM is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload =
500 Ω, and TA ≅ 25°C (unless otherwise noted)
3
G=1
G=2
G=5
0
-3
-6
-9
-12
10
100
1000
Frequency (MHz)
Vo = 100 mVPP
VO = 2 VPP
.
图7-1. Small-Signal Frequency Response vs Gain
图7-2. Large-Signal Frequency Response
2
1.5
1
-60
-70
HD2
HD3
-80
-90
0.5
0
-100
-110
-120
-130
-140
-150
-160
-0.5
-1
-1.5
-2
0.01
0.1
Frequency (MHz)
1
10
0
2
4
6
8
10 12 14 16 18 20 22 24
Time (ns)
50 MHz input, 0.5-ns input edge rate, single-ended to
2 VPP output, see 图8-1
.
differential output, split supply, DC-coupled, see 图8-2
图7-4. Harmonic Distortion Over Frequency
图7-3. Large-Signal Step Response
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7.8 Typical Characteristics: 3 V Single Supply
at Vs+ = 3 V, Vs–= GND, VOCM is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≅ 25°C (unless otherwise noted)
3
3
G=1
G=2
G=5
0
0
-3
-3
-6
-9
-6
-9
-12
10
100
1000
10
100
1000
Frequency (MHz)
Frequency (MHz)
Rf = 402 Ω, Vout = 100 mVPP
Rf = 402 Ω, Vout = 2 VPP
图7-5. Small-Signal Frequency Response vs Gain
图7-6. Large-Signal Frequency Response
2
1.5
1
-60
-70
HD2
HD3
-80
-90
0.5
0
-100
-110
-120
-130
-140
-150
-160
-0.5
-1
-1.5
-2
0.01
0.1
Frequency (MHz)
1
10
0
2
4
6
8
10 12 14 16 18 20 22 24
Time (ns)
50 MHz input, 0.5-ns input edge rate, single-ended input to
2 VPP output, see 图8-1 with Vs+ = 3 V, VOCM = 1.5 V
.
differential output, split supply, DC coupled, see 图8-2
图7-8. Harmonic Distortion Over Frequency
图7-7. Large-Signal Step Response
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7.9 Typical Characteristics: 3 V to 5 V Supply Range
at Vs+ = 3 V and 5 V, Vs–= GND, VOCM is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500
Ω, and TA ≅ 25°C (unless otherwise noted)
10
Gain=2, +3 V
Gain=2, +5 V
Gain=5, +3 V
1
Gain=5, +5 V
0.1
0.01
0.001
0.0001
1k
10k
100k 1M
Frequency (Hz)
10M
100M
D038
.
.
Single-ended input to differential output, simulated differential
output impedance, see 图8-1
图7-9. Main Amplifier Differential Open-Loop Gain and Phase
图7-10. Closed-Loop Output Impedance
vs Frequency
50
eN
iN
-50
+3 V supply
+5 V supply
-55
-60
-65
-70
-75
-80
10
1
1k
10k
100k
Frequency (Hz)
1M
10M
1k
10k
100k 1M
Frequency (Hz)
10M
100M
.
.
D040
Single-ended input to differential output, gain of 2 (see 图8-1),
simulated with 1% resistor, worst-case mismatch
图7-11. Input Spot Noise Over Frequency
图7-12. Output Balance Error Over Frequency
110
100
90
90
+3 V +Vs
+5 V +Vs
+3 V -Vs
+5 V -Vs
85
80
75
70
65
60
55
50
45
40
80
70
60
50
1k
10k
100k 1M
Frequency (Hz)
10M
100M
10k
100k
1M
Frequency (Hz)
10M
100M
D041
D042
Common-mode in to differential out, gain of 2 simulation
.
Single-ended to differential, gain of 2 (see 图8-1) PSRR
simulated to differential output
图7-13. CMRR Over Frequency
图7-14. PSRR Over Frequency
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7.9 Typical Characteristics: 3 V to 5 V Supply Range (continued)
at Vs+ = 3 V and 5 V, Vs–= GND, VOCM is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500
Ω, and TA ≅ 25°C (unless otherwise noted)
1000
100
10
10
8
+5 V Vocm driven
+5 V Vocm floating
+3 V Vocm driven
+3 V Vocm floating
+5 V supply
+3 V supply
6
4
2
0
-2
-4
-6
-8
-10
1
100
1k
10k 100k
Frequency (Hz)
1M
10M
0.8
1.2
1.6
2
2.4
2.8
Vocm Input Voltage (V)
3.2
3.6
4
D045
D046
VOCM input either driven to mid-supply by low impedance
source, or allowed to float and default to mid-supply
Average VOCM output offset of 37 units, Standard deviation
< 2.5 mV, see 图8-2
图7-15. Output Common-Mode Noise
图7-16. VOCM Offset vs VOCM Setting
100
100
+3 V supply
+5 V supply
95
95
90
85
80
90
85
80
75
70
75
+3 V supply
+5 V supply
70
0.85
0.85
1.35
1.85
2.35
Vocm (V)
2.85
3.35
3.85
1.35
1.85
2.35
Vocm (V)
2.85
3.35 3.85
D047
D048
Single-ended to differential gain of 2 (see 图8-1), PSRR for
Single-ended to differential gain of 2 (see 图8-1), PSRR for
negative supply to differential output (1-kHz simulation)
positive supply to differential output (1-kHz simulation)
图7-17. –PSRR vs VOCM Approaching Vs–
图7-18. +PSRR vs VOCM Approaching Vs+
450
700
+5 V Supply
+3 V Supply
+5 V Supply
+3 V Supply
400
350
300
250
200
150
100
50
600
500
400
300
200
100
0
0
Input Offset Voltage V
Input Offset Current (nA)
Total of 1281 units for each supply. For Vs = 5 V: μ= 34.1
Total of 1281 units for each supply. For Vs = 5 V: μ= 7.0 nA,
σ= 35.9 nA
μV,
σ= 47.1 μV
图7-20. Input Offset Current
图7-19. Input Offset Voltage
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7.9 Typical Characteristics: 3 V to 5 V Supply Range (continued)
at Vs+ = 3 V and 5 V, Vs–= GND, VOCM is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500
Ω, and TA ≅ 25°C (unless otherwise noted)
11
10.5
10
9.5
9
10
9
8
7
6
5
4
3
2
1
0
5 V supply
3 V supply
5 V supply
3 V supply
8.5
8
7.5
7
0
1
2
3
Disable Pin Voltage (PD) Volts
4
5
10
100
1000
D056
Differential Load ()
.
Maximum differential output swing, VOCM at mid-supply
图7-22. Supply Current vs PD Voltage
图7-21. Differenital Output Voltage vs Rload
600
550
500
450
400
350
300
250
200
150
100
50
400
+5 V Supply
+3 V Supply
+5 V Supply
+3 V Supply
350
300
250
200
150
100
50
0
0
VOCM Offset Voltage (mV)
VOCM Offset Voltage (mV)
Total of 1281 units for each supply. For Vs = 5 V: μ= 0.52
VOCM input floating. Total of 1281 units for each supply.
For Vs = 5 V: μ= 8.1 mV, σ= 4.3 mV
mV, σ= 1.4 mV
.
图7-23. Common-Mode Output Offset from Vs+ / 2 Default Value
图7-24. Common-Mode Output Offset from Driven VOCM
5
5
PD 3 V
Out 3 V
Out 5 V
PD 5 V
PD 3 V
4
4
3
PD 5 V
3
2
1
3-V Supply
2
1
5-V Supply
0
-1
-2
0
-1
-2
0.04
0.06
0.08
0.1
Time (µs)
0.12
0.14
0.16
0.18
0.28
0.3
0.32
Time (µs)
0.34
0.36
D059
D060
10 MHz, 1 VPP input single to differential gain of 2,
10 MHz, 1 VPP input single to differential gain of 2,
see 图8-2
see 图8-2
图7-25. PD Turn On Waveform
图7-26. PD Turn Off Waveform
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8 Parameter Measurement Information
8.1 Example Characterization Circuits
The LMH5485-SEP offers the advantages of a fully differential amplifier (FDA) design, with the trimmed input
offset voltage of a precision op amp. The FDA is an extremely flexible device that provides a purely differential
output signal centered on a settable output common-mode level. The primary options revolve around the choices
of single-ended or differential inputs, AC-coupled or DC-coupled signal paths, gain targets, and resistor Value
selections. Differential sources can certainly be supported and are often simpler to both implement and analyze.
Examples of both AC and DC coupled single-ended to differential circuits is shown in 图8-1 and 图8-2.
Because most lab equipment is single-ended, the characterization circuits typically operate with a single-ended,
matched, 50 Ω input termination to a differential output at the FDA output pins. That output is then translated
back to single-ended through a variety of baluns (or transformers) depending on the test and frequency range.
DC-coupled, step-response testing uses two 50 Ωscope inputs with trace math.
LMH5485-SEP Wideband,
Fully-Differential Amplifier
50- Input Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
Rf1
402
C1
100 nF
Vcc
Rg1
191
50-
Source
–
Output
Measurement
Point
+
Rt
60.2
Rload
500
Vocm
FDA
–
+
PD
Rg2
221
Vcc
C2
100 nF
Rf2
402
图8-1. AC-Coupled, Single-Ended Source to a Differential Gain of a 2 V/V Test Circuit
LMH5485-SEP
Wideband,
Fully-Differential Amplifier
50- Input Match,
Gain of 5 V/V from Rt,
Single-Ended Source to
Rf1
402
Differential Step-Response Test
Vcc
Rg1
68.1
50-
–
Source
Output
Measurement
Point
+
–
R1
500
Rt
80.6
Vocm
FDA
+
PD
Rg2
100
Vcc
Rf2
402
图8-2. DC-Coupled, Single-Ended-to-Differential, Basic Test Circuit Set for a Gain of 5 V/V
图 8-1 shows how most characterization plots fix the Rf value at 402 Ω. This value is completely flexible in
application, but the 402 Ωprovides a good compromise for the issues linked to this value, specifically:
• Added output loading. The FDA appears like an inverting op amp design with both feedback resistors as an
added load across the outputs (approximate total differential load in 图8-1 is 500 Ω|| 804 Ω= 308 Ω).
• Noise contributions because of the resistor values. The resistors contribute both a 4kTR term and provide
gain for the input current noise.
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• Parasitic feedback pole at the input summing nodes. This pole created by the feedback R value and the
differential input capacitance (as well as any board layout parasitic) introduces a zero in the noise gain,
decreasing the phase margin in most situations. This effect must be managed for best frequency response
flatness or step response overshoot. The 402 Ωvalue selected does degrade the phase margin slightly over
a lower value, but does not decrease the loading significantly from the nominal 500 Ωvalue across the
output pins.
9 Detailed Description
9.1 Overview
The LMH5485-SEP is a voltage-feedback (VFA) based, fully-differential amplifier (FDA) with a trimmed supply
current and input offset voltage. The core differential amplifier is a slightly decompensated voltage-feedback
design with a high slew-rate, precision input stage. This design gives a MHz gain of 2 V/V small-signal
bandwidth shown in the characterization curves, with a V/µs slew rate, yielding approximately a MHz, 2 VPP
large-signal bandwidth in the same circuit configuration.
,
The outputs offer near rail-to-rail output swing (0.2 V headroom to either supply), while the device inputs are
negative rail inputs with approximately 1.2 V of headroom required to the positive supply. 图 8-2 shows how this
negative rail input directly supports a bipolar input around ground in a DC-coupled, single-supply design. Similar
to all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode loop.
The target for this output average is set by the VOCM input pin that can be either floated to default near mid-
supply or driven to a desired output common-mode voltage. The VOCM range extends from a very low 0.91 V
above the negative supply to 1.1 V below the positive supply, supporting a wide range of modern analog-to-
digital converter (ADC) input common-mode requirements using a single 2.7 V to 5.4 V supply range for the
LMH5485-SEP.
A power-down pin (PD) is included. Pull the PD pin voltage to the negative supply to turn the device off, putting
the LMH5485-SEP into a very-low quiescent current state. To be able to use the full supply range of the device,
the device must be kept in normal operation by keeping the PD pin asserted high. When the device is disabled,
remember that the signal path is still present through the passive external resistors. Input signals applied to a
disabled LMH5485-SEP still appear at the outputs at some level through this passive resistor path as they would
for any disabled FDA device.
9.2 Functional Block Diagram
Vs+
OUT+
–
IN–
IN+
2.5 k
2.5 k
High-Aol
Differential I/O
Amplifier
+
–
+
OUT–
Vs+
100 k
–
Vcm
Error
Amplifier
+
Vocm
CMOS
Buffer
PD
100 k
Vs–
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9.3 Feature Description
9.3.1 Differential I/O
The LMH5485-SEP combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage with a dominant pole at
approximately 900 Hz. This voltage feedback structure projects a single-pole, unity-gain Aol at 850 MHz (gain
bandwidth product). The high-speed differential outputs include an internal averaging resistor network to sense
the output common-mode voltage. This voltage is compared by a separate Vcm error amplifier to the voltage on
the VOCM pin. If floated, this reference is at half the total supply voltage across the device using two 100-kΩ
resistors. This Vcm error amplifier transmits a correction signal into the main amplifier to force the output
average voltage to meet the target voltage on the VOCM pin. The bandwidth of this error amplifier is
approximately the same bandwidth as the main differential I/O amplifier.
The differential outputs are collector outputs to obtain the rail-to-rail output swing. These outputs are relatively
high-impedance, open-loop sources; however, closing the loop provides a very low output impedance for load
driving. No output current limit or thermal shutdown features are provided in this lower-power device. The
differential inputs are PNP inputs to provide a negative-rail input range.
To operate the LMH5485-SEP connect the OUT– pin to the IN+ pin through an Rf, and the OUT+ pin to the
IN– pin through the same value of Rf. Bring in the inputs through additional resistors to the IN+ and IN– pins.
The differential I/O op amp operates similarly to an inverting op amp structure where the source must drive the
input resistor and the gain is the ratio of the feedback to the input resistor.
9.3.2 Power-Down Control Pin (PD)
The LMH5485-SEP includes a power-down control pin, PD. This pin must be asserted high for correct amplifier
operation. The PD pin cannot be floated because there is no internal pullup or pulldown resistor on this pin to
reduce disabled power consumption. Asserting this pin low (within 0.7 V of the negative supply) puts the
LMH5485-SEP into a very low quiescent state (approximately 2 µA). Switches in the default VOCM resistor string
open to eliminate the fixed bias current (25 µA) across the supply in this 200-kΩvoltage divider to mid-supply.
9.3.2.1 Operating the Power Shutdown Feature
When the PD pin is asserted high, close to the positive supply, the device will be in normal active mode of
operation. To disable the device for reduced power consumption, PD pin must be asserted low, close to the
negative supply. 图 7-22 shows the PD pin voltage and the corresponding quiescent current drawn. For
applications that require the device to only be powered on when the supplies are present, tie the PD pin to the
positive supply voltage.
The disable operation is referenced from the negative supply (normally, ground). For split-supply operation, with
the negative supply below ground, a disable control voltage below ground is required to turn the LMH5485-SEP
off when the negative supply exceeds –0.7 V.
For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to
assure operation. This minimum logic-high level allows for direct operation from 1.8 V supply logic.
9.3.3 Input Overdrive Operation
The LMH5485-SEP input stage architecture is intrinsically robust to input overdrives with the series input resistor
required by all applications. High input overdrives cause the outputs to limit into their maximum swings with the
remaining input current through the Rg resistors absorbed by internal, back-to-back protection diodes across the
two inputs. These diodes are normally off in application, and only turn on to absorb the currents that a large input
overdrive might produce through the source impedance and or the series Rg elements required by all designs.
The internal input diodes can safely absorb up to ±15 mA in an overdrive condition. For designs that require
more current to be absorbed, consider adding an external protection diode such as BAV99.
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9.4 Device Functional Modes
This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than (Vs–) + 1.7 V or turned off by asserting PD low. Disabling the amplifier shuts
off the quiescent current and stops the correct amplifier operation. The signal path is still present for the source
signal through the external resistors.
The VOCM control pin sets the output average voltage. Left open, VOCM defaults to an internal mid-supply value.
Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal Vcm
error amplifier.
9.4.1 Operation from Single-Ended Sources to Differential Outputs
One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. While the output side is relatively
straightforward, the device input pins move in a common-mode sense with the input signal. This common-mode
voltage at the input pins moving with the input signal acts to increase the apparent input impedance to be
greater than the Rg value. This input active impedance issue applies to both AC- and DC-coupled designs, and
requires somewhat more complex solutions for the resistors to account for this active impedance, as shown in
the following subsections.
9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path can be AC-coupled, the DC biasing for the LMH5485-SEP becomes a relatively simple
task. In all designs, start by defining the output common-mode voltage. The AC-coupling issue can be separated
for the input and output sides of an FDA design. In any case, the design starts by setting the desired VOCM
.
When an AC-coupled path follows the output pins, the best linearity is achieved by operating VOCM at mid-
supply. The VOCM voltage must be within the linear range for the common-mode loop, as specified in the
headroom specifications (approximately 0.91 V greater than the negative supply and 1.1 V less than the positive
supply). If the output path is also AC coupled, simply letting the VOCM control pin float is usually preferred in
order to get a mid-supply default VOCM bias with minimal elements. To limit noise, place a 0.1 µF decoupling
capacitor on the VOCM pin to ground.
After VOCM is defined, check the target output voltage swing to ensure that the VOCM plus the positive or negative
output swing on each side does not clip into the supplies. Check that VOCM ±Vp does not exceed the absolute
supply rails for this rail-to-rail output (RRO) device.
Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side
are DC blocked (see 图 8-1), no common-mode current flows from the output common-mode voltage, thus
setting the input common-mode equal to the output common-mode voltage.
This input headroom also sets a limit for higher VOCM voltages. Because the input Vicm is the output VOCM for
AC-coupled sources, the 1.2 V minimum headroom for the input pins to the positive supply overrides the 1.1 V
headroom limit for the output VOCM. The input signal also moves this input Vicm around the DC bias point.
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9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled
while the output is AC-coupled. A DC-coupled input with an AC-coupled output might have some advantages to
move the input Vicm down if the source is ground referenced. 图8-2 shows how when the source is DC-coupled
into the LMH5485-SEP, both sides of the input circuit must be DC coupled to retain differential balance.
Normally, the nonsignal input side has an Rg element biased to whatever the source midrange is expected to be.
Providing this midscale reference gives a balanced differential swing around VOCM at the outputs.
One significant consideration for a DC-coupled input is that VOCM sets up a common-mode bias current from the
output back through Rf and Rg to the source on both sides of the feedback. Without input balancing networks,
the source must sink or source this DC current. After the input signal range and biasing on the other Rg element
is set, check that the voltage divider from VOCM to Vin through Rf and Rg (and possibly Rs) establishes an input
Vicm at the device input pins that is in range. If the average source is at ground, the negative rail input stage for
the LMH5485-SEP is in range for applications using a single positive supply and a positive output VOCM setting
because this DC current lifts the average FDA input summing junctions up off of ground to a positive voltage (the
average of the V+ and V–input pin voltages on the FDA).
9.4.2 Differential-Input to Differential-Output Operation
In many ways, this method is a much simpler way to operate the FDA from a design equations perspective.
Assuming the two sides of the circuit are balanced with equal Rf and Rg elements, the differential input
impedance is the sum of the two Rg elements to a differential inverting summing junction. In these designs, the
input common-mode voltage at the summing junctions does not move with the signal, but must be DC biased in
the allowable range for the input pins with consideration given to the voltage headroom required from each
supply. Slightly different considerations apply to AC- or DC-coupled, differential-in to differential-out designs, as
described in the following sections.
9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
There are two typical ways to use the LMH5485-SEP with an AC-coupled differential source. In the first method,
the source is differential and can be coupled in through two blocking capacitors. The second method uses either
a single-ended or a differential source and couples in through a transformer (or balun). 图 9-1 shows a typical
blocking capacitor approach to a differential input. An optional input differential termination resistor (Rm) is
included in this design. This Rm element allows the input Rg resistors to be scaled up while still delivering lower
differential input impedance to the source. In this example, the Rg elements sum to show a 200 Ω differential
impedance, while the Rm element combines in parallel to give a net 100 Ω, AC-coupled, differential impedance
to the source. Again, the design proceeds ideally by selecting the Rf element values, then the Rg to set the
differential gain, then an Rm element (if needed) to achieve a target input impedance. Alternatively, the Rm
element can be eliminated, the Rg elements set to the desired input impedance, and Rf set to the get the
differential gain (= Rf / Rg).
LMH5485-SEP
Wideband,
Fully-Differential Amplifier
Rf1
402
C1
100 nF
Vcc
Rg1
100
–
+
Output
Measurement
Point
+
–
R1
500
Vocm
FDA
Downconverter
Differential
Output
Rm
200
PD
C2
100 nF
Rg2
100
Vcc
Rf2
402
图9-1. Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the LMH5485-SEP
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The DC biasing here is very simple. The output VOCM is set by the input control voltage. Because there is no DC
current path for the output common-mode voltage, that DC bias also sets the input pins common-mode operating
points.
Transformer input coupling allows either a single-ended or differential source to be coupled into the LMH5485-
SEP, which also improves the input-referred noise figure. These designs assume a source impedance that must
be matched in the balun interface. 图9-2 shows the simplest approach where an example 1:2 turns ratio step-up
transformer is used from a 50 Ωsource.
LMH5485-SEP
Wideband,
Fully-Differential Amplifier
Rf1
402
Pulse
CX2047LNL
1:2 Turns Ratio
Vcc
Balun
Rg1
100
C1
100 nF
Rs
50
M1
–
+
90.4
H
Output
Measurement
Point
+
–
R1
500
Vocm
FDA
+
–
PD
VG1
N1
N2
Rg2
100
Vcc
Rf2
402
图9-2. Input Balun Interface Delivers a Differential Input to the LMH5485-SEP
In this example, this 1:2 turns ratio step-up transformer provides a source and load match from the 50 Ω source
if the secondary is terminated in 200 Ω (turns-ratio squared is the impedance ratio across a balun). The two Rg
elements provide that termination as they sum to the differential virtual ground at the FDA summing junctions.
The input blocking cap (C1) is optional and included only to eliminate DC shorts to ground from the source. This
solution often improves the total noise figure compared to using just the FDA, as it allows for the noise gain of
the amplifier to be reduced.
9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
Operating the LMH5485-SEP with a DC-coupled differential input source is very simple and only requires that
the input pins stay in range of the DC common-mode operating voltage. One example is a DC-to-50 MHz
quadrature down-converter output. These outputs typically sit on a DC level with some internal source
impedance to the external loads. The example of 图 9-3 shows a design using the LMH5485-SEP with a simple,
passive RLC filter to the inputs (the Rg elements act as the differential termination for the filter design). From the
original source behind the internal 250 Ω outputs, this circuit is a gain of 1 to the LMH5485-SEP output pins.
The DC common-mode operating voltage level shifts from the 1.2 V internal, to the mixer, to an output at the
ADC Vcm voltage of 0.95 V. In this case, a simple average of the two DC voltages in the gain of 1 stage gives a
1.08 V input pin common-mode result that is well within range.
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LMH5485-SEP Wideband,
Fully-Differential Amplifier
Quadrature Downconverter
DC Bias and
Third-Order
Rf1
499
50-MHz, 0.2-dB Ripple,
Chebychev, DC-Coupled
Low-Pass Filter
Output Impedance
100-MHz,
Single-RC
Pole
Vcc
–
R2
250
Rg1
250
R1
22
L1
920 nH
VG1
Low-Power
ADC3664
+
–
Vocm
C3
30 pF
R4
22
14-Bit, Dual,
125-MSPS
FDA
C1
C2
7.5 pF
Rg2
250
+
PD
ADC
7.5 pF
R3
250
Vcc
L2
920 nH
VG2
Rf2
499
+
–
VS2
1.2 V
ADC Vcm
0.95-V Output
图9-3. Example DC-Coupled, Differential I/O Design from a Quadrature Mixer to an ADC
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The LMH5485-SEP offers an effective solution over a broad range of applications. Two examples are developed
here. First, an attenuator stage that directly receives a higher input signal voltage and translates it to a lower
differential swing on a fixed common-mode is shown. This design requires some attention to frequency-response
flatness issues, and one approach to managing these issues is shown. The second example is a gain of 2 V/V,
matched input of 50 Ω to an output set to 0.95 V common-mode followed by a third-order Bessel filter with
approximately 20 MHz of bandwidth, designed for interfacing with a high-speed ADC.
10.2 Typical Applications
10.2.1 Designing Attenuators
LMH5485-SEP
Wideband,
Fully-Differential Amplifier
Gain of 0.1 V/V from Rg1,
Single-Ended to Differential,
DC-Coupled, Single Supply
Rf1
402
Vcc
Rg1
4.02 k
Vcc
Vcm
–
+
+
–
R1
500
+
–
+
+
–
+
–
Vcc
5 V
Vcm
2.5 V
Vocm
FDA
VM1
VG1
–
PD
Rg2
4.02 k
Vcc
Rf2
402
图10-1. Divide-by-10 Attenuator Application for the LMH5485-SEP
10.2.1.1 Design Requirements
In this design, the aim is to do the following:
1. Present a 4 kΩinput impedance to a ±40 V input signal (maximum ±10 mA from the prior stage).
2. Attenuate that swing by a factor 1/10 (–20 dB) to a differential output swing.
3. Place that swing on a 2.5 V common-mode voltage at the LMH5485-SEP outputs.
4. Operate on a single + 5 V supply and ground.
5. Tune the frequency response to a flat Butterworth response with external capacitors.
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10.2.1.2 Detailed Design Procedure
Operating the LMH5485-SEP at a low DC noise gain, or with higher feedback resistors, can cause a lower phase
margin to exist, giving the response peaking shown in 图 10-3 for the gain of 0.1 (a 1/10 attenuator) condition.
Although it is often useful operating the LMH5485-SEP as an attenuator (taking a large input range to a purely
differential signal around a controlled-output, common-mode voltage), the response peaking illustrated in 图10-3
is usually undesirable. Several methods can be used to reduce or eliminate this peaking; usually, at the cost of
higher output noise. Using DC techniques always increases the output noise broadband, while using an ac
noise-gain-shaping technique peaks the noise, but only at higher frequencies that can then be filtered off with the
typical passive filters often used after this stage. 图10-1 shows a simplified schematic for the gain of 0.1 V/V test
from 图8-1.
This configuration simulates to a nominal 18° phase margin; therefore, a very highly-peaked response is shown
in 图 10-3. This peaking can be eliminated by placing two feedback capacitors across the Rf elements and a
differential input capacitor. Adding these capacitors provides a transition from a resistively set noise gain to a
capacitive divider at high-frequency flattening out to a higher noise gain (NG2 here). The key for this approach is
to target a Zo, where the noise gain begins to peak up. Using only the following terms, and targeting a closed-
loop flat (Butterworth) response, gives this solution sequence for Zo and then the capacitor values.
1. Gain bandwidth product in Hz (850 MHz for the LMH5485-SEP)
2. Low frequency noise gain, NG1 ( = 1.1 in the attenuator gain of 0.1 V/V design)
3. Target high-frequency noise gain selected to be higher than NG1 (NG2 = 3.1 V/V is selected for this design)
4. Feedback resistor value, Rf (assumed balanced for this differential design = 402 Ωfor this design example)
From these elements, for any decompensated voltage-feedback op amp or FDA, solve for Zo (in Hz) using 方程
式1:
≈
’
GBP
NG1
NG2
NG1
NG2
Zo =
1-
- 1- 2
∆
∆
÷
÷
2
NG1
«
◊
(1)
From this target zero frequency in the noise gain, solve for the feedback capacitors using 方程式2:
1
Cf =
2
p • Rf • Zo • NG2
(2)
The next step is to resolve the input capacitance on the summing junction. 方程式3 is for a single-ended op amp
where that capacitor goes to ground. To use 方程式 3 for a voltage-feedback FDA, cut the target value in half,
and place the result across the two inputs (reducing the external value by the specified internal differential
capacitance).
Cs = NG2 - 1 Cf
(3)
Setting the external compensation elements using 方程式 1 to 方程式 3 allows an estimate of the resulting flat
bandwidth f–3dB frequency, as shown in 方程式4:
f-3dB
ö GBP • Zo
(4)
Running through these steps for the LMH5485-SEP in the attenuator circuit of 图 10-1 gives the proposed
compensation of 图10-2 where 方程式4 estimates a bandwidth of 252 MHz (Zo target is 74.7 MHz).
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C1
1.7 pF
LMH5485-SEP Wideband,
Fully-Differential Amplifier
Gain of 0.1 V/V from Rg1,
Single-Ended to Differential,
DC-Coupled, Single Supply
Rf1
402
Vcc
Rg1
4.02 k
Vcc
Vcm
–
+
+
R1
500
+
–
+
+
–
+
–
C3
Vocm
FDA
Vcc
5 V
Vcm
2.5 V
VM1
VG1
–
1 pF
–
PD
Vcc
Rg2
4.02 k
Rf2
402
C2
1.7 pF
图10-2. Compensated Attenuator Circuit Using the LMH5485-SEP
The 1 pF across the inputs is really a total 1.9 pF, including the internal differential capacitance. These two
designs (with and without the capacitors) were both bench tested and simulated using the LMH5485-SEP TINA
model giving the results of 图10-3.
This method does a good job of flattening the response for what starts out as a low phase-margin attenuator
application. The simulation model does a very good job of predicting the peaking and showing the same
improvement with the external capacitors; both giving a flat, approximately 250 MHz, closed-loop bandwidth for
this gain of a 0.1 V/V design. In this example, the output noise begins to peak up (as a result of the noise-gain
shaping of the capacitors) above 70 MHz. Use postfiltering to minimize any increase in the integrated noise
using this technique. Using this solution to deliver an 8 VPP differential output to a successive approximation
register (SAR) ADC (using the 2.5 V VOCM shown), the circuit accepts up to ±40 V inputs, where the 4 kΩ input
Rg1 draws ±10 mA from the source.
10.2.1.3 Application Curve
-11
Bench without caps
Bench with caps
Sim without caps
Sim with caps
-17
-14
-20
-23
-26
-29
-32
1M
10M
100M
Frequency (Hz)
1G
D064
图10-3. Attenuator Response Shapes with and without External Compensation
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10.2.2 Interfacing to High-Performance ADCs
Vcc
R9
499 ꢀ
D1
BAV99
Vcc
C1
0.2 ꢁF
50-ꢀ
Source
R12
35.7 ꢀ
R16
6.2 ꢀ
L2
250 nH
ADC
Input
R7
205 ꢀ
R4
59 ꢀ
œ
+
R15
442 ꢀ
C5
33 pF
C6
180 pF
R6
205 ꢀ
Vocm
FDA
œ
R13
35.7 ꢀ
R17
6.2 ꢀ
+
L3
250 nH
PD
ADC
Input
Vcc
R8
499 ꢀ
R1
49.9 ꢀ
R5
59 ꢀ
2
0.95 V
ADC Vcm
Output
3
1
2-to-3 for
ac-coupled Vin
2-to-1 for
dc-coupled Vin
R11
100 ꢀ
Vcc
JP1
C7
1 ꢁF
C3
10 nF
图10-4. DC-Coupled, Bipolar Input Gain of 2 V/V Single-Ended to Differential Interface to ADC
10.2.2.1 Design Requirements
In this example design, an impedance matched input assuming a 50 Ω source is implemented with a DC-
coupled gain of 2 V/V to the ADC. This configuration effectively reduces the required full-scale input to ±0.5 V for
a 2 VPP full-scale input ADC. Add a low insertion-loss interstage filter to the ADC to control the broadband noise
where the goal is to show minimal SNR reduction in the FFT, as well as minimal degradation in SFDR
performance.
10.2.2.2 Detailed Design Procedure
The LMH5485-SEP provides a simple interface to a wide variety of precision SAR, ΔΣ, or higher-speed
pipeline ADCs. To deliver the exceptional distortion at the output pins, considerably wider bandwidth than
typically required in the signal path to the ADC inputs is provided by the LMH5485-SEP. For instance, the gain of
2 single-ended to differential design example provides approximately a 500 MHz, small-signal bandwidth. Even if
the source signal is Nyquist bandlimited, this broad bandwidth can possibly integrate enough LMH5485-SEP
noise to degrade the SNR through the ADC if the broadband noise is not bandlimited between the amplifier and
ADC. 图10-4 shows an example DC-coupled, gain of 2 interface with a controlled, interstage-bandwidth filter.
Designed for a DC-coupled 50 Ω input match, this design starts with a 499 Ω feedback resistor, and provides a
gain of 2.35 V/V to the LMH5485-SEP output pins. The third-order interstage, low-pass filter provides a 20 MHz
Bessel response with a 0.85 V/V insertion loss to the ADC, providing a net gain of 2 V/V from board edge to the
ADC inputs. Although the LMH5485-SEP can absorb overdrives, an external protection element is added using
the BAV99 low-capacitance device, shown in 图 10-4. For DC-coupled testing, pins 1 and 2 of JP1 are jumpered
together. When the source is an AC-coupled, 50 Ω source, pins 2 and 3 of JP1 are jumpered to maintain
differential balance.
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11 Power Supply Recommendations
The LMH5485-SEP is principally intended to operate with a nominal single-supply voltage of +3 V to +5 V.
Supply decoupling is required, as described in the Layout Guidelines. The amplifier signal path is flexible for
single or split-supply operation. Most applications are intended to be single supply, but any split-supply design
can be used, as long as the total supply across the LMH5485-SEP is less than 5.25 V and the required input,
output, and common-mode pin headrooms to each supply are observed. Left open, the VOCM pin defaults to near
mid-supply for any combination of split or single supplies used. The disable pin is negative-rail referenced. Using
a negative supply requires the disable pin to be pulled down to within 0.7 V of the negative supply to disable the
amplifier.
12 Layout
12.1 Layout Guidelines
Similar to all high-speed devices, best system performance is achieved with a close attention to board layout.
The LMH5485-SEP evaluation module (EVM) shows a good example of high frequency layout techniques as a
reference. This EVM includes numerous extra elements and features for characterization purposes that may not
apply to some applications. General high-speed, signal-path layout suggestions include the following:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, ground and power planes around the capacitive sensitive input and output device pins should be
open. After the signal is sent into a resistor, the parasitic capacitance becomes more of a band limiting issue
and less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins.
Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and
shared among devices. A supply decoupling capacitor across the two power supplies (for bipolar operation)
should also be added. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that
offer a much higher self-resonance frequency over standard capacitors.
• For each LMH5485-SEP, attach a separate 0.1 µF capacitor to a nearby ground plane. With cascaded or
multiple parallel channels, including ferrite beads from the larger capacitor is often useful to the local high-
frequency decoupling capacitor.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
• The input summing junctions are very sensitive to parasitic capacitance. Connect any Rg elements into the
summing junction with minimal trace length to the device pin side of the resistor. The other side of the Rg
elements can have more trace length if needed to the source or to ground.
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Design for a Wideband, Differential Transimpedance DAC Output application report
• Texas Instruments, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero
Volts reference guide
• Texas Instruments, LMH6554 2.8-GHz Ultra Linear Fully Differential Amplifier data sheet
• Texas Instruments, Maximizing the dynamic range of analog front ends having a transimpedance amplifier
technical brief
• Texas Instruments, Fully Differential Amplifiers application note
• Texas Instruments, Maximizing Signal Chain Distortion Performance Using High Speed Amplifiers application
note
• Texas Instruments, TI Precision Labs - Fully Differential Amplifiers video series
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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22-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PLMH5485DGKSEP
ACTIVE
VSSOP
DGK
8
80
TBD
Call TI
Call TI
-55 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMH5485-SEP :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2022
Space : LMH5485-SP
•
NOTE: Qualified Version Definitions:
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 2
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