LMH6321MR/NOPB [TI]
具有可调节电流限制的 300mA 高速缓冲器 | DDA | 8 | -40 to 125;
| 型号： | LMH6321MR/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 300mA 高速缓冲器 | DDA | 8 | -40 to 125 放大器 光电二极管 |
| 文件： | 总37页 (文件大小：1658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6321
ZHCSOM5D –APRIL 2006 –REVISED SEPTEMBER 2021
LMH6321 具有可调节电流限制的300 mA 高速缓冲器
1 特性
3 描述
• 高压摆率1800V/μs
• 高带宽110MHz
LMH6321 是一种高速单位增益缓冲器，其压摆率为
1800V/µs，在驱动 50Ω 负载时具有 110MHz 的低信号
带宽。它可以连续驱动±300mA，在驱动大容性负载时
不会振荡。
• 持续输出电流±300mA
• 输出电流限制容差±5mA ±5%
• 宽电源电压范围5V 至±15V
• 宽温度范围−40°C 至+125°C
• 可调节电流限制
LMH6321 具有可调电流限制。电流限制可在 10mA 至
300mA 范围内以 ±5mA ±5% 的精度连续调节。可使用
电阻器调整外部基准电流，从而设置电流限制。通过将
电阻器连接到 DAC 以形成基准电流，可以根据需要轻
松、即时地调整电流。拉电流和灌电流具有共同的电流
限制。
• 高容性负载驱动
• 热关断错误标志
2 应用
LMH6321 采用节省空间的 8 引脚 SO PowerPAD 或 7
引脚 DDPAK 电源封装。SO PowerPAD™ 封装在封装
的底部具有裸焊盘以提高其散热能力。LMH6321 可用
于运算放大器的反馈环路内以提高电流输出，或用作独
立缓冲器。
• 线路驱动器
• 引脚驱动器
• 声纳驱动器
• 电机控制
表3-1. 器件信息
器件型号
LMH6231
封装(1)
SO PowerPAD (8)
DDPAK (7)
封装尺寸（标称值）
1.7 mm × 1.27 mm
4.65 mm × 1.27 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1
8
7
6
5
EF
NC
G = 1
2
+
V
CL
G = 1
1
2
3
4
5
6 7
3
V
V
OUT
IN
4
-
V
GND
A. V− 引脚连接到每个封装背面的凸片上。
图3-2. 连接图：7 引脚DDPAK(A)
图3-1. 连接图：8 引脚SO PowerPAD
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSAL8
LMH6321
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ZHCSOM5D –APRIL 2006 –REVISED SEPTEMBER 2021
Table of Contents
6.4 Source Inductance....................................................17
6.5 Overvoltage Protection............................................. 17
6.6 Bandwidth and Stability.............................................18
6.7 Output Current and Short Circuit Protection............. 18
6.8 Thermal Management...............................................19
6.9 Error Flag Operation................................................. 23
6.10 Single Supply Operation......................................... 24
6.11 Slew Rate................................................................24
7 Device and Documentation Support............................26
7.1 接收文档更新通知..................................................... 26
7.2 支持资源....................................................................26
7.3 Trademarks...............................................................26
7.4 Electrostatic Discharge Caution................................26
7.5 术语表....................................................................... 26
8 Mechanical, Packaging, and Orderable Information..26
1 特性................................................................................... 1
2 应用................................................................................... 1
3 描述................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Absolute Maximum Ratings........................................ 3
5.2 Operating Ratings.......................................................3
5.3 Thermal Information....................................................3
5.4 ±15 V Electrical Characteristics.................................. 4
5.5 ±5 V Electrical Characteristics.................................... 5
5.6 Typical Characteristics................................................8
6 Application Hints...........................................................16
6.1 Buffers.......................................................................16
6.2 Supply Bypassing..................................................... 16
6.3 Load Impedence....................................................... 17
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (March 2013) to Revision D (September 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 添加了器件信息表..............................................................................................................................................1
• Removed the Thermal Resistance (θJA), (θJC), and SO PowerPAD Package details from the Operating
Ratings table.......................................................................................................................................................3
• Added the Thermal Information section..............................................................................................................3
• Added the Device and Documentation Support sections................................................................................. 26
• Added the Mechanical, Packaging, and Orderable Information section...........................................................26
Changes from Revision B (March 2013) to Revision C (March 2013)
Page
• Changed layout of National Data Sheet to TI format........................................................................................24
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5 Specifications
5.1 Absolute Maximum Ratings
See (1) (2)
ESD Tolerance (3)
Human Body Model
Machine Model
2.5 kV
250 V
Supply Voltage
36 V (±18 V)
±5 V
Input to Output Voltage (4)
Input Voltage
±VSUPPLY
Output Short-Circuit to GND (5)
Storage Temperature Range
Continuous
−65°C to +150°C
+150°C
Junction Temperature (TJMAX
)
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
260°C
(6)
CL Pin to GND Voltage
±1.2 V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see
the Electrical Characteristics Table.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model is 1.5 kΩ in series with 100 pF. Machine Model is 0 Ω in series with 200 pF.
(4) If the input-output voltage differential exceeds ±5 V, internal clamping diodes will turn on. The current through these diodes should be
limited to 5 mA max. Thus for an input voltage of ±15 V and the output shorted to ground, a minimum of 2 kΩ should be placed in
series with the input.
(5) The maximum continuous current must be limited to 300 mA. See 节6 for more details.
(6) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = TJ(MAX)–TA)/θJA. See 节6.8 of 节6.
5.2 Operating Ratings
Operating Temperature Range
Operating Supply Range
−40°C to +125°C
5 V to ±16 V
5.3 Thermal Information
LMH6321
DDA SO Power Pad DDAPAK
THERMAL METRIC1
8 Pins
37.8
51.6
11.7
2.5
7 Pins
21.5
34.4
6.7
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R θJA
Junction-to-ambient thermal resistance
R θJC(top)
R θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
3.2
ψJT
Junction-to-board characterization parameter 11.7
Junction-to-case (bottom) thermal resistance 3.6
6.3
ψJB
R θJC(bot)
1.1
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5.4 ±15 V Electrical Characteristics
The following specifications apply for Supply Voltage = ±15 V, VCM = 0, RL ≥100 kΩand RS = 50 Ω, CL open, unless
otherwise noted. Italicized limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AV
Voltage Gain
0.99
0.98
0.995
RL = 1 kΩ, VIN = ±10 V
V/V
0.86
0.84
0.92
±4
RL = 50 Ω, VIN = ±10 V
RL = 1 kΩ, RS = 0 V
VIN = 0 V, RL = 1 kΩ, RS = 0 V
R.L = 50 Ω
V/V
mV
μA
VOS
IB
Input Offset Voltage
Input Bias Current
±35
±52
±2
±15
±17
R.IN
CIN
RO
IS
Input Resistance
250
3.5
5
kΩ
pF
Ω
Input Capacitance
Output Resistance
Power Supply Current
IO = ±10 mA
11
14.5
RL = ∞, VIN = 0
16.5
mA
V
750 µA into
CL Pin
14.9
11.9
18.5
20.5
VO1
VO2
VO3
Positive Output Swing
Negative Output Swing
IO = 300 mA, RS = 0 V, VIN = ±VS
11.2
10.8
IO = 300 mA, RS = 0 V, VIN = ±VS
−11.3
13.4
−10.3
−9.8
Positive Output Swing
Negative Output Swing
13.1
12.9
RL = 1 kΩ, RS = 0 V, VIN = ±VS
RL = 1 kΩ, RS = 0 V, VIN = ±VS
V
−13.4
12.2
−12.9
−12.6
Positive Output Swing
Negative Output Swing
11.6
11.2
RL = 50 Ω, RS = 0 V, VIN = ±VS
RL = 50 Ω, RS = 0 V, VIN = ±VS
V
−11.9
−10.9
−10.6
VEF
Error Flag Output Voltage
Normal
5.00
0.25
RL = ∞, VIN = 0,
EF pulled up with 5 kΩ
to +5 V
During
Thermal
Shutdown
V
TSH
Thermal Shutdown Temperature
Measure Quantity is Die (Junction)
Temperature
168
°C
Hysteresis
10
3
ISH
Supply Current at Thermal
Shutdown
mA
EF pulled up with 5 kΩ to +5 V
PSSR
Power Supply Rejection Ratio
Positive
Negative
58
54
66
64
RL = 1 kΩ, VIN = 0 V,
VS = ±5 V to ±15 V
dB
58
54
SR
Slew Rate
2900
1800
110
VIN = ±11 V, RL = 1 kΩ
VIN = ±11 V, RL = 50 Ω
VIN = ±20 mVPP, RL = 50 Ω
VIN = 2 VPP, RL = 50 Ω
V/μs
BW
MHz
MHz
−3 dB Bandwidth
LSBW
Large Signal Bandwidth
48
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5.4 ±15 V Electrical Characteristics (continued)
The following specifications apply for Supply Voltage = ±15 V, VCM = 0, RL ≥100 kΩand RS = 50 Ω, CL open, unless
otherwise noted. Italicized limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
−59
−70
−57
−68
−59
−70
−62
−73
2.8
Max
Units
HD2
2nd Harmonic Distortion
VO = 2 VPP, f = 100 kHz
RL = 50 Ω
RL = 100 Ω
RL = 50 Ω
RL = 100 Ω
RL = 50 Ω
RL = 100 Ω
RL = 50 Ω
RL = 100 Ω
dBc
VO = 2 VPP, f = 1 MHz
VO = 2 VPP, f = 100 kHz
VO = 2 VPP, f = 1 MHz
HD3
3rd Harmonic Distortion
dBc
en
in
Input Voltage Noise
Input Current Noise
f ≥10 kHz
f ≥10 kHz
nV/√Hz
pA/√Hz
2.4
ISC1
Output Short Circuit Current
Source (1)
VO = 0 V,
Program Current
into CL = 25 µA
Sourcing
VIN = +3 V
4.5
4.5
10
15.5
15.5
mA
mA
mA
Sinking
4.5
10
15.5
4.5
15.5
VIN = −3 V
VO = 0 V
Program Current
into CL = 750 µA
Sourcing
VIN = +3 V
280
273
295
295
570
515
308
325
Sinking
VIN = −3 V
280
275
310
325
ISC2
Output Short Circuit Current
Source
RS = 0 V, VIN = +3 V(1) (2)
320
300
750
920
RS = 0 V, VIN = −3 V(1) (2)
Output Short Circuit Current Sink
300
305
750
910
V/I Section
CLVOS
Current Limit Input Offset Voltage
Current Limit Input Bias Current
±0.5
−0.2
69
±4.0
±8.0
RL = 1 kΩ, GND = 0 V
RL = 1 kΩ
mV
μA
dB
CLIB
−0.5
−0.8
CL
CMRR
Current Limit Common Mode
Rejection Ratio
60
56
RL = 1 kΩ, GND = −13 to +14 V
(1) VIN = + or −4 V at TJ = −40°C.
(2) For the condition where the CL pin is left open the output current should not be continuous, but instead, should be limited to low duty
cycle pulse mode such that the RMS output current is less than or equal to 300 mA.
5.5 ±5 V Electrical Characteristics
The following specifications apply for Supply Voltage = ±5 V, VCM = 0, RL ≥100 kΩand RS = 50 Ω, CL Open, unless
otherwise noted. Italicized limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AV
Voltage Gain
0.99
0.994
RL = 1 kΩ, VIN = ±3 V
0.98
V/V
0.86
0.84
0.92
±2.5
±2
RL = 50 Ω, VIN = ±3 V
RL = 1 kΩ, RS = 0 V
VIN = 0 V, RL = 1 kΩ, RS = 0 V
RL = 50 Ω
VOS
IB
Offset Voltage
±35
±50
mV
Input Bias Current
±15
±17
μA
RIN
CIN
Input Resistance
Input Capacitance
250
3.5
kΩ
pF
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5.5 ±5 V Electrical Characteristics (continued)
The following specifications apply for Supply Voltage = ±5 V, VCM = 0, RL ≥100 kΩand RS = 50 Ω, CL Open, unless
otherwise noted. Italicized limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RO
Output Resistance
IOUT = ±10 mA
5
Ω
IS
Power Supply Current
10
13.5
mA
RL = ∞, VIN = 0 V
14.7
14
1.9
−1.3
3.5
−3.5
3.1
−3.0
66
17.5
19.5
750 μA into CL Pin
VO1
Positive Output Swing
Negative Output Swing
IO = 300 mA, RS = 0 V, VIN = ±VS
IO = 300 mA, RS = 0 V, VIN = ±VS
1.3
0.9
V
V
−0.5
−0.1
VO2
Positive Output Swing
Negative Output Swing
3.2
2.9
RL = 1 kΩ, RS = 0 V, VIN = ±VS
RL = 1 kΩ, RS = 0 V, VIN = ±VS
−3.1
−2.9
V
V
VO3
Positive Output Swing
Negative Output Swing
2.8
2.5
RL = 50 Ω, RS = 0 V, VIN = ±VS
RL = 50 Ω, RS = 0 V, VIN = ±VS
−2.6
−2.4
V
PSSR
Power Supply Rejection Ratio
Positive
Negative
VO = 0 V, Program Current Sourcing
58
54
RL = 1 kΩ, VIN = 0,
VS = ±5 V to ±15 V
dB
58
54
64
ISC1
Output Short Circuit Current
4.5
9
14.0
VIN = +3 V
4.5
15.5
into CL = 25 μA
Sinking
4.5
9
14.0
4.5
15.5
VIN = −3 V
mA
VO = 0 V, Program Current Sourcing
275
270
290
290
470
305
320
VIN = +3 V
into CL = 750 μA
Sinking
VIN = −3 V
275
270
310
320
ISC2
Output Short Circuit Current
Source
RS = 0 V, VIN = +3 V1 2
300
mA
Output Short Circuit Current Sink
Slew Rate
300
400
450
210
90
RS = 0 V, VIN = −3 V1 2
VIN = ±2 VPP, RL = 1 kΩ
VIN = ±2 VPP, RL = 50 Ω
VIN = ±20 mVPP, RL = 50 Ω
VIN = 2 VPP, RL = 50 Ω
Temperature
SR
V/μs
BW
MHz
MHz
−3 dB Bandwidth
LSBW
TSD
Large Signal Bandwidth
Thermal Shutdown
39
170
10
°C
Hysteresis
V/I Section
CLVOS
Current Limit Input Offset Voltage
Current Limit Input Bias Current
2.7
−0.2
65
+5
±5.0
RL = 1 kΩ, GND = 0 V
RL = 1 kΩ, CL = 0 V
mV
μA
dB
CLIB
−0.5
−0.6
CL
CMRR
Current Limit Common Mode
Rejection Ratio
60
56
RL = 1 kΩ, GND = −3 V to +4 V
1. VIN = + or −4 V at TJ = −40°C.
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2. For the condition where the CL pin is left open the output current should not be continuous, but instead,
should be limited to low duty cycle pulse mode such that the RMS output current is less than or equal to 300
mA.
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5.6 Typical Characteristics
60
3000
2600
2200
1800
1400
1000
600
UNDERSHOOT
R
= 1 kW
L
50
40
OVERSHOOT
30
R
= 50W
L
20
V
= 100 mV
= OPEN
IN
PP
10
0
R
L
V
= 15V
S
200
0
4
8
12
16
20
10
100
1k
10k
SUPPLY VOLTAGE ( V)
C
(pF)
L
图5-2. Slew Rate
图5-1. Overshoot vs. Capacitive Load
3000
V
= 15V
S
2600
2200
1800
1400
1000
600
R
= 1 kW
L
V
= 200 mV
IN
PP
R
= 1 kW
L
V
S
= 5V
R
L
= 50W
200
TIME (10 ns/DIV)
0
4
8
12
16
20
24
图5-4. Small Signal Step Response
INPUT AMPLITUDE (V
)
PP
图5-3. Slew Rate
10
25°C
85°C
9
V
IN
= 200 mV
PP
R
= 1 kW
L
V
S
=
15V
8
125°C
-40°C
7
6
TIME (10 ns/DIV)
5
7
9
11
13
15
3
SUPPLY VOLTAGE ( V)
图5-5. Small Signal Step Response
图5-6. Input Offset Voltage of Amplifier vs. Supply Voltage
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5.6 Typical Characteristics (continued)
V
IN
= 200 mV
V
IN
= 200 mV
PP
PP
R
= 50W
R
= 50W
L
L
V
S
=
5V
V
S
=
15V
TIME (10 ns/DIV)
TIME (10 ns/DIV)
图5-7. Small Signal Step Response
图5-8. Small Signal Step Response
V
= 20 V
V
= 20 V
IN
PP
IN
PP
R
V
= 1 kW
R
V
= 50W
L
L
=
15V
=
15V
S
S
TIME (5 ns/DIV)
TIME (5 ns/DIV)
图5-9. Large Signal Step Response—Leading Edge
图5-10. Large Signal Step Response —Leading Edge
V
IN
= 20 V
V
IN
= 20 V
PP
PP
R
L
= 1 kW
R
L
= 50W
V
S
=
15V
V
S
=
15V
TIME (5 ns/DIV)
TIME (5 ns/DIV)
图5-11. Large Signal Step Response —Trailing Edge
图5-12. Large Signal Step Response —Trailing Edge
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5.6 Typical Characteristics (continued)
R
V
= 1 kW
R
V
= 50W
L
L
=
5V
=
15V
S
S
TIME (20 ns/DIV)
TIME (20 ns/DIV)
图5-13. Large Signal Step Response
图5-14. Large Signal Step Response
R
= 50W
R
= 1 kW
L
L
V
=
5V
V
=
15V
S
S
TIME (20 ns/DIV)
TIME (20 ns/DIV)
图5-15. Large Signal Step Response
图5-16. Large Signal Step Response
-20
-20
V
=
15V
V
=
15V
S
S
f = 1 MHz
f = 1 MHz
-30
-40
-50
-60
-70
-80
-30
-40
-50
-60
-70
-80
HD2
HD2
HD3
HD3
0
5
10
20
25
)
30
15
0
5
10
20
25
)
30
15
OUTPUT AMPLITUDE (V
OUTPUT AMPLITUDE (V
PP
PP
图5-17. Harmonic Distortion with 50 Ω Load
图5-18. Harmonic Distortion with 100 Ω Load
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5.6 Typical Characteristics (continued)
-30
10000
V
=
15V
S
-35
-40
-45
-50
-55
-60
-65
-70
R
= 50W
f = 100 kHz
L
1000
HD2
100
10
VOLTAGE nV/
Hz)
CURRENT pA/
Hz)
HD3
1.0
0.1
1.0
0
5
10
15
20
25
1k
FREQUENCY (Hz)
100k
10
100
10k
OUTPUT VOLTAGE (V)
图5-19. Harmonic Distortion with 50 Ω Load
图5-20. Noise vs. Frequency
5
5
0
0
-5
-5
-10
-15
-20
-10
-15
-20
-25
V
=
5V
V
=
15V
R = 50W
L
S
S
R
= 50W
L
-25
100k
1M
10M
100M
100k
1M
10M
100M
1G
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
图5-21. Gain vs. Frequency
图5-22. Gain vs. Frequency
5
0
5
0
-5
-5
-10
-15
-20
-10
-15
-20
V
=
5V
V
=
15V
S
S
R
= 1 kW
R
= 1 kW
L
L
100k
1M
10M
100M
100k
1M
10M
100M
1G
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
图5-23. Gain vs. Frequency
图5-24. Gain vs. Frequency
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5.6 Typical Characteristics (continued)
14
5.2
5
125°C
V
S
= 5V
-40°C
12
85°C
25°C
10
8
-40°C
4.8
125°C
6
4.6
4.4
4.2
4
2
0
85°C
25°C
1
3
5
7
9
11 13 15 17 19
5
7
9
11 13 15 17 19
SUPPLY VOLTAGE ( V)
SOURCING CURRENT (mA)
图5-25. Supply Current vs. Supply Voltage
图5-26. Output Impedance vs. Sourcing Current
5.6
5
V
= 15V
S
V
= 5V
S
-40°C
5.4
5.2
4.8
4.6
-40°C
125°C
25°C
5
4.8
4.6
4.4
4.2
4
125°C
85°C
85°C
25°C
5
7
9
11 13 15 17 19
5
7
9
11 13 15 17 19
SINKING CURRENT (mA)
SOURCING CURRENT (mA)
图5-27. Output Impedance vs. Sinking Current
图5-28. Output Impedance vs. Sourcing Current
5.2
400
V
= 15V
V
= 15V
S
S
5
-40°C
300
200
100
0
125°C
25°C
4.8
85°C
-40°C
25°C
4.6
4.4
4.2
85°C
125°C
25 125 225 325 425 525 625 725 825
5
7
9
11 13 15 17 19
PROGRAM CURRENT (mA)
SINKING CURRENT (mA)
图5-29. Output Impedance vs. Sinking Current
图5-30. Output Short Circuit Current —Sourcing vs. Program
Current
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5.6 Typical Characteristics (continued)
400
400
V
= 5V
S
V
= 15V
S
300
200
300
200
100
0
125°C
25°C
125°C
25°C
-40°C
-40°C
85°C
85°C
100
0
25 125 225 325 425 525 625 725 825
25 125 225 325 425 525 625 725 825
PROGRAM CURRENT (mA)
PROGRAM CURRENT (mA)
图5-31. Output Short Circuit Current —Sinking vs. Program
图5-32. Output Short Circuit Current —Sourcing vs. Program
Current
Current
400
4
V
= 5V
125°C
S
3.5
85°C
3
300
200
100
0
125°C
25°C
2.5
25°C
-40°C
85°C
2
-40°C
1.5
1
V
V
= 5V
+
IN
S
= V
0.5
0
C
= OPEN
L
25 125 225 325 425 525 625 725 825
0
100
200
300
400
500
PROGRAM CURRENT (mA)
SOURCING CURRENT (mA)
图5-33. Output Short Circuit Current —Sinking vs. Program
图5-34. Positive Output Swing vs. Sourcing Current
Current
0
-0.5
-1
14
125°C
85°C
V
V
= 15V
+
IN
S
= V
13
C
= OPEN
L
25°C
-1.5
12
11
10
9
-40°C
-40°C
-2
25°C
-2.5
-3
85°C
125°C
V
V
= 5V
-
IN
S
= V
-3.5
-4
C
= OPEN
L
0
100
200
300
400
500
-500
-400
-300
-200
-100
0
SOURCING CURRENT (mA)
SINKING CURRENT (mA)
图5-36. Positive Output Swing vs. Sourcing Current
图5-35. Negative Output Swing vs. Sinking Current
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5.6 Typical Characteristics (continued)
-9
1000
800
V
V
= 15V
-
IN
S
-40°C
25°C
= V
-10
C
= OPEN
L
-11
-12
-13
-14
600
25°C
-40°C
85°C
400
200
125°C
125°C
V
= +3
IN
85°C
C
= OPEN
L
0
-500
-400
-300
-200
-100
0
2
4
6
8
10 12 14 16 18
SINKING CURRENT (mA)
SUPPLY VOLTAGE ( V)
图5-37. Negative Output Swing vs. Sinking Current
图5-38. Output Short Circuit Current —Sourcing vs. Supply
Voltage
800
15
-40°C
R
= 50W
L
25°C
13
600
11
9
85°C
125°C
125°C
25°C
400
85°C
-40°C
7
-40°C
200
5
3
V
= -3V
IN
C
= OPEN
L
0
2
4
6
8
10 12 14 16 18
5
7
9
11
13
15
SUPPLY VOLTAGE ( V)
SUPPLY VOLTAGE ( V)
图5-39. Output Short Circuit Current —Sinking vs. Supply
图5-40. Positive Output Swing vs. Supply Voltage
Voltage
15
-3
R
L
= 50W
R
= 1 kW
L
13
-5
-40°C
125°C
11
9
-7
-9
25°C
125°C
25°C
85°C
85°C
-40°C
7
-11
5
3
-13
-15
5
7
9
11
13
15
5
7
9
11
13
15
SUPPLY VOLTAGE ( V)
SUPPLY VOLTAGE ( V)
图5-41. Positive Output Swing vs. Supply Voltage
图5-42. Negative Output Swing vs. Supply Voltage
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5.6 Typical Characteristics (continued)
-3
15
10
V
=
5V
S
R
L
= 1 kW
-5
-40°C
125°C
-40°C
-7
-9
25°C
85°C
5
0
25°C
-11
-13
-15
125°C
85°C
-5
5
7
9
11
13
15
0
-2
-1
1
2
3
-3
SUPPLY VOLTAGE ( V)
COMMON MODE VOLTAGE (V)
图5-43. Negative Output Swing vs. Supply Voltage
图5-44. Input Offset Voltage of Amplifier vs. Common Mode
Voltage
25
0
V
= 15V
125°C
25°C
S
125°C
15
-2
85°C
-40°C
5
-5
-4
-40°C
125°C
25°C
-40°C
-6
85°C
-15
-8
-25
-10
-12
-8
-4
0
4
8
12
3
5
7
9
11
13
15
SUPPLY VOLTAGE ( V)
COMMON MODE VOLTAGE (V)
图5-46. Input Bias Current of Amplifier vs. Supply Voltage
图5-45. Input Offset Voltage of Amplifier vs. Common Mode
Voltage
5
4
V
=
5V
V
=
S
15V
S
4
3
2
0
25°C
25°C
-40°C
-40°C
2
-2
125°C
-40°C
1
0
-4
-6
85°C
85°C
-1
-2
-8
-10
-12
-8
-4
0
4
8
12
-3
-2
-1
0
1
2
3
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
图5-47. Input Offset Voltage of V/I Section vs. Common Mode
图5-48. Input Offset Voltage of V/I Section vs. Common Mode
Voltage
Voltage
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6 Application Hints
6.1 Buffers
Buffers are often called voltage followers because they have largely unity voltage gain, thus the name has
generally come to mean a device that supplies current gain but no voltage gain. Buffers serve in applications
requiring isolation of source and load, for example, high input impedance and low output impedance (high output
current drive). In addition, they offer gain flatness and wide bandwidth.
Most operational amplifiers that meet the other given requirements in a particular application can be configured
as buffers, though they are generally more complex and are, for the most part, not optimized for unity gain
operation. The commercial buffer is a cost effective substitute for an op amp. Buffers serve several useful
functions, either in tandem with op amps or in standalone applications. As mentioned, their primary function is to
isolate a high impedance source from a low impedance load, since a high Z source cannott supply the needed
current to the load. For example, in the case where the signal source to an analog to digital converter is a
sensor, it is recommended that the sensor be isolated from the A/D converter. The use of a buffer ensures a low
output impedance and delivery of a stable output to the converter. In A/D converter applications buffers need to
drive varying and complex reactive loads.
Buffers come in two flavors: Open Loop and Closed Loop. While sacrificing the precision of some DC
characteristics, and generally displaying poorer gain linearity, open loop buffers offer lower cost and increased
bandwidth, along with less phase shift and propagation delay than do closed loop buffers. The LMH6321 is of
the open loop variety.
图 6-1 shows a simplified diagram of the LMH6321 topology, revealing the open loop complementary follower
design approach. 图6-2 shows the LMH6321 in a typical application, in this case, a 50 Ω coaxial cable driver.
+
V
Q5
Q7
Q3
R
R
3
1
D1 D3 D5 D7 D9 D11
2W
Q1
V
OUT
V
IN
D4
D8D10 D12
D6
D2
R
4
Q2
2W
R
2
Q4
Q8
Q6
-
V
图6-1. Simplified Schematic
6.2 Supply Bypassing
The method of supply bypassing is not critical for frequency stability of the buffer, and, for light loads, capacitor
values in the neighborhood of 1 nF to 10 nF are adequate. However, under fast slewing and large loads, large
transient currents are demanded of the power supplies, and when combined with any significant wiring
inductance, these currents can produce voltage transients. For example, the LMH6321 can slew typically at
1000 V/μs. Therefore, under a 50 Ω load condition the load can demand current at a rate, di/dt, of 20 A/μs.
This current flowing in an inductance of 50 nH (approximately 1.5” of 22 gauge wire) will produce a 1 V
transient. Thus, it is recommended that solid tantalum capacitors of 5 μF to 10 μF, in parallel with a ceramic 0.1
μF capacitor be added as close as possible to the device supply pins.
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TP1
EF
+
V
V
CL
C
2
0.1 mF
R
3
R
2
10 kW 1%
10 kW 1%
+
V
R
1
EF
50W COAXIAL
CABLE
10 kW
C
L
V
IN
V
OUT
INPUT
LMH6321
OUTPUT
R
4
GND
C
IN
R
6
-
V
50W
50W
C
1
1 nF
C
3
0.1 mF
-
V
图6-2. 50 Ω Coaxial Cable Driver with Dual Supplies
For values of capacitors in the 10 μF to 100 μF range, ceramics are usually larger and more costly than
tantalums but give superior AC performance for bypassing high frequency noise because of their very low ESR
(typically less than 10 MΩ) and low ESL.
6.3 Load Impedence
The LMH6321 is stable under any capacitive load when driven by a 50 Ω source. As shown by 图 5-1 in 节 5.6,
worst case overshoot is for a purely capacitive load of about 1 nF. Shunting the load capacitance with a resistor
will reduce the overshoot.
6.4 Source Inductance
Like any high frequency buffer, the LMH6321 can oscillate with high values of source inductance. The worst
case condition occurs with no input resistor, and a purely capacitive load of 50 pF, where up to 100 nH of source
inductance can be tolerated. With a 50 Ω load, this goes up to 200 nH. However, a 100 Ω resistor placed in
series with the buffer input will ensure stability with a source inductances up to 400 nH with any load.
6.5 Overvoltage Protection
(Refer to the simplified schematic in 图6-1).
If the input-to-output differential voltage were allowed to exceed the Absolute Maximum Rating of 5 V, an internal
diode clamp would turn on and divert the current around the compound emitter followers of Q1/Q3 (D1 – D11
for positive input), or around Q2/Q4 (D2 – D12 for negative inputs). Without this clamp, the input transistors Q1
–Q4 would zener, thereby damaging the buffer.
To limit the current through this clamp, a series resistor should be added to the buffer input (see R1 in 图 6-2).
Although the allowed current in the clamp can be as high as 5 mA, which would suggest a 2 kΩ resistor from a
15 V source, it is recommended that the current be limited to about 1 mA, hence the 10 kΩ shown.
The reason for this larger resistor is explained in the following: One way that the input or output voltage
differential can exceed the Absolute Maximum value is under a short circuit condition to ground while driving the
input with up to ±15 V. However, in the LMH6321 the maximum output current is set by the programmable
Current Limit pin (CL). The value set by this pin is specified to be accurate to 5 mA ±5%. If the input/output
differential exceeds 5 V while the output is trying to supply the maximum set current to a shorted condition or to
a very low resistance load, a portion of that current will flow through the clamp diodes, thus creating an error in
the total load current. If the input resistor is too low, the error current can exceed the 5 mA ±5% budget.
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6.6 Bandwidth and Stability
As can be seen in the schematic of 图 6-2, a small capacitor is inserted in parallel with the series input resistors.
The reason for this is to compensate for the natural band-limiting effect of the 1st order filter formed by this
resistor and the input capacitance of the buffer. With a typical CIN of 3.5 pF (图6-2), a pole is created at
fp2 = 1/(2πR1CIN) = 4.5 MHz
(1)
This will band-limit the buffer and produce further phase lag. If used in an op amp-loop application with an
amplifier that has the same order of magnitude of unity gain crossing as fp2, this additional phase lag will
produce oscillation.
The solution is to add a small feed-forward capacitor (phase lead) around the input resistor, as shown in 图 6-2.
The value of this capacitor is not critical but should be such that the time constant formed by it and the input
resistor that it is in parallel with (RIN) be at least five times the time constant of RINCIN. Therefore,
C1 = (5RIN/R1)(CIN)
(2)
from 节5.4, RIN is 250 kΩ.
In the case of the example in 图6-2, RINCIN produces a time-constant of 870 ns, so C1 should be chosen to be a
minimum of 4.4 μs, or 438 pF. The value of C1 (1000 pF) shown in 图6-2 gives 10 μs.
6.7 Output Current and Short Circuit Protection
The LMH6321 is designed to deliver a maximum continuous output current of 300 mA. However, the maximum
available current, set by internal circuitry, is about 700 mA at room temperature. The output current is
programmable up to 300 mA by a single external resistor and voltage source.
The LMH6321 is not designed to safely output 700 mA continuously and should not be used this way. However,
the available maximum continuous current will likely be limited by the particular application and by the package
type chosen, which together set the thermal conditions for the buffer (see 节6.8) and could require less than 300
mA.
The programming of both the sourcing and sinking currents into the load is accomplished with a single resistor.
Figure 6-3 shows a simplified diagram of the V to I converter and ISC protection circuitry that, together, perform
this task.
Referring to Figure 6-3, the two simplified functional blocks, labeled V/I Converter and Short Circuit Protection,
comprise the circuitry of the Current Limit Control.
The V/I converter consists of error amplifier A1 driving two PNP transistors in a Darlington configuration. The two
input connections to this amplifier are VCL (inverting input) and GND (non-inverting input). If GND is connected to
zero volts, then the high open loop gain of A1, as well as the feedback through the Darlington, will force CL, and
thus one end REXT to be at zero volts also. Therefore, as shown in 方程式 3 a voltage applied to the other end of
REXT will force a current into this pin.
IEXT = VPROG/REXT
(3)
Through the VCL pin, IOUT is programmable from 10 mA to 300 mA by setting IEXT from 25 μA to 750 µA by
means of a fixed REXT of 10 kΩ and making VPROG variable from 0.25 V to 7.5 V. Thus, an input voltage VPROG is
converted to a current IEXT. This current is the output from the V/I converter. It is gained up by a factor of two and
sent to the Short Circuit Protection block as IPROG. IPROG sets a voltage drop across RSC which is applied to the
non-inverting input of error amp A2. The other input is across RSENSE. The current through RSENSE, and hence
the voltage drop across it, is proportional to the load current, through the current sense transistor QSENSE. The
output of A2 controls the drive (IDRIVE) to the base of the NPN output transistor, Q3 which is, proportional to the
amount and polarity of the voltage differential (VDIFF) between AMP2 inputs, that is, how much the voltage
across RSENSE is greater than or less than the voltage across RSC. This loop gains IEXT up by another 200, thus
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ISC = 2 x 200 (IEXT) = 400 IEXT
(4)
Therefore, combining 方程式3 and 方程式4, and solving for REXT, we get
REXT = 400 VPROG/ISC
(5)
If the VCL pin is left open, the output short circuit current will default to about 700 mA. At elevated temperatures
this current will decrease.
I
25 mA to 750 mA
EXT
R
EXTERNAL
V
CL
V
PROG
V/I CONVERTER
-
A1
CONNECT TO GROUND
(FOR DUAL SUPPLIES)
OR MID RAIL FOR
GND
+
SINGLE SUPPLY
ö
+
V
+
V
NPN OUTPUT
XTR
I
SENSE
OUT
XTR
I
DRIVE
AMP2
Q
SENSE
V
DIFF
I
PROG
R
SENSE
TO INPUT
STAGE
R
3
R
SC
400W
50 mA to 1.5 mA
200W
2W
I
I
OUTPUT
LOAD
SENSE
SHORT CIRCUIT
PROTECTION
TO LOWER OUTPUT STAGE
Only the NPN output ISC protection is shown. Depending on the polarity of VDIFF, AMP2 will turn IDRIVE either on or off.
图6-3. Simplified Diagram of Current Limit Control
6.8 Thermal Management
6.8.1 Heatsinking
For some applications, a heat sink may be required with the LMH6321. This depends on the maximum power
dissipation and maximum ambient temperature of the application. To accomplish heat sinking, the tabs on
DDPAK and SO PowerPAD package may be soldered to the copper plane of a PCB for heatsinking (note that
these tabs are electrically connected to the most negative point in the circuit, for example,V−).
Heat escapes from the device in all directions, mainly through the mechanisms of convection to the air above it
and conduction to the circuit board below it and then from the board to the air. Natural convection depends on
the amount of surface area that is in contact with the air. If a conductive plate serving as a heatsink is thick
enough to ensure perfect thermal conduction (heat spreading) into the far recesses of the plate, the temperature
rise would be simply inversely proportional to the total exposed area. PCB copper planes are, in that sense, an
aid to convection, the difference being that they are not thick enough to ensure perfect conduction. Therefore,
eventually we will reach a point of diminishing returns (as seen in 图 6-5). Very large increases in the copper
area will produce smaller and smaller improvement in thermal resistance. This occurs, roughly, for a 1 inch
square of 1 oz copper board. Some improvement continues until about 3 square inches, especially for 2 oz
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boards and better, but beyond that, external heatsinks are required. Ultimately, a reasonable practical value
attainable for the junction to ambient thermal resistance is about 30 °C/W under zero air flow.
A copper plane of appropriate size may be placed directly beneath the tab or on the other side of the board. If
the conductive plane is placed on the back side of the PCB, it is recommended that thermal vias be used per
JEDEC Standard JESD51-5.
6.8.2 Determining Copper Area
One can determine the required copper area by following a few basic guidelines:
1. Determine the value of the circuit’s power dissipation, PD
2. Specify a maximum operating ambient temperature, TA(MAX). Note that when specifying this parameter, it
must be kept in mind that, because of internal temperature rise due to power dissipation, the die
temperature, TJ, will be higher than TA by an amount that is dependent on the thermal resistance from
junction to ambient, θJA. Therefore, TA must be specified such that TJ does not exceed the absolute
maximum die temperature of 150°C.
3. Specify a maximum allowable junction temperature, TJ(MAX), which is the temperature of the chip at
maximum operating current. Although no strict rules exist, typically one should design for a maximum
continuous junction temperature of 100°C to 130°C, but no higher than 150°C which is the absolute
maximum rating for the part.
4. Calculate the value of junction to ambient thermal resistance, θJA
5. Choose a copper area that will ensure the specified TJ(MAX) for the calculated θJA. θJA as a function of
copper area in square inches is shown in 图6-4.
The maximum value of thermal resistance, junction to ambient θJA, is defined as:
θJA = (TJ(MAX) - TA(MAX) )/ PD(MAX)
(6)
where
• TJ(MAX) = the maximum recommended junction temperature
• TA(MAX) = the maximum ambient temperature in the user’s environment
• PD(MAX) = the maximum recommended power dissipation
Note
The allowable thermal resistance is determined by the maximum allowable heat rise , TRISE = TJ(MAX)
-
TA(MAX) = (θJA) (PD(MAX)). Thus, if ambient temperature extremes force TRISE to exceed the design
maximum, the part must be de-rated by either decreasing PD to a safe level, reducing θJA, further, or,
if available, using a larger copper area.
6.8.3 Procedure
1. First determine the maximum power dissipated by the buffer, PD(MAX). For the simple case of the buffer
driving a resistive load, and assuming equal supplies, PD(MAX) is given by:
PD(MAX) = IS (2V+) + V+2/4RL
(7)
where
• IS = quiescent supply current
2. Determine the maximum allowable die temperature rise,
TR(MAX) = TJ(MAX)-TA(MAX) = PD(MAX)θJA
(8)
(9)
3. Using the calculated value of TR(MAX) and PD(MAX) the required value for junction to ambient thermal
resistance can be found:
θJA = TR(MAX)/PD(MAX)
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4. Finally, using this value for θJA choose the minimum value of copper area from 图6-4.
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6.8.4 Example
Assume the following conditions:
V+ = V− = 15 V, RL = 50 Ω, IS = 15 mA TJ(MAX) = 125°C, TA(MAX) = 85°C.
1. From 方程式7
• PD(MAX) = IS (2 V+) + V+2/4RL = (15 mA)(30 V) + 15 V2/200 Ω = 1.58 W
2. From 方程式8
• TR(MAX) = 125°C - 85°C = 40°C
3. From 方程式9
• θJA = 40°C/1.58 W = 25.3°C/W
Examining 图 6-4, we see that we cannot attain this low of a thermal resistance for one layer of 1 oz copper. It
will be necessary to derate the part by decreasing either the ambient temperature or the power dissipation. Other
solutions are to use two layers of 1 oz foil, or use 2 oz copper (see 表 6-1), or to provide forced air flow. One
should allow about an extra 15% heat sinking capability for safety margin.
80
70
60
50
40
30
20
0
1
2
3
COPPER FOIL AREA (SQ. IN.)
图6-4. Thermal Resistance (Typical) for 7-L DDPAK Package Mounted on 1 oz. (0.036 mm) PC Board Foil
5
4
3
2
1
TO-263 PACKAGE
PCB MOUNT
1 SQ. IN. COPPER
0
75
AMBIENT TEMPERATURE (°C)
125
-40 -25
25
图6-5. Derating Curve for DDPAK package. No Air Flow
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表6-1. θJA vs. Copper Area and PD for DDPAK. 1.0 oz cu Board. No Air Flow. Ambient Temperature =
24°C
Copper Area
θJA at 1.0W
θJA at 2.0W
(°C/W)
(°C/W)
62.4
36.4
23.5
19.8
54.7
32.1
22.0
17.2
1 Layer = 1”x2”cu Bottom
2 Layer = 1”x2”cu Top and Bottom
2 Layer = 2”x2”cu Top and Bottom
2 Layer = 2”x4”cu Top and Bottom
As seen in the previous example, buffer dissipation in DC circuit applications is easily computed. However, in AC
circuits, signal wave shapes and the nature of the load (reactive, non-reactive) determine dissipation. Peak
dissipation can be several times the average with reactive loads. It is particularly important to determine
dissipation when driving large load capacitance.
A selection of thermal data for the SO PowerPAD package is shown in 表 6-2. The table summarizes θJA for
both 0.5 watts and 0.75 watts. Note that the thermal resistance, for both the DDPAK and the SO PowerPAD
package is lower for the higher power dissipation levels. This phenomenon is a result of the principle of Newtons
Law of Cooling. Restated in term of heatsink cooling, this principle says that the rate of cooling and hence the
thermal conduction, is proportional to the temperature difference between the junction and the outside
environment (ambient). This difference increases with increasing power levels, thereby producing higher die
temperatures with more rapid cooling.
表6-2. θJA vs. Copper Area and PD for SO PowerPAD. 1.0 oz cu Board. No Airflow. Ambient Temperature
= 22°C
Copper Area/Vias
θJA at 0.5W
θJA at 0.75W
(°C/W)
(°C/W)
1 Layer = 0.05 sq. in. (Bottom) + 3 Via Pads
1 Layer = 0.1 sq. in. (Bottom) + 3 Via Pads
1 Layer = 0.25 sq. in. (Bottom) + 3 Via Pads
1 Layer = 0.5 sq. in. (Bottom) + 3 Via Pads
1 Layer = 1.0 sq. in. (Bottom) + 3 Via Pads
141.4
134.4
115.4
105.4
100.5
93.7
138.2
131.2
113.9
104.7
100.2
92.5
2 Layer = 0.5 sq. in. (Top)/ 0.5 sq. in. (Bottom) + 33 Via
Pads
2 Layer = 1.0 sq. in. (Top)/ 1.0 sq. in. (Bottom) + 53 Via
Pads
82.7
82.2
6.9 Error Flag Operation
The LMH6321 provides an open collector output at the EF pin that produces a low voltage when the Thermal
Shutdown Protection is engaged, due to a fault condition. Under normal operation, the Error Flag pin is pulled up
to V+ by an external resistor. When a fault occurs, the EF pin drops to a low voltage and then returns to V+ when
the fault disappears. This voltage change can be used as a diagnostic signal to alert a microprocessor of a
system fault condition. If the function is not used, the EF pin can be either tied to ground or left open. If this
function is used, a 10 kΩ, or larger, pull-up resistor (R2 in 图 6-2) is recommended. The larger the resistor the
lower the voltage will be at this pin under thermal shutdown. 表 6-3 shows some typical values of VEF for 10 kΩ
and 100 kΩ.
表6-3. VEF vs. R2
At V+ = 5 V
At V+ = 15 V
R2 (in 图6-2)
0.24 V
0.55 V
10 kΩ
0.036 V
0.072 V
100 KΩ
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ZHCSOM5D –APRIL 2006 –REVISED SEPTEMBER 2021
6.10 Single Supply Operation
If dual supplies are used, then the GND pin can be connected to a hard ground (0 V) (as shown in 图 6-2).
However, if only a single supply is used, this pin must be set to a voltage of one VBE (≈0.7 V) or greater, or more
commonly, mid rail, by a stiff, low impedance source. This precludes applying a resistive voltage divider to the
GND pin for this purpose. 图6-6 shows one way that this can be done.
+
V
LMH6321
+
V
GND
-
V
-
R
R
1
OP AMP
+
2
图6-6. Using an Op Amp to Bias the GND Pin to ½ V+ for Single Supply Operation
In 图6-6, the op amp circuit pre-biases the GND pin of the buffer for single supply operation.
The GND pin can be driven by an op amp configured as a constant voltage source, with the output voltage set
by the resistor voltage divider, R1 and R2. It is recommended that These resistors be chosen so as to set the
GND pin to V+/2, for maximum common mode range.
6.11 Slew Rate
Slew rate is the rate of change of output voltage for large-signal step input changes. For resistive load, slew rate
is limited by internal circuit capacitance and operating current (in general, the higher the operating current for a
given internal capacitance, the faster is the slew rate). 图 6-7 shows the slew capabilities of the LMH6321 under
large signal input conditions, using a resistive load.
3000
V
= 15V
S
2600
2200
1800
1400
1000
600
R
= 1 kW
L
R
L
= 50W
200
0
4
8
12
16
20
24
INPUT AMPLITUDE (V
)
PP
图6-7. Slew Rate vs. Peak-to-Peak Input Voltage
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However, when driving capacitive loads, the slew rate may be limited by the available peak output current
according to the following expression.
dv/dt = IPK/CL
(10)
and rapidly changing output voltages will require large output load currents. For example if the part is required to
slew at 1000 V/μs with a load capacitance of 1 nF the current demand from the LMH6321 would be 1A.
Therefore, fast slew rate is incompatible with large CL. Also, since CL is in parallel with the load, the peak current
available to the load decreases as CL increases.
图 6-8 illustrates the effect of the load capacitance on slew rate. Slew rate tests are specified for resistive loads
and/or very small capacitive loads, otherwise the slew rate test would be a measure of the available output
current. For the highest slew rate, it is obvious that stray load capacitance should be minimized. Peak output
current should be kept below 500 mA. This translates to a maximum stray capacitance of 500 pF for a slew rate
of 1000 V/μs.
10000
1000
100
10
1
0.1
0.1
1
10
100
1000
CAPACITANCE (nF)
图6-8. Slew Rate vs. Load Capacitance
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ZHCSOM5D –APRIL 2006 –REVISED SEPTEMBER 2021
7 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
7.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
7.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
7.3 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
7.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6321MR/NOPB
LMH6321MRX/NOPB
LMH6321TS/NOPB
LMH6321TSX/NOPB
ACTIVE SO PowerPAD
DDA
8
8
7
7
95
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LMH63
21MR
ACTIVE SO PowerPAD
DDA
2500 RoHS & Green
SN
SN
SN
LMH63
21MR
ACTIVE
ACTIVE
DDPAK/
TO-263
KTW
45
RoHS-Exempt
& Green
LMH6321TS
DDPAK/
TO-263
KTW
500
RoHS-Exempt
& Green
LMH6321TS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6321MRX/NOPB
LMH6321TSX/NOPB
SO
PowerPAD
DDA
KTW
8
7
2500
500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
DDPAK/
TO-263
330.0
24.4
10.75 14.85
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6321MRX/NOPB
LMH6321TSX/NOPB
SO PowerPAD
DDPAK/TO-263
DDA
KTW
8
7
2500
500
356.0
367.0
356.0
367.0
35.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6321MR/NOPB
LMH6321TS/NOPB
DDA
KTW
HSOIC
TO-263
8
7
95
45
495
502
8
4064
3.05
9.19
25
8204.2
Pack Materials-Page 3
MECHANICAL DATA
KTW0007B
TS7B (Rev E)
BOTTOM SIDE OF PACKAGE
www.ti.com
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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