LMH6514SQE/NOPB [TI]
具有 6.02dB 步进的 600MHz 数字控制、可变增益放大器 | RGH | 16 | -40 to 85;
| 型号： | LMH6514SQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 6.02dB 步进的 600MHz 数字控制、可变增益放大器 | RGH | 16 | -40 to 85 放大器 |
| 文件： | 总31页 (文件大小：774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6514
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SNOSB06A –JANUARY 2008–REVISED MARCH 2013
LMH6514 600 MHz, Digital Controlled, Variable Gain Amplifier
Check for Samples: LMH6514
1
FEATURES
DESCRIPTION
The LMH6514 is
a high performance, digitally
2
•
•
•
•
•
•
•
•
Adjustable Gain with a 42 dB Range
Precise 6.02 dB Gain Steps
controlled variable gain amplifier (DVGA). It combines
precision gain control with a low noise, ultra-linear,
differential amplifier. Typically, the LMH6514 drives a
high performance ADC in a broad range of mixed
signal and digital communication applications such as
mobile radio and cellular base stations where
automatic gain control (AGC) is required to increase
system dynamic range. When used in conjunction
with a high speed ADC, system dynamic range can
be extended by up to 42 dB.
Parallel 3 Bit Gain Control
On Chip Register Gain Setting
Fully Differential Signal Path
Single Ended to Differential Capable
200Ω Input Impedance
Small Footprint (4 mm x 4 mm) WQFN Package
The LMH6514 has a differential input and output
allowing large signal swings on a single 5V supply. It
is designed to accept signals from RF elements and
maintain a terminated impedance environment. The
input impedance is 200Ω resistive. The output
impedance is either 200Ω or 400Ω and is user
selectable. A unique internal architecture allows use
with both single ended and differential input signals.
APPLICATIONS
•
•
•
•
•
•
Cellular Base Stations
IF Sampling Receivers
Instrumentation
Modems
Imaging
Differential Line Receiver
Input signals to the LMH6514 are scaled by a highly
linear, digitally controlled attenuator with seven
accurate 6 dB steps. The attenuator output provides
the input signal for a high gain, ultra linear differential
transconductor. The transconductor differential output
current can be converted into a voltage by using the
on-chip 200Ω or 400Ω loads. The transconductance
gain is 0.1 Amp/Volt resulting in a maximum voltage
gain of +32 dB when driving a 200Ω load, or 38 dB
when driving the 400Ω load.
KEY SPECIFICATIONS
•
•
•
•
•
•
•
600 MHz bandwidth at 100Ω load
39 dBm OIP3 at 75 MHz, 200Ω load
26 dB to 38 dB maximum gain
Selectable output impedance of 200Ω or 400Ω.
8.3 dB noise figure
5 ns gain step switching time
100 mA supply current
The LMH6514 operates over the industrial
temperature range of −40°C to +85°C. The LMH6514
is available in a 16-Pin, thermally enhanced, WQFN
package.
Typical Application
V
CC
LMH6514
ADC14155
RF
LO
3
GAIN
LATCH
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LMH6514
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
(3)
ESD Tolerance
Human Body Model
2 kV
150V
Machine Model
Positive Supply Voltage (Pin 3)
Output Voltage (Pin 14,15)
Differential Voltage between Any Two Grounds
Analog Input Voltage Range
Digital Input Voltage Range
−0.6V to 5.5V
−0.6V to 6.8V
<200 mV
−0.6V to VCC
−0.6V to 3.6V
Output Short Circuit Duration
(one pin to ground)
Infinite
+150°C
Junction Temperature
Storage Temperature Range
Soldering Information
−65°C to +150°C
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235°C
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Operating Ratings(1)
Supply Voltage (Pin 3)
4V to 5.25V
1.4V to 6.4V
<10 mV
Output Voltage Range (Pin 14, 15)
Differential Voltage Between Any Two Grounds
Analog Input Voltage Range,
AC Coupled
±1.4V
(2)
Temperature Range
−40°C to +85°C
Package Thermal Resistance (θJA
)
16-Pin WQFN
47°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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5V Electrical Characteristics(1)
The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL = 100Ω (200Ω external || 200Ω
internal), VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(3)
(2)
Dynamic Performance
SSBW
−3 dB Bandwidth
Average of all Gain Settings
600
MHz
Noise and Distortion
Third Order Intermodulation
Products
f = 75 MHz, V OUT = 2 VPP
f = 150 MHz, V OUT = 2 VPP
f = 250 MHz, V OUT = 2 VPP
f = 450 MHz, V OUT = 2 VPP
−70
−66
−60
−52
35
dBc
dBm
dBm
OIP3
Output Third Order Intercept Point
f = 75 MHz, V OUT = 2 VPP
,
Tone Spacing = 0.5 MHz
f = 150 MHz, V OUT = 2 VPP
Tone Spacing = 2 MHz
,
,
33
31
39
37
34
f = 250 MHz, V OUT = 2 VPP
Tone Spacing = 2 MHz
f = 75 MHz, RL= 200Ω, V OUT = 2 VPP
Tone Spacing = 0.5 MHz
f = 150 MHz, RL = 200Ω, V OUT = 2 VPP
Tone Spacing = 2 MHz
,
f = 250 MHz, RL = 200Ω, V OUT = 2 VPP
Tone Spacing = 2 MHz
,
P1 dB
Output Level for 1 dB Gain
Compression
f = 75 MHz, R L = 200Ω
f = 250 MHz, R L = 200Ω
f = 75 MHz
16.7
14.7
14.5
13.2
1.8
f = 450 MHz
VNI
Input Noise Voltage
Output Noise Voltage
Noise Figure
Maximum Gain, f = 40 MHz
Maximum Gain, f = 40 MHz
Maximum Gain
nV/√Hz
nV/√Hz
dB
VNO
36
NF
8.3
Analog I/O
Differential Input Resistance
Input Common Mode Resistance
Differential Output Resistance
165
158
188
955
220
230
Ω
Ω
825
785
1120
1160
Low Gain Option
High Gain Option
186
370
Ω
Ω
330
325
420
425
Internal Load Resistors
Between Pins 13, 14 and Pins 15, 16
165
158
187
215
225
Input Signal Level (AC Coupled)
Maximum Differential Input Signal
Input Common Mode Voltage
Max Gain, VO = 2 VPP, RL = 1 kΩ
AC Coupled
63
5.6
1.4
mVPP
VPP
Self Biased
1.3
1.1
1.5
1.7
V
V
Input Common Mode Voltage
Range
Driven Externally
0.9 to 2.0
Minimum Input Voltage
Maximum Input Voltage
DC
DC
0
V
V
3.3
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance
is indicated in the electrical tables under conditions different than those tested
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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5V Electrical Characteristics(1) (continued)
The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL = 100Ω (200Ω external || 200Ω
internal), VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(3)
(2)
Maximum Differential Output
Voltage Swing
VCC = 5V, Output Common Mode = 5V
5.5
VPP
VOS
Output Offset Voltage
All Gain Settings
Maximum Gain
Maximum Gain
−21
81
mV
dB
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
63
61
81
dB
Gain Parameters
Maximum Gain
DC, Internal RL = 186Ω,
External RL = 1280Ω
29.3
28.7
30
30.3
30.9
dB
Minimum Gain
DC, Internal RL = 186Ω,
External RL = 1280Ω
−12.75
−13.15
−12
−11.85
−11.45
dB
dB
Gain Step Size
Gain Step Error
DC
6.02
0.02
0.07
0.02
DC
dB
f = 150 MHz
Cumulative Gain Step Error
Gain Step Switching Time
DC, Gain Step 7 to Gain Step 0
−0.35
−0.50
0.30
0.45
dB
ns
5
Digital Inputs/Timing
Logic Compatibility
CMOS Logic
3.3
V
V
VIL
Logic Input Low Voltage
Logic Input High Voltage
Logic Input High Input Current(4)
Setup Time
0.8
40
VIH
2.0
V
IIH
Digital Input Voltage = 3.3V
33
3
μA
ns
ns
ns
TSU
THOLD
TPW
Hold Time
3
Minimum Latch Pulse Width
10
Power Requirements
ICC Total Supply Current
VOUT = 0V Differential, VOUT Common
Mode = 5V
107
56
124
134
mA
mA
mA
Amplifier Supply Current
Pin 3 Only
66
74
Output Stage Bias Currents
Pins 13, 14 and Pins 15, 16;
VOUT Common Mode = 5 V
51
58
60
(4) Negative input current implies current flowing out of the device.
4
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Connection Diagram
5
6
7
8
16
15
14
13
LOAD-
OUT-
GND
IN+
OUT+
LOAD+
IN-
GND
GND
Figure 1. 16-Pin WQFN (Top View)
Gain Control Pins
Pin Number
Pin Name
GAIN_0
GAIN_1
GAIN_2
Gain Step Size
6.02 dB
11
10
9
12.04 dB
24.08 dB
spacer
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PIN DESCRIPTIONS
Pin Number
Analog I/O
6
Symbol
Description
IN+
Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or
go below GND by more than 0.5V.
7
IN−
Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or go
below GND by more than 0.5V. If using amplifier single ended this input should be capacitively
coupled to ground.
15
14
16
13
OUT−
Open collector inverting output. This pin is an output that also requires a power source. This
pin should be connected to 5V through either an RF choke or an appropriately sized inductor
that can form part of a filter. See Application Information for details.
OUT+
Open collector non-inverting output. This pin is an output that also requires a power source.
This pin should be connected to 5V through either an RF choke or an appropriately sized
inductor that can form part of a filter. See Application Information for details.
LOAD−
LOAD+
Internal 200Ω resistor connection to pin 15. This pin can be left floating for higher gain or
shorted to pin 13 for lower gain and lower effective output impedance. See Application
Information for details.
Internal 200Ω resistor connection to pin 14. This pin can be left floating for higher gain or
shorted to pin 16 for lower gain and lower effective output impedance. See Application
Information for details.
Power
3
VCC
5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers everything
except the output stage.
5,8
GND
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is also a ground connection.
Digital Inputs
11,10,9
GAIN_0 to
GAIN_2
Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V CMOS
logic compatible. 5V inputs may cause damage.
2
LATCH
This pin controls the function of the gain setting pins mentioned above. With LATCH in the
logic HIGH state the gain is fixed and will not change. With the LATCH in the logic LOW state
the gain is set by the state of the gain control pins. Any changes in gain made with the LATCH
pin in the LOW state will take effect immediately. This pin is 3.3V CMOS logic compatible. 5V
inputs may cause damage.
1,4,12
NC
These pins are not connected. They can be grounded or left floating.
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Typical Performance Characteristics
VCC = 5V
Frequency Response All Gain Settings
26
Frequency Response over Temperature, Maximum Gain
26
23
20
17
14
25
11
8
5
-40°C
24
2
-1
-4
25°C
23
-7
85°C
-10
-13
-16
-19
-22
22
P
= -16 dBm
IN
R
L
= 100W
R
= 100W
L
21
1
10
100
1000
100
1000
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 2.
Figure 3.
Frequency Response over Temperature, Minimum Gain
OIP3 High Gain Mode
40
38
36
34
32
30
28
26
24
22
20
-16
f = 75 MHz
f = 150 MHz
f = 250 MHz
-17
-40°C
-18
25°C
INPUT CLIPPING
-19
85°C
-20
V
= 2 V
OUT
PP
P
= 10 dBm
IN
R
= 200W
L
R
L
= 100W
-21
0
1
2
3
4
5
6
7
100
1000
10
GAIN STEP (0 = MAXIMUM GAIN)
FREQUENCY (MHz)
Figure 4.
Figure 5.
OIP3 Low Gain Mode
OIP3 Over Temperature
40
38
36
34
32
30
28
26
24
22
20
45
40
35
30
25
20
f = 75 MHz
f = 150 MHz
75 MHz
150 MHz
250 MHz
f = 250 MHz
INPUT CLIPPING
V
= 2 V
OUT
PP
R
= 200W
R
= 100W
L
L
0
1
2
3
4
5
6
7
-40
-20
0
20
40
60
80
GAIN STEP (0 = MAXIMUM GAIN)
TEMPERATURE (°C)
Figure 6.
Figure 7.
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Typical Performance Characteristics
VCC = 5V (continued)
IMD3 Low Gain Mode
IMD3 High Gain Mode
-40
-45
-50
-55
-60
-65
-70
-55
-60
-65
-70
-75
-80
-85
V
= 2 V
PP
V
= 2 V
PP
OUT
OUT
INPUT CLIPPING
R
= 200W
R
= 100W
L
L
INPUT CLIPPING
f = 250 MHz
f = 250 MHz
f = 150 MHz
f = 75 MHz
f = 150 MHz
f = 75 MHz
0
1
2
3
4
5
6
1
2
3
4
5
6
7
0
7
GAIN STEP (0 = MAXIMUM GAIN)
GAIN STEP (0 = MAXIMUM GAIN)
Figure 8.
Figure 9.
HD2
vs.
Frequency
HD3
vs.
Frequency
-30
-30
-40
R
L
= 100W
R
L
= 100W
-40
-50
2.8 V
PP
2.8 V
PP
-50
-60
-70
2 V
PP
-60
-70
2 V
PP
1 V
PP
-80
1 V
PP
-80
-90
-90
-100
0
50 100 150 200 250 300 350 400
0
50 100 150 200 250 300 350 400
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10.
Figure 11.
HD2
vs.
Frequency
HD3
vs.
Frequency
-30
-40
-50
-60
-70
-80
-90
-30
R
= 200W
L
R
= 200W
L
-40
-50
2.8 V
PP
-60
2 V
PP
2.8 V
PP
-70
-80
2 V
PP
1 V
PP
-90
-100
-110
1 V
PP
200
50
100
150
250
300
0
50
100
200
250 300
0
150
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12.
Figure 13.
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Typical Performance Characteristics
VCC = 5V (continued)
Noise Figure for All Gain Settings
Noise Figure vs. Frequency
MAXIMUM GAIN
55
50
45
40
35
30
25
20
15
10
5
13
12
f = 150 MHz
11
10
9
f = 75 MHz
8
0
1
2
3
4
5
6
7
0
100
200
300
400
GAIN SETTING (0 = MAXIMUM GAIN)
FREQUENCY (MHz)
Figure 14.
Figure 15.
Differential Output Noise
Maximum Gain vs. Supply Voltage
26
60
50
40
30
20
10
0
R
P
= 100W
f = 75 MHz
L
= -25 dBm
IN
R
= 133W
25.5
L
f = 75 MHz
25
24.5
24
R
L
= 100W
f = 150 MHz
f = 250 MHz
3.5
4
4.5
5
5.5
0
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
GAIN SETTING (0 = MAXIMUM GAIN)
Figure 16.
Figure 17.
Gain vs. External Load
Maximum Gain over Temperature
42
26
400W INTERNAL WITH 400W
EXTERNAL = 32 dB NET
38
34
30
26
22
18
25.5
25
f = 75 MHz
INTERNAL LOAD
= 400W
f = 150 MHz
24.5
24
INTERNAL LOAD =
200W
f = 250 MHz
200W INTERNAL WITH 200W
EXTERNAL = 26 dB NET
23.5
23
V
= 2 V
OUT
PP
R
= 100W
L
10
100
1k
10k
100k
-40
-20
0
20
40
60
80
EXTERNAL DIFFERENTIAL LOAD (W)
TEMPERATURE (°C)
Figure 18.
Figure 19.
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Typical Performance Characteristics
VCC = 5V (continued)
Worst Case Gain Step Error
vs
Frequency
Gain Steps over Temperature
6.25
6.20
6.15
6.45
6.40
6.35
6.30
6.25
6.20
6.15
6.10
6.05
6.00
5.95
f = 150 MHz
V
= 1 V
OUT
PP
V
= 2 V
OUT
PP
R
= 100W
L
R
= 100W
85°C
L
f = 250 MHz
f = 150 MHz
f = 75 MHz
6.10
6.05
6.00
25°C
-40°C
5.95
5.90
IDEAL
5
1
2
3
5
6
7
4
1
2
3
4
6
7
HIGH
GAIN
LOW
GAIN
GAIN STEP (0 = MAXIMUM GAIN)
GAIN STEP
Figure 20.
Figure 21.
Worst Case Gain Step Error over Temperature
0.4
Input Impedance (S11) at Maximum Gain
350
R
= 100W
L
0.35
0.3
300
250
200
150
100
50
|Z|
0.25
0.2
85°C
R
0.15
0.1
25°C
jX
-40°C
0.05
0
0
-50
0
50
100
200
250 300
150
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22.
Figure 23.
Input Impedance (S11) at Minimum Gain
350
Output Impedance (S22) at Maximum Gain Low Gain Mode
350
300
250
200
150
100
50
300
|Z|
250
|Z|
200
150
R
R
100
jX
50
jX
0
0
-50
-50
50 100 150 200 250 300 350 400 450
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24.
Figure 25.
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Typical Performance Characteristics
VCC = 5V (continued)
Output Impedance (S22) at
Maximum Gain High Gain Mode
Digital Crosstalk
LATCH = 0
40
350
300
250
200
150
100
50
30
20
|Z|
10
0
-10
-20
-30
-40
R
3
0
jX
0
PINS 9, 10, 11,12
-50
0
10 20 30 40 50 60 70 80 90 100
50 100 150 200 250 300 350 400 450
TIME (ns)
FREQUENCY (MHz)
Figure 26.
Figure 27.
Digital Crosstalk
Digital Pin to Output Isolation
40
30
-30
P
= -10 dBm
IN
LATCH = 3.3V
LOAD = 200W
MAX GAIN
-40
-50
20
10
LATCH
0
-60
-70
-80
-90
-10
-20
-30
-40
3
GAIN 1
PINS 9, 10, 11,12
0
0
10 20 30 40 50 60 70 80 90 100
1
10
100
1000
TIME (ns)
FREQUENCY (MHz)
Figure 28.
Figure 29.
Minimum Gain to Maximum Gain Switching
Using Latch Pin
Maximum Gain to Minimum Gain Switching
Using Latch Pin
4
4
R
L
= 100W
R = 100W
L
3
2
1
0
3
2
1
0
LATCH PIN
LATCH PIN
1.5
1
1.5
1
0.5
0
0.5
0
V
OUT
V
OUT
-0.5
-0.5
-1
-1
-1.5
-1.5
0
10
20
30
40
0
10
20
30
40
TIME (ns)
TIME (ns)
Figure 30.
Figure 31.
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Typical Performance Characteristics
VCC = 5V (continued)
24 dB Gain Step
24 dB Gain Step
4
3
2
4
3
2
1
0
GAIN BIT 2
GAIN BIT 2
1
0
1.5
1
1.5
1
0.5
0
0.5
0
V
V
OUT
OUT
-0.5
-0.5
-1
-1
-1.5
-1.5
0
0
0
10
20
30
40
0
0
0
10
20
30
40
TIME (ns)
TIME (ns)
Figure 32.
Figure 33.
12 dB Gain Step
12 dB Gain Step
4
4
3
2
1
0
3
2
1
0
GAIN BIT 1
GAIN BIT 1
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
V
V
OUT
OUT
-1
-1
-1.5
-1.5
10
20
30
40
10
20
30
40
TIME (ns)
TIME (ns)
Figure 34.
Figure 35.
6 dB Gain Step
6 dB Gain Step
4
4
3
2
1
0
3
2
1
0
GAIN BIT 0
GAIN BIT 0
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-1
-1
V
V
OUT
OUT
-1.5
-1.5
10
20
30
40
10
20
30
40
TIME (ns)
TIME (ns)
Figure 36.
Figure 37.
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Typical Performance Characteristics
VCC = 5V (continued)
Power On Timing, Maximum Gain
Power On Timing, Minimum Gain
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
+
+
V
V
V
V
OUT
OUT
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
f = 250 MHz
ENVELOPE DISPLAYED
f = 250 MHz
ENVELOPE DISPLAYED
-10 -5
0
5
10 15 20 25 30
TIME (ms)
Figure 38.
-10 -5
0
5
10 15 20 25 30
TIME (ms)
Figure 39.
Power Off Timing, Maximum Gain
Power Off Timing, Minimum Gain
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
f = 250 MHz
ENVELOPE DISPLAYED
f = 250 MHz
ENVELOPE DISPLAYED
V
V
OUT
OUT
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
+
V
+
V
-10 -5
0
5
10 15 20 25 30
TIME (ms)
Figure 40.
-10 -5
0
5
10 15 20 25 30
TIME (ms)
Figure 41.
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APPLICATION INFORMATION
The LMH6514 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6514
has a 200Ω input. The absolute gain is load dependent, however the gain steps are always 6 dB. The LMH6514
output stage is a class A amplifier. This class A operation results in excellent distortion and linearity
characteristics. This makes the LMH6514 ideal for voltage amplification and an ideal ADC driver where high
linearity is necessary.
V
CC
V
CC
44.3 nH
LMH6514
V
CM
= V
CC
ADC
10 pF
3
GAIN
LATCH
Figure 42. LMH6514 Typical Application
The LMH6514 output common mode should be set carefully. Using inductors to set the output common mode is
one preferred method and will give maximum output swing. AC coupling of the output is recommended. The
inductors mentioned above will shift the idling output common mode to the positive supply. Also, with the
inductors, the output voltage can exceed the supply voltage. Other options for setting the output common mode
require supply voltages above 5V. If using a supply higher than 5V care should be taken to make sure the output
common mode does not exceed the 5.25V supply rating.
It is also important to note the maximum voltage limits for the OUT+ and OUT− pins, which is 6.4V. When using
inductors these pins will experience voltage swings beyond the supply voltage. With a 5V output common mode
operating point this makes the effective maximum swing 5.6 VPP differential. System calibration and automatic
gain control algorithms should be tailored to avoid exceeding this limit. Figure 43 shows how output voltage and
output common mode add together and approach the maximum output voltage.
7
MAXIMUM OUTPUT VOLTAGE = 6.4V
OUT +
6
1.4 V
P
5
COMMON MODE
= 5V
4
3
2
OUT -
V
= 5.6 V DIFFERENTIAL
PP
OUT
0
1
2
3
4
5
6
PHASE (RADIANS)
Figure 43. Output Voltage with Respect to the Output Common Mode
In order to help with system design Texas Instruments offers the ADC14V155KDRB High IF Receiver reference
design board. This board combines the LMH6514 DVGA with the ADC14V155 ADC and provides a ready made
solution for many IF receiver applications. Using an IF frequency of 169 MHz it achieves a small signal SNR of
72 dBFS and an SFDR of greater than 90 dBFS. Large signal measurements show an SNR of 68 dBFS and an
SFDR of 77 dBFS. The High IF Receiver board also features the LMK03000 low-jitter precision clock conditioner.
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16
15
13
OUT-
200W
200W
OUT+
0 to -42 dB
14
+38 dB
+IN
-IN
6
400W
+
-
6dB STEP
VARIABLE
ATTENUATOR
200W
7
5, 8
Figure 44. LMH6514 Block Diagram
INPUT CHARACTERISTICS
The LMH6514 input impedance is set by internal resistors to a nominal 200Ω. Process variations will result in a
range of values as shown in the Electrical Characteristics table. At higher frequencies parasitics will start to
impact the impedance. This characteristic will also depend on board layout and should be verified on the
customer’s system board.
At maximum gain the digital attenuator is set to 0 dB and the input signal will be much smaller than the output. At
minimum gain the output is 4 dB or more smaller than the input. In this configuration the input signal size may
limit the amplifier output amplitude, depending on the output configuration and the desired output signal voltage.
The input signal cannot swing more than 0.5V below the negative supply voltage (normally 0V) nor should it
exceed the positive supply voltage. The input signal will clip and cause severe distortion if it is too large. Because
the input stage self biases to approximately 1.4V the lower supply voltage will impose the limit for input voltage
swing. To drive larger input signals the input common mode can be forced higher than 1.4V to allow for more
swing. An input common mode of 2.0V will allow an 8 VPP maximum input signal. The trade off for input signal
swing is that as the input common mode is shifted away from the 1.4V internal bias point the distortion
performance will suffer slightly.
5V
INTERNAL BIAS = 1.4V
LMH6514
C
1
Vin
= R || 200
R
1
R
IN
1
C
2
3
GAIN
LATCH
Figure 45. Single Ended Input
(Note capacitor on grounded input)
At the frequencies where the LMH6514 is the most useful the input impedance is not 200 Ω and it may not be
purely resistive. For many AC coupled applications the impedance can be easily changed using LC circuits to
transform the actual impedance to the desired impedance.
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SOURCE IMPEDANCE = 50W
f = 100 MHz
5V
C
3
LMH6514
C
1
V
Z
IN
L
1
C
2
IN
5
C
= 22 pF
3
L
1
= 169 nH
GAIN 1-5
LATCH
C
1
2
= 1 nF
= 1 nF
C
Z
= (150 œ j0)W
= (50 œ j1)W
AMP
Z
IN
Figure 46. Single Ended Input with LC Matching
As shown in Figure 46 a single ended 50Ω source is matched to the LMH6514 input at 100 MHz. The loss in this
circuit is related to the parasitic resistance in the inductor and capacitor and the bandwidth is related to the
loaded Q of the circuit. Since the Q, at 1.4 is quite low, the bandwidth is very wide. (59 MHz 0.3 dB bandwidth).
The input match of this circuit is quite good. It converts the ZAMP of the amplifier, which is (150 +j0)Ω to (50+j1)Ω.
The benefit of LC matching circuits over a transformer is the ability to match ratios that are not commonly found
on transformers and also the ability to neutralize reactance to present a purely resistive load to the voltage
source.
SOURCE IMPEDANCE = 200W
f = 100 MHz
5V
LMH6514
C
1
V
IN
L
1
C
2
Z
IN
L
1
= 550 nH
5
C
C
= 36 pF
= 36 pF
1
2
GAIN 1-5
LATCH
Z
= (150 œ j0)W
AMP
Z
= (202 œ j0.5)W
IN
Figure 47. Differential 200Ω LC Conversion Circuit
In Figure 47 the input source resistance is 200Ω differential. Here the desired input impedance is higher than the
amplifier input impedance, and is differential as well. The amplifier impedance of (150–j0)Ω is increased to
(202–j0.5)Ω. For an easy way to calculate the L and C circuit values there are several options for online tools or
down-loadable programs. The following tool might be helpful.
http://www.circuitsage.com/matching/matcher2.html
Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate
complex numbers.
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OUTPUT CHARACTERISTICS
The LMH6514 has the option of two different output configurations. The LMH6514 is an open collector topology.
As shown in Figure 52 each output has an on chip 200Ω pull up resistor. In addition there is an internal 400Ω
resistor between the two outputs. This results in a 200Ω or a 400Ω differential load in parallel with the external
load. The 400Ω option is the high gain option and the 200Ω provides for less gain. The 200Ω configuration is
recommended unless more gain is required.
The output common mode of the LMH6514 must be set by external components. Most applications will benefit
from the use of inductors on the output stage. In particular, the 400Ω option as shown in Figure 53 will require
inductors in order to be able to develop an output voltage. The 200Ω option as shown in Figure 54 or Figure 55
will also require inductors since the voltage drop due to the on chip 200Ω resistors will saturate the output
transistors. It is also possible to use resistors and high voltage power supplies to set the output common mode.
This operation is not recommended, unless it is necessary to DC couple the output. If DC coupling is required the
input common mode and output common mode voltages must be taken into account.
Maximum bandwidth with the LMH6514 is achieved by using the low gain, low impedance output option and
using a low load resistance. With an effective load of 67Ω a bandwidth of nearly a 1 GHz can be realized. As the
effective resistance on the output stage goes up the capacitance of the board traces and amplifier output stage
limit bandwidth in a roughly linear fashion. At an output impedance of 100Ω the bandwidth is down to 600 MHz,
and at 200Ω the bandwidth is 260 MHz. For this reason driving very high impedance loads is not recommended.
Although bandwidth goes down with higher values of load resistance, the distortion performance improves and
gain increases. The LMH6514 has a common emitter Class A output stage and minimizing the amount of current
swing in the output devices improves distortion substantially.
The LMH6514 output stage is powered through the collectors of the output transistors. Power for the output
stage is fed through inductors and the reactance of the inductors allows the output voltage to develop. In
Figure 42 the inductors are shown with a value of 44.4 nH. The value of the inductors used will be different for
different applications. In Figure 42 the inductors have been chosen to resonate with the ADC and the load
capacitor to provide a weak band pass filter effect. For broad band applications higher value inductors will allow
for better low frequency operation. However, large valued inductors will reduce high frequency performance,
particularly inductors of small physical sizes like 0603 or smaller. Larger inductors will tend to perform better than
smaller ones of the same value even for narrow band applications. This is because the larger inductors will have
a lower DC resistance and less inter-winding capacitance and hence a higher Q and a higher self resonance
frequency. The self resonance frequency should be higher than any desired signal content by at least a factor of
2. Another consideration is that the power inductors and the filter inductors need to be placed on the circuit board
such that their magnetic fields do not cause coupling. Mutual coupling of inductors can compromise filter
characteristics and lead to unwanted distortion products.
1
0
1 mH
-1
-2
-3
470 nH
-4
-5
200 nH
-6
-7
-8
R
= 100W TOTAL
L
-9
1
10
100
1000
FREQUENCY (MHz)
Figure 48. Bandwidth Changes Due to Different Inductor Values
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26
25.5
25
f = 75 MHz
f = 150 MHz
24.5
24
f = 250 MHz
23.5
23
V
= 2 V
OUT
PP
R
= 100W
L
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
Figure 49. Gain vs. External Load
DIGITAL CONTROL
The LMH6514 has eight gain settings covering a range of 42 dB. To avoid undesirable signal transients the
LMH6514 should be powered on at the minimum gain state (all logic input pins at 0V). The LMH6514 has a 3-bit
gain control bus as well as a Latch pin. When the Latch pin is low, data from the gain control pins is immediately
sent to the gain circuit (i.e. gain is changed immediately). When the Latch pin transitions high the current gain
state is held and subsequent changes to the gain set pins are ignored. To minimize gain change glitches multiple
gain control pins should not change while the latch pin is low. In order to achieve the very fast gain step
switching time of 5 ns the internal gain change circuit is very fast. Gain glitches could result from timing skew
between the gain set bits. This is especially the case when a small gain change requires a change in state of
three or more gain control pins. If continuous gain control is desired the Latch pin can be tied to ground. This
state is called transparent mode and the gain pins are always active. In this state the timing of the gain pin logic
transitions should be planned carefully to avoid undesirable transients.
The LMH6514 was designed to interface with 3.3V CMOS logic circuits. If operation with 5V logic is required a
simple voltage divider at each logic pin will allow for this. To properly terminate 100Ω transmission lines a divider
with a 66.5Ω resistor to ground and a 33.2Ω series resistor will properly terminate the line as well as give the
3.3V logic levels. Care should be taken not to exceed the 3.6V absolute maximum voltage rating of the logic
pins.
EXPOSED PAD WQFN PACKAGE
The LMH6514 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It
is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any
case, the thermal dissipation of the device is largely dependent on the attachment of this pad. The exposed pad
should be attached to as much copper on the circuit board as possible, preferably external copper. However, it is
also very important to maintain good high speed layout practices when designing a system board. Please refer to
the LMH6514 evaluation board for suggested layout techniques.
Package information is available on the TI web site.
http://www.ti.com/packaging
INTERFACING TO ADC
The LMH6514 was designed to be used with high speed ADCs such as the ADC14155. As shown in the Typical
Application on page 1, AC coupling provides the best flexibility especially for IF sub-sampling applications. Any
resistive networks on the output will also cause a gain loss because the output signal is developed across the
output resistors. The chart Maximum Gain vs. External Load shows the change in gain when an external load is
added.
The inputs of the LMH6514 will self bias to the optimum voltage for normal operation. The internal bias voltage
for the inputs is approximately 1.4V. In most applications the LMH6514 input will need to be AC coupled.
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The output common mode voltage is not self biasing, it needs to be pulled up to the positive supply rail with
external inductors as shown in Figure 42. This gives the LMH6514 the capability for large signal swings with very
low distortion on a single 5V supply. The internal load resistors provide the LMH6514 with very consistent gain.
A unique internal architecture allows the LMH6514 to be driven by either a differential or single ended source. If
driving the LMH6514 single ended the unused input should be terminated to ground with a 0.01 µF capacitor.
Directly shorting the unused input to ground will disrupt the internal bias circuitry and will result in poor
performance.
5V
680 nH
3 pF
390 nH
ADC C
27 nH
200W
41 pF
IN
390 nH
200
3 pF
680 nH
5V
Center Frequency is 140 MHz with a 20 MHz Bandwidth
Designed for 200Ω Impedance
Figure 50. Bandpass Filter
ADC Noise Filter
Below is a filter schematic and a table of values for some common IF frequencies. The filter shown below offers
a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on
the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12 and
14 bit sub-sampling analog to digital converters shown in the Table 2 table.
Table 1. Filter Component Values
Filter Component Values
Fc
75 MHz
40 MHz
10 µH
390 nH
10 pF
140 MHz
20 MHz
10 µH
39 0nH
3 pF
170 MHz
25 MHz
10 µH
560 nH
1.4 pF
32 pF
250 MHz
Narrow Band
10 µH
—
BW
Components
L1, L2
L3, L4
C1, C2
C3
47 pF
22 pF
41 pF
27 nH
200
11 pF
L5
220 nH
100
30 nH
100
22 nH
499
R1, R2
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5V
L1
C1
L3
L5
AMP V
OUT
-
ADC V
+
IN
C2
L4
ADC V
-
IN
AMP V
OUT
+
L2
ADC V
CM
5V
Figure 51. Sample Filter
POWER SUPPLIES
As shown in Figure 52, the LMH6514 has a number of options for power supply connections on the output pins.
Pin 3 (VCC) is always connected. The output stage can be connected as shown in Figure 53, Figure 54, and
Figure 55. The supply voltage range for VCC is 4V to 5.25V. A 5V supply provides the best performance while
lower supplies will result in less power consumption. Power supply regulation of 2.5% or better is advised.
Of special note is that the digital circuits are powered from an internal supply voltage of 3.3V. The logic pins
should not be driven above the absolute maximum value of 3.6V. See the DIGITAL CONTROL section for
details.
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5V
LOAD-
NC
5
6
7
8
16
15
14
5
6
7
8
16
15
14
13
GND
IN+
IN-
GND
IN+
IN-
-
OUT-
OUT+
OUT-
V
OUT
OUT+
+
13 LOAD+
NC
GND
GND
5V
Figure 52. Internal Load Resistors
Figure 53. Using High Gain Mode (400Ω Load)
5V
5V
5
6
7
8
16
15
14
13
5
6
7
8
16
15
14
13
GND
GND
IN+
IN-
-
-
OUT-
OUT-
IN+
IN-
V
V
OUT
OUT
OUT+
OUT+
+
+
GND
GND
5V
5V
Figure 54. Using Low Gain Mode (200Ω Load)
Figure 55. Alternate Connection for Low Gain
Mode (200Ω Load)
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Table 2. Compatible High Speed Analog to Digital Converters
Product Number
ADC12L063
Max Sampling Rate (MSPS)
62
Resolution
Channels
12
12
12
12
12
12
12
12
12
12
12
14
14
14
14
14
8
SINGLE
DUAL
ADC12DL065
ADC12L066
ADC12DL066
CLC5957
65
66
SINGLE
DUAL
66
70
SINGLE
SINGLE
DUAL
ADC12L080
ADC12DL080
ADC12C080
ADC12C105
ADC12C170
ADC12V170
ADC14C080
ADC14C105
ADC14DS105
ADC14155
80
80
80
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
105
170
170
80
105
105
155
155
500
500
1000
1000
1500
1500
3000
60
SINGLE
SINGLE
DUAL
ADC14V155
ADC08D500
ADC08500
8
SINGLE
DUAL
ADC08D1000
ADC081000
ADC08D1500
ADC081500
ADC08(B)3000
ADC08L060
ADC08060
8
8
SINGLE
DUAL
8
8
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
8
8
60
8
ADC10DL065
ADC10065
65
10
10
10
8
65
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
ADC10080
80
ADC08100
100
170
200
125
170
ADCS9888
8
ADC08(B)200
ADC11C125
ADC11C170
8
11
11
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REVISION HISTORY
Changes from Original (March 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6514SQ/NOPB
LMH6514SQE/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RGH
RGH
16
16
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
L6514SQ
L6514SQ
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6514SQ/NOPB
LMH6514SQE/NOPB
WQFN
WQFN
RGH
RGH
16
16
1000
250
178.0
178.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6514SQ/NOPB
LMH6514SQE/NOPB
WQFN
WQFN
RGH
RGH
16
16
1000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGH0016A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
0.5
0.3
PIN 1 INDEX AREA
0.3
0.2
4.1
3.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIM A
OPT 1 OPT 1
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2.6 0.1
(A) TYP
5
8
SEE TERMINAL
DETAIL
EXPOSED
THERMAL PAD
12X 0.5
4
9
17
SYMM
4X
1.5
1
12
0.3
16X
0.2
0.1
C A B
0.05
16
13
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
16X
4214978/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGH0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
16
13
16X (0.6)
(R0.05)
TYP
1
12
16X (0.25)
SYMM
(3.8)
17
(1)
9
4
12X (0.5)
(
0.2) TYP
VIA
5
8
(1)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214978/B 01/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGH0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
16
(0.675) TYP
13
17
16X (0.6)
1
(0.675)
TYP
12
16X (0.25)
SYMM
(3.8)
12X (0.5)
9
4
EXPOSED METAL
TYP
5
8
(R0.05)
TYP
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214978/B 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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