LMH6559MA [TI]
1750MHz 高速闭环缓冲器 | D | 8 | -40 to 85;
| 型号： | LMH6559MA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1750MHz 高速闭环缓冲器 | D | 8 | -40 to 85 放大器 光电二极管 |
| 文件： | 总40页 (文件大小：1699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6559
www.ti.com
SNOSA57C –APRIL 2003–REVISED MARCH 2013
LMH6559 High-Speed, Closed-Loop Buffer
Check for Samples: LMH6559
1
FEATURES
DESCRIPTION
The LMH6559 is a high-speed, closed-loop buffer
designed for applications requiring the processing of
very high frequency signals. While offering a small
signal bandwidth of 1750MHz, and an ultra high slew
rate of 4580V/μs the LMH6559 consumes only 10mA
of quiescent current. Total harmonic distortion into a
load of 100Ω at 20MHz is −52dBc. The LMH6559 is
configured internally for a loop gain of one. Input
resistance is 200kΩ and output resistance is but
1.2Ω. These characteristics make the LMH6559 an
ideal choice for the distribution of high frequency
signals on printed circuit boards. Differential gain and
phase specifications of 0.06% and 0.02° respectively
at 3.58MHz make the LMH6559 well suited for the
buffering of video signals.
2
•
•
•
•
•
•
•
Closed-Loop Buffer
1750MHz Small Signal Bandwidth
4580V/μs Slew Rate
0.06% / 0.02° Differential Gain/Phase
−52dBc THD at 20MHz
Single Supply Operation (3V Min.)
75mA Output Current
APPLICATIONS
•
•
•
•
•
•
•
•
Video Switching and Routing
Test Point Drivers
High Frequency Active Filters
Wideband DC Clamping Buffers
High-Speed Peak Detector Circuits
Transmission Systems
The device is fabricated on Texas Instruments' high-
speed VIP10 process using TI's proven high
performance circuit architectures.
Telecommunications
Test Equipment and Instrumentation
Typical Schematic
V
CC
10nF
10kW
1
100nF
100nF
50W
4
8
LMH6559
5
50W
10kW
Figure 1.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6559
SNOSA57C –APRIL 2003–REVISED MARCH 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3)
Human Body Model
Machine Model
2000V
200V
(6)
Output Short Circuit Duration
Supply Voltage (V+ – V−)
Voltage at Input/Output Pins
Soldering Information
See(4) (5)
, and
13V
V+ +0.8V, V− −0.8V
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
235°C
260°C
Storage Temperature Range
Junction Temperature
−65°C to +150°C
+150°C
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) Short circuit test is a momentary test.
(6) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Supply Voltage (V+ - V−)
Temperature Range(2)(3)
Package Thermal Resistance(2)(3)
3 - 10V
−40°C to +85°C
172°C/W
8-Pin SOIC
5-Pin SOT-23
235°C/W
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PC board.
(3) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. There is no specification of parametric performance as indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. See Applications section for information on temperature de-rating of this
device.
2
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = +5V, V− = −5V, VO = VCM = 0V and RL = 100Ω to 0V.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(1)
(2)
(1)
Frequency Domain Response
SSBW
GFN
Small Signal Bandwidth
Gain Flatness < 0.1dB
Full Power Bandwidth (−3dB)
Differential Gain
VO < 0.5VPP
VO < 0.5VPP
1750
200
MHz
MHz
MHZ
%
FPBW
DG
VO = 2VPP (+10dBm)
1050
0.06
RL = 150Ω to 0V,
f = 3.58 MHz
DP
Differential Phase
RL = 150Ω to 0V,
0.02
deg
f = 3.58 MHz
Time Domain Response
tr
Rise Time
3.3V Step (20-80%)
0.4
0.5
9
ns
ns
tf
Fall Time
ts
Settling Time to ±0.1%
Overshoot
3.3V Step
1V Step
See(3)
ns
OS
SR
4
%
Slew Rate
4580
V/µs
Distortion And Noise Performance
HD2
HD3
THD
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input-Referred Voltage Noise
1dB Compression point
Signal to Noise Ratio
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
f = 1MHz
−58
−53
−52
5.7
dBc
dBc
dBc
nV/√Hz
dBm
dB
CP
f = 10MHz
+23
89
SNR
f > 100kHz, BW = 5MHz,
VO = 350mVrms
(1) All limits are specified by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Slew rate is the average of the positive and negative slew rate.
Copyright © 2003–2013, Texas Instruments Incorporated
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = +5V, V− = −5V, VO = VCM = 0V and RL = 100Ω to 0V.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(1)
(2)
(1)
Static, DC Performance
ACL
Small Signal Voltage Gain
VO = 100mVPP
RL = 100Ω to 0V
.97
.99
.996
.998
3
V/V
VO = 100mVPP
RL = 2kΩ to 0V
VOS
Input Offset Voltage
20
25
mV
μV/°C
μA
TC VOS
IB
Temperature Coefficient Input Offset See(4)
Voltage
23
Input Bias Current
See(5)
−10
−14
−3
TC IB
ROUT
Temperature Coefficient Input Bias
Current
See(4)
−3.6
nA/°C
Output Resistance
RL = 100Ω to 0V, f = 100kHz
RL = 100Ω to 0V, f = 10MHz
VS = ±5V to VS = ±5.25V
1.2
1.3
63
Ω
PSRR
IS
Power Supply Rejection Ratio
Supply Current
48
44
dB
No Load
10
14
mA
17
Miscellaneous Performance
RIN
CIN
VO
Input Resistance
200
1.7
kΩ
Input Capacitance
Output Swing Positive
pF
RL = 100Ω to 0V
RL = 2kΩ to 0V
RL = 100Ω to 0V
RL = 2kΩ to 0V
3.20
3.18
3.45
V
3.55
3.54
3.65
−3.45
−3.65
Output Swing Negative
−3.20
−3.18
V
−3.55
−3.54
ISC
Output Short Circuit Current
Linear Output Current
Sourcing: VIN = +VS, VO = 0V
Sinking: VIN = −VS, VO = 0V
Sourcing: VIN - VO = 0.5V(5)
−83
83
mA
mA
IO
−50
−43
−74
Sinking: VIN - VO = −0.5V(5)
50
74
43
(4) Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature
change.
(5) Positive current corresponds to current flowing into the device.
4
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(1)
(2)
(1)
Frequency Domain Response
SSBW
GFN
Small Signal Bandwidth
Gain Flatness < 0.1dB
Full Power Bandwidth (−3dB)
Differential Gain
VO < 0.5VPP
VO < 0.5VPP
745
90
MHz
MHz
MHZ
%
FPBW
DG
VO = 2VPP (+10dBm)
RL = 150Ω to V+/2,
485
0.29
f = 3.58 MHz
DP
Differential Phase
RL = 150Ω to V+/2,
0.06
deg
f = 3.58 MHz
Time Domain Response
tr
Rise Time
2.3VPP Step (20-80%)
0.6
0.9
9.6
3
ns
ns
tf
Fall Time
ts
Settling Time to ±0.1%
Overshoot
2.3V Step
1V Step
See(3)
ns
OS
SR
%
Slew Rate
2070
V/µs
Distortion And Noise Performance
HD2
HD3
THD
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input-Referred Voltage Noise
1dB Compression point
Signal to Noise Ratio
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
f = 1MHz
−53
−56
−52
4.0
+7
dBc
dBc
dBc
nV/√Hz
dBm
dB
CP
f = 10MHz
SNR
f > 100kHz, BW = 5MHz,
VO = 350mVrms
92
Static, DC Performance
ACL
Small Signal Voltage Gain
VO = 100mVPP
.97
.99
.996
.998
1.52
23
RL = 100Ω to V+/2
V/V
VO = 100mVPP
RL = 2kΩ to V+/2
VOS
Input Offset Voltage
12
16
mV
μV/°C
μA
TC VOS
IB
Temperature Coefficient Input Offset See(4)
Voltage
Input Bias Current
See(5)
−5
−8
−2.7
1.6
TC IB
ROUT
Temperature Coefficient Input Bias
Current
See(4)
nA/°C
Output Resistance
RL = 100Ω to V+/2, f = 100kHz
RL = 100Ω to V+/2, f = 10MHz
1.4
1.6
68
Ω
PSRR
IS
Power Supply Rejection Ratio
Supply Current
VS = +5V to VS = +5.5V,
VIN = VS/2
48
44
dB
No Load
4.7
7
mA
8.5
(1) All limits are specified by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Slew rate is the average of the positive and negative slew rate.
(4) Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature
change.
(5) Positive current corresponds to current flowing into the device.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(1)
(2)
(1)
Miscellaneous Performance
RIN
CIN
VO
Input Resistance
200
2.0
kΩ
Input Capacitance
Output Swing Positive
pF
RL = 100Ω to V+/2
3.80
3.88
3.75
V
RL = 2kΩ to V+/2
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
3.94
3.92
3.98
1.12
1.03
Output Swing Negative
1.20
1.25
V
1.06
1.09
ISC
Output short circuit Current
Linear Output Current
Sourcing: VIN = +VS, VO = V+/2
Sinking: VIN = −VS, VO = V+/2
Sourcing: VIN - VO = 0.5V(6)
−57
26
mA
mA
IO
−50
−43
−64
Sinking: VIN - VO = −0.5V(6)
30
42
23
(6) Positive current corresponds to current flowing into the device.
3V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Conditions
Units
(1)
(2)
(1)
Frequency Domain Response
SSBW
GFN
Small Signal Bandwidth
Gain Flatness < 0.1dB
VO < 0.5VPP
VO < 0.5VPP
315
44
MHz
MHz
MHZ
FPBW
Full Power Bandwidth (−3dB)
VO = 1VPP (+4.5dBm)
265
Time Domain Response
tr
Rise Time
1.0V Step (20-80%)
0.8
1.2
10
ns
ns
tf
Fall Time
ts
Settling Time to ±0.1%
Overshoot
1V Step
0.5V Step
See(3)
ns
OS
SR
0
%
Slew Rate
770
V/µs
Distortion And Noise Performance
HD2
HD3
THD
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input-Referred Voltage Noise
1dB Compression point
Signal to Noise Ratio
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
f = 1MHz
−74
−57
−56
3.9
+4
dBc
dBc
dBc
nV/Hz
dBm
dB
CP
f = 10MHz
SNR
f > 100kHz, BW = 5MHz,
VO = 350mVrms
92
(1) All limits are specified by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Slew rate is the average of the positive and negative slew rate.
6
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
3V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Conditions
Units
(1)
(2)
(1)
Static, DC Performance
ACL
Small Signal Voltage Gain
VO = 100mVPP
.97
.99
.995
.998
1
RL = 100Ω to V+/2
V/V
VO = 100mVPP
RL = 2kΩ to V+/2
VOS
Input Offset Voltage
7
9
mV
μV/°C
μA
TC VOS
IB
Temperature Coefficient Input Offset See(4)
Voltage
3.5
Input Bias Current
See(5)
−3
−3.5
−1.5
0.46
TC IB
ROUT
Temperature Coefficient Input Bias
Current
See(4)
nA/°C
Output Resistance
RL = 100Ω to V+/2, f = 100kHz
RL = 100Ω to V+/2, f = 10MHz
1.8
2.3
68
Ω
PSRR
IS
Power Supply Rejection Ratio
Supply Current
VS = +3V to VS = +3.5V,
VIN = V+/2
48
46
dB
No Load
2.4
3.5
mA
4.5
Miscellaneous Performance
RIN
CIN
VO
Input Resistance
200
2.3
kΩ
Input Capacitance
Output Swing Positive
pF
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
2.02
1.95
2.07
V
2.12
2.02
2.17
.930
.830
Output Swing Negative
.970
1.050
V
.880
.980
ISC
Output Short Circuit Current
Linear Output Current
Sourcing: VIN = +VS, VO = V+/2
Sinking: VIN = −VS, VO = V+/2
Sourcing: VIN - VO = 0.5V(5)
−32
15
mA
mA
IO
−20
−13
−28
Sinking: VIN - VO = −0.5V(5)
12
17
8
(4) Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature
change.
(5) Positive current corresponds to current flowing into the device.
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CONNECTION DIAGRAMS
1
8
V
CC
5
V
OUT
1
V
CC
V
OUT
2
7
6
5
NC
NC
2
V
EE
3
NC
NC
4
3
NC
4
V
IN
V
EE
V
IN
Figure 2. 8-Pin SOIC (Top View)
See Package Number D (R-PDSO-G8)
Figure 3. 5-Pin SOT-23 (Top View)
See Package Number DBV (R-PDSO_G5)
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
Typical Performance Charac teristics
At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified.
Frequency Response
= 100W
Frequency Response Over Temperature
3
0
3
0
R
L
V
S
= 10V
-40°C
-3
25°C
85°C
125°C
-3
-6
-9
V
= 5V
S
-6
-9
V
= 10V
S
V
= 3V
R
= 100W
L
S
-12
1M
10M
100M
1G 2G
100M
1G
FREQUENCY (Hz)
Figure 5.
2G 3G
FREQUENCY (Hz)
Figure 4.
Gain Flatness
Differential Gain and Phase
V = 10V
S
1.0
0.036
0.030
0.024
0.018
0.012
0.006
0.12
0.10
0.08
0.06
0.04
0.02
0
R
= 100W
L
R
L
=150W
f =3.58MHz
0.5
0.0
+0.1dB
-0.1dB
10V
GAIN
5V
3V
-0.5
0
-0.02
-0.04
-0.006
PHASE
-0.012
-1.0
-700 -525 -350 -175
0
175 350 525 700
1M
10M
100M
1G
DC OUTPUT VOLTAGE (mV)
FREQUENCY (Hz)
Figure 6.
Figure 7.
Differential Gain and Phase
Transient Response Positive
0.35
2.0
1.5
1.0
0.5
0
0.140
0.120
V
= 5V
S
0.30
0.25
0.20
0.15
0.10
0.05
0
R
= 150W
L
f = 3.58MHz
0.100
0.080
0.060
0.040
GAIN
-0.5
-1.0
-1.5
-2.0
-2.5
PHASE
0.020
V
S
= 10V
STEP = 3.3V
-0.000
R
L
= 100W
-0.020
-0.05
-700 -525 -350 -175
0
175 350 525 700
0
1
2
3
4
5
6
DC OUTPUT VOLTAGE (mV)
TIME (ns)
Figure 8.
Figure 9.
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Typical Performance Charac teristics (continued)
At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified.
Transient Response Negative
Transient Response Positive for Various VSUPPLY
2.0
2.5
V
= 10V, STEP 3.3V
PP
V
= 10V
S
S
2.0
1.5
1.0
0.5
0
STEP = 3.3V
1.5
R
= 100W
L
1.0
0.5
V
= 5V, STEP 2.3V
S
PP
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-0.5
-1.0
-1.5
-2.0
-2.5
V
= 3V, STEP 1V
PP
S
R
L
= 100W
0
2
4
6
8
10 12 14 16
0
1
2
3
4
5
6
TIME (ns)
Figure 10.
TIME (ns)
Figure 11.
Transient Response Negative for Various VSUPPLY
Harmonic Distortion vs. VOUT @ 5MHz
2.5
0
V
= 10V, STEP 3.3V
PP
S
R
= 100W
V
= 10V
L
S
-10
2.0
1.5
R
L
= 100W
-20
-30
THD
1.0
nd
V
= 3V, STEP 1V
PP
0.5
-40
-50
S
2
HD
0.0
rd
3
HD
-60
-0.5
-1.0
-1.5
-2.0
-2.5
V
= 5V, STEP 2.3V
S
PP
-70
-80
th
4
HD
-90
V
= 10V, STEP 3.3V
S
PP
-100
0.5
1
1.5
2
2.5
V
3
3.5
(V
4 5 5.5 6
4.5
0
2
4
6
8
10 12 14 16
TIME (ns)
)
OUT PP
Figure 12.
Harmonic Distortion vs. VOUT @ 10MHz
Figure 13.
Harmonic Distortion vs. VOUT @ 20MHz
0
0
V
= 10V
S
V
= 10V
S
-10
-10
R
= 100W
L
R
= 100W
L
-20
-30
-20
-30
THD
rd
THD
nd
3
HD
nd
-40
-50
-40
-50
2
HD
-60
-60
-70
-80
-70
-80
2
HD
rd
3
HD
th
4
HD
-90
th
-90
4
HD
4.5
-100
-100
0.5
1
1.5
2
2.5
3
3.5 4 4.5
(V
5 5.5 6
0.5
1
1.5
2
2.5
3
3.5
(V
4
5 5.5 6
V
)
V
)
OUT PP
OUT PP
Figure 14.
Figure 15.
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Typical Performance Charac teristics (continued)
At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified.
THD vs. VOUT for Various Frequencies
Voltage Noise
40
35
30
25
20
15
10
5
-40
V
= 10V
S
1MHz
R
= 100W
L
-45
5MHz
-50
10MHz
-55
-60
-65
-70
20MHz
10MHz
V
S
= 10V
R
L
= 100W
0
0.5
1
1.5
2
2.5
3
3.5
(V
4
4.5
5
5.5
6
100
10k
100k
1M
10M
1k
V
)
FREQUENCY (Hz)
OUT PP
Figure 16.
Linearity VOUT vs. VIN
= 10V
Figure 17.
VOS vs. VSUPPLY for 3 Units
T = 25°C
25
20
15
10
5
5
4
3
V
S
10MHz
R
= 100W
L
UNIT 3
2
1
50MHz
0
-1
UNIT 1
250MHz
500MHz
0
-2
-3
-5
-4
-5
-6
750MHz
-10
UNIT 2
-15
-10
-5
0
10
15
20
4
5
6
7
8
9
5
3
10
INPUT (dBm)
V
(V)
SUPPLY
Figure 18.
Figure 19.
VOS vs. VSUPPLY for Unit 1
VOS vs. VSUPPLY for Unit 2
0.5
0
0
-1
-2
-3
-4
125°C
-0.5
-40°C
125°C
-1
-1.5
-2
-40°C
85°C
25°C
-5
85°C
6
-2.5
-3
-6
-7
25°C
9
-3.5
3
4
5
6
7
8
9
10
3
4
5
7
8
10
V
(V)
V
(V)
SUPPLY
SUPPLY
Figure 20.
Figure 21.
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Typical Performance Charac teristics (continued)
At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified.
(1)
VOS vs. VSUPPLY for Unit 3
IB vs. VSUPPLY
6
0
-1
5
125°C
-2
4
85°C
-3
-4
-5
3
-40°C
-40°C
2
25°C
85°C
1
-6
-7
25°C
0
125°C
8
-1
-8
3
4
5
6
7
8
9
10
3
4
5
6
7
9
10
V
(V)
V
(V)
SUPPLY
SUPPLY
Figure 22.
ROUT vs. Frequency
Figure 23.
PSRR vs. Frequency
80
16
14
12
10
8
70
60
50
40
30
20
10
0
V
= 3V
S
V
= 5V
S
V
= 10V
S
6
4
V
= 10V
S
2
R
L
= 100W
0
100k
10M
100
10k
1M
100M
1k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24.
Figure 25.
ISUPPLY vs. VSUPPLY
ISUPPLY vs. VIN
12
14
11
125°C
12
10
125°C
85°C
85°C
10
9
25°C
8
6
8
-40°C
-40°C
7
4
2
25°C
6
5
V
= 10V
6
S
0
0
2
4
8
10
3
4
5
6
7
8
9
10
V
(V)
V
IN
(V)
SUPPLY
Figure 26.
Figure 27.
(1) Positive current corresponds to current flowing into the device.
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Typical Performance Charac teristics (continued)
At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified.
VOUT vs. IOUT Sinking
VOUT vs. IOUT Sourcing
4.5
4
0
V
V
= ±5V
= -4V
S
-0.5
-1
IN
3.5
3
125°C
85°C
-40°C
-1.5
-2
-2.5
-3
2.5
2
25°C
25°C
85°C
1.5
1
-40°C
125°C
-.35
-4
V
= ±5V
= +4V
S
0.5
0
V
IN
-4.5
-40
0
-20
-60
-80
-100
0
20
40
60
80
100
I
(mA)
SOURCE
I
(mA)
SINK
Figure 28.
Figure 29.
IO Sourcing vs. VSUPPLY
IO Sinking vs. VSUPPLY
-20
-30
90
80
70
60
50
40
30
20
10
0
V
V
= V /2
SUPPLY
OUT
= V
+0.5V
IN
OUT
25°C
85°C
-40
-50
-60
-70
125°C
125°C
85°C
-40°C
-80
-90
V
V
= V /2
SUPPLY
OUT
= V
- 0.5V
-40°C
IN
OUT
25°C
(V)
-100
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
V
(V)
V
SUPPLY
SUPPLY
Figure 30.
Small Signal Pulse Response
V = 10V
Figure 31.
Large Signal Pulse Response @ VS = 3V
0.6
0.4
0.3
0.2
0.1
0
S
0.4
0.2
V
= 5V
= 3V
S
S
V
= 1V
PP
PULSE
0
-0.2
-0.4
R
= 100W
V
L
V
S
= 3V
-0.1
-0.2
-0.3
-0.4
R
L
= 100W
-0.6
-0.8
V
= 0.5V
PP
PULSE
0
10
20
TIME (ns)
Figure 33.
30
40
50
0
5
10
15
TIME (ns)
20 25
30
35
Figure 32.
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Typical Performance Charac teristics (continued)
At TJ = 25°C; V+ = +5V; V− = −5V; Unless otherwise specified.
Large Signal Pulse Response @ VS = 5V
Large Signal Pulse Response @ VS = 10V
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
V
= 3.3V
PP
PULSE
V
= 2.3V
PP
PULSE
0
-0.5
-1.0
R
= 100W
L
R
= 100W
L
-0.5
-1.0
-1.5
-2.0
-2.5
-1.5
-2.0
0
10
20
30
40
50
0
10
20
30
40
50
TIME (ns)
TIME (ns)
Figure 34.
Figure 35.
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APPLICATION NOTES
USING BUFFERS
A buffer is an electronic device delivering current gain but no voltage gain. It is used in cases where low
impedances need to be driven and more drive current is required. Buffers need a flat frequency response and
small propagation delay. Furthermore, the buffer needs to be stable under resistive, capacitive and inductive
loads. High frequency buffer applications require that the buffer be able to drive transmission lines and cables
directly.
IN WHAT SITUATION WILL WE USE A BUFFER?
In case of a signal source not having a low output impedance one can increase the output drive capability by
using a buffer. For example, an oscillator might stop working or have frequency shift which is unacceptably high
when loaded heavily. A buffer should be used in that situation. Also in the case of feeding a signal to an A/D
converter it is recommended that the signal source be isolated from the A/D converter. Using a buffer assures a
low output impedance, the delivery of a stable signal to the converter, and accommodation of the complex and
varying capacitive loads that the A/D converter presents to the OpAmp. Optimum value is often found by
experimentation for the particular application.
The use of buffers is strongly recommended for the handling of high frequency signals, for the distribution of
signals through transmission lines or on pcb's, or for the driving of external equipment. There are several driving
options:
•
•
•
Use one buffer to drive one transmission line (see Figure 36)
Use one buffer to drive to multiple points on one transmission line (see Figure 37)
Use one buffer to drive several transmission lines each driving a different receiver. (see Figure 38)
R = Z0
Z0
E
INPUT
A =1X
A
B
R = Z0
Figure 36.
D
B
Z0
A
E
INPUT
A =1X
R = Z0
C
Figure 37.
E
R = Z0
Z0
OPEN END
A
B
INPUT
A =1X
OPEN END
OPEN END
Figure 38.
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In these three options it is seen that there is more than one preferred method to reach an (end) point on a
transmission line. Until a certain point the designer can make his own choice but the designer should keep in
mind never to break the rules about high frequency transport of signals. An explanation follows in the text below.
TRANSMISSION LINES
Introduction to transmission lines. The following is an overview of transmission line theory. Transmission lines
can be used to send signals from DC to very high frequencies. At all points across the transmission line, Ohm's
law must apply. For very high frequencies, parasitic behavior of the PCB or cables comes into play. The type of
cable used must match the application. For example an audio cable looks like a coax cable but is unusable for
radar frequencies at 10GHz. In this case one have to use special coax cables with lower attenuation and
radiation characteristics.
Normally a pcb trace is used to connect components on a pcb board together. An important considerations is the
amount of current carried by these pcb traces. Wider pcb traces are required for higher current densities and for
applications where very low series resistance is needed. When routed over a ground plane, pcb traces have a
defined Characteristic Impedance. In many design situations characteristic impedance is not utilized. In the case
of high frequency transmission, however it is necessary to match the load impedance to the line characteristic
impedance (more on this later). Each trace is associated with a certain amount of series resistance and series
inductance plus each trace exhibits parallel capacitance to the ground plane. The combination of these
parameters defines the line's characteristic impedance. The formula with which we calculate this impedance is as
follows:
Z0 = √(L/C)
In this formula L and C are the value/unit length, and R is assumed to be zero. C and L are unknown in many
cases so we have to follow other steps to calculate the Z0. The characteristic impedance is a function of the
geometry of the cross section of the line. In (Figure 39) we see three cross sections of commonly used
transmission lines.
D
W
S
h
d
d
TRACK OVER
GROUND
PARALLEL
WIRE
COAX CABLE
Figure 39.
Z0 can be calculated by knowing some of the physical dimensions of the pcb line, such as pcb thickness, width of
the trace and εr, relative dielectric constant. The formula given in transmission line theory for calculating Z0 is as
follows:
(5.98 x h)
87
x ln
Z =
(th + 0.8W)
(e r + 1.41)
where
•
•
•
•
εr= relative dielectric constant
h= pcb height
W= trace width
th= thickness of the copper
(1)
If we ignore the thickness of the copper in comparison to the width of the trace then we have the following
equation:
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(5.98 x h)
(0.8W)
87
x ln
Z =
(e r + 1.41)
(2)
With this formula it is possible to calculate the line impedance vs. the trace width. Figure 40 shows the
impedance associated with a given line width. Using the same formula it is also possible to calculate what
happens when εr varies over a certain range of values. Varying the εr over a range of 1 to 10 gives a variation for
the Characteristic Impedance of about 40Ω from 80Ω to 38Ω. Most transmission lines are designed to have 50Ω
or 75Ω impedance. The reason for that is that in many cases the pcb trace has to connect to a cable whose
impedance is either 50Ω or 75Ω. As shown εr and the line width influence this value.
VARIATION OF e
r
1.0 2.3 3.6 4.9 6.2 7.5 8.8 10.1
120
120
110
100
VARIABLE TRACE WIDTH
110
100
90
80
70
60
50
40
30
20
10
e = 4.7
h = 1.6mm
r
90
80
70
60
50
40
30
20
10
VARIABLE RELATIVE DIELECTRIC
CONSTANT
WIDTH = 2.85mm
h = 1.6mm
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0
TRACE WIDTH (mm)
Figure 40.
Next, there will be a discussion of some issues associated with the interaction of the transmission line at the
source and at the load.
Connecting A Load Using A Transmission Line
In most cases, it is unrealistic to think that we can place a driver or buffer so close to the load that we don't need
a transmission line to transport the signal. The pcb trace length between a driver and the load may affect
operation depending upon the operating frequency. Sometimes it is possible to do measurements by connecting
the DUT directly to the analyzer. As frequencies become higher the short lines from the DUT to the analyzer
become long lines. When this happens there is a need to use transmission lines. The next point to examine is
what happens when the load is connected to the transmission line. When driving a load, it is important to match
the line and load impedance, otherwise reflections will occur and this phenomena will distort the signal. If a
transient is applied at T = 0 (Figure 41, trace A) the resultant waveform may be observed at the start point of the
transmission line. At this point (begin) on the transmission line the voltage increases to (V) and the wave front
travels along the transmission line and arrives at the load at T = 10. At any point across along the line I = V/Z0,
where Z0 is the impedance of the transmission line. For an applied transient of 2V with Z0 = 50Ω the current from
the buffer output stage is 40mA. Many vintage opamps cannot deliver this level of current because of an output
current limitation of about 20mA or even less. At T = 10 the wave front arrives at the load. Since the load is
perfectly matched to the transmission line all of the current traveling across the line will be absorbed and there
will be no reflections. In this case source and load voltages are exactly the same. When the load and the
transmission line have unequal values of impedance a different situation results. Remember there is another
basic which says that energy cannot be lost. The power in the transmission line is P = V2/R. In our example the
total power is 22/50 = 80mW. Assume a load of 75Ω. In that case a power of 80mW arrives at the 75Ω load and
causes a voltage of the proper amplitude to maintain the incoming power.
-3
(P x R)
V =
= 2.45V
=
(80 x 10 x 75)
(3)
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The voltage wavefront of 2.45V will now set about traveling back over the transmission line towards the source,
thereby resulting in a reflection caused by the mismatch. On the other hand if the load is less then 50Ω the
backwards traveling wavefront is subtracted from the incoming voltage of 2V. Assume the load is 40Ω. Then the
voltage across the load is:
-3
= 1.79V
(80 x 10 x 40)
(4)
This voltage is now traveling backwards through the line toward the start point. In the case of a sinewave
interferences develop between the incoming waveform and the backwards-going reflections, thus distorting the
signal. If there is no load at all at the end point the complete transient of 2V is reflected and travels backwards to
the beginning of the line. In this case the current at the endpoint is zero and the maximum voltage is reflected. In
the case of a short at the end of the line the current is at maximum and the voltage is zero.
BEGIN
END
TRANSMISSION LINE LENGTH
V
V/2
0
A
B
V/2
0
V
V/2
C
0
V
V/2
0
D
E
V
V/2
0
6
0
4
10
2
8
TIME
Figure 41.
Using Serial And Parallel Termination
Many applications, such as video, use a series resistance between the driver and the transmission line (see
Figure 36). In this case the transmission line is terminated with the characteristic impedance at both ends of the
line. See Figure 41 trace B. The voltage traveling through the transmission line is half the voltage seen at the
output of the buffer, because the series resistor in combination with Z0 forms a two-to-one voltage divider. The
result is a loss of 6dB. For video applications, amplifier gain is set to 2 in order to realize an overall gain of 1.
Many operational amplifiers have a relatively flat frequency response when set to a gain of two compared to unity
gain. In trace B it is seen that, if the voltage reaches the end of the transmission line, the line is perfectly
matched and no reflections will occur. The end point voltage stays at half the output voltage of the opamp or
buffer.
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Driving More Than One Input
Another transmission line possibility is to route the trace via several points along a transmission line (Figure 37)
This is only possible if care is taken to observe certain restrictions. Failure to do so will result in impedance
discontinuities that will cause distortion of the signal. In the configuration of Figure 37 there is a transmission line
connected to the buffer output and the end of the line is terminated with Z0. We have seen in the Connecting A
Load Using A Transmission Line section that for the condition above, the signal throughout the entire
transmission line has the same value, that the value is the nominal value initiated by the opamp output, and no
reflections occur at the end point. Because of the lack of reflections no interferences will occur. Consequently the
signal has every where on the line the same amplitude. This allows the possibility of feeding this signal to the
input port of any device which has high ohmic impedance and low input capacitance. In doing so keep in mind
that the transient arrives at different times at the connected points in the transmission line. The speed of light in
vacuum, which is about 3 * 108 m/sec, reduces through a transmission line or a cable down to a value of about 2
* 108 m/sec. The distance the signal will travel in 1ns is calculated by solving the following formula:
S = V*t
where
•
•
•
S = distance
V = speed in the cable
t = time
(5)
This calculation gives the following result: s = 2*108 * 1*10−9 = 0.2m
That is for each nanosecond the wave front shifts 20cm over the length of the transmission line. Keep in mind
that in a distance of just 2cm the time displacement is already 100ps.
Using Serial Termination To More Than One Transmission Line
Another way to reach several points via a transmission line is to start several lines from one buffer output (see
Figure 38). This is possible only if the output can deliver the needed current into the sum of all transmission
lines. As can be seen in this figure there is a series termination used at the beginning of the transmission line
and the end of the line has no termination. This means that only the signal at the endpoint is usable because at
all other points the reflected signal will cause distortion over the line. Only at the endpoint will the measured
signal be the same as at the startpoint. Referring to Figure 41 trace C, the signal at the beginning of the line has
a value of V/2 and at T = 0 this voltage starts traveling towards the end of the transmission line. Once at the
endpoint the line has no termination and 100% reflection will occur. At T = 10 the reflection causes the signal to
jump to 2V and to start traveling back along the line to the buffer (see Figure 41 trace D). Once the wavefront
reaches the series termination resistor, provided the termination value is Z0, the wavefront undergoes total
absorption by the termination. This is only true if the output impedance of the buffer/driver is low in comparison to
the characteristic impedance Z0. At this moment the voltage in the whole transmission line has the nominal value
of 2V (see Figure 41 trace E). If the three transmission lines each have a different length the particular point in
time at which the voltage at the series termination resistor jumps to 2V is different for each case. However, this
transient is not transferred to the other lines because the output of the buffer is low and this transient is highly
attenuated by the combination of the termination resistor and the output impedance of the buffer. A simple
calculation illustrates the point. Assume that the output impedance is 5Ω. For the frequency of interest the
attenuation is VB/VA = 55/5 = 11, where A and B are the points in Figure 38. In this case the voltage caused by
the reflection is 2/11 = 0.18V. This voltage is transferred to the remaining transmission lines in sequence and
following the same rules as before this voltage is seen at the end points of those lines. The lower the output
resistance the higher the decoupling between the different lines. Furthermore one can see that at the endpoint of
these transmission lines there is a normal transient equal to the original transient at the beginning point. However
at all other points of the transmission line there is a step voltage at different distances from the startpoint
depending at what point this is measured (see trace D).
Measuring The Length Of A Transmission Line
An open transmission line can be used to measure the length of a particular transmission line. As can be seen in
Figure 42 the line of interest has a certain length. A transient is applied at T = 0 and at that point in time the
wavefront starts traveling with an amplitude of V/2 towards the end of the line where it is reflected back to the
startpoint.
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A
B
R = Z0
Z0
E
INPUT
A =1X
BEGIN
END
TRANSMISSION LINE LENGTH
V
V/2
0
0
2
3
5
1
4
TIME (ns)
Figure 42.
To calculate the length of the line it is necessary to measure immediately after the series termination resistor.
The voltage at that point remains at half nominal voltage, thus V/2, until the reflection returns and the voltage
jumps to V. During an interval of 5ns the signal travels to the end of the line where the wave front is reflected and
returns to the measurement point. During the time interval when the wavefront is traveling to the end of the
transmission line and back the voltage has a value of V/2. This interval is 10ns. The length can be calculated
with the following formula: S = (V*T)/2
8
-9
(2 x 10 ) x (10 x 10 )
2
S =
= 1mtr
(6)
As calculated before in the Driving More Than One Input section the signal travels 20cm/ns so in 5ns this
distance indicated distance is 1m. So this example is easily verified.
APPLYING A CAPACITIVE LOAD
The assumption of pure resistance for the purpose of connecting the output stage of a buffer or opamp to a load
is appropriate as a first approximation. Unfortunately that is only a part of the truth. Associated with this resistor
is a capacitor in parallel and an inductor in series. Any capacitance such as CL-1 which is connected directly to
the output stage is active in the loop gain as seen in Figure 43. Output capacitance, present also at the minus
input in the case of a buffer, causes an increasing phase shift leading to instability or even oscillation in the
circuit.
+
R
V
V
SERIES
+
-
-
R
IN
C -1
C -2
L
L
BUFFER INTERNAL CONNECTIONS
Figure 43.
Unfortunately the leads of the output capacitor also contain series inductors which become more and more
important at high frequencies. At a certain frequency this series capacitor and inductor forms an LC combination
which becomes series resonant. At the resonant frequency the reactive component vanishes leaving only the
ohmic resistance (R-1 or R-2) of the series L/C combination. (see Figure 44).
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+
-
R
V
SERIES
+
-
R
IN
V
C -1
L
C -2
L
L-2
L-1
R-1
R-2
BUFFER INTERNAL
CONNECTIONS
Figure 44.
Consider a frequency sweep over the entire spectrum for which the LMH6559 high frequency buffer is active. In
the first instance peaking occurs due to the parasitic capacitance connected at the load whereas at higher
frequencies the effects of the series combination of L and C become noticeable. This causes a distinctive dip in
the output frequency sweep and this dip varies depending upon the particular capacitor as seen in Figure 45.
12
6
0
C
= 47pF
= 22pF
L
C
L
-6
C
= 10pF
L
-12
-18
-24
C
= 4.7pF
L
C
= 0pF
L
-30
-36
-42
-48
V
S
= 10V
1M
100M
10M
1G
100k
FREQUENCY (Hz)
Figure 45.
To minimize peaking due to CL a series resistor for the purpose of isolation from the output stage should be
used. A low valued resistor will minimize the influence of such a load capacitor. In a 50Ω system as is common
in high frequency circuits a 50Ω series resistor is often used. Usage of the series resistor, as seen in Figure 46
eliminates the peaking but not the dip. The dip will vary with the particular capacitor. Using a resistor in series
with a capacitor creates in a single pole situation a 6dB/oct rolloff. However, at high frequencies the internal
inductance is appreciable and forms a series LC combination with the capacitor. Choice of a higher valued
resistor, for example 500 to 1kΩ, and a capacitor of hundreds of pF's provides the expected response at lower
frequencies.
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6
C
= 0pF
L
0
-6
C
= 10pF, R = 50W
S
L
-12
-18
-24
-30
C
= 47pF, R = 50W
S
L
C
= 100pF, R = 50W
S
L
-36
-42
-48
V
= 10V
1M
S
100k
10M
100M
1G
FREQUENCY (Hz)
Figure 46.
USING GROUND PLANES
The use of ground planes is recommended both for providing a low impedance path to ground (or to one of the
other supply voltages) and also for forming effective controlled impedance transmission lines for the high
frequency signal flow on the board. Multilayer boards often make use of inner conductive layers for routing
supply voltages. These supply voltage layers form a complete plane rather than using discrete traces to connect
the different points together for the specified supply. Signal traces on the other hand are routed on outside layers
both top and bottom. This allows for easy access for measurement purposes. Fortunately, only very high density
boards have signal layers in the middle of the board. In an earlier section, the formula for Z0 was derived as:
(5.98 x h)
(0.8W)
87
x ln
Z =
(er + 1.41)
(7)
The width of a trace is determined by the thickness of the board. In the case of a multilayer board the thickness
is the space between the trace and the first supply plane under this trace layer. By common practice, layers do
not have to be evenly divided in the construction of a pcb. Refer to Figure 47. The design of a transmission line
design over a pcb is based upon the thickness of the different internal layers and the εr of the board material.
The pcb manufacturer can supply information about important specifications. For example, a nominal 1.6mm
thick pcb produces a 50Ω trace for a calculated width of 2.9mm. If this layer has a thickness of 0.35mm and for
the same εr, the trace width for 50Ω should be of 0.63mm, as calculated from Equation 8, a derivation from
Equation 7.
5.98 x h
w =
A
e
(e + 1.41)
r
Z
O
x
where A =
87
(8)
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
TRACK WIDTH
(w)
HEIGHT OVER
GROUND PLANE
(h)
UPPER TRACK LAYER
INNER LAYER A
TOTAL
PCB
HEIGHT
INNER LAYER B
BOTTOM TRACK LAYER
Figure 47.
Using a trace over a ground plane has big advantages over the use of a standard single or double sided board.
The main advantage is that the electric field generated by the signal transported over this trace is fixed between
the trace and the ground plane e.g. there is almost no possibility of radiation (see Figure 48).
TRACKWIDTH
GROUNDPLANE
Figure 48.
This effect works to both sides because the circuit will not generate radiation but the circuit is also not sensible if
exposed to a certain radiation level. The same is also noticeable when placing components flat on the printed
circuit board. Standard through hole components when placed upright can act as an antenna causing an electric
field which could be picked up by a nearby upright component. If placed directly at the surface of the pcb this
influence is much lower.
The Effect Of Variation For εr
When using pcb material the εr has a certain shift over the used frequency spectrum, so if necessary to work with
very accurate trace impedances one must taken into account for which frequency region the design has to be
functional. Figure 49 (Courtesy of Islola Corporation) gives an example what the drift in εr will be when using the
pcb material produced by Isola. If working at frequencies of 100MHz then a 50Ω trace has a width of 3.04mm for
standard 1.6mm FR4 pcb material, and the same trace needs a width of 3.14mm. for frequencies around 10GHz.
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5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
RESIN = 40%
RESIN = 45%
RESIN = 50%
RESIN = 55%
RESIN = 60%
1M
10M
100M
1G
10G
FREQUENCY (Hz)
Figure 49.
Routing Power Traces
Power line traces routed over a pcb should be kept together for best practice. If not a ground loop will occur
which may cause more sensitivity to radiation. Also additional ground trace length may lead to more ringing on
digital signals. Careful attention to power line distribution leads to improved overall circuit performance. This is
especially valid for analog circuits which are more sensitive to spurious noise and other unwanted signals.
+
GND
V
Figure 50.
As demonstrated in Figure 50 the power lines are routed from both sides on the pcb. In this case a current loop
is created as indicated by the dotted line. This loop can act as an antenna for high frequency signals which
makes the circuit sensitive to RF radiation. A better way to route the power traces can be seen in the following
setup. (see Figure 51)
24
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
+
GND
V
Figure 51.
In this arrangement the power lines have been routed in order to avoid ground loops and to minimize sensitivity
to noise etc. The same technique is valid when routing a high frequent signal over a board which has no ground
plane. In that case is it good practice to route the high frequency signal alongside a ground trace. A still better
way to create a pcb carrying high frequency signals is to use a pcb with a ground plane or planes.
Discontinuities In A Ground Plane
A ground plane with traces routed over this plane results in the build up of an electric field between the trace and
the ground plane as seen in Figure 48. This field is build up over the entire routing of the trace. For the highest
performance the ground plane should not be interrupted because to do so will cause the field lines to follow a
roundabout path. In Figure 52 it was necessary to interrupt the ground plane with a crossing trace. This
interruption causes the return current to follow a longer route than the signal path follows to overcome the
discontinuity.
RETURN PATH
+
SIGNAL IN
GND
V
Figure 52.
If needed it is possible to bypass the interruption with traces that are parallel to the signal trace in order to reduce
the negative effects of the discontinuity in the ground plane. In doing so, the current in the ground plane closely
follows the signal trace on the return path as can be seen in Figure 53. Care must be taken not to place too
many traces in the ground plane or the ground plane effectively vanishes such that even bypasses are
unsuccessful in reducing negative effects.
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RETURN PATH
+
SIGNAL IN
V
GND
Figure 53.
If the overall density becomes too high it is better to make a design which contains additional metal layers such
that the ground planes actually function as ground planes. The costs for such a pcb are increased but the payoff
is in overall effectiveness and ease of design.
Ground Planes At Top And Bottom Layer Of A PCB
In addition to the bottom layer ground plane another useful practice is to leave as much copper as possible at the
top layer. This is done to reduce the amount of copper to be removed from the top layer in the chemical process.
This causes less pollution of the chemical baths allowing the manufacturer to make more pcb's with a certain
amount of chemicals. Connecting this upper copper to ground provides additional shielding and signal
performance is enhanced. For lower frequencies this is specifically true. However, at higher frequencies other
effects become more and more important such that unwanted coupling may result in a reduction in the bandwidth
of a circuit. In the design of a test circuit for the LMH6559 this effect was clearly noticeable and the useful
bandwidth was reduced from 1500MHz to around 850MHz.
3
V
= 10V
S
0
-3
WITH COPPER FIELD
-6
-9
-12
10M
100M
1G 2G
FREQUENCY (Hz)
Figure 54.
As can be seen in Figure 54 the presence of a copper field close to the transmission line to and from the buffer
causes unwanted coupling effects which can be seen in the dip at about 850MHz. This dip has a depth of about
5dB for the case when all of the unused space is filled with copper. In case of only one area being filled with
copper this dip is about 9dB.
26
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SNOSA57C –APRIL 2003–REVISED MARCH 2013
PCB Board Layout And Component Selection
Sound practice in the area of high frequency design requires that both active and passive components be used
for the purposes for which they were designed. It is possible to amplify signals at frequencies of several
hundreds of MHz using standard through hole resistors. Surface mount devices, however, are better suited for
this purpose. Surface mount resistors and capacitors are smaller and therefore parasitics are of lower value and
therefore have less influence on the properties of the amplifier. Another important issue is the pcb itself, which is
no longer a simple carrier for all the parts and a medium to interconnect them. The pcb board becomes a real
component itself and consequently contributes its own high frequency properties to the overall performance of
the circuit. Sound practice dictates that a design have at least one ground plane on a pcb which provides a low
impedance path for all decoupling capacitors and other ground connections. Care should be taken especially that
on- board transmission lines have the same impedance as the cables to which they are connected - 50Ω for
most applications and 75Ω in case of video and cable TV applications. Such transmission lines usually require
much wider traces on a standard double sided PCB board than needed for a 'normal' trace. Another important
issue is that inputs and outputs must not 'see' each other. This occurs if inputs and outputs are routed together
over the pcb with only a small amount of physical separation, particularly when there is a high differential in
signal level between them. Furthermore components should be placed as flat and low as possible on the surface
of the PCB. For higher frequencies a long lead can act as a coil, a capacitor or an antenna. A pair of leads can
even form a transformer. Careful design of the pcb avoids oscillations or other unwanted behaviors. For ultra
high frequency designs only surface mount components will give acceptable results. (for more information see
OA-15 (Literature Number SNOA367).
TI suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing
and characterization.
Device
Package
SOIC
Evaluation Board Part Number
CLC730245
LMH6559MA
LMH6559MAX
LMH6559MF
LMH6559MFX
SOIC
CLC730245
SOT-23
SOT-23
CLC730136
CLC730136
These free evaluation boards are shipped when a device sample request is placed with Texas Instruments.
POWER SEQUENCING OF THE LMH6559
Caution should be exercised in applying power to the LMH6559. When the negative power supply pin is left
floating it is recommended that other pins, such as positive supply and signal input should also be left
unconnected. If the ground is floating while other pins are connected the input circuitry is effectively biased to
ground, with a mostly low ohmic resistor, while the positive power supply is capable of delivering significant
current through the circuit. This causes a high input bias current to flow which degrades the input junction. The
result is an input bias current which is out of specification. When using inductive relays in an application care
should be taken to connect first both power connections before connecting the bias resistor to the input.
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
28
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6559MA
LMH6559MA/NOPB
LMH6559MAX/NOPB
LMH6559MF
NRND
SOIC
SOIC
D
D
8
8
8
5
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LMH65
59MA
ACTIVE
ACTIVE
ACTIVE
95
RoHS & Green
SN
SN
LMH65
59MA
SOIC
D
2500 RoHS & Green
LMH65
59MA
SOT-23
DBV
1000
Non-RoHS
& Green
Call TI
B05A
LMH6559MF/NOPB
LMH6559MFX/NOPB
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
1000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
B05A
B05A
3000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6559MAX/NOPB
LMH6559MF
SOIC
D
8
5
5
5
2500
1000
1000
3000
330.0
178.0
178.0
178.0
12.4
8.4
8.4
8.4
6.5
3.2
3.2
3.2
5.4
3.2
3.2
3.2
2.0
1.4
1.4
1.4
8.0
4.0
4.0
4.0
12.0
8.0
8.0
8.0
Q1
Q3
Q3
Q3
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
LMH6559MF/NOPB
LMH6559MFX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6559MAX/NOPB
LMH6559MF
SOIC
D
8
5
5
5
2500
1000
1000
3000
367.0
208.0
208.0
208.0
367.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
LMH6559MF/NOPB
LMH6559MFX/NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6559MA
LMH6559MA
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
LMH6559MA/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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