LMH6570MA/NOPB [TI]
具有 2:1 高速多路复用器的 500MHz 高速运算放大器 | D | 8 | -40 to 85;
| 型号： | LMH6570MA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 2:1 高速多路复用器的 500MHz 高速运算放大器 | D | 8 | -40 to 85 放大器 PC 光电二极管 输出元件 运算放大器 复用器 |
| 文件： | 总29页 (文件大小：1389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6570
SNCS104D –APRIL 2005–REVISED DECEMBER 2014
LMH6570 2:1 High Speed Video Multiplexer
1 Features
3 Description
The LMH6570 is
a
high performance analog
1
•
•
•
•
•
•
•
•
500 MHz, 500 mVPP, −3 dB Bandwidth, AV=2
400 MHz, 2VPP, −3 dB Bandwidth, AV=2
8 ns Channel Switching Time
multiplexer optimized for professional grade video
and other high fidelity, high bandwidth analog
applications. The output amplifier selects one of two
buffered input signals based on the state of the SEL
pin. The LMH6570 provides a 400 MHz bandwidth at
2-VPP output signal levels. Multimedia and high
definition television (HDTV) applications can benefit
from the 0.1-dB bandwidth of 150 MHz and the 2200-
V/μs slew rate of LMH6570.
70 dB Channel to Channel Isolation @ 10 MHz
0.02%, 0.05° Diff. Gain, Diff. Phase
0.1 dB Gain Flatness to 150 MHz
2200 V/μs Slew Rate
Wide Supply Voltage Range: 6 V (±3 V) to 12 V
(±6 V)
The LMH6570 supports composite video applications
with its 0.02% and 0.05° differential gain and phase
errors for NTSC and PAL video signals while driving
a single, back terminated 75-Ω load. An 80-mA linear
output current is available for driving multiple video
load applications.
•
•
−68 dB HD2 @ 5 MHz
−84 dB HD3 @ 5 MHz
2 Applications
•
•
•
•
•
•
Video Router
The LMH6570 gain is set by external feedback and
gain set resistors for maximum flexibility.
Multi Input Video Monitor
Instrumentation / Test Equipment
Receiver IF Diversity Switch
Multi Channel A/D Driver
Picture in Picture Video Switch
The LMH6570 is available in the 8-pin SOIC
package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMH6570
SOIC (8)
4.9 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Frequency Response vs. Gain
Frequency Response vs. VOUT
1
0
1
0
-1
-1
A
= 1, R = 1.5 k:
F
V
V
= 0.5 V
PP
OUT
-2
-3
-4
-2
-3
-4
A
= 2, R = 575:
F
V
V
= 1 V
PP
OUT
A
= 6, R = 300:
F
V
V
= 2 V
PP
OUT
-5
-6
-7
-8
-9
-5
-6
-7
-8
-9
A
= 10, R = 180:
F
V
V
= 4 V
OUT
PP
V = ±5V
S
V
= ±5V
S
V = 2 V
OUT PP
A
V
= 2V/V
10
100
FREQUENCY (MHz)
1000
10
100
1000
FREQUENCY (MHz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6570
SNCS104D –APRIL 2005–REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics ±5V .................................. 5
6.6 Electrical Characteristics ±3.3V ............................... 7
6.7 Typical Performance Characteristics ........................ 8
7
Application and Implementation ........................ 12
7.1 Application Information............................................ 12
7.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 19
8.1 Power Dissipation ................................................... 19
Layout ................................................................... 19
9.1 Layout Guidelines ................................................... 19
8
9
10 Device and Documentation Support ................. 20
10.1 Documentation Support ........................................ 20
10.2 Trademarks........................................................... 20
10.3 Electrostatic Discharge Caution............................ 20
10.4 Glossary................................................................ 20
11 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2013) to Revision D
Page
•
Added the following sections: Device Information Table; Power Supply Recommendations; Layout; Device and
Documentation Support; Mechanical, Packaging, and Ordering Information ........................................................................ 1
Revised text in Application and Implementation section, formerly titled "Application Notes"............................................... 12
Revised text in Multiplexer Expansion section. Added Figure 27, Figure 28, and Figure 29 .............................................. 14
•
•
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
2
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SNCS104D –APRIL 2005–REVISED DECEMBER 2014
5 Pin Configuration and Functions
8-Pin SOIC
D Package
(Top View)
8
1
FB
IN0
-
+
7
6
OUT
SEL
2
3
4
+
V
SD
-
IN1
5
V
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
IN0
SEL
SD
I
I
Input Channel 0
Select Pin
Shutdown
2
3
I
4
IN1
V-
I
Input Channel 1
V- Supply
5
I
6
V+
I
V+ Supply
7
OUT
FB
O
I
Output
8
Feedback
Truth Table
SEL
1
SD
OUTPUT
IN1 * (1+RF/RG)
IN0 * (1+RF/RG)
Shutdown
0
0
0
X
1
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SNCS104D –APRIL 2005–REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN
MAX
13.2
UNIT
V
Supply Voltage (V+ − V−)
(3)
IOUT
130
mA
V
Signal & Logic Input Pin Voltage
Signal & Logic Input Pin Current
Maximum Junction Temperature
Storage Temperature
±(VS + 0.6)
±20
mA
°C
+150
+150
235
−65
°C
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
°C
Soldering Information
260
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model (MM)(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. Human
body model, 1.5kΩ in series with 100 pF.
(2) Machine model, 0 Ω In series with 200 pF
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
−40
6
NOM
MAX
85
UNIT
°C
Operating Temperature
Supply Voltage
12
V
6.4 Thermal Information
D
THERMAL METRIC(1)
UNIT
8 PINS
150
RθJA
Junction-to-ambient thermal resistance
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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SNCS104D –APRIL 2005–REVISED DECEMBER 2014
6.5 Electrical Characteristics ±5V
VS = ±5 V, RL = 100 Ω, RF = 576 Ω, AV = 2 V/V, TJ = 25 °C, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN(2)
TYP(3) MAX(2)
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
LSBW
.1 dBBW
DG
−3 dB Bandwidth
VOUT = 0.5 VPP
500
400
MHz
MHz
MHz
(4)
–3 dB Bandwidth
VOUT = 2 VPP
0.1 dB Bandwidth
Differential gain
VOUT = 0.25 VPP
150
RL = 150 Ω, f = 4.43 MHz
RL = 150 Ω, f = 4.43 MHz
All Hostile, f = 5 MHz
0.02%
0.05
−70
DP
Differential phase
Channel to channel crosstalk
deg
dBc
XTLK
TIME DOMAIN RESPONSE
Channel to channel switching
time
ns
TRS
Logic transition to 90% output
8
Enable and disable times
Rise and fall time
Settling time to 0.05%
Overshoot
Logic transition to 90% or 10% output.
10
2.4
ns
ns
ns
TRL
TSS
OS
SR
4 V Step
2 V Step
17
2 V Step
4 V Step(4)(5)
5%
Slew rate
2200
V/μs
DISTORTION
HD2
HD3
2nd Harmonic distortion
3rd Harmonic distortion
3rd Order intermodulation
products
2 VPP , 5 MHz
2 VPP , 5 MHz
−68
−84
dBc
dBc
dBc
IMD
10 MHz, Two tones 2 Vpp at output
−80
EQUIVALENT INPUT NOISE
VN
Voltage
Current
>1 MHz, Input Referred
>1 MHz, Input Referred
5
5
nV√HZ
pA/√Hz
ICN
STATIC, DC PERFORMANCE
±0.005% ±0.034%
±0.036%
Channel to channel gain
difference
DC, Difference in gain
between channels
CHGM
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
1
±15
±21
mV
VIO
Input offset voltage
Offset voltage drift(6)
Input bias current(7)
Bias current drift(6)
VIN = 0 V
DVIO
IBN
30
µV/°C
µA
−3
±8
VIN = 0 V
-40°C ≤ TJ ≤ 85°C
±10
DIBN
11
nA/°C
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Thermal Information for information on temperature de-rating of this device.
Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Parameter ensured by design.
(5) Slew Rate is the average of the rising and falling edges.
(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(7) Positive Value is current into device.
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Electrical Characteristics ±5V (continued)
VS = ±5 V, RL = 100 Ω, RF = 576 Ω, AV = 2 V/V, TJ = 25 °C, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN(2)
TYP(3) MAX(2)
UNIT
−3
±18
±22
uA
Pin 8, Feedback point,
VIN = 0 V
IBI
Inverting input bias current(7)
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
48
46
50
dB
mA
mA
PSRR
ICC
Power supply rejection ratio
Supply current
DC, Input referred
13.8
1.1
15
16
No Load, Shutdown Pin
(SD) > 0.8 V
1.3
1.4
Supply current shutdown
Shutdown Pin (SD) > 2 V
VIH
VIL
Logic high threshold
Logic low threshold
Select Pin & Shutdown pin (SEL, SD)
Select Pin & Shutdown pin (SEL, SD)
2.0
V
V
0.8
Logic Input = 0 V Select
Pin & Shutdown Pin (SEL,
SD)
−8
−1
µA
IiL
Logic pin input current low(7)
-40°C ≤ TJ ≤ 85°C
-10
Logic Input = 5.0 V, Select
57
68
75
µA
IiH
Logic pin input current high(7) Pin & Shutdown Pin (SEL,
SD)
-40°C ≤ TJ ≤ 85°C
MISCELLANEOUS PERFORMANCE
RIN+
CIN
Input resistance
5
0.8
kΩ
pF
Ω
Input capacitance
Output resistance
Output resistance
Output capacitance
ROUT
ROUT
COUT
Output Active, (SD < 0.8 V)
Output Disabled, (SD > 2 V)
Output Disabled, (SD > 2 V)
0.04
3000
3.1
Ω
pF
V
±3.51
±3.50
±3.16
±3.15
±2.5
+60
±3.7
VO
No Load
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
Output voltage range
±3.5
V
VOL
RL = 100 Ω
CMIR
Input voltage range
±2.6
±80
V
mA
IO
Linear output current(7)
Short circuit current(8)
VIN = 0 V
-70
-40°C ≤ TJ ≤ 85°C
±55
ISC
VIN = ±2 V, Output shorted to ground
±230
mA
(8) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
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SNCS104D –APRIL 2005–REVISED DECEMBER 2014
6.6 Electrical Characteristics ±3.3V
VS = ±3.3 V, RL = 100 Ω, RF = 576 Ω, AV = 2 V/V, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN(2)
TYP(3)
MAX(2)
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
LSBW
−3 dB Bandwidth
−3 dB Bandwidth
VOUT = 0.5 VPP
475
MHz
MHz
MHz
dB
VOUT = 2.0 VPP
375
100
0.4
0.1 dBBW 0.1 dB Bandwidth
VOUT = 0.5 VPP
GFP
Peaking
DC to 200 MHz
All Hostile, f = 5 MHz
XTLK
Channel to channel crosstalk
−70
dBc
TIME DOMAIN RESPONSE
TRL
TSS
OS
SR
Rise and Fall time
Settling time to 0.05%
Overshoot
2 V Step
2 V Step
2 V Step
2 V Step
2
20
ns
ns
5%
Slew rate
1400
V/μs
DISTORTION
HD2
HD3
2nd Harmonic distortion
3rd Harmonic distortion
2 VPP, 10 MHz
2 VPP, 10 MHz
−67
−87
dBc
dBc
STATIC, DC PERFORMANCE
VIO
Input offset voltage
Input bias current(4)
Power supply rejection ratio
Supply current
VIN = 0 V
1
-3
mV
μA
dB
mA
V
IBN
VIN = 0 V
PSRR
ICC
DC, Input Referred
No Load
49
12.5
Select Pin & Shutdown pin (SEL, SD),
VIH
VIL
Logic high threshold
Logic low threshold
1.3
0.4
VIH ≊ V+ * 0.4
Select Pin & Shutdown pin (SEL, SD),
V
VIL ≊ V+ * 0.12
MISCELLANEOUS PERFORMANCE
RIN+
CIN
Input resistance
Input capacitance
Output resistance
5
0.8
kΩ
pF
Ω
ROUT
VO
0.06
±2
No Load
V
Output voltage range
VOL
CMIR
IO
RL = 100 Ω
±1.8
±1.2
±60
±150
V
Input voltage range
V
Linear output current(5)
Short circuit current(5)
VIN = 0 V
mA
mA
ISC
VIN = ±1 V, Output shorted to ground
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Thermal Information for information on temperature de-rating of this device.
Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Positive Value is current into device.
(5) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
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6.7 Typical Performance Characteristics
Vs = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 576 Ω, unless otherwise specified.
1
0
1
0
-1
-1
A
= 1, R = 1.5 k:
F
V
V
= 0.5 V
PP
OUT
V
-2
-3
-4
-2
-3
-4
A
V
= 2, R = 575:
F
= 1 V
PP
OUT
A
= 6, R = 300:
F
V
V
= 2 V
PP
OUT
-5
-6
-7
-8
-9
-5
-6
-7
-8
-9
A
= 10, R = 180:
F
V
V
= 4 V
OUT
PP
V
= ±5V
V = ±5V
S
S
A
V
= 2V/V
V
= 2 V
OUT PP
10
100
10
100
FREQUENCY (MHz)
1000
1000
FREQUENCY (MHz)
Figure 1. Frequency Response vs. VOUT
Figure 2. Frequency Response vs. Gain
2
90
C
= 8.6 pF, R
= 63:
V
= ±5V
L
OUT
S
80
70
60
50
40
30
20
LOAD = 1 k:ꢀ|| C
0
L
C
C
= 18 pF, R
= 56 pF, R
= 48:
= 24:
L
L
L
OUT
-2
OUT
-4
-6
C
= 100 pF, R = 19:
OUT
V
= 1 V
PP
OUT
C
|| 1 k:
L
S
V
-8
V
A
= ±5V
= 2 (V/V)
10
0
-10
1
10
100
1000
1
10
100
1000
CAPACTIVE LOAD (pF)
FREQUENCY (MHz)
Figure 4. Suggested ROUT vs. Capacitive Load
Figure 3. Frequency Response vs. Capacitive Load
1600
1400
1200
1000
800
600
400
200
0
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
V
= ±5V
S
-2
-2.5
2
3
4
5
6
7
8
9
10
1
0
2
4
6
8
10
12
14 16 18 20
GAIN (V/V)
TIME (ns)
Figure 5. Suggested Value of RF vs. Gain
Figure 6. Pulse Response 4VPP
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Typical Performance Characteristics (continued)
Vs = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 576 Ω, unless otherwise specified.
1.5
1.5
1
V
S
= ±5V
V = ±3.3V
S
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 7. Pulse Response 2VPP
Figure 8. Pulse Response 2VPP
10000
1000
10000
1000
DISABLED
DISABLED
V
V
A
= ±5V
= 0V
S
100
10
100
10
V
V
A
= ±5V
= 0V
S
IN
V
IN
V
= 2V/V
= 1V/V
1
1
ENABLED
ENABLED
0.1
0.1
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Closed Loop Output Impedance
Figure 10. Closed Loop Output Impedance
60
1
PSRR +
0.5
50
CH 1
CH 0
0
-0.5
-1
40
PSRR -
30
20
10
0
-1.5
4
2
0
CONTROL SIGNAL
10 20 30 40 50 60 70 80
TIME (ns)
0
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 11. PSRR vs. Frequency
Figure 12. Channel Switching
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Typical Performance Characteristics (continued)
Vs = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 576 Ω, unless otherwise specified.
0.08
0.06
0.04
0.02
0.5
SHUTDOWN GLITCH
0.25
V
OUT
0
-0.25
-0.5
SHUTDOWN
ON
0
3
2
1
0
-0.02
4
2
0
SHUTDOWN SIGNAL
SHUTDOWN
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
10 20 30 40 50 60 70 80
TIME (ns)
Figure 13. SHUTDOWN Switching
Figure 14. Shutdown Glitch
-40
-40
-50
V
OUT
= 2 V
PP
V = 2 V
OUT PP
-50
-60
-70
-80
-60
-70
-80
CH 1
HD3 ALL CHANNELS
CH 0
-90
-90
-100
-100
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
1
Figure 15. HD2 vs. Frequency
Figure 16. HD3 vs. Frequency
-60
-65
-70
-75
-80
-85
-90
-95
-100
-40
-45
-50
-55
-60
-65
-70
-75
-80
f = 5 MHz
f = 5 MHz
V
=
2 V
PP
V
OUT
= 2 V
PP
OUT
CH1
CH1
CH1
CH0
CH0
11
11
5
6
7
9
10
12
5
6
7
8
9
10
12
8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 17. HD2 vs. VS
Figure 18. HD3 vs. VS
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Typical Performance Characteristics (continued)
Vs = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 576 Ω, unless otherwise specified.
-40
-30
f = 5 MHz
f = 5 MHz
-40
-50
-50
CH 1
-60
-70
-60
-70
-80
-80
CH 0
-90
-90
-100
-100
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
OUTPUT VOLTAGE (V
)
PP
OUTPUT VOLTAGE (V
)
PP
Figure 19. HD2 vs. VOUT
Figure 20. HD3 vs. VOUT
-2.4
-2.6
-2.8
4
3.8
3.6
3.4
3.2
3
-3
-3.2
-3.4
-3.6
-3.8
-4
2.8
0
20
40
60
80
100
-100
-80
-60
-40
-20
0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Positive value is current into device
Positive value is current into device
Figure 21. Minimum VOUT vs. IOUT
Figure 22. Maximum VOUT vs. IOUT
-40
-20
-30
-40
-50
-60
-70
-80
-90
-100
-50
-60
-70
-80
-60
-100
-110
10
FREQUENCY (MHz)
100
0.01
0.1
1
1000
1
10
100
1000
FREQUENCY (MHz)
Figure 24. Off Isolation
Figure 23. Crosstalk vs. Frequency
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
The LMH6570 is a high-speed 2:1 analog multiplexer, optimized for very high speed and low distortion. With
selectable gain and excellent AC performance, the LMH6570 is ideally suited for switching high resolution,
presentation grade video signals. The LMH6570 has no internal ground reference. Single or split supply
configurations are both possible, however, all logic functions are referenced to the mid supply point. The
LMH6570 features very high speed channel switching and disable times. When disabled the LMH6570 output is
high impedance making MUX expansion possible by combining multiple devices. See Multiplexer Expansion. The
LMH6570 SEL defaults to logic low (IN0 active). The default state for the SD pin is also logic low (device
enabled). Both pins can be left floating if the default state is desired.
7.2 Typical Application
+
V
6
SEL
IN 0
1
R
T
2
R
IN0
V
OUT
7
8
3
+
-
R
OUT
R
F
IN 1
4
R
G
SD
R
IN1
R
T
5
-
V
Figure 25. Typical Application
7.2.1 Video Performance
The LMH6570 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-
terminated loads. The back termination reduces reflections from the transmission line and effectively masks
transmission line and other parasitic capacitances from the amplifier output stage. Figure 25 shows a typical
configuration for driving a 75-Ω cable. The output buffer is configured for a gain of 2, so using back terminated
loads will give a net gain of 1.
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Typical Application (continued)
7.2.2 Feedback Resistor Selection
1600
1400
1200
1000
800
600
400
200
0
1
2
3
4
5
6
7
8
9
10
GAIN (V/V)
Figure 26. Suggested RF vs. Gain
The LMH6570 has a current feedback output buffer with gain determined by external feedback (RF) and gain set
(RG) resistors. With current feedback amplifiers, the closed loop frequency response is a function of RF. For a
gain of 2 V/V, the recommended value of RF is 576 Ω. For other gains, see Figure 26. Generally, lowering RF
from the recommended value will peak the frequency response and extend the bandwidth while increasing the
value of RF will cause the frequency response to roll off faster. Reducing the value of RF too far below the
recommended value will cause overshoot, ringing and, eventually, oscillation.
Since all applications are slightly different, it is worth some experimentation to find the optimal RF for a given
circuit. For more information see Current Feedback Loop Gain Analysis and Performance Enhancement,
Application Note OA-13 (SNOA366), which describes the relationship between RF and closed-loop frequency
response for current feedback operational amplifiers. The impedance looking into pin 8 is approximately 20 Ω.
This allows for good bandwidth at gains up to 10 V/V. When used with gains over 10 V/V, the LMH6570 will
exhibit a “gain bandwidth product” similar to a typical voltage feedback amplifier. For gains of over 10 V/V
consider selecting a high performance video amplifier like the LMH6720 to provide additional gain.
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Typical Application (continued)
7.2.3 Multiplexer Expansion
It is possible to use multiple LMH6570 devices to expand the number of inputs that can be selected for output.
Figure 27 shows a 4:1 MUX using two LMH6570 devices.
Figure 27. 4:1 MUX Using Two LMH6570 Devices
In such an application, the output settling may be longer than the LMH6570 switching specifications (~20 ns),
while switching between two separate LMH6570 devices. The switching time limiting factor occurs when one
LMH6570 is turned off and another one is turned on, using the SD (shutdown) pin. The output settling time
consists of the time needed for the first LMH6570 to enter high impedance state plus the time required for the
second LMH6570 output to dissipate left-over output charge of the first device (limited by the output current
capability of the second device) and the time needed to settle to the final voltage value.
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Typical Application (continued)
While Figure 27 MUX expansion benefits from more isolation, originating from the parasitic loading of the un-
selected channels on the selected channel, afforded by individual ROUT on each multiplexer output, this
configuration does not produce the fastest transition between individual LMH6570 devices. For fastest transition
between LMH6570 devices, the configuration of Figure 28 can be used where the LMH6570 output pins are all
shorted together.
Figure 28. Alternate 4:1 MUX Expansion Schematic (for Faster SD Switching)
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Typical Application (continued)
Figure 29 shows typical transition waveforms and shows that SD pin switching settles in less than 145 ns.
5
3
145 ns
4
2
3
1
SD_MUX1
SD_MUX2
Vout
2
0
1
-1
-2
-3
Settled final value
0
-1
-1E-07
-5E-08
0
5E-08
0.0000001
1.5E-07
0.0000002
2.5E-07
Time (50 ns/div)
Figure 29. SD pin Switching Waveform and Output Settling
If it is important in the end application to make sure that no two inputs are presented to the output at the same
time, an optional delay block can be added, to drive the SHUTDOWN pin of each device. Figure 30 shows one
possible approach to this delay circuit. The delay circuit shown will delay H to L transitions of SHUTDOWN (R1
and C1 decay) but will not delay its L to H transition. R2 should be kept small compared to R1 in order to not
reduce the SHUTDOWN voltage and to produce little or no delay to SHUTDOWN.
Figure 30. Delay Circuit Implementation
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Typical Application (continued)
With the SHUTDOWN pin putting the output stage into a high impedance state, several LMH6570 devices can be
tied together to form a larger input MUX. However, there is a loading effect on the active output caused by the
unselected devices. The circuit in Figure 31 shows how to compensate for this effect. For the 8:1 MUX function
shown in Figure 31, the gain error would be about 0.7% or −0.06dB. In the circuit in Figure 31, resistor ratios
have been adjusted to compensate for this gain error. By adjusting the gain of each multiplexer circuit the error
can be reduced to the tolerance of the resistors used (1% in this example).
Figure 31. Multiplexer Gain Compensation
NOTE
Disabling of the LMH6570 using the EN pin is not recommended for use when doing
multiplexer expansion. While disabled, If the voltage between the selected input and the
chip output exceeds approximately 2 V the device will begin to enter a soft breakdown
state. This will show up as reduced input to output isolation. The signal on the non-
inverting input of the output driver amplifier will leak through to the inverting input, and
then to the output through the feedback resistor. The worst case is a gain of 1
configuration where the non-inverting input follows the active input buffer and (through the
feedback resistor) the inverting input follows the voltage driving the output stage. The
solution for this is to use shutdown mode for multiplexer expansion.
7.2.4 Other Applications
The LMH6570 could support a dual antenna receiver with two physically separate antennas. Monitoring the
signal strength of the active antenna and switching to the other antenna when a fade is detected is a simple way
to achieve spacial diversity. This method gives about a 3 dB boost in average signal strength and is the least
expensive method for combining signals.
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Typical Application (continued)
7.2.5 Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 32 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
Figure 33 gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The
values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This gives a
good compromise between settling time and bandwidth. For applications where maximum frequency response is
needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values.
R
OUT
V
OUT
45:
C
R
L
L
LMH6570
10 pF
1 k:
Figure 32. Decoupling Capacitive Loads
90
80
70
60
50
40
30
20
2
C
= 8.6 pF, R
= 63:
V
= ±5V
L
OUT
S
LOAD = 1 k:ꢀ|| C
L
0
C
C
= 18 pF, R
= 56 pF, R
= 48:
= 24:
L
L
L
OUT
-2
OUT
-4
-6
C
= 100 pF, R = 19:
OUT
V
= 1 V
PP
OUT
C
|| 1 k:
L
S
V
-8
V
A
= ±5V
= 2 (V/V)
10
0
-10
1
10
100
1000
1
10
100
1000
CAPACTIVE LOAD (pF)
FREQUENCY (MHz)
Figure 33. Suggested ROUT vs. Capacitive Load
Figure 34. Frequency Response vs. Capacitive Load
7.2.6 ESD Protection
The LMH6570 is protected against electrostatic discharge (ESD) on all pins. The LMH6570 will survive 2000-V
Human Body model and 200-V Machine model events. Under normal operation the ESD diodes have no effect
on circuit performance. However, there are occasions when the ESD diodes will be evident. If the LMH6570 is
driven by a large signal while the device is powered down, the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device. Therefore,
it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one
way to conserve power and still prevent unexpected operation.
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8 Power Supply Recommendations
8.1 Power Dissipation
The LMH6570 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package. To ensure maximum output drive and highest performance, thermal shutdown is not provided.
Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power
dissipation.
Follow these steps to determine the maximum power dissipation for the LMH6570:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS),
where
•
VS = V+ - V−
(1)
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms ((VS - VOUT) * IOUT
)
where
•
•
VOUT and IOUT are the voltage across
The current through the external load and VS is the total supply voltage
(2)
(3)
3. Calculate the total RMS power:
PT = PAMP + PD
The maximum power that t-he LMH6570 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ RθJA
where
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SOIC package RθJA is 150 °C/W
R
(4)
9 Layout
9.1 Layout Guidelines
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins.
For long signal paths controlled impedance lines should be used, along with impedance matching elements at
both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each
rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the
device, whereas the smaller ceramic capacitors should be placed as close to the device as possible. In
Figure 25, the capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion.
Another way to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply
bypass.
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
•
•
Current Feedback Loop Gain Analysis and Performance Enhancement, Application Note OA-13 (SNOA366)
IC Package Thermal Metrics Application Report (SPRA953)
10.2 Trademarks
All trademarks are the property of their respective owners.
10.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6570MA/NOPB
LMH6570MAX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMH65
70MA
ACTIVE
2500 RoHS & Green
SN
LMH65
70MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6570MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMH6570MAX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6570MA/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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