LMH6580VS/NOPB [TI]
具有可选增益的 5V、交叉点/交换、8 输入 4 输出 500MHz 开关 | PFB | 48 | -40 to 85;
| 型号： | LMH6580VS/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可选增益的 5V、交叉点/交换、8 输入 4 输出 500MHz 开关 | PFB | 48 | -40 to 85 开关 |
| 文件： | 总31页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6580, LMH6581
www.ti.com
SNOSAY4C –AUGUST 2007–REVISED MAY 2013
LMH6580/LMH6581 8x4 500 MHz Analog Crosspoint Switch, Gain of 1,
Gain of 2
Check for Samples: LMH6580, LMH6581
1
FEATURES
DESCRIPTION
The LMH™ family of products is joined by the
LMH6580 and the LMH6581, high speed, non-
blocking, analog, crosspoint switches. The
23
•
8 Inputs and 4 Outputs
48-pin TQFP Package
•
•
−3 dB Bandwidth (VOUT = 2 VPP, RL = 1 kΩ)
LMH6580/LMH6581 are designed for high speed, DC
coupled, analog signals such as high resolution video
(UXGA and higher). The LMH6580/LMH6581 each
has eight inputs and four outputs. The non-blocking
architecture allows any output to be connected to any
input, including an input that is already selected. With
fully buffered inputs the LMH6580/LMH6581 can be
impedance matched to nearly any source impedance.
The buffered outputs of the LMH6580/LMH6581 can
drive up to two back terminated video loads (75Ω
load). The outputs and inputs also feature high
impedance inactive states allowing high performance
input and output expansion for array sizes such as 8
x 8 or 16 x 4 by combining two devices. The
LMH6580/LMH6581 are controlled with a 4 pin serial
interface that can be configured as a 3 wire interface.
Both serial mode and addressed modes are
available.
500 MHz
•
−3 dB Bandwidth (VOUT = 2 VPP, RL = 150Ω)
450 MHz
•
•
Fast Slew Rate 2100 V/μs
Channel to Channel Crosstalk (10/100 MHz)
−70/ −52 dBc
•
•
•
All Hostile Crosstalk (10/100 MHz) −55/−45 dBc
Easy to Use Serial Programming 4 Wire Bus
Two Programming Modes Serial & Addressed
Modes
•
•
•
Symmetrical Pinout Facilitates Expansion.
Output Current ±70 mA
Two Gain Options AV = 1 or AV = 2
APPLICATIONS
The LMH6580/LMH6581 come in 48-pin TQFP
packages. They also have diagonally symmetrical pin
assignments to facilitate double sided board layouts
and easy pin connections for expansion.
•
•
•
•
•
•
•
•
Studio Monitoring/Production Video Systems
Conference Room Multimedia Video Systems
KVM (Keyboard Video Mouse) Systems
Security/Surveillance Systems
Multi-Antenna Diversity Radio
Video Test Equipment
Medical Imaging
Wide-Band Routers & Switches
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH6580, LMH6581
SNOSAY4C –AUGUST 2007–REVISED MAY 2013
www.ti.com
Connection Diagram
GND
IN4
VEE
OUT3
GND
VCC
GND
VEE
IN5
VCC
GND
OUT2
VEE
VCC
VCC
IN6
VEE
VEE
IN7
BCST
CFG
CLK
GND
DOUT
Block Diagram
SWITCH
MATRIX
36
CONFIGURATION
REGISTER
CFG
BCST
DATA IN
RST
16
LOAD
DATA OUT
REGISTER
CS
CLK
MODE
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNOSAY4C –AUGUST 2007–REVISED MAY 2013
ABSOLUTE MAXIMUM RATINGS(1)(2)
ESD Tolerance(3)
Human Body Model
Machine Model
2000V
200V
VS
±6V
IIN (Input Pins)
±20 mA
IOUT
See(4)
Input Voltage Range
Maximum Junction Temperature
Storage Temperature Range
Soldering Information
V− to V+
+150°C
−65°C to +150°C
235°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical
Characteristics and ±5V Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum output current (IOUT) is determined by device power dissipation limitations. The maximum power dissipation is a function
of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for
packages soldered directly onto a PC Board.
OPERATING RATINGS(1)
Temperature Range(2)
−40°C to +85°C
±3V to ±5.5V
44°C/W
Supply Voltage Range
Thermal Resistance 48-Pin TQFP
θJA
θJC
12°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical
Characteristics and ±5V Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
±3.3V ELECTRICAL CHARACTERISTICS(1)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Frequency Domain Performance
SSBW
LSBW
−3 dB Bandwidth
VOUT = 0.5 VPP
LMH6580 VOUT = 1 VPP
LMH6581 V OUT = 2 VPP, RL = 1 kΩ
LMH6580 VOUT = 1 VPP
LMH6581 VOUT = 2 VPP, RL = 150Ω
LMH6580 VOUT = 1 VPP
425
500
,
MHz
MHz
,
450
70
GF
0.1 dB Gain Flatness
,
LMH6581 V OUT = 2 VPP, RL = 150Ω
Time Domain Response
tr
Rise Time
LMH6580 1V Step, LMH6581
2V Step, 10% to 90%
3.1
1.4
ns
ns
tf
Fall Time
LMH6580 1V Step, LMH6581
2V Step, 10% to 90%
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensured parametric performance is
indicated in the electrical tables under conditions different than those tested.
(2) Room Temperature limits are 100% production tested at 25°C. Factory testing conditions result in very limited self-heating of the device
such that TJ = TA. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC)
methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Copyright © 2007–2013, Texas Instruments Incorporated
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±3.3V ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
Symbol
OS
Parameter
Conditions
Min(2)
Typ(3)
<1
Max(2)
Units
%
Overshoot
Slew Rate
Slew Rate
2V Step
SR
LMH6580, 2 VPP, 40% to 60%(4)
LMH6581, 2 VPP, 40% to 60%(4)
2V Step, VOUT within 0.5%
900
1700
7
V/µs
V/µs
ns
ts
Settling Time
Distortion And Noise Response
HD2
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Input Referred Voltage Noise
Input Referred Noise Current
Crosstalk
2 VPP, 10 MHz
2 VPP, 10 MHz
>1 MHz
−76
−76
12
dBc
dBc
nV/ √Hz
pA/ √Hz
dBc
in
>1 MHz
2
XTLK
ISOL
All Hostile, f = 100 MHz
f = 100 MHz
−45
−60
Off Isolation
dBc
Static, DC Performance
AV
Gain
LMH6581
LMH6580
1.986
0.994
2.00
1.00
±3
2.014
1.005
±17
VOS
TCVOS
IB
Input Offset Voltage
mV
µV/°C
µA
Input Offset Voltage Average Drift
Input Bias Current
See(5)
Non-Inverting(6)
38
−5
TCIB
VO
Input Bias Current Average Drift
Output Voltage Range
Non-Inverting(5)
−12
±2.1
±1.3
±2.2
±1.3
−45
50
nA/°C
LMH6581, RL = 100Ω
LMH6580, RL = 100Ω
LMH6581, RL = ∞Ω,(7)
LMH6580 RL = ∞Ω,
±1.8
±1.24
±2.08
±1.25
V
V
VO
Output Voltage Range
PSRR
ICC
Power Supply Rejection Ratio
Positive Supply Current
Negative Supply Current
Tri State Supply Current
dBc
mA
mA
mA
RL = ∞
60
56
13
IEE
RL = ∞
50
RST Pin > 2.0V
10
Miscellaneous Performance
RIN
CIN
RO
RO
Input Resistance
Non-Inverting
Non-Inverting
Closed Loop, Enabled
LMH6580
100
1
kΩ
pF
Input Capacitance
Output Resistance Enabled
Output Resistance Disabled
300
50
mΩ
kΩ
LMH6581
1100
2.0
1350
±1.3
1500
CMVR
IO
Input Common Mode Voltage
Range
V
Output Current
Sourcing, VO = 0 V
±50
mA
Digital Control
VIH
VIL
Input Voltage High
V
V
Input Voltage Low
Output Voltage High
Output Voltage Low
Switching Time
Setup Time
0.8
VOH
VOL
>2.0
<0.4
15
V
V
ns
ns
ns
TS
TH
7
Hold Time
7
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
(7) This parameter is specified by design and/or characterization and is not tested in production.
4
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SNOSAY4C –AUGUST 2007–REVISED MAY 2013
±5V ELECTRICAL CHARACTERISTICS(1)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Frequency Domain Performance
(4)
SSBW
−3 dB Bandwidth
VOUT = 0.5 VPP
450
500
LMH6580 VOUT = 1 VPP
,
LMH6581 VOUT = 2 VPP, RL = 1 kΩ
MHz
MHz
LSBW
GF
LMH6580 VOUT = 1 VPP
,
450
100
LMH6581 VOUT = 2 VPP, RL = 150Ω
0.1 dB Gain Flatness
LMH6580, VOUT = 1 VPP,
LMH6581, VOUT = 2 VPP, RL = 150Ω
RL = 150Ω, 3.58 MHz/4.43 MHz
RL = 150Ω, 3.58 MHz/4.43 MHz
DG
DP
Differential Gain
.05
.05
%
Differential Phase
deg
Time Domain Response
tr
Rise Time
LMH6580 2V, Step, 10% to 90%
LMH6581 2V, Step, 10% to 90%
2V Step, 10% to 90%
2.8
1.2
ns
tf
Fall Time
1.6
ns
%
OS
SR
SR
ts
Overshoot
Slew Rate
Slew Rate
Settling Time
2V Step
<1
LMH6580, 2 VPP, 40% to 60%(5)
LMH6581, 6 VPP, 40% to 60%(5)
2V Step, VOUT Within 0.5%
1200
2100
6
V/µs
V/µs
ns
Distortion And Noise Response
HD2
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Input Referred Voltage Noise
Input Referred Noise Current
Cross Talk
2 VPP, 5 MHz
−80
−70
12
dBc
dBc
2 VPP, 5 MHz
>1 MHz
nV/ √Hz
pA/ √Hz
dBc
in
>1 MHz
2
XTLK
All Hostile, f = 100 MHz
Channel to Channel, f = 100 MHz
f = 100 MHz
−45
−52
−65
dBc
ISOL
Off Isolation
dBc
Static, DC Performance
AV
Gain
LMH6581
LMH6580
1.986
0.995
2.00
1.00
±2
2.014
1.005
±17
Vos
Input Offset Voltage
mV
µV/°C
µA
TCVos
IB
Input Offset Voltage Average Drift
Input Bias Current
See(6)
38
Non-Inverting(7)
Non-Inverting(6)
LMH681, RL = 100Ω
LMH6580, RL = 100Ω
LMH6581, RL = ∞Ω
LMH6580, RL = ∞Ω
DC
−5
±12
TCIB
VO
Input Bias Current Average Drift
Output Voltage Range
−12
±3.6
±3.0
±3.9
±3.0
−45
nA/°C
±3.4
±2.9
±3.7
±2.9
−42
V
VO
Output Voltage Range
V
PSRR
Power Supply Rejection Ratio
dBc
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensured parametric performance is
indicated in the electrical tables under conditions different than those tested.
(2) Room Temperature limits are 100% production tested at 25°C. Factory testing conditions result in very limited self-heating of the device
such that TJ = TA. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC)
methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Slew Rate is the average of the rising and falling edges.
(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(7) Negative input current implies current flowing out of the device.
Copyright © 2007–2013, Texas Instruments Incorporated
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±5V ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
Symbol
XTLK
OISO
ICC
Parameter
DC Crosstalk Rejection
DC Off Isloation
Conditions
DC, Channel to Channel
DC
Min(2)
−62
Typ(3)
−90
−90
54
Max(2)
Units
dBc
dBc
mA
−60
Positive Supply Current
Negative Supply Current
Tri State Supply Current
RL = ∞
66
62
17
IEE
RL = ∞
50
mA
RST Pin > 2.0V
14
mA
Miscellaneous Performance
RIN
CIN
RO
RO
Input Resistance
Non-Inverting
100
1
kΩ
pF
Input Capacitance
Non-Inverting
Output Resistance Enabled
Output Resistance Disabled
Closed Loop, Enabled
LMH6580, Resistance to Ground
LMH6581, Resistance to Ground
300
50
mΩ
kΩ
1100
1300
±3.0
1500
CMVR
IO
Input Common Mode Voltage
Range
V
Output Current
Sourcing, VO = 0 V
±60
2.0
±70
mA
Digital Control
VIH
VIL
Input Voltage High
V
V
Input Voltage Low
Output Voltage High
Output Voltage Low
Switching Time
Setup Time
0.8
VOH
VOL
>2.4
<0.4
15
V
V
ns
ns
ns
TS
TH
5
Hold Time
5
6
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SNOSAY4C –AUGUST 2007–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS LMH6580
1 VPP Frequency Response
1 VPP Frequency Response
1
0
1
0
GAIN
GAIN
-1
-2
-1
-2
0
0
PHASE
+
PHASE
+
-3
-4
-5
-6
-7
-45
-90
-135
-180
-225
-3
-4
-5
-6
-7
-45
-90
-135
-180
-225
V
= +5V
V
= +3.3V
-
-
V = -5V
= 1 V
V = -3.3V
V
V
= 1 V
OUT
PP
OUT
PP
R
L
= 150W
R
L
= 150W
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1.
Figure 2.
1 VPP Frequency Response Broadcast
1 VPP Frequency Response Broadcast
2
1
1
0
GAIN
GAIN
0
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
0
0
PHASE
PHASE
-45
-45
-90
-90
+
+
V
= +5V
V
= +3.3V
-
-
-135
-135
V = -5V
V = -3.3V
V
= 1 V
PP
V
= 1 V
PP
OUT
OUT
-180
-225
-180
-225
R
= 150W
R
= 150W
L
L
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Frequency Response 1 kΩ Load
Frequency Response 1kΩ Load
1
0
1
0
GAIN
GAIN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
0
0
PHASE
= +3.3V
PHASE
-45
-45
+
-
-90
-90
V
+
V
= +5V
V = -3.3V
-
-135
-180
-225
-135
-180
-225
V = -5V
= 1 V
V
= 1 V
PP
OUT
V
OUT
= 1 kW
PP
R
L
= 1 kW
R
L
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued)
Frequency Response with Input Expansion
Frequency Response with Input Expansion
2
1
1
0
GAIN
GAIN
0
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
0
0
PHASE
= +5V
PHASE
= +3.3V
-45
-90
-135
-180
-225
-45
-90
-135
+
-
+
-
V
V
V = -5V
V = -3.3V
V
= 1 V
PP
V
= 1 V
PP
OUT
OUT
-180
-225
R
L
= 150W
R
L
= 150W
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7.
Figure 8.
2 VPP Pulse Response
2 VPP Pulse Response
1.5
1
1.5
1
0.5
0
0.5
0
+
+
V
= +5V
-0.5
-1
-0.5
-1
V
= +3.3V
-
-
V = -5V
= 100W
V = -3.3V
= 100W
R
R
L
L
SINGLE CHANNEL
SINGLE CHANNEL
-1.5
-1.5
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
Figure 9.
Figure 10.
2 VPP Pulse Response, Broadcast Mode
1.5
2 VPP Pulse Response, Broadcast Mode
1.5
1
1
0.5
0.5
0
0
+
+
V
= +5V
V
= +3.3V
-
-
V = -5V
= 100W
V = -3.3V
= 100W
-0.5
-1
-0.5
-1
R
R
L
L
BROADCAST
BROADCAST
-1.5
-1.5
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
Figure 11.
Figure 12.
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SNOSAY4C –AUGUST 2007–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued)
1 VPP Pulse Response
1 VPP Pulse Response
0.75
0.5
0.75
0.5
0.25
0
0.25
0
+
+
V
= +3.3V
-0.25
-0.5
-0.75
V
= +5V
-0.25
-0.5
-0.75
-
-
V = -3.3V
= 100W
V = -5V
= 100W
R
L
R
L
SINGLE CHANNEL
SINGLE CHANNEL
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
Figure 13.
Figure 14.
Channel to Channel Crosstalk
All Hostile Crosstalk
-40
-50
-30
-40
-50
INPUTS ONLY
-60
OUTPUTS ONLY
-60
-70
-70
-80
-80
-90
INPUTS & OUTPUTS
-90
-100
-100
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15.
Figure 16.
Second Order Distortion (HD2) vs. Frequency
Third Order Distortion (HD3) vs. Frequency
-50
-50
+
+
V
= +5V
V = +5V
-
-
V = -5V
V = -5V
-60
-60
R
= 100W
R = 100W
L
L
V
= 3V
OUT
-70
-80
-70
-80
V
= 1V
V
= 3V
OUT
OUT
V
= 1V
OUT
V
= 0.5V
OUT
-90
-90
V
= 0.5V
OUT
-100
-100
10
100
10
100
1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17.
Figure 18.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued)
Second Order Distortion (HD2) vs. Frequency
Third Order Distortion (HD3) vs. Frequency
-50
-50
+
-
+
-
V
= +3.3V
V
= +3.3V
V
= 2V
OUT
V = -3.3V
V = -3.3V
-60
-60
R
= 100W
R = 100W
L
L
-70
-80
-70
-80
V
= 1V
V
= 2V
OUT
OUT
V
= 1V
OUT
V
= 0.5V
OUT
-90
-90
V
= 0.5V
OUT
-100
-100
10
100
10
100
1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19.
Figure 20.
Positive Voltage Swing over Temperature
Negative Voltage Swing over Temperature
3.5
-2.5
+
+
V
= +5V
V
= +5V
-
100°C
-
V = -5V
V = -5V
100W LOAD
100W LOAD
3.25
-2.75
25°C
-40°C
100°C
3
2.75
2.5
-3
-3.25
-3.5
-40°C
25°C
-3.5
-3.25
-3
-2.75
-2.5
2.5
2.75
3
3.25
3.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 21.
Figure 22.
Positive Voltage Swing over Temperature
Negative Voltage Swing over Temperature
1.75
-0.75
+
+
100°C
V
= +3.3V
V
= +3.3V
-
-
V = -3.3V
V = -3.3V
25°C
100W LOAD
100W LOAD
1.5
-1
-40°C
1.25
1
-1.25
-1.5
-40°C
25°C
100°C
0.75
0.75
-1.75
-1.75
-1.5
-1.25
-1
-0.75
1
1.25
1.5
1.75
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 23.
Figure 24.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued)
Enabled Output Impedance
Enabled Output Impedance
100
10
100
+
-
+
-
V
= +5V
V
= +3.3V
V = -5V
V = -3.3V
10
1
1
0.1
0.1
0.1
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25.
Figure 26.
Disabled Output Impedance
Disabled Output Impedance
100
10
100
10
+
+
V
= +3.3V
V
= +5V
-
-
V = -3.3V
V = -5V
1
1
0.1
0.01
0.1
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27.
Figure 28.
Switching Time
1
0.5
0
4
3.5
3
2.5
2
1.5
1
-0.5
-1
0.5
CFG
0
DISABLE TO ENABLE
-0.5
ENABLE TO DISABLE
-1.5
-1
-50 -40 -30 -20 -10
0
10 20 30 40 50
TIME (ns)
Figure 29.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6581
2 VPP Frequency Response
2 VPP Frequency Response
1
0
1
0
GAIN
GAIN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
0
0
PHASE
PHASE
-45
-90
-135
-180
-225
-45
-90
-135
V
V
= ±5V
V
V
= ±3.3V
S
S
= 2 V
= 2 V
PP
OUT
PP
OUT
-180
-225
R
L
= 150W
R
L
= 150W
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30.
Figure 31.
Large Signal Bandwidth
Large Signal Bandwidth
1
0
1
0
GAIN
GAIN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
0
0
PHASE
PHASE
-45
-90
-135
-180
-225
-45
-90
-135
-180
-225
V
V
= ±5V
S
V
V
= ±3.3V
S
= 2 V
OUT
PP
= 2 V
PP
OUT
R
= 1 kW
L
R = 1 kW
L
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 32.
Figure 33.
Small Signal Bandwidth
Small Signal Bandwidth
1
0
1
0
135
90
GAIN
GAIN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
45
0
0
PHASE
PHASE
+
-45
-90
-135
-180
-225
-45
-90
-135
-180
-225
V
= +3.3V
-
V
V
= ±5V
V = -3.3V
= 0.5 V
S
= 0.5 V
PP
V
OUT
OUT
= 150W
PP
R
= 150W
R
L
L
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34.
Figure 35.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued)
Frequency Response 1 kΩ Load
Group Delay
1
0
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
V
V
= ±5V
S
GAIN
= 1V
OUT
V
S
= ±5V
-1
-2
-3
-4
-5
-6
-7
V
S
= ±3.3V
0
PHASE
-45
-90
-135
-180
-225
V
= ±3.3V
100
S
V
= 2 V
PP
OUT
R
= 1 kW
L
1000
10
0
100
200
300
400
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36.
Figure 37.
2 VPP Pulse Response
2 VPP Pulse Response
1.5
1.0
1.5
1
V
= ±3.3V
SINGLE CHANNEL
S
0.5
0.5
0.0
0
-0.5
-0.5
+
-
V
= +5V
V = -5V
-1
-1.0
-1.5
R
L
= 100W
SINGLE CHANNEL
-1.5
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
5
10 15 20 25 30 35 40
TIME (ns)
Figure 38.
Figure 39.
4 VPP Pulse Response
4 VPP Pulse Response Broadcast
2.5
2
2.5
2.0
1.5
V
= ±5V
S
BROADCAST
1.5
1
1.0
0.5
0.5
0
0.0
-0.5
-1
-0.5
-1.0
-1.5
-2
-1.5
V
= ±5V
S
-2.0
-2.5
SINGLE CHANNEL
-2.5
0
5
10
15
20
25
30
0
5
10 15 20 25 30 35 40
TIME (ns)
TIME (ns)
Figure 41.
Figure 40.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued)
4 VPP Pulse Response
6 VPP Pulse Response
2.5
2.0
1.5
4
3
2
1.0
0.5
1
0.0
0
-0.5
-1.0
-1
-2
-3
-4
-1.5
V
= ±3.3V
S
V
S
= ±5V
-2.0
-2.5
SINGLE CHANNEL
SINGLE CHANNEL
0
5
10 15 20 25 30 35 40
TIME (ns)
0
5
10 15 20 25 30 35 40
TIME (ns)
Figure 42.
Figure 43.
Off Isolation
All Hostile Crosstalk
-40
-50
-30
-40
-50
OUTPUTS ONLY
-60
INPUTS ONLY
-60
-70
-70
-80
-80
-90
INPUTS & OUTPUTS
-90
-100
-100
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 44.
Figure 45.
Second Order Distortion (HD2) vs. Frequency
Third Order Distortion (HD3) vs. Frequency
-60
-55
+
V
= +5V
-
-65
-70
-60
V = -5V
V
= 2V
OUT
R
L
= 100W
-65
V
= 4V
V
= 0.5V
OUT
OUT
-85
-80
-85
-90
-95
-70
-75
-80
-85
-90
V
= 2V
OUT
V
OUT
= 4V
+
V
= +5V
-
V = -5V
= 100W
V
= 0.5V
OUT
R
L
10
100
10
100
1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 46.
Figure 47.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued)
Second Order Distortion vs. Frequency
Third Order Distortion vs. Frequency
-55
-55
-60
-65
+
V
= +3.3V
-
-60
-65
V = -3.3V
= 100W
V
= 2V
OUT
R
L
V
= 3V
OUT
V
= 0.5V
OUT
-70
-75
-80
-85
-90
-70
-75
-80
-85
-90
V
= 2V
OUT
V
= 4V
OUT
+
V
= +5V
V
= 0.5V
OUT
-
V = -5V
= 100W
R
L
10
100
10
100
1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 48.
Figure 49.
No Load Output Swing
Positive Swing over Temperature
3.75
3.5
4
3
100°C
V
= ±5V
S
NO LOAD
2
-40°C
25°C
1
3.25
3
0
-1
-2
-3
-4
+
V
= +5V
-
V = -5V
100W LOAD
2.75
-3
-2
-1
1
2
3
0
1.5
1.75
2
2.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 50.
Figure 51.
Negative Swing Over Temperature
No Load Output Swing
-2.25
2.5
2
+
V
= +5V
V
= ±3.3V
S
-
V = -5V
NO LOAD
1.5
1
100W LOAD
-3
-3.25
-3.5
0.5
0
-0.5
-1
25°C
-40°C
-1.5
-2
100°C
-3.75
-2.5
-2
-1
0
1
2
-2.25
-2
-1.75
-1.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 52.
Figure 53.
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TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued)
Positive Swing over Temperature
Negative Swing over Temperature
2.25
2
-1.25
+
V
= +3.3V
100°C
-
V = -3.3V
100W LOAD
-1.5
-40°C
25°C
1.75
1.5
-1.75
-2
25°C
-40°C
+
V
= +3.3V
-
V = -3.3V
100W LOAD
100°C
1.25
0.75
-2.25
1
1.25
1.5
-1.5
-1.25
-1
-0.75
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 54.
Figure 55.
Enabled Output Impedance
Disabled Output Impedance
100
10
10000
1000
100
10
1
0.1
0.01
1
0.1
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 56.
Figure 57.
Switching Time
1
0.5
0
4
3.5
3
2.5
2
1.5
1
-0.5
-1
0.5
CFG
0
DISABLE TO ENABLE
-0.5
ENABLE TO DISABLE
-1.5
-1
-50 -40 -30 -20 -10
0
10 20 30 40 50
TIME (ns)
Figure 58.
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APPLICATION INFORMATION
INTRODUCTION
The LMH6580/LMH6581 are high speed, fully buffered, non- blocking, analog crosspoint switches. Having fully
buffered inputs allows the LMH6580/LMH6581 to accept signals from low or high impedance sources without the
worry of loading the signal source. The fully buffered outputs will drive 75Ω or 50Ω back terminated transmission
lines with no external components other than the termination resistor. When disabled, the outputs are in a high
impedance state. The LMH6580/LMH6581 can have any input connected to any (or all) output(s). Conversely, a
given output can have only one associated input.
INPUT AND OUTPUT EXPANSION
The LMH6580/LMH6581 have high impedance inactive states for both inputs and outputs allowing maximum
flexibility for crosspoint expansion. In addition the LMH6580/LMH6581 employ diagonal symmetry in pin
assignments. The diagonal symmetry makes it easy to use direct pin to pin vias when the parts are mounted on
opposite sides of a board. As an example two LMH6580/LMH6581 chips can be combined on one board to form
either an 8 x 8 crosspoint or a 16 x 4 crosspoint. To make an 8 x 8 crosspoint all 8 input pins would be tied
together (Input 0 on side 1 to input 7 on side 2 and so on) while the 4 output pins on each chip would be left
separate. To make the 16 x 4 crosspoint, the 4 outputs would be tied together while all 16 inputs would remain
independent. In the 16 x 4 configuration it is important not to have 2 connected outputs active at the same time.
With the 8 x 8 configuration, on the other hand, having two connected inputs active is a valid state. Crosspoint
expansion as detailed above has the advantage that the signal will go through only one crosspoint. Expansion
methods that have cascaded stages will suffer bandwidth loss far greater than the small loading effect of parallel
expansion.
Output expansion as shown in Figure 59 is very straight forward. Connecting the inputs of two crosspoint
switches has a very minor impact on performance. Input expansion requires more planning. Input expansion, as
show in Figure 60 and Figure 61 gives the option of two ways to connect the outputs of the crosspoint switches.
In Figure 60 the crosspoint switch outputs are connected directly together and share one termination resistor.
This is the easiest configurarion to implement and has only one drawback. Because the disabled output of the
unused crosspoint (only one output can be active at a time) has a small amount of capacitance, the frequency
response of the active crosspoint will show peaking. This is illustrated in Figure 62 and Figure 63. In most cases
this small amount of peaking is not a problem.
As illustrated in Figure 61 each crosspoint output can be given its own termination resistor. This results in a
frequency response nearly identical to the non expansion case. There is one drawback for the gain of 2
crosspoint, and that is gain error. With a 75Ω termination resistor the 1250Ω resistance of the disabled crosspoint
output will cause a gain error. In order to counter act this the termination resistors of both crosspoints should be
adjusted to approximately 80Ω. This will provide very good matching, but the gain accuracy of the system will
now be dependent on the process variations of the crosspoint resistors which have a variability of approximately
±20%.
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1
2
3
4
1
2
1
IN
OUT
4 x 4
3
4
2
3
4
1
5
2
3
6
7
8
4 x 4
IN
OUT
4
Figure 59. Output Expansion
1
1
2
1
2
4 x 4
IN
OUT
3
4
3
4
2
3
5
6
1
2
4
4 x 4
IN
OUT
3
4
7
8
Figure 60. Input Expansion with Shared Termination Resistors
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1
2
1
2
1
4 x 4
OUT
IN
3
4
3
4
2
3
4
5
6
1
2
4 x 4
IN
OUT
3
4
7
8
Figure 61. Input Expansion with Separate Termination Resistors
2
OUTPUT CONNECTED DIRECTLY
1
0
-1
NO EXPANSION
-2
-3
-4
-5
V
V
= ±3.3V
S
-6
-7
-8
= 2 V
OUT
PP
R
= 150W
L
1
10
100
1000
FREQUENCY (MHz)
Figure 62. Input Expansion Frequency Response
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2
OUTPUTS CONNECTED DIRECTLY
1
0
-1
-2
-3
-4
-5
CONNECTED THROUGH 71W
RESISTORS
+
V
= +5V
-
V = -5V
V
= 2 V
OUT
PP
-6
-7
R
= 150W
L
1
10
100
1000
FREQUENCY (MHz)
Figure 63. Input Expansion Frequency Response
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Capacitive loads
of 5 pF to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
Since most capacitive loading is due to undesired parasitic capacitances the values of the capacitive loading will
not usually be known exactly. It is best to start with a conservative value of ROUT and decrease the value until the
bandwidth shows slight peaking. At this point the value of the isloation resistor will be determined by whether flat
frequency response or maximum bandwidth is the desired goal. Smaller values of ROUT will produce some
peaking, but maximum bandwidth. Larger resistor values will decrease bandwidth and suppress peaking.
As starting values, a capacitive load of 5 pF should have around 75 Ω of isolation resistance. A value of 120 pF
would require around 12Ω. When driving transmission lines, the output termination resistor is normally sufficient.
USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH AND INCREASE REBIABILITY
The LMH6580/LMH6581 crosspoint switch can offer enhanced bandwidth and reliability with the use of external
buffers on the outputs. The bandwidth is increased by unloading the outputs and driving the high impedance of
an external buffer. See the Frequency Response 1 kΩ Load curve in Typical Performance section for an example
of bandwidth achieved with less loading on the outputs. For this technique to provide maximum benefit a very
high speed amplifier such as the LMH6703 should be used. As shown in Figure 64 the resistor RL is placed
between the crosspoint output and the buffer amplifier. This resistor will provide a load for the crosspoint output
buffer and reduce peaking caused by the buffer input capacitance. A recommended value for RL is 500Ω to
1000Ω. Higher values of RL will give higher bandwidth, but also higher peaking. The optimum value of RL will
depend greatly on board layout and the input capacitance of the buffer amplifier.
Besides offering enhanced bandwidth performance using an external buffer provides greater system reliability.
The first advantage is to reduce thermal loading on the crosspoint switch. This reduced die temperature will
increase the life of the crosspoint. The second advantage is enhanced ESD reliability. It is very difficult to build
high speed devices that can withstand all possible ESD events. With external buffers the crosspoint switch is
isolated from ESD events on the external system connectors.
LMH6703
+
-
V
OUT
R
L
LMH6583
OUTPUT
BUFFER
560W
560W
1 kW
Figure 64. Buffered Output
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CROSSTALK
When designing a large system such as a video router crosstalk can be a very serious problem. Extensive
testing in our lab has shown that most crosstalk is related to board layout rather than occurring in the crosspoint
switch. There are many ways to reduce board related crosstalk. Using controlled impedance lines is an important
step. Using well decoupled power and ground planes will help as well. When crosstalk does occur within the
crosspoint switch itself it is often due to signals coupling into the power supply pins. Using appropriate supply
bypassing will help to reduce this mode of coupling. Another suggestion is to place as much grounded copper as
possible between input and output signal traces. Care must be taken, though, not to influence the signal trace
impedances by placing shielding copper too closely. One other caveat to consider is that as shielding materials
come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low. Using
thin signal traces will result in unacceptable losses due to trace resistance. This effect becomes even more
pronounced at higher frequencies due to the skin effect. The skin effect reduces the effective thickness of the
trace as frequency increases. Resistive losses make crosstalk worse because as the desired signal is attenuated
with higher frequencies crosstalk increases at higher frequencies.
DIGITAL CONTROL
SWITCH
MATRIX
36
CONFIGURATION
REGISTER
CFG
BCST
DATA IN
RST
16
LOAD
REGISTER
DATA OUT
CS
CLK
MODE
Figure 65. Block Diagram
Table 1. Logic Pins
Pin Name
CLK
Level Sensitive
Edge Triggered
Triggered by
Yes
CS
Yes
Yes
Yes
CLK rising edge
CLK falling edge
CLK rising edge
DATA IN
DATA OUT
CFG
Yes
Yes
Yes
Yes
MODE
RST
BCST
There are two modes for programing the LMH6580/LMH6581, Serial Mode and Addressed Mode. The
LMH6580/LMH6581 have internal control registers that store the programming states of the crosspoint switch.
The logic is two staged to allow for maximum programming flexibility. The first stage of the control logic is tied
directly to the crosspoint switching matrix. This logic consists of one register for each output that stores the on/off
state and the address of which input to connect to. These registers are not directly accessible to the user. The
second level of logic is another bank of registers identical to the first, but set up as shift registers. These registers
are accessed by the user via the serial input bus.
The LMH6580/LMH6581 is programmed via a serial input bus with the support of four other digital control pins.
The Serial bus consists of a clock pin (CLK), a serial data in pin (DIN), and a serial data out pin (DOUT). The
serial bus is gated by a chip select pin (CS). The chip select pin is active low. While the chip select pin is high all
data on the serial input pin and clock pins is ignored. When the chip select pin is brought low the internal logic is
set to begin receiving data by the first positive transition (0 to 1) of the clock signal. The chip select pin must be
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brought low at least 5 ns before the first rising edge of the clock signal. The first data bit is clocked in on the next
negative transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the
clock signal. Once the last valid data has been clocked in, either the chip select pin must go high or, the clock
signal must stop. Otherwise invalid data will be clocked into the chip. The data clocked into the chip is not
transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of the state of
the MODE pin. The CFG pin is not dependent on the state of the Chip select pin. If no new data is clocked into
the chip subsequent pulses on the CFG pin will have no effect on device operation.
The programming format of the incoming serial data is selected by the MODE pin. When the MODE pin is HIGH
the crosspoint can be programmed one output at a time by entering a string of data that contains the address of
the output that is going to be changed (Addressed Mode). When the mode pin is LOW the crosspoint is in Serial
Mode. In this mode the crosspoint accepts a 16 bit array of data that programs all of the outputs. In both modes
the data fed into the chip does not change the chip operation until the Configure pin is pulsed high. The configure
and mode pins are independent of the chip select pin.
THREE WIRE VS. FOUR WIRE CONTROL
There are two ways to connect the serial data pins. The first way is to control all four pins separately, and the
second option is to connect the CFG and the CS pins together for a 3 wire interface. The benefit of the 4-wire
interface is that the chip can be configured independently using the CS pin. This would be an advantage in a
system with multiple crosspoint chips where all of them could be programmed ahead of time and then configured
simultaneously. The 4-wire solution is also helpful in a system that has a free running clock on the CLK pin. In
this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being
clocked into the chip.
The 3-wire option provides the advantage of one less pin to control at the expense of having less flexibility with
the configure pin. One way around this loss of flexibility would be if the clock signal is generated by an FPGA or
microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip select
function is provided by the presence or absence of the clock signal.
SERIAL PROGRAMMING MODE
Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 16-bits
programs all four outputs of the crosspoint. The data is fed to the chip as shown in Table 2 and Table 3 (two
tables are required to show the entire data frame). The table is arranged such that the first bit clocked into the
crosspoint register is labeled bit number 0. The register labeled Load Register in Figure 65 is a shift register. If
the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then
additional data will be shifted into the register, and the desired data will be shifted out.
Also illustrated is the timing relationships for the digital pins in Figure 66. It is important to note that all the pin
timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS)
must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to
synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high
after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid
data from being clocked into the chip. Another way to accomplish the same thing is to strobe the clock pin with
only the desired number of pulses starting and ending with clock in the low condition. The configure (CFG) pin
timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers.
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T
1
T
15
T
-1
T
T
T
16
T
0
T
12
13
14
1
CLK
0
T
S
T
S
1
CS_N
0
1
CFG
0
T
T
S
H
1
I...
I
I
14
I
15
I
12
I
16
DIN
I
I
1
13
0
0
1
MODE
0
T
D
1
OUT
I
0
I
1
D
0
Figure 66. Timing Diagram for Serial Mode
Table 2. Serial Mode Data Frame (First Two Words)(1)
Output 0
Output 1
Input Address
LSB
On = 0
Off = 1
3
Input Address
On = 0
Off = 1
7
MSB
2
LSB
4
LSB
0
1
5
6
(1) Off = TRI-STATE, Bit 0 is first bit clocked into device.
Table 3. Serial Mode Data Frame (Continued)
Output 2
Input Address
LSB
Output 3
On = 0
Off = 1
11
Input Address
LSB
On = 0
Off = 1
15
MSB
10
MSB
14
8
9
12
13
ADDRESSED PROGRAMMING MODE
Addressed programming mode makes it possible to change only one output register at a time. To utilize this
mode the mode pin must be High. All other pins function the same as in serial programming mode except that
the word clocked in is 5 bits and is directed only at the output specified. In addressed mode the data format is
shown below in Table 4.
Also illustrated is the timing relationships for the digital pins in Figure 67. It is important to note that all the pin
timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS)
must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to
synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high
after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid
data from being clocked into the chip. Also, in addressed mode is it necessary for the clock signal to make a low
to high transition after the chip select pin has been brought high. If there is not a low to high transition of the
clock after the chip select pin goes high subsequent data wil not be loaded into the chip properly. The configure
(CFG) pin timing is not critical, but it does need to be kept low until all data has been shifted into the crosspoint
registers.
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T
5
T
1
T
2
T
3
T
4
T
6
T
T
T
9
T
10
7
8
1
CLK
0
T
S
T
S
1
CS_N
0
1
CFG
0
T
T
H
S
1
DIN
0
T
A
0
A
1
I
2
I
1
I
0
1
MODE
0
1
OUT
HIGH IMPEDANCE
D
0
Figure 67. Timing Diagram for Addressed Mode
Table 4. Addressed Mode Word Format(1)
Output Address
Input Address
LSB
TRI-STATE
LSB
MSB
MSB
4
1 = TRI-STATE
0 = On
0
1
2
3
5
(1) Bit 0 is first bit clocked into device.
DAISY CHAIN OPTION IN SERIAL MODE
The LMH6580/LMH6581 supports daisy chaining of the serial data stream between multiple chips. This feature is
available only in the Serial Programming Mode. To use this feature serial data is clocked into the first chip DIN
pin, and the next chip DIN pin is connected to the DOUT pin of the first chip. Both chips may share a chip select
signal, or the second chip can be enabled separately. When the chip select pin goes low on both chips a double
length word is clocked into the first chip. As the first word is clocking into the first chip the second chip is
receiving the data that was originally in the shift register of the first chip (invalid data). When a full 16 bits have
been clocked into the first chip the next clock cycle begins moving the first frame of the new configuration data
into the second chip. With a full 32 clock cycles both chips have valid data and the chip select pin of both chips
should be brought high to prevent the data from overshooting. A configure pulse will activate the new
configuration on both chips simultaneously, or each chip can be configured separately. The mode, chip select,
configure and clock pins of both chips can be tied together and driven from the same sources.
SPECIAL CONTROL PINS
The LMH6580/LMH6581 have two special control pins that function independent of the serial control bus. One of
these pins is the reset (RST) pin. The RST pin is active high meaning that at logic 1 level the chip is configured
with all outputs disabled and in a high impedance state. The RST pin programs all the registers with input
address 0 and all the outputs are turned off. In this configuration the device draws only 11mA. The RST pin can
be used as a shutdown function to reduce power consumption. The other special control pin is the broadcast
(BCST) pin. The BCST pin is also active high and sets all the outputs to the on state connected to input 0. This is
sometimes referred to as broadcast mode, where input 0 is broadcast to all eight outputs.
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THERMAL MANAGEMENT
The LMH6580/LMH6581 are high performance devices that produce a significant amount of heat. With ±5V
supplies, the LMH6580/LMH6581 will dissipate approximately 0.5 W of idling power with all outputs enabled.
Idling power is calculated based on the typical supply current of 50 mA and a 10V supply voltage. This power
dissipation will vary within the range of 0.4 W to 0.6 W due to process variations. In addition, each equivalent
video load (150Ω) connected to the outputs should be budgeted 30 mW of power. For a typical application with
one video load for each output this would be a total power of 0.62 W. With a θJA of 44 °C/W this will result in the
silicon being 27°C over the ambient temperature. A more aggressive application would be two video loads per
output which would result in 0.74 W of power dissipation. This would result in a 33°C temperature rise. For
heavier loading, the TQFP package thermal performance can be significantly enhanced with an external heat
sink and by providing for moving air ventilation. Also, be sure to calculate the increase in ambient temperature
from all devices operating in the system case. Because of the high power output of this device, thermal
management should be considered very early in the design process. Generous passive venting and vertical
board orientation may avoid the need for fan cooling or heat sinks. Also, the LMH6580/LMH6581 can be
operated with a ±3.3V power supply. This will cut power dissipation substantially while only reducing bandwidth
by about 10% (2 VPP output). The LMH6580/LMH6581 are fully characterized and factory tested at the ±3.3V
power supply condition for applications where reduced power is desired.
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power supply and ground traces away from the input and
output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 for more information). If digital control lines must cross
analog signal lines (particularly inputs) it is best if they cross perpendicularly. Texas Instruments suggests the
following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Device
Package
Evaluation Board Part Number
LMH6580
48–Pin
LMH730164EF
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6580VS/NOPB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
LMH6580
VS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
LMH6580VS/NOPB
PFB
TQFP
48
250
10 x 25
150
315 135.9 7620 12.2
11.1 11.25
Pack Materials-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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