LMH6580VSX [TI]
IC 8-CHANNEL, CROSS POINT SWITCH, PQFP48, TQFP-48, Multiplexer or Switch;
| 型号： | LMH6580VSX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC 8-CHANNEL, CROSS POINT SWITCH, PQFP48, TQFP-48, Multiplexer or Switch |
| 文件： | 总25页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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information and details on our current products and services.
September 2007
LMH6580/LMH6581
8x4 500 MHz Analog Crosspoint Switch, Gain of 1,
Gain of 2
General Description
Features
The LMH® family of products is joined by the LMH6580 and
the LMH6581, high speed, non-blocking, analog, crosspoint
switches. The LMH6580/LMH6581 are designed for high
speed, DC coupled, analog signals such as high resolution
video (UXGA and higher). The LMH6580/LMH6581 each has
eight inputs and four outputs. The non-blocking architecture
allows any output to be connected to any input, including an
input that is already selected. With fully buffered inputs the
LMH6580/LMH6581 can be impedance matched to nearly
any source impedance. The buffered outputs of the
LMH6580/LMH6581 can drive up to two back terminated
video loads (75Ω load). The outputs and inputs also feature
high impedance inactive states allowing high performance in-
put and output expansion for array sizes such as 8 x 8 or 16
x 4 by combining two devices. The LMH6580/LMH6581 are
controlled with a 4 pin serial interface that can be configured
as a 3 wire interface. Both serial mode and addressed modes
are available.
8 inputs and 4 outputs
■
■
48-pin TQFP package
−3 dB bandwidth (VOUT = 2 VPP, RL = 1 kΩ)
−3 dB bandwidth (VOUT = 2 VPP, RL = 150Ω)
Fast slew rate
Channel to channel crosstalk (10/100 MHz) −70/ −52 dBc
All hostile crosstalk (10/100 MHz)
Easy to use serial programming
Two programming modes
Symmetrical pinout facilitates expansion.
Output current
500 MHz
450 MHz
2100 V/μs
■
■
■
■
■
■
■
■
■
■
−55/−45 dBc
4 wire bus
Serial & addressed modes
±70 mA
AV = 1 or AV = 2
Two gain options
Applications
Studio monitoring/production video systems
Conference room multimedia video systems
KVM (keyboard video mouse) systems
Security/surveillance systems
Multi-antenna diversity radio
■
■
■
■
■
■
■
■
The LMH6580/LMH6581 come in 48-pin TQFP packages.
They also have diagonally symmetrical pin assignments to
facilitate double sided board layouts and easy pin connec-
tions for expansion.
Video test equipment
Medical imaging
Wide-band routers & switches
Connection Diagram
Block Diagram
30007211
30007202
LMH® is a registered trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
300072
www.national.com
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
−65°C to +150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
235°C
260°C
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Operating Ratings (Note 1)
Temperature Range (Note 4)
2000V
200V
−40°C to +85°C
±3V to ±5.5V
Supply Voltage Range
VS
±6V
IIN (Input Pins)
±20 mA
(Note 3)
V− to V+
+150°C
Thermal Resistance
48-Pin TQFP
θJA
θJC
IOUT
44°C/W
12°C/W
Input Voltage Range
Maximum Junction Temperature
±3.3V Electrical Characteristics (Note 5)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 8)
(Note 7)
(Note 8)
Frequency Domain Performance
SSBW
LSBW
−3 dB Bandwidth
VOUT = 0.5 VPP
LMH6580 VOUT = 1 VPP
LMH6581 V OUT = 2 VPP, RL = 1 kΩ
LMH6580 VOUT = 1 VPP
LMH6581 VOUT = 2 VPP, RL = 150Ω
LMH6580 VOUT = 1 VPP
425
500
,
MHz
MHz
,
450
70
GF
0.1 dB Gain Flatness
,
LMH6581 V OUT = 2 VPP, RL = 150Ω
Time Domain Response
tr
Rise Time
LMH6580 1V Step, LMH6581
2V Step, 10% to 90%
3.1
1.4
ns
ns
tf
Fall Time
LMH6580 1V Step, LMH6581
2V Step, 10% to 90%
OS
SR
Overshoot
Slew Rate
2V Step
<1
%
LMH6580, 2 VPP, 40% to 60%
(Note 6)
900
V/µs
Slew Rate
LMH6581, 2 VPP, 40% to 60%
(Note 6)
1700
7
V/µs
ns
ts
Settling Time
2V Step, VOUT within 0.5%
Distortion And Noise Response
HD2
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Input Referred Voltage Noise
2 VPP, 10 MHz
2 VPP, 10 MHz
>1 MHz
−76
−76
12
dBc
dBc
nV/
pA/
dBc
in
Input Referred Noise Current
>1 MHz
2
XTLK
ISOL
Crosstalk
All Hostile, f = 100 MHz
f = 100 MHz
−45
−60
Off Isolation
dBc
Static, DC Performance
AV
Gain
LMH6581
LMH6580
1.986
0.994
2.00
1.00
±3
2.014
1.005
±17
VOS
Input Offset Voltage
mV
µV/°C
µA
TCVOS
IB
Input Offset Voltage Average Drift (Note 10)
38
Non-Inverting (Note 9)
−5
Input Bias Current
TCIB
Non-Inverting (Note 10)
−12
Input Bias Current Average Drift
nA/°C
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2
Symbol
VO
Parameter
Conditions
LMH6581, RL = 100Ω
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Units
Output Voltage Range
±1.8
±1.24
±2.08
±1.25
±2.1
±1.3
±2.2
±1.3
V
V
LMH6580, RL = 100Ω
LMH6581, RL = ∞Ω, (Note 11)
LMH6580 RL = ∞Ω,
VO
Output Voltage Range
PSRR
ICC
Power Supply Rejection Ratio
Positive Supply Current
−45
50
dBc
mA
60
56
13
RL = ∞
RL = ∞
IEE
Negative Supply Current
Tri State Supply Current
50
10
mA
mA
RST Pin > 2.0V
Miscellaneous Performance
RIN
CIN
RO
RO
Input Resistance
Non-Inverting
Non-Inverting
Closed Loop, Enabled
LMH6580
100
1
kΩ
pF
Input Capacitance
Output Resistance Enabled
Output Resistance Disabled
300
50
mΩ
kΩ
V
LMH6581
1100
2.0
1350
±1.3
1500
CMVR
IO
Input Common Mode Voltage
Range
Output Current
Sourcing, VO = 0 V
±50
mA
Digital Control
VIH
VIL
Input Voltage High
V
V
Input Voltage Low
Output Voltage High
Output Voltage Low
Switching Time
Setup Time
0.8
VOH
VOL
>2.0
<0.4
15
V
V
ns
ns
ns
TS
TH
7
Hold Time
7
±5V Electrical Characteristics (Note 5)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the tem-
perature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 8)
(Note 7)
(Note 8)
Frequency Domain Performance
SSBW
−3 dB Bandwidth
VOUT = 0.5 VPP (Note 11)
450
500
LMH6580 VOUT = 1 VPP
LMH6581 VOUT = 2 VPP, RL = 1 kΩ
LMH6580 VOUT = 1 VPP
LMH6581 VOUT = 2 VPP, RL = 150Ω
LMH6580, VOUT = 1 VPP
,
MHz
MHz
LSBW
GF
,
450
100
0.1 dB Gain Flatness
,
LMH6581, VOUT = 2 VPP, RL = 150Ω
RL = 150Ω, 3.58 MHz/4.43 MHz
RL = 150Ω, 3.58 MHz/4.43 MHz
DG
DP
Differential Gain
.05
.05
%
Differential Phase
deg
Time Domain Response
tr
Rise Time
LMH6580 2V, Step, 10% to 90%
LMH6581 2V, Step, 10% to 90%
2V Step, 10% to 90%
2.8
1.2
1.6
<1
ns
tf
Fall Time
ns
%
OS
Overshoot
2V Step
3
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Symbol
SR
Parameter
Conditions
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Units
V/µs
V/µs
ns
Slew Rate
Slew Rate
LMH6580, 2 VPP, 40% to 60%
(Note 6)
1200
2100
6
SR
LMH6581, 6 VPP, 40% to 60%
(Note 6)
ts
Settling Time
2V Step, VOUT Within 0.5%
Distortion And Noise Response
HD2
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Input Referred Voltage Noise
2 VPP, 5 MHz
2 VPP, 5 MHz
>1 MHz
−80
−70
12
dBc
dBc
nV/
pA/
dBc
in
Input Referred Noise Current
Cross Talk
>1 MHz
2
XTLK
All Hostile, f = 100 MHz
Channel to Channel, f = 100 MHz
f = 100 MHz
−45
−52
−65
dBc
dBc
ISOL
Off Isolation
Static, DC Performance
AV
Gain
LMH6581
LMH6580
1.986
0.995
2.00
1.00
±2
2.014
1.005
±17
Vos
Input Offset Voltage
mV
µV/°C
µA
TCVos
IB
Input Offset Voltage Average Drift (Note 10)
38
Non-Inverting (Note 9)
−5
±12
Input Bias Current
TCIB
VO
Non-Inverting (Note 10)
LMH681, RL = 100Ω
LMH6580, RL = 100Ω
LMH6581, RL = ∞Ω
−12
±3.6
nA/°C
Input Bias Current Average Drift
Output Voltage Range
±3.4
±2.9
±3.7
±2.9
V
V
±3.0
±3.9
±3.0
VO
Output Voltage Range
LMH6580, RL = ∞Ω
PSRR
XTLK
OISO
ICC
Power Supply Rejection Ratio
DC Crosstalk Rejection
DC Off Isloation
DC
−42
−62
−60
−45
−90
−90
54
dBc
dBc
dBc
mA
DC, Channel to Channel
DC
Positive Supply Current
66
62
17
RL = ∞
RL = ∞
IEE
Negative Supply Current
Tri State Supply Current
50
14
mA
mA
RST Pin > 2.0V
Miscellaneous Performance
RIN
CIN
RO
RO
Input Resistance
Non-Inverting
100
1
kΩ
pF
Input Capacitance
Non-Inverting
Output Resistance Enabled
Output Resistance Disabled
Closed Loop, Enabled
LMH6580, Resistance to Ground
LMH6581, Resistance to Ground
300
50
mΩ
kΩ
V
1100
1300
±3.0
1500
CMVR
IO
Input Common Mode Voltage
Range
Output Current
Sourcing, VO = 0 V
±60
2.0
±70
mA
Digital Control
VIH
VIL
Input Voltage High
V
V
Input Voltage Low
Output Voltage High
Output Voltage Low
Switching Time
Setup Time
0.8
VOH
VOL
>2.4
<0.4
15
V
V
ns
ns
ns
TS
TH
5
Hold Time
5
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations.
Note 4: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 5: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the
electrical tables under conditions different than those tested.
Note 6: Slew Rate is the average of the rising and falling edges.
Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 8: Room Temperature limits are 100% production tested at 25°C. Factory testing conditions result in very limited self-heating of the device such that TJ
=
TA. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods.
Note 9: Negative input current implies current flowing out of the device.
Note 10: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Note 11: This parameter is guaranteed by design and/or characterization and is not tested in production.
Ordering Information
Package
Part Number
LMH6580VS
LMH6580VSX
LMH6581VS
LMH6581VSX
Package Marking
Transport Media
250 Units/Tray
NSC Drawing
LMH6580VS
1k Tape and Reel
250 Units/Tray
48-Pin QFP
VBC48A
LMH6581VS
1k Tape and Reel
5
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Typical Performance Characteristics LMH6580
1 VPP Frequency Response
1 VPP Frequency Response
30007253
30007254
1 VPP Frequency Response Broadcast
1 VPP Frequency Response Broadcast
30007255
30007256
Frequency Response 1 kΩ Load
Frequency Response 1kΩ Load
30007274
30007252
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Frequency Response with Input Expansion
Frequency Response with Input Expansion
30007275
30007276
2 VPP Pulse Response
2 VPP Pulse Response
30007265
30007263
2 VPP Pulse Response, Broadcast Mode
2 VPP Pulse Response, Broadcast Mode
30007258
30007264
7
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1 VPP Pulse Response
1 VPP Pulse Response
30007261
30007259
Channel to Channel Crosstalk
All Hostile Crosstalk
30007277
30007278
Second Order Distortion (HD2) vs. Frequency
Third Order Distortion (HD3) vs. Frequency
30007272
30007270
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Second Order Distortion (HD2) vs. Frequency
Third Order Distortion (HD3) vs. Frequency
30007271
30007273
Positive Voltage Swing over Temperature
Negative Voltage Swing over Temperature
30007266
30007267
Positive Voltage Swing over Temperature
Negative Voltage Swing over Temperature
30007269
30007268
9
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Enabled Output Impedance
Disabled Output Impedance
Switching Time
Enabled Output Impedance
30007281
30007279
Disabled Output Impedance
30007282
30007280
30007257
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Typical Performance Characteristics LMH6581
2 VPP Frequency Response
2 VPP Frequency Response
30007248
30007249
Large Signal Bandwidth
Large Signal Bandwidth
30007222
30007223
Small Signal Bandwidth
Small Signal Bandwidth
30007224
30007225
11
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Group Delay
Frequency Response 1 kΩ Load
30007245
30007241
2 VPP Pulse Response
2 VPP Pulse Response
30007214
30007213
4 VPP Pulse Response
4 VPP Pulse Response Broadcast
30007216
30007217
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4 VPP Pulse Response
6 VPP Pulse Response
30007215
30007218
Off Isolation
All Hostile Crosstalk
30007219
30007221
Second Order Distortion (HD2) vs. Frequency
Third Order Distortion (HD3) vs. Frequency
30007227
30007226
13
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Second Order Distortion vs. Frequency
Third Order Distortion vs. Frequency
30007228
30007229
No Load Output Swing
Positive Swing over Temperature
30007234
30007238
Negative Swing Over Temperature
No Load Output Swing
30007231
30007239
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Positive Swing over Temperature
Enabled Output Impedance
Switching Time
Negative Swing over Temperature
30007236
30007237
Disabled Output Impedance
30007250
30007251
30007257
15
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Application Information
INTRODUCTION
The LMH6580/LMH6581 are high speed, fully buffered, non-
blocking, analog crosspoint switches. Having fully buffered
inputs allows the LMH6580/LMH6581 to accept signals from
low or high impedance sources without the worry of loading
the signal source. The fully buffered outputs will drive 75Ω or
50Ω back terminated transmission lines with no external com-
ponents other than the termination resistor. When disabled,
the outputs are in a high impedance state. The LMH6580/
LMH6581 can have any input connected to any (or all) output
(s). Conversely, a given output can have only one associated
input.
INPUT AND OUTPUT EXPANSION
The LMH6580/LMH6581 have high impedance inactive
states for both inputs and outputs allowing maximum flexibility
for crosspoint expansion. In addition the LMH6580/LMH6581
employ diagonal symmetry in pin assignments. The diagonal
symmetry makes it easy to use direct pin to pin vias when the
parts are mounted on opposite sides of a board. As an ex-
ample two LMH6580/LMH6581 chips can be combined on
one board to form either an 8 x 8 crosspoint or a 16 x 4 cross-
point. To make an 8 x 8 crosspoint all 8 input pins would be
tied together (Input 0 on side 1 to input 7 on side 2 and so on)
while the 4 output pins on each chip would be left separate.
To make the 16 x 4 crosspoint, the 4 outputs would be tied
together while all 16 inputs would remain independent. In the
16 x 4 configuration it is important not to have 2 connected
outputs active at the same time. With the 8 x 8 configuration,
on the other hand, having two connected inputs active is a
valid state. Crosspoint expansion as detailed above has the
advantage that the signal will go through only one crosspoint.
Expansion methods that have cascaded stages will suffer
bandwidth loss far greater than the small loading effect of
parallel expansion.
30007242
FIGURE 1. Output Expansion
Output expansion as shown in Figure 1 is very straight for-
ward. Connecting the inputs of two crosspoint switches has a
very minor impact on performance. Input expansion requires
more planning. Input expansion, as show in Figure 2 and
Figure 3 gives the option of two ways to connect the outputs
of the crosspoint switches. In Figure 2 the crosspoint switch
outputs are connected directly together and share one termi-
nation resistor. This is the easiest configurarion to implement
and has only one drawback. Because the disabled output of
the unused crosspoint (only one output can be active at a
time) has a small amount of capacitance, the frequency re-
sponse of the active crosspoint will show peaking. This is
illustrated in Figure 4 and Figure 5. In most cases this small
amount of peaking is not a problem.
As illustrated in Figure 3 each crosspoint output can be given
its own termination resistor. This results in a frequency re-
sponse nearly identical to the non expansion case. There is
one drawback for the gain of 2 crosspoint, and that is gain
error. With a 75Ω termination resistor the 1250Ω resistance
of the disabled crosspoint output will cause a gain error. In
order to counter act this the termination resistors of both
crosspoints should be adjusted to approximately 80Ω. This
will provide very good matching, but the gain accuracy of the
system will now be dependent on the process variations of
the crosspoint resistors which have a variability of approxi-
mately ±20%.
30007243
FIGURE 2. Input Expansion with Shared Termination
Resistors
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30007247
FIGURE 5. Input Expansion Frequency Response
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the
use of a series output resistor ROUT. Capacitive loads of
5 pF to 120 pF are the most critical, causing ringing, frequency
response peaking and possible oscillation. Since most ca-
pacitive loading is due to undesired parasitic capacitances the
values of the capacitive loading will not usually be known ex-
actly. It is best to start with a conservative value of ROUT and
decrease the value until the bandwidth shows slight peaking.
At this point the value of the isloation resistor will be deter-
mined by whether flat frequency response or maximum band-
width is the desired goal. Smaller values of ROUT will produce
some peaking, but maximum bandwidth. Larger resistor val-
ues will decrease bandwidth and suppress peaking.
30007244
FIGURE 3. Input Expansion with Separate Termination
Resistors
As starting values, a capacitive load of 5 pF should have
around 75 Ω of isolation resistance. A value of 120 pF would
require around 12Ω. When driving transmission lines, the out-
put termination resistor is normally sufficient.
30007246
FIGURE 4. Input Expansion Frequency Response
17
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USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH
AND INCREASE REBIABILITY
DIGITAL CONTROL
Block Diagram
The LMH6580/LMH6581 crosspoint switch can offer en-
hanced bandwidth and reliability with the use of external
buffers on the outputs. The bandwidth is increased by un-
loading the outputs and driving the high impedance of an
external buffer. See the Frequency Response 1 kΩ Load
curve in the Typical Performance section for an example of
bandwidth achieved with less loading on the outputs. For this
technique to provide maximum benefit a very high speed am-
plifier such as the LMH6703 should be used. As shown in
Figure 6 the resistor RL is placed between the crosspoint out-
put and the buffer amplifier. This resistor will provide a load
for the crosspoint output buffer and reduce peaking caused
by the buffer input capacitance. A recommended value for
RL is 500Ω to 1000Ω. Higher values of RL will give higher
bandwidth, but also higher peaking. The optimum value of
RL will depend greatly on board layout and the input capaci-
tance of the buffer amplifier.
30007211
Besides offering enhanced bandwidth performance using an
external buffer provides greater system reliability. The first
advantage is to reduce thermal loading on the crosspoint
switch. This reduced die temperature will increase the life of
the crosspoint. The second advantage is enhanced ESD re-
liability. It is very difficult to build high speed devices that can
withstand all possible ESD events. With external buffers the
crosspoint switch is isolated from ESD events on the external
system connectors.
FIGURE 7.
Edge
Logic Pins
Pin Name Level
Triggered by
Sensitive
Triggered
CLK
CS
Yes
Yes
Yes
Yes
CLK rising
edge
DATA IN
CLK falling
edge
DATA
OUT
CLK rising
edge
CFG
Yes
Yes
Yes
Yes
MODE
RST
30007240
BCST
FIGURE 6. Buffered Output
There are two modes for programing the LMH6580/
LMH6581, Serial Mode and Addressed Mode. The LMH6580/
LMH6581 have internal control registers that store the pro-
gramming states of the crosspoint switch. The logic is two
staged to allow for maximum programming flexibility. The first
stage of the control logic is tied directly to the crosspoint
switching matrix. This logic consists of one register for each
output that stores the on/off state and the address of which
input to connect to. These registers are not directly accessible
to the user. The second level of logic is another bank of reg-
isters identical to the first, but set up as shift registers. These
registers are accessed by the user via the serial input bus.
CROSSTALK
When designing a large system such as a video router
crosstalk can be a very serious problem. Extensive testing in
our lab has shown that most crosstalk is related to board lay-
out rather than occurring in the crosspoint switch. There are
many ways to reduce board related crosstalk. Using con-
trolled impedance lines is an important step. Using well de-
coupled power and ground planes will help as well. When
crosstalk does occur within the crosspoint switch itself it is
often due to signals coupling into the power supply pins. Using
appropriate supply bypassing will help to reduce this mode of
coupling. Another suggestion is to place as much grounded
copper as possible between input and output signal traces.
Care must be taken, though, not to influence the signal trace
impedances by placing shielding copper too closely. One oth-
er caveat to consider is that as shielding materials come
closer to the signal trace the trace needs to be smaller to keep
the impedance from falling too low. Using thin signal traces
will result in unacceptable losses due to trace resistance. This
effect becomes even more pronounced at higher frequencies
due to the skin effect. The skin effect reduces the effective
thickness of the trace as frequency increases. Resistive loss-
es make crosstalk worse because as the desired signal is
attenuated with higher frequencies crosstalk increases at
higher frequencies.
The LMH6580/LMH6581 is programmed via a serial input bus
with the support of four other digital control pins. The Serial
bus consists of a clock pin (CLK), a serial data in pin (DIN),
and a serial data out pin (DOUT). The serial bus is gated by a
chip select pin (CS). The chip select pin is active low. While
the chip select pin is high all data on the serial input pin and
clock pins is ignored. When the chip select pin is brought low
the internal logic is set to begin receiving data by the first
positive transition (0 to 1) of the clock signal. The chip select
pin must be brought low at least 5 ns before the first rising
edge of the clock signal. The first data bit is clocked in on the
next negative transition (1 to 0) of the clock signal. All input
data is read from the bus on the negative edge of the clock
signal. Once the last valid data has been clocked in, either the
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chip select pin must go high or, the clock signal must stop.
Otherwise invalid data will be clocked into the chip. The data
clocked into the chip is not transferred to the crosspoint matrix
until the CFG pin is pulsed high. This is the case regardless
of the state of the MODE pin. The CFG pin is not dependent
on the state of the Chip select pin. If no new data is clocked
into the chip subsequent pulses on the CFG pin will have no
effect on device operation.
figure pin. One way around this loss of flexibility would be if
the clock signal is generated by an FPGA or microcontroller
where the clock signal can be stopped after the data is
clocked in. In this case the Chip select function is provided by
the presence or absence of the clock signal.
SERIAL PROGRAMMING MODE
Serial programming mode is the mode selected by bringing
the MODE pin low. In this mode a stream of 16-bits programs
all four outputs of the crosspoint. The data is fed to the chip
as shown in the Serial Mode Data Frame tables below (two
tables are required to show the entire data frame). The table
is arranged such that the first bit clocked into the crosspoint
register is labeled bit number 0. The register labeled Load
Register in the block diagram is a shift register. If the chip
select pin is left low after the valid data is shifted into the chip
and if the clock signal keeps running then additional data will
be shifted into the register, and the desired data will be shifted
out.
The programming format of the incoming serial data is se-
lected by the MODE pin. When the MODE pin is HIGH the
crosspoint can be programmed one output at a time by en-
tering a string of data that contains the address of the output
that is going to be changed (Addressed Mode). When the
mode pin is LOW the crosspoint is in Serial Mode. In this
mode the crosspoint accepts a 16 bit array of data that pro-
grams all of the outputs. In both modes the data fed into the
chip does not change the chip operation until the Configure
pin is pulsed high. The configure and mode pins are inde-
pendent of the chip select pin.
Also illustrated is the timing relationships for the digital pins
in the Timing Diagram for Serial Mode shown below. It is im-
portant to note that all the pin timing relationships are impor-
tant, not just the data and clock pins. One example is that the
Chip Select pin (CS) must transition low before the first rising
edge of the clock signal. This allows the internal timing circuits
to synchronize to allow data to be accepted on the next falling
edge. The chip select pin must then transition high after the
final data bit has been clocked in and before another clock
signal positive edge occurs to prevent invalid data from being
clocked into the chip. Another way to accomplish the same
thing is to strobe the clock pin with only the desired number
of pulses starting and ending with clock in the low condition.
The configure (CFG) pin timing is not so critical, but it does
need to be kept low until all data has been shifted into the
crosspoint registers.
THREE WIRE VS. FOUR WIRE CONTROL
There are two ways to connect the serial data pins. The first
way is to control all four pins separately, and the second op-
tion is to connect the CFG and the CS pins together for a 3
wire interface. The benefit of the 4-wire interface is that the
chip can be configured independently using the CS pin. This
would be an advantage in a system with multiple crosspoint
chips where all of them could be programmed ahead of time
and then configured simultaneously. The 4-wire solution is
also helpful in a system that has a free running clock on the
CLK pin. In this case, the CS pin needs to be brought high
after the last valid data bit to prevent invalid data from being
clocked into the chip.
The 3-wire option provides the advantage of one less pin to
control at the expense of having less flexibility with the con-
30007209
Timing Diagram for Serial Mode
19
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Serial Mode Data Frame (First Two Words)
Output 0
Input Address
LSB
Output 1
On = 0
Off = 1
3
Input Address
On = 0
Off = 1
7
MSB
2
LSB
4
LSB
0
1
5
6
Off = TRI-STATE®, Bit 0 is first bit clocked into device.
Serial Mode Data Frame (Continued)
Output 2
Output 3
Input Address
LSB
On = 0
Off = 1
11
Input Address
LSB
On = 0
Off = 1
15
MSB
10
MSB
14
8
9
12
13
ADDRESSED PROGRAMMING MODE
first rising edge of the clock signal. This allows the internal
timing circuits to synchronize to allow data to be accepted on
the next falling edge. The chip select pin must then transition
high after the final data bit has been clocked in and before
another clock signal positive edge occurs to prevent invalid
data from being clocked into the chip. Also, in addressed
mode is it necessary for the clock signal to make a low to high
transition after the chip select pin has been brought high. If
there is not a low to high transition of the clock after the chip
select pin goes high subsequent data wil not be loaded into
the chip properly. The configure (CFG) pin timing is not criti-
cal, but it does need to be kept low until all data has been
shifted into the crosspoint registers.
Addressed programming mode makes it possible to change
only one output register at a time. To utilize this mode the
mode pin must be High. All other pins function the same as
in serial programming mode except that the word clocked in
is 5 bits and is directed only at the output specified. In ad-
dressed mode the data format is shown below in the table
titled Addressed Mode Word Format.
Also illustrated is the timing relationships for the digital pins
in the Timing Diagram for Addressed Mode shown below. It
is important to note that all the pin timing relationships are
important, not just the data and clock pins. One example is
that the Chip Select pin (CS) must transition low before the
30007210
Timing Diagram for Addressed Mode
www.national.com
20
Addressed Mode Word Format
Output Address
Input Address
TRI-STATE
LSB
MSB
1
LSB
2
MSB
4
1 = TRI-STATE
0 = On
0
3
5
Bit 0 is first bit clocked into device.
DAISY CHAIN OPTION IN SERIAL MODE
lated based on the typical supply current of 50 mA and a 10V
supply voltage. This power dissipation will vary within the
range of 0.4 W to 0.6 W due to process variations. In addition,
each equivalent video load (150Ω) connected to the outputs
should be budgeted 30 mW of power. For a typical application
with one video load for each output this would be a total power
of 0.62 W. With a θJA of 44 °C/W this will result in the silicon
being 27°C over the ambient temperature. A more aggressive
application would be two video loads per output which would
result in 0.74 W of power dissipation. This would result in a
33°C temperature rise. For heavier loading, the TQFP pack-
age thermal performance can be significantly enhanced with
an external heat sink and by providing for moving air ventila-
tion. Also, be sure to calculate the increase in ambient tem-
perature from all devices operating in the system case.
Because of the high power output of this device, thermal
management should be considered very early in the design
process. Generous passive venting and vertical board orien-
tation may avoid the need for fan cooling or heat sinks. Also,
the LMH6580/LMH6581 can be operated with a ±3.3V power
supply. This will cut power dissipation substantially while only
reducing bandwidth by about 10% (2 VPP output). The
LMH6580/LMH6581 are fully characterized and factory tested
at the ±3.3V power supply condition for applications where
reduced power is desired.
The LMH6580/LMH6581 supports daisy chaining of the serial
data stream between multiple chips. This feature is available
only in the Serial Programming Mode. To use this feature se-
rial data is clocked into the first chip DIN pin, and the next chip
DIN pin is connected to the DOUT pin of the first chip. Both chips
may share a chip select signal, or the second chip can be
enabled separately. When the chip select pin goes low on
both chips a double length word is clocked into the first chip.
As the first word is clocking into the first chip the second chip
is receiving the data that was originally in the shift register of
the first chip (invalid data). When a full 16 bits have been
clocked into the first chip the next clock cycle begins moving
the first frame of the new configuration data into the second
chip. With a full 32 clock cycles both chips have valid data and
the chip select pin of both chips should be brought high to
prevent the data from overshooting. A configure pulse will ac-
tivate the new configuration on both chips simultaneously, or
each chip can be configured separately. The mode, chip se-
lect, configure and clock pins of both chips can be tied to-
gether and driven from the same sources.
SPECIAL CONTROL PINS
The LMH6580/LMH6581 have two special control pins that
function independent of the serial control bus. One of these
pins is the reset (RST) pin. The RST pin is active high mean-
ing that at logic 1 level the chip is configured with all outputs
disabled and in a high impedance state. The RST pin pro-
grams all the registers with input address 0 and all the outputs
are turned off. In this configuration the device draws only 11-
mA. The RST pin can be used as a shutdown function to
reduce power consumption. The other special control pin is
the broadcast (BCST) pin. The BCST pin is also active high
and sets all the outputs to the on state connected to input 0.
This is sometimes referred to as broadcast mode, where input
0 is broadcast to all eight outputs.
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power sup-
ply and ground traces away from the input and output pins.
Parasitic capacitances on these nodes to ground will cause
frequency response peaking and possible circuit oscillations
(see Application Note OA-15 for more information). If digital
control lines must cross analog signal lines (particularly in-
puts) it is best if they cross perpendicularly. National Semi-
conductor suggests the following evaluation boards as a
guide for high frequency layout and as an aid in device testing
and characterization:
THERMAL MANAGEMENT
Device
Package
Evaluation Board
Part Number
The LMH6580/LMH6581 are high performance devices that
produce a significant amount of heat. With ±5V supplies, the
LMH6580/LMH6581 will dissipate approximately 0.5 W of
idling power with all outputs enabled. Idling power is calcu-
LMH6580
48–Pin
LMH730164EF
21
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Pin QFP
NS Package Number VBC48A
www.national.com
22
Notes
23
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Notes
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