LMH6583YA/NOPB [TI]
增益为 2 的 5V、交叉点/交换、16 输入 8 输出模拟开关 | PAP | 64 | -40 to 85;
| 型号： | LMH6583YA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增益为 2 的 5V、交叉点/交换、16 输入 8 输出模拟开关 | PAP | 64 | -40 to 85 开关 输出元件 |
| 文件： | 总25页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
LMH6583 16x8 550 MHz Analog Crosspoint Switch, Gain of 2
Check for Samples: LMH6583
1
FEATURES
DESCRIPTION
The LMH™ family of products is joined by the
23
•
16 Inputs and 8 Outputs
LMH6583, high speed, non-blocking, analog,
a
•
64-pin Exposed Pad HTQFP Package
crosspoint switch. The LMH6583 is designed for high
speed, DC coupled, analog signals like high
resolution video (UXGA and higher). The LMH6583
has 16 inputs and 8 outputs. The non-blocking
architecture allows an output to be connected to any
input, including an input that is already selected. With
fully buffered inputs the LMH6583 can be impedance
matched to nearly any source impedance. The
buffered outputs of the LMH6583 can drive up to two
back terminated video loads (75Ω load). The outputs
and inputs also feature high impedance inactive
states allowing high performance input and output
expansion for array sizes such as 16 x 16 or 32 x 8
by combining two devices. The LMH6583 is
controlled with a 4 pin serial interface. Both single
serial mode and addressed chain modes are
available.
–
−3 dB Bandwidth (VOUT = 2 VPP, RL = 1 kΩ)
550 MHz
–
−3 dB Bandwidth (VOUT = 2 VPP,RL = 150Ω)
450 MHz
•
•
Fast Slew Rate 1800 V/μs
Channel to Channel Crosstalk (10/ 100 MHz)
−70/ −52 dBc
•
All Hostile Crosstalk (10/ 100 MHz) −55/−45
dBc
•
•
Easy to Use Serial Programming 4 Wire Bus
Two Programming Modes Serial & Addressed
Modes
•
•
•
Symmetrical Pinout Facilitates Expansion.
Output Current ±60 mA
The LMH6583 comes in a 64-pin thermally enhanced
HTQFP package. It also has diagonally symmetrical
pin assignments to facilitate double sided board
layouts and easy pin connections for expansion.
Gain of 1 Version also Available LMH6582
APPLICATIONS
•
•
•
•
•
•
•
•
Studio Monitoring/Production Video Systems
Conference Room Multimedia Video Systems
KVM (Keyboard Video Mouse) Systems
Security/Surveillance Systems
Multi Antenna Diversity Radio
Video Test Equipment
Medical Imaging
Wide-Band Routers & Switches
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
Connection Diagram
48
32
SWITCH
MATRIX
IN8
VEE
IN9
OUT7
GND
VEE
VCC
IN10
VEE
IN11
VCC
GND
OUT6
VCC
136
CONFIGURATION
REGISTER
OUT5
GND
VEE
CFG
BCST
RST
DATA OUT
40
IN12
VEE
DATA IN
LOAD
GND
OUT4
VCC
REGISTER
CS
CLK
IN13
VCC
GND
MODE
BCST
CFG
IN14
VEE
CLK
IN15
VCC
DOUT
64
1
16
Figure 1. 64-Pin Exposed Pad HTQFP
See Package Number PAP0064A
Figure 2. Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance
(3)
Human Body Model
Machine Model
2000V
200V
±6V
VS
IIN (Input Pins)
±20 mA
(4)
IOUT
Input Voltage Range
Maximum Junction Temperature
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
V− to V+
+150°C
−65°C to +150°C
235°C
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical
Characteristics and ±5V Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum output current (IOUT) is determined by device power dissipation limitations.
2
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
(1)
Operating Ratings
Temperature Range
(2)
−40°C to +85°C
±3V to ±5.5V
θJC
Supply Voltage Range
Thermal Resistance
θJA
64–Pin Exposed Pad HTQFP
27°C/W
0.82°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical
Characteristics and ±5V Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX)and θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(1)
±3.3V Electrical Characteristics
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Performance
SSBW
LSBW
−3 dB Bandwidth
VOUT = 0.5 VPP
425
VOUT = 2 VPP, RL = 1 kΩ
500
450
80
MHz
VOUT = 2 VPP, RL = 150Ω
GF
DG
DP
0.1 dB Gain Flatness
Differential Gain
VOUT = 2 VPP, RL = 150Ω
MHz
%
RL = 150Ω, 3.58 MHz/ 4.43 MHz
RL = 150Ω, 3.58 MHz/ 4.43 MHz
0.05
0.05
Differential Phase
deg
Time Domain Response
tr
Rise Time
Fall Time
2V Step, 10% to 90%
2V Step, 10% to 90%
2V Step
1.7
1.4
4
ns
ns
tf
OS
SR
ts
Overshoot
Slew Rate
Settling Time
%
(4)
4 VPP, 40% to 60%
1700
9
V/µs
ns
2V Step, VOUT within 0.5%
Distortion And Noise Response
HD2
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Input Referred Voltage Noise
Input Referred Noise Current
Switching Time
2 VPP, 10 MHz
2 VPP, 10 MHz
>1 MHz
−76
−76
12
dBc
dBc
nV/ √Hz
pA/ √Hz
ns
in
>1 MHz
2
16
XTLK
ISOL
Crosstalk
All Hostile, f = 100 MHz
f = 100 MHz
−45
−60
dBc
Off Isolation
dBc
Static, DC Performance
AV
Gain
1.986
±1.75
2.00
±3
2.014
±17
VOS
TCVOS
IB
Output Offset Voltage
Output Offset Voltage Average Drift
Input Bias Current
mV
µV/°C
µA
(5)
38
(6)
Non-Inverting
−5
(5)
TCIB
VO
Input Bias Current Average Drift
Output Voltage Range
Non-Inverting
-12
±2.1
nA/°C
V
RL = 100Ω
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensurance of parametric performance is
indicated in the electrical tables under conditions different than those tested.
(2) Room Temperature limits are 100% production tested at 25°C. Device self heating results in TJ ≥ TA, however, test time is insufficient for
TJto reach steady state conditions. Limits over the operating temperature range are ensured through correlation using Statistical Quality
Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
±3.3V Electrical Characteristics (1) (continued)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
(2)
(3)
(2)
Symbol
VO
Parameter
Conditions
Min
Typ
±2.2
Max
Units
(7)
Output Voltage Range
RL = ∞
+2.1
V
-2.05
PSRR
ICC
Power Supply Rejection Ratio
Positive Supply Current
Negative Supply Current
Tri State Supply Current
45
98
92
17
dB
mA
mA
mA
RL = ∞
RL = ∞
120
IEE
115
25
RST Pin > 2.0V
Miscellaneous Performance
RIN
CIN
RO
Input Resistance
Non-Inverting
Non-Inverting
Closed Loop, Enabled
Disabled
100
1
kΩ
pF
mΩ
Ω
Input Capacitance
Output Resistance Enabled
Output Resistance Disabled
Input Common Mode Voltage Range
Output Current
300
1300
±1.3
±50
RO
1100
2.0
1450
CMVR
IO
V
Sourcing, VO = 0 V
mA
Digital Control
VIH
VIL
VOH
VOL
TS
Input Voltage High
V
V
Input Voltage Low
Output Voltage High
Output Voltage Low
Setup Time
0.8
>2.2
<0.4
7
V
V
ns
ns
TH
Hold Time
7
(7) This parameter is ensured by design and/or characterization and is not tested in production.
(1)
±5V Electrical Characteristics
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Performance
SSBW
LSBW
−3 dB Bandwidth
VOUT = 0.5 VPP
475
VOUT = 2 VPP, RL = 1 kΩ
550
450
100
0.04
0.04
MHz
VOUT = 2 VPP, RL = 150Ω
GF
DG
DP
0.1 dB Gain Flatness
Differential Gain
VOUT = 2 VPP, RL = 150Ω
MHz
%
RL = 150Ω, 3.58 MHz/ 4.43 MHz
RL = 150Ω, 3.58 MHz/ 4.43 MHz
Differential Phase
deg
Time Domain Response
tr
Rise Time
Fall Time
2V Step, 10% to 90%
2V Step, 10% to 90%
2V Step
1.4
1.3
2
ns
ns
tf
OS
SR
ts
Overshoot
Slew Rate
Settling Time
%
(4)
6 VPP, 40% to 60%
1800
7
V/µs
ns
2V Step, VOUT Within 0.5%
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensurance of parametric performance is
indicated in the electrical tables under conditions different than those tested.
(2) Room Temperature limits are 100% production tested at 25°C. Device self heating results in TJ ≥ TA, however, test time is insufficient for
TJto reach steady state conditions. Limits over the operating temperature range are ensured through correlation using Statistical Quality
Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Slew Rate is the average of the rising and falling edges.
4
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
±5V Electrical Characteristics (1) (continued)
Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the
temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Distortion And Noise Response
HD2
HD3
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Input Referred Voltage Noise
Input Referred Noise Current
Switching Time
2 VPP, 5 MHz
−80
dBc
dBc
2 VPP, 5 MHz
>1 MHz
−70
12
nV/ √Hz
pA/ √Hz
ns
in
>1 MHz
2
15
XTLK
ISOL
Cross Talk
All Hostile, f = 100 MHz
Channel to Channel, f = 100 MHz
f = 100 MHz
−45
−52
−65
dBc
dBc
Off Isolation
dBc
Static, DC Performance
AV
Gain
LMH6583
1.986
2.00
±2
2.014
±17
VOS
TCVOS
IB
Offset Voltage
Input Referred
(5)
mV
µV/°C
µA
Output Offset Voltage Average Drift
Input Bias Current
38
(6)
Non-Inverting
−5
−12
(5)
TCIB
VO
Input Bias Current Average Drift
Output Voltage Range
Non-Inverting
−12
±3.6
nA/°C
V
RL = 100Ω
+3.3
−3.4
VO
Output Voltage Range
Power Supply Rejection Ratio
DC Crosstalk
RL = ∞
±3.7
42
±3.9
45
V
PSRR
XTLK
ISOL
ICC
DC
dB
dB
dB
mA
mA
mA
DC, Channel to Channel
−58
−60
−90
−90
110
104
22
DC Off Isloation
DC
Positive Supply Current
Negative Supply Current
Tri State Supply Current
RL = ∞
130
124
30
IEE
RL = ∞
RST Pin > 2.0V
Miscellaneous Performance
RIN
CIN
RO
Input Resistance
Non-Inverting
100
1
kΩ
pF
mΩ
Ω
Input Capacitance
Non-Inverting
Output Resistance Enabled
Output Resistance Disabled
Input Common Mode Voltage Range
Output Current
Closed Loop, Enabled
Disabled, Resistance to Ground
300
1300
±3.0
±70
RO
1100
±60
2.0
1450
CMVR
IO
V
Sourcing, VO = 0 V
mA
Digital Control
VIH
VIL
VOH
VOL
TS
Input Voltage High
V
V
Input Voltage Low
Output Voltage High
Output Voltage Low
Setup Time
0.8
>2.4
<0.4
5
V
V
ns
ns
TH
Hold Time
5
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics
2 VPP Frequency Response
2 VPP Frequency Response
1
0
1
0
GAIN
GAIN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
0
0
PHASE
PHASE
-45
-45
-90
-135
-180
-225
-90
-135
-180
-225
V
V
= ±5V
V
V
= ±3.3V
S
S
= 2 V
PP
= 2 V
PP
OUT
OUT
R
L
= 150W
R
L
= 150W
100
1000
10
100
1000
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Large Signal Bandwidth
Large Signal Bandwidth
1
1
GAIN
GAIN
0
-1
-2
-3
-4
-5
-6
-7
0
-1
-2
-3
-4
-5
-6
-7
0
0
PHASE
PHASE
-45
-90
-135
-180
-225
-45
-90
-135
-180
-225
V
= ±5V
V
= ±3.3V
S
S
V
= 2.8 V
PP
V
= 2.8 V
PP
OUT
OUT
R
= 150W
R
= 150W
L
L
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
Small Signal Bandwidth
Small Signal Bandwidth
1
0
1
0
GAIN
GAIN
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
0
0
PHASE
= ±3.3V
PHASE
-45
-90
-135
-180
-225
-45
-90
-135
-180
-225
V
V
= ±5V
S
S
V
= 0.7 V
PP
V
= 0.7 V
PP
OUT
OUT
R
= 100W
R
= 100W
L
L
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7.
Figure 8.
6
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Frequency Response 1 kΩ Load
Group Delay
1
0
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
V
V
= ±5V
S
GAIN
= 1V
OUT
V
S
= ±5V
-1
-2
-3
-4
-5
-6
-7
V
S
= ±3.3V
0
PHASE
-45
-90
-135
-180
-225
V
= ±3.3V
100
S
V
= 2 V
PP
OUT
R
= 1 kW
L
1000
10
0
100
200
300
400
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9.
Figure 10.
2 VPP Pulse Response
2 VPP Pulse Response
1.5
1.0
1.5
1.0
V
= ±5V
SINGLE CHANNEL
V = ±3.3V
S
SINGLE CHANNEL
S
0.5
0.0
0.5
0.0
-0.5
-0.5
-1.0
-1.5
-1.0
-1.5
0
5
10 15 20 25 30 35 40
TIME (ns)
0
5
10 15 20 25 30 35 40
TIME (ns)
Figure 11.
Figure 12.
4 VPP Pulse Response
4 VPP Pulse Response Broadcast
2.5
2
2.5
2.0
1.5
V
= ±5V
S
BROADCAST
1.5
1
1.0
0.5
0.5
0
0.0
-0.5
-1
-0.5
-1.0
-1.5
-2
-1.5
V
= ±5V
S
-2.0
-2.5
SINGLE CHANNEL
-2.5
0
5
10
15
20
25
30
0
5
10 15 20 25 30 35 40
TIME (ns)
TIME (ns)
Figure 14.
Figure 13.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
4 VPP Pulse Response
6 VPP Pulse Response
2.5
2.0
1.5
4
3
2
1.0
0.5
1
0.0
0
-0.5
-1.0
-1
-2
-3
-4
-1.5
V
= ±3.3V
S
V
S
= ±5V
-2.0
-2.5
SINGLE CHANNEL
SINGLE CHANNEL
0
5
10 15 20 25 30 35 40
TIME (ns)
0
5
10 15 20 25 30 35 40
TIME (ns)
Figure 15.
Figure 16.
2 VPP Off Isolation
2 VPP Crosstalk
-50
-60
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-110
-120
-100
-110
1
100
0.1
10
1000
1
100
0.1
10
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17.
Figure 18.
Second Order Distortion (HD2)
vs.
Frequency
2 VPP All Hostile Crosstalk
-60
-65
-70
-75
-40
V
= ±5V
S
R
= 100W
L
-50
V
= 4V
OUT
BOTH INPUTS & OUTPUTS
-60
-70
V
= 2V
OUT
-80
-85
-90
-80
OUTPUTS ONLY
INPUTS ONLY
V
OUT
= 0.25V
-90
-100
0.001
-95
1
100
0.01
0.1
10
1000
100
10
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19.
Figure 20.
8
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Third Order Distortion (HD3)
Second Order Distortion
vs.
vs.
Frequency
Frequency
-55
-60
-65
-70
-75
-80
-85
-90
-95
-55
-60
-65
-70
-75
-80
-85
-90
-95
V
= ±5V
V
= ±3.3V
S
S
R
= 100W
R
= 100W
L
L
V
= 4V
OUT
V
= 3V
OUT
V
= 2V
V
= 2V
OUT
OUT
V
OUT
= 0.25V
V
= 0.25V
OUT
10
100
1
10
100
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21.
Figure 22.
Third Order Distortion
vs.
Frequency
No Load Output Swing
-55
-60
-65
-70
-75
-80
-85
-90
-95
4
3
V
= ±3.3V
S
V
= ±5V
S
R
= 100W
L
NO LOAD
2
V
OUT
= 3V
1
V
= 2V
OUT
0
-1
-2
-3
-4
V
= 0.25V
OUT
-3
-2
-1
1
2
3
0
10
100
1
INPUT VOLTAGE (V)
FREQUENCY (MHz)
Figure 23.
Figure 24.
Positive Swing over Temperature
Negative Swing Over Temperature
3.75
3.5
-2.75
100°C
V
= ±5V
S
V
= ±5V
S
100W LOAD
100W LOAD
-3
-3.25
-3.5
-40°C
25°C
3.25
3
25°C
-40°C
100°C
2.75
1.5
-3.75
-2.25
1.75
2
2.25
-2
-1.75
-1.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 25.
Figure 26.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
No Load Output Swing
Positive Swing over Temperature
2.25
2.5
2
100°C
V
= ±3.3V
V
= ±3.3V
S
S
100W LOAD
NO LOAD
1.5
1
2
25°C
-40°C
0.5
0
1.75
1.5
-0.5
-1
-1.5
-2
1.25
0.75
-2.5
1
1.25
1.5
-2
-1
0
1
2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 27.
Figure 28.
Negative Swing over Temperature
Enabled Output Impedance
-1.25
-1.5
1000
100
10
V
= ±3.3V
S
100W LOAD
-1.75
-2
25°C
-40°C
100°C
1
0.1
0.1
-2.25
1
10
100
1000
-1.5
-1.25
-1
-0.75
INPUT VOLTAGE (V)
FREQUENCY (MHz)
Figure 29.
Figure 30.
Disabled Output Impedance
Switching Time
10000
1000
100
10
1
4
3.5
0.5
0
3
2.5
2
1.5
1
-0.5
-1
0.5
CFG
0
DISABLE TO ENABLE
-0.5
ENABLE TO DISABLE
1
-1.5
-1
0.1
1
10
100
1000
-50 -40 -30 -20 -10
0
10 20 30 40 50
FREQUENCY (MHz)
TIME (ns)
Figure 31.
Figure 32.
10
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
APPLICATION INFORMATION
INTRODUCTION
The LMH6583 is a high speed, fully buffered, non blocking, analog crosspoint switch. Having fully buffered inputs
allows the LMH6583 to accept signals from low or high impedance sources without the worry of loading the
signal source. The fully buffered outputs will drive 75Ω or 50Ω back terminated transmission lines with no
external components other than the termination resistor. When disabled, the outputs are in a high impedance
state. The LMH6583 can have any input connected to any (or all) output(s). Conversely, a given output can have
only one associated input.
INPUT AND OUTPUT EXPANSION
The LMH6583 has high impedance inactive states for both inputs and outputs allowing maximum flexibility for
Crosspoint expansion. In addition the LMH6583 employs diagonal symmetry in pin assignments. The diagonal
symmetry makes it easy to use direct pin to pin vias when the parts are mounted on opposite sides of a board.
As an example two LMH6583 chips can be combined on one board to form either an 16 x 16 crosspoint or a 32 x
8 crosspoint. To make a 16 x 16 cross-point all 16 input pins would be tied together (Input 0 on side 1 to input 15
on side 2 and so on) while the 8 output pins on each chip would be left separate. To make the 32 x 8 crosspoint,
the 8 outputs would be tied together while all 32 inputs would remain independent. In the 32 x 8 configuration it is
important not to have 2 connected outputs active at the same time. With the 16 x 16 configuration, on the other
hand, having two connected inputs active is a valid state. Crosspoint expansion as detailed above has the
advantage that the signal path has only one crosspoint in it at a time. Expansion methods that have cascaded
stages will suffer bandwidth loss far greater than the small loading effect of parallel expansion.
Output expansion is very straight forward. Connecting the inputs of two crosspoint switches has a very minor
impact on performance. Input expansion requires more planning. As shown in Figure 34 and Figure 35 there are
two ways to connect the outputs of the crosspoint switches. In Figure 34 the crosspoint switch outputs are
connected directly together and share one termination resistor. This is the easiest configuration to implement and
has only one drawback. Because the disabled output of the unused crosspoint (only one output can be active at
a time) has a small amount of capacitance the frequency response of the active crosspoint will show peaking.
This is illustrated in Figure 36 and Figure 37. In most cases this small amount of peaking is not a problem.
As illustrated in Figure 35 each crosspoint output can be given its own termination resistor. This results in a
frequency response nearly identical to the non expansion case. There is one drawback for the gain of 2
crosspoint, and that is gain error. With a 75Ω termination resistor the 1250Ω resistance of the disabled crosspoint
output will cause a gain error. In order to counter act this the termination resistors of both crosspoints should be
adjusted to approximately 71Ω. This will provide very good matching, but the gain accuracy of the system will
now be dependent on the process variations of the crosspoint resistors which have a variability of approximately
±20%.
1
1
1
1
1
2
3
4
1
2
1
1
1
2
2
2
2
IN
OUT
4 x 4
3
4
4 x 4
IN
OUT
4 x 4
OUT
IN
3
4
3
4
3
4
3
4
2
3
2
2
3
4
3
4
5
6
1
2
4
5
6
1
2
1
5
2
3
6
7
8
4 x 4
IN
OUT
4 x 4
IN
OUT
4 x 4
IN
OUT
3
4
7
8
3
4
7
8
4
Figure 33. Output Expansion
Figure 34. Input Expansion with
Shared Termination Resistors
Figure 35. Input Expansion with
Separate Termination Resistors
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
2
2
1
OUTPUT CONNECTED DIRECTLY
NO EXPANSION
OUTPUT CONNECTED DIRECTLY
1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-5
-6
-7
-8
NO EXPANSION
V
V
= ±3.3V
V
V
= ±5V
= 2 V
S
S
= 2 V
OUT
PP
OUT
PP
R
= 150W
R
= 150W
L
L
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. Input Expansion Frequency Response
Figure 37. Input Expansion Frequency Response
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Capacitive loads
of 5 pF to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. For
applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT
can be reduced slightly from the recommended values. When driving transmission lines the 50Ω or 75Ω
matching resistor makes the series output resistor unnecessary.
USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH AND INCREASE RELIABILITY
The LMH6583 crosspoint switch can offer enhanced bandwidth and reliability with the use of external buffers on
the outputs. The bandwidth is increased by unloading the outputs and driving a higher impedance. The 1 kΩ load
resistor was chosen to provide the best performance on our evaluation board. See Figure 9 in Typical
Performance Characteristics for an example of bandwidth achieved with less loading on the outputs. For this
technique to provide maximum benefit a very high speed amplifier such as the LMH6703 should be used, as
shown in Figure 38.
Besides offering enhanced bandwidth performance using an external buffer provides for greater system
reliability. The first advantage is to reduce thermal loading on the crosspoint switch. This reduced die
temperature will increase the life of the crosspoint. The second advantage is enhanced ESD reliability. It is very
difficult to build high speed devices that can withstand all possible ESD events. With external buffers the
crosspoint switch is isolated from ESD events on the external system connectors.
LMH6703
+
-
V
OUT
R
560W
560W
LMH6583
OUTPUT
BUFFER
L
1 kW
Figure 38. Buffered Output
12
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
In the example in Figure 38, the resistor RL is required to provide a load for the crosspoint output buffer. Without
RLexcessive frequency response peaking is likely and settling times of transient signals will be poor. As the value
of RL is reduced the bandwidth will also go down. The amplifier shown in the example is an LMH6703 this
amplifier offers high speed and flat bandwidth. Another suitable amplifiers is the LMH6702. The LMH6702 is a
faster amplifier that can be used to generate high frequency peaking in order to equalize longer cable lengths. If
board space is at a premium the LMH6739 or the LMH6734 are triple, selectable gain buffers which require no
external resistors.
CROSSTALK
When designing a large system such as a video router crosstalk can be a very serious problem. Extensive
testing in our lab has shown that most crosstalk is related to board layout rather than occurring in the crosspoint
switch. There are many ways to reduce board related crosstalk. Using controlled impedance lines is an important
step. Using well decoupled power and ground planes will help as well. When crosstalk does occur within the
crosspoint switch itself it is often due to signals coupling into the power supply pins. Using appropriate supply
bypassing will help to reduce this mode of coupling. Another suggestion is to place as much grounded copper as
possible between input and output signal traces. Care must be taken, though, not to influence the signal trace
impedances by placing shielding copper too closely. One other caveat to consider is that as shielding materials
come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low. Using
thin signal traces will result in unacceptable losses due to trace resistance. This effect becomes even more
pronounced at higher frequencies due to the skin effect. The skin effect reduces the effective thickness of the
trace as frequency increases. Resistive losses make crosstalk worse because as the desired signal is attenuated
with higher frequencies crosstalk increases at higher frequencies.
DIGITAL CONTROL
SWITCH
MATRIX
136
CONFIGURATION
REGISTER
CFG
BCST
RST
40
LOAD
REGISTER
DATA IN
DATA OUT
CS
CLK
MODE
Figure 39. Block Diagram
The LMH6583 has internal control registers that store the programming states of the crosspoint switch. The logic
is two staged to allow for maximum programming flexibility. The first stage of the control logic is tied directly to
the crosspoint switching matrix. This logic consists of one register for each output that stores the on/off state and
the address of which input to connect to. These registers are not directly accessible by the user. The second
level of logic is another bank of registers identical to the first, but set up as shift registers. These registers are
accessed by the user via the serial input bus. As described further below, there are two modes for programing
the LMH6582, SERIAL PROGRAMMING MODE and ADDRESSED PROGRAMMING MODE.
The LMH6583 is programmed via a serial input bus with the support of 4 other digital control pins. The Serial bus
consists of a clock pin (CLK), a serial data in pin (DIN), and a serial data out pin (DOUT). The serial bus is gated
by a chip select pin (CS). The chip select pin is active low. While the chip select pin is high all data on the serial
input pin and clock pins is ignored. When the chip select pin is brought low the internal logic is set to begin
receiving data by the first positive transition (0 to 1) of the clock signal. The chip select pin must be brought low
at least 5 ns before the first rising edge of the clock signal. The first data bit is clocked in on the next negative
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the clock signal.
Once the last valid data has been clocked in, the chip select pin must go high then the clock signal must make at
least one more low to high transition. Otherwise invalid data will be clocked into the chip. The data clocked into
the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of
the state of the Mode pin. The CFG pin is not dependent on the state of the Chip select pin. If no new data is
clocked into the chip subsequent pulses on the CFG pin will have no effect on device operation.
The programming format of the incoming serial data is selected by the MODE pin. When the mode pin is HIGH
the crosspoint can be programmed one output at a time by entering a string of data that contains the address of
the output that is going to be changed (Addressed Mode). When the mode pin is LOW the crosspoint is in Serial
Mode. In this mode the crosspoint accepts a 40 bit array of data that programs all of the outputs. In both modes
the data fed into the chip does not change the chip operation until the Configure pin is pulsed high. The configure
and mode pins are independent of the chip select pin.
THREE WIRE VS. FOUR WIRE CONTROl
There are two ways to connect the serial data pins. The first way is to control all 4 pins separately, and the
second option is to connect the CFG and the CS pins together for a 3 wire interface. The benefit of the 4 wire
interface is that the chip can be configured independently of the CS pin. This would be an advantage in a system
with multiple crosspoint chips where all of them could be programmed ahead of time and then configured
simultaneously. The 4 wire solution is also helpful in a system that has a free running clock on the CLK pin. In
this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being
clocked into the chip.
The three wire option provides the advantage of one less pin to control at the expense of having less flexibility
with the configure pin. One way around this loss of flexibility would be If the clock signal is generated by an
FPGA or microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip
select function is provided by the presence or absence of the clock signal.
SERIAL PROGRAMMING MODE
Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 40 bits
programs all 8 outputs of the crosspoint. The data is fed to the chip as shown in Table 1 through Table 4 (4
tables are required to show the entire data frame). The table is arranged such that the first bit clocked into the
crosspoint register is labeled bit number 0. The register labeled Load Register in Figure 39 is a shift register. If
the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then
additional data will be shifted into the register, and the desired data will be shifted out.
Also illustrated is the timing relationships for the digital pins in Figure 40. It is important to note that all the pin
timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS)
must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to
synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the
chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown
in Figure 40, the chip select pin state should always occur while the clock signal is low. The configure (CFG) pin
timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers.
14
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
T
T
-1
T
41
T
0
T
1
T
T
T
39
40
37
38
1
CLK
0
T
S
T
S
1
CS_N
0
1
CFG
0
T
T
S
H
1
DIN
0
I...
I
I
40
I
39
I
41
I
37
I
I
38
0
1
1
MODE
0
T
D
I
1
OUT
I
D
0
1
0
Figure 40. Timing Diagram for Serial Mode
Table 1. Serial Mode Data Frame (First 2 Words)(1)
Output 0
Output 1
Input Address
On = 0
Off = 1
4
Input Address
On = 0
Off = 1
9
LSB
0
MSB
3
LSB
5
MSB
8
1
2
6
7
(1) Off = TRI-STATE, Bit 0 is first bit clocked into device.
Table 2. Serial Mode Data Frame (Continued)
Output 2
Input Address
LSB
Output 3
On = 0
Off = 1
14
Input Address
On = 0
Off = 1
19
MSB
13
LSB
15
MSB
18
10
11
12
16
17
Table 3. Serial Mode Data Frame (Continued)
Output 4
Input Address
LSB
Output 5
On = 0
Off = 1
24
Input Address
On = 0
Off = 1
29
MSB
23
LSB
25
MSB
28
20
21
22
26
27
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
Table 4. Serial Mode Data Frame (Last 2 Words)(1)
Output 6
Input Address
LSB
Output 7
Input Address
LSB
On = 0
Off = 1
34
On = 0
Off = 1
39
MSB
33
MSB
38
30
31
32
35
36
37
(1) Bit 39 is last bit clocked into device.
ADDRESSED PROGRAMMING MODE
Addressed programming mode makes it possible to change only one output register at a time. To utilize this
mode the mode pin must be High. All other pins function the same as in serial programming mode except that
the word clocked in is 8 bits and is directed only at the output specified. In addressed mode the data format is
shown in Table 5.
Also illustrated is the timing relationships for the digital pins in Figure 41. It is important to note that all the pin
timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS)
must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to
synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the
chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown
in Figure 41, the chip select pin state should always occur while the clock signal is low. The configure (CFG) pin
timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers.
T
T
T
T
T
T
T
T
8
T
9
T
10
5
1
2
3
4
6
7
1
CLK
0
T
T
S
S
1
CS_N
0
1
CFG
0
T
H
T
S
1
DIN
0
I
I
I
I
3
I
4
A
2
A
A
1
1
O
2
0
1
MODE
0
1
OUT
HIGH IMPEDANCE
D
0
Figure 41. Timing Diagram for Addressed Mode
Table 5. Addressed Mode Word Format(1)
Output Address
LSB
Input Address
TRI-STATE
MSB
2
LSB
MSB
6
1 = TRI-STATE
0 = On
0
1
3
4
5
7
(1) Bit 0 is first bit clocked into device.
16
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
DAISY CHAIN OPTION IN SERIAL MODE
The LMH6583 supports daisy chaining of the serial data stream between multiple chips. This feature is available
only in the Serial programming mode. To use this feature serial data is clocked into the first chip DIN pin, and the
next chip DIN pin is connected to the DOUT pin of the first chip. Both chips may share a chip select signal, or the
second chip can be enabled separately. When the chip select pin goes low on both chips a double length word is
clocked into the first chip. As the first word is clocking into the first chip the second chip is receiving the data that
was originally in the shift register of the first chip (invalid data). When a full 40 bits have been clocked into the
first chip the next clock cycle begins moving the first frame of the new configuration data into the second chip.
With a full 80 clock cycles both chips have valid data and the chip select pin of both chips should be brought high
to prevent the data from overshooting. A configure pulse will activate the new configuration on both chips
simultaneously, or each chip can be configured separately. The mode, chip select, configure and clock pins of
both chips can be tied together and driven from the same sources.
SPECIAL CONTROL PINS
The LMH6583 has two special control pins that function independent of the serial control bus. One of these pins
is the reset (RST) pin. The RST pin is active high meaning that a logic 1 level the chip is configured with all
outputs disabled and in a high impedance state. The RST pin programs all the registers with input address 0 and
all the outputs are turned off. In this configuration the device draws only 20 mA. The reset pin can used as a
shutdown function to reduce power consumption. The other special control pin is the broadcast (BCST) pin. The
BCST pin is also active high and sets all the outputs to the on state connected to input 0. Both of these pins are
level sensitive and require no clock signal. The two special control pins overwrite the contents of the
configuration register.
THERMAL MANAGEMENT
The LMH6583 is packaged in a thermally enhanced Quad Flat Pack package. Even so, it is a high performance
device that produces a significant amount of heat. With a ±5V supply, the LMH6583 will dissipate approximately
1.1W of idling power with all outputs enabled. Idling power is calculated based on the typical supply current of
110 mA and a 10V supply voltage. This power dissipation will vary within the range of 800 mW to 1.4W due to
process variations. In addition, each equivalent video load (150Ω) connected to the outputs should be budgeted
30 mW of power. For a typical application with one video load for each output this would be a total power of 1.14
W. With a typical θJA of 27°C/W this will result in the silicon being 31°C over the ambient temperature. A more
aggressive application would be two video loads per output which would result in 1.38 W of power dissipation.
This would result in a 37°C temperature rise. For heavier loading, the HTQFP package thermal performance can
be significantly enhanced with an external heat sink and by providing for moving air ventilation. Also, be sure to
calculate the increase in ambient temperature from all devices operating in the system case. Because of the high
power output of this device, thermal management should be considered very early in the design process.
Generous passive venting and vertical board orientation may avoid the need for fan cooling or heat sinks. Also,
the LMH6583 can be operated with a ±3.3V power supply. This will cut power dissipation substantially while only
reducing bandwidth by about 10% (2 VPP output). The LMH6583 is fully characterized and factory tested at the
±3.3V power supply condition for applications where reduced power is desired.
If a heat sink is desired AAVD/Thermalloy part # 375324B00035G is the proper size for the LMH6583 package.
This heat sink comes with adhesive tape for ease in assembly. With natural convection the heat sink will reduce
the θJA from 27°C/W to approximately 21°C/W. Using a fan will increase the effectiveness of the heat sink
considerably. When doing thermal design it is important to note that everything from board layout to case
material will impact the actual θJA of the device. The θJA specified in the datasheet is for a typical board layout.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LMH6583
LMH6583
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
www.ti.com
5
4.5
4
3.5
3.0
2.5
2
1.5
1
JUNCTION TEMPERATURE = 125°C
0.5
0
q
JA
= 27°C/W
-40
-15
10
35
60
85
AMBIENT TEMPERATURE (°C)
Figure 42. Maximum Dissipation vs. Ambient Temperature
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power supply and ground traces away from the input and
output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 for more information). If digital control lines must cross
analog signal lines (particularly inputs) it is best if they cross perpendicularly. TI suggests the following evaluation
boards as a guide for high frequency layout and as an aid in device testing and characterization:
Device
Package
Evaluation Board Part Number
LMH6583
64-Pin HTQFP
LMH730156
18
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6583
LMH6583
www.ti.com
SNOSAP5E –APRIL 2006–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LMH6583
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6583YA/NOPB
ACTIVE
HTQFP
PAP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LMH6583YA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
LMH6583YA/NOPB
PAP
HTQFP
64
160
8 X 20
150
322.6 135.9 7620 15.2
13.1
13
Pack Materials-Page 1
PACKAGE OUTLINE
TM
PAP0064E
PowerPAD TQFP - 1.2 mm max height
SCALE 1.300
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
16
33
17
32
A
0.27
64X
60X 0.5
0.17
0.08
C A B
4X 7.5
C
SEATING PLANE
1.2 MAX
(0.127)
TYP
SEE DETAIL A
17
32
0.25
GAGE PLANE
(1)
33
16
0.15
0.05
0.08 C
0 -7
0.75
0.45
65
6.08
4.67
DETAIL A
A
17
TYPICAL
1
48
49
64
4228332/A 01/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PAP0064E
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
8)
NOTE 8
(
6.08)
SYMM
SOLDER MASK
49
64
DEFINED PAD
64X (1.5)
(R0.05)
TYP
1
48
64X (0.3)
65
(11.4)
SYMM
(1.3 TYP)
60X (0.5)
33
16
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
17
32
SEE DETAILS
(1.3 TYP)
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4228332/A 01/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
PAP0064E
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
6.08)
BASED ON 0.125
THICK STENCIL
SYMM
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
64
49
64X (1.5)
1
48
64X (0.3)
(R0.05) TYP
SYMM
65
(11.4)
60X (0.5)
33
16
METAL COVERED
BY SOLDER MASK
17
32
(11.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
6.80 X 6.80
6.08 X 6.08 (SHOWN)
5.55 X 5.55
0.125
0.15
0.175
5.14 X 5.14
4228332/A 01/2022
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明