首页 |元器件品牌

LMH6586 [TI]

5V、32 输入 16 输出视频交叉点开关;
LMH6586
型号： LMH6586
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

5V、32 输入 16 输出视频交叉点开关

开关
文件： 总35页 (文件大小：1041K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
LMH6586 32x16 Video Crosspoint Switch  
Check for Samples: LMH6586  
1
FEATURES  
DESCRIPTION  
The LMH6586 is  
2
•
•
32 Inputs and 16 Outputs  
a non-blocking analog video  
AC-Coupled Inputs with Integrated DC Restore  
Clamp  
crosspoint switch designed for routing standard  
NTSC or PAL composite video signals. The non-  
blocking architecture allows any of the 32 inputs to be  
connected to any of the 16 outputs, including any  
input that is already connected. Each input has an  
integrated DC restore clamp for biasing of the AC-  
coupled video signal. The output buffers have a  
common selectable gain setting of 1X or 2X and can  
drive loads of 150Ω.  
•
•
Individually Addressable Outputs  
Pin-Selectable Output Buffer Gain (1 V/V or 2  
V/V)  
•
•
•
•
•
•
–3 dB Bandwidth = 66 MHz  
DG = 0.05%, DP = 0.05° @ RL = 150Ω, AV = 2V/V  
−70 dB Off-Isolation @ 6 MHz  
Individual Input and Output Shutdown Modes  
Device Power Down Mode  
The LMH6586 features two types of input signal  
detection for convenient monitoring of activity on any  
input channel. Video detection can be configured to  
indicate when either “presence of video” or “loss of  
video” is detected across the video threshold level  
controlled by a programmable register. Additionally,  
sync detection can be configured to indicate when  
“loss of sync” is detected across the sync threshold  
level controlled by a DC voltage input.  
Video Detection with Programmable Threshold  
(8 Levels)  
•
•
Sync Detection with Pin-Configurable  
Threshold  
100 kHz I2C Interface with 2-Bit Configurable  
Slave Address  
The switch configuration and other parameters are  
programmable via the I2C bus interface. The slave  
device address is configurable via two external pins  
allowing up to four LMH6586 devices, each with a  
unique address, on a common I2C bus. This helps  
facilitate expansion of the crosspoint matrix array size  
(e.g. 64 x 16). The LMH6586 operates from a  
common single 5V supply for its analog sections as  
well as its control logic and I2C interface. The  
LMH6586 is offered in a space-saving 80-pin TQFP.  
•
•
Single 5V Supply Operation  
Extra Video Output (VOUT_16) for External  
Video Sync Separator  
APPLICATIONS  
•
•
CCTV Security and Surveillance Systems  
Analog Video Routing  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Application Diagram  
5V  
MICROCONTROLLER  
0.1 mF  
5V  
0.1 mF  
10k  
0.1 mF  
5V  
DVDD  
DVSS  
5V  
5V  
0.1 mF  
75W  
0.1 mF  
75W  
VIN_15  
VIN_31  
LMH6586  
32 X 16 VIDEO  
CROSSPOINT SWITCH  
5V  
5V  
0.1 mF  
75W  
0.1 mF  
75W  
VIN_0  
VIN_16  
5V  
V
DD  
GND  
0.1 mF  
75W  
75W  
0.1 mF  
LMH1980  
SYNC SEPARATOR  
SYNC  
OUTPUTS  
OPTIONAL FUNCTION  
2
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Functional Diagram  
LMH6586  
32 INPUTS  
16 OUTPUTS  
INTERNAL BLOCK DIAGRAM  
VREF_SYNC  
32 COMPARATORS  
2
TO I C BLOCK  
2
2
FROM I C BLOCK  
32  
FROM I C BLOCK  
16  
0.1 mF  
VOUT 0  
VIN_0  
VIN 0  
VOUT 0  
1X/2X  
1X/2X  
1X  
1X  
1X  
75W  
OUTPUT  
POWER  
SAVE  
INPUT  
POWER  
SAVE  
32 x 16  
SWITCH  
MATRIX  
16 OUTPUTS  
32 VIDEO  
INPUTS  
VOUT 15  
VOUT 16  
VOUT 15  
VOUT 16  
0.1 mF  
VIN_31  
VIN 31  
TO SYNC SEPARATOR  
(OPTIONAL)  
75W  
32 BLOCKS  
DC RESTORE  
CLAMP  
VREF_CLAMP  
ADDR [1]  
ADDR [0]  
GAIN_SEL  
+
2
TO I C BLOCK  
VIDEO  
DETECT  
2
DAC  
2
I C  
+
BLOCK  
32 BLOCKS  
FROM I C BLOCK  
FLAG  
SCL SDA  
RESET PWDN  
Figure 1. Functional Diagram  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Connection Diagram  
60 VIN_15  
59  
58 VIN_13  
VIN_31  
1
2
3
4
5
VIN_14  
VIN_30  
VIN_29  
VIN_28  
VIN_27  
VIN_26  
VIN_25  
VIN_24  
VDD  
VIN_12  
VIN_11  
VIN_10  
57  
56  
55  
54  
6
7
8
9
VIN_9  
53 VIN_8  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
VDD  
GND  
LMH6586  
GND  
10  
VIN_23 11  
VIN_7  
VIN_6  
VIN_5  
VIN_22  
12  
VIN_21  
VIN_20  
13  
14  
VIN_4  
VIN_3  
VIN_2  
VIN_19 15  
VIN_18  
16  
VIN_17  
VIN_16  
17  
18  
VIN_1  
VIN_0  
VDD  
VDD 19  
20  
41 GND  
GND  
4
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
PIN DESCRIPTIONS  
Pin #  
1
Pin Name  
VIN_31  
VIN_30  
VIN_29  
VIN_28  
VIN_27  
VIN-26  
VIN_25  
VIN_24  
VDD  
Pin Description  
VIDEO INPUT 31  
VIDEO INPUT 30  
VIDEO INPUT 29  
VIDEO INPUT 28  
VIDEO INPUT 27  
VIDEO INPUT 26  
VIDEO INPUT 25  
VIDEO INPUT 24  
VDD (connect to 5V supply)  
GND  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
GND  
VIN_23  
VIN_22  
VIN_21  
VIN_20  
VIN_19  
VIN_18  
VIN_17  
VIN_16  
VDD  
VIDEO INPUT 23  
VIDEO INPUT 22  
VIDEO INPUT 21  
VIDEO INPUT 20  
VIDEO INPUT 19  
VIDEO INPUT 18  
VIDEO INPUT 17  
VIDEO INPUT 16  
VDD (connect to 5V supply)  
GND  
GND  
VBIAS 1  
VOUT_16  
VOUT_15  
VOUT_14  
VOUT_13  
VOUT_12  
VOUT_11  
VOUT_10  
VOUT_9  
VOUT_8  
GND  
VBIAS 1 (connect to external 0.1 µF capacitor)  
VIDEO OUTPUT 16  
VIDEO OUTPUT 15  
VIDEO OUTPUT 14  
VIDEO OUTPUT 13  
VIDEO OUTPUT 12  
VIDEO OUTPUT 11  
VIDEO OUTPUT 10  
VIDEO OUTPUT 9  
VIDEO OUTPUT 8  
GND  
VDD  
VDD (connect to 5V supply)  
VIDEO OUTPUT 7  
VIDEO OUTPUT 6  
VIDEO OUTPUT 5  
VIDEO OUTPUT 4  
VIDEO OUTPUT 3  
VIDEO OUTPUT 2  
VIDEO OUTPUT 1  
VIDEO OUTPUT 0  
GND  
VOUT_7  
VOUT_6  
VOUT_5  
VOUT_4  
VOUT_3  
VOUT_2  
VOUT_1  
VOUT_0  
GND  
VDD  
VDD (connect to 5V supply)  
VIDEO INPUT 0  
VIN_0  
VIN_1  
VIDEO INPUT 1  
VIN_2  
VIDEO INPUT 2  
VIN_3  
VIDEO INPUT 3  
VIN_4  
VIDEO INPUT 4  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
PIN DESCRIPTIONS (continued)  
Pin #  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
Pin Name  
VIN_5  
Pin Description  
VIDEO INPUT 5  
VIN_6  
VIDEO INPUT 6  
VIN_7  
VIDEO INPUT 7  
GND  
GND  
VDD  
VDD (connect to 5V supply)  
VIDEO INPUT 8  
VIN_8  
VIN_9  
VIDEO INPUT 9  
VIN_10  
VIN_11  
VIN_12  
VIN_13  
VIN_14  
VIN_15  
GAIN  
VIDEO INPUT 10  
VIDEO INPUT 11  
VIDEO INPUT 12  
VIDEO INPUT 13  
VIDEO INPUT 14  
VIDEO INPUT 15  
GAIN SELECT INPUT (set low for 1X gain, or set high for 2X gain)  
VDD (connect to 5V supply)  
GND  
VDD  
GND  
VBIAS 2  
VREF_SYNC  
VREF_CLAMP  
R_EXT  
GND  
VBIAS 2 (connect to external 0.1 µF capacitor)  
SYNC DETECTION THRESHOLD VOLTAGE INPUT (bias to 350 mVDC, recommended)  
DC RESTORE CLAMP VOLTAGE INPUT (bias to 300 mVDC, recommended)  
R_EXT BIAS RESISTOR (connect to external 10 kΩ 1% resistor)  
GND  
VDD  
VDD (connect to 5V supply)  
PWDN  
POWER DOWN INPUT (set low for normal operation, set high to power down all video I/O  
blocks and I2C interface)  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
ADDR [0]  
ADDR [1]  
SDA  
I2C SLAVE ADDRESS BIT 0 INPUT (set low for bit0 = 0, or set low for bit0 = 1)  
I2C SLAVE ADDRESS BIT 1 INPUT (set low for bit1 = 0, or set low for bit1 = 1)  
I2C DATA IN/OUT (requires external pull-up resistor to DVDD supply)  
I2C CLOCK INPUT (requires external pull-up resistor to DVDD supply)  
DETECTION FLAG OUTPUT (active high)  
SCL  
FLAG  
DVDD  
DVSS  
GND  
DIGITAL VDD (connect to 5V supply)  
DIGITAL GND  
GND  
VDD  
VDD (connect to 5V supply)  
RESET  
RESET INPUT (set low for normal operation, set high to reset device registers to default  
settings)  
6
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)  
ESD Tolerance(3)  
Human Body Model  
Machine Model  
2500V  
250V  
Supply Voltage (VDD  
)
5V  
Video Input Voltage Range, VIN  
Storage Temperature Range  
Lead Temperature (Soldering, 10 sec)  
Junction Temperature  
−0.3V to VDD +0.3V  
−65°C to +150°C  
300°C  
+150°C  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical  
Characteristics tables.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and  
specifications.  
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of  
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).  
Operating Ratings(1)(2)  
Supply Voltage (VDD  
)
5V ± 10%  
−40°C ≤ TA ≤ 85°C  
25°C/W  
Ambient Temperature Range  
θJA  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical  
Characteristics tables.  
(2) The maximum power dissipation is a function of TJ(MAX) and θJA. The maximum allowable power dissipation at any ambient temperature  
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.  
Electrical Characteristics(1)  
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, VREF_CLAMP = 300 mV, RL =  
150Ω, CL = 12 pF.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
DC Specifications  
VDD  
IDD  
Operating Supply Voltage  
Supply Current  
4.5  
5.5  
V
No Load, AV = 1 V/V  
300  
1.5  
360  
mA  
mA  
Power Save Supply Current  
No Load, AV = 1 V/V, SCL= SDA=  
PWDN= DVDD  
AV  
Gain  
2x Gain Buffer  
1x Gain Buffer  
AV = 1 V/V  
1.92  
0.95  
2.00  
0.99  
1.2  
2.07  
1.03  
3
V/V  
ΔAV_CH-CH Gain Matching (Ch to Ch)  
%
VOS  
Output Offset Voltage  
AV = 1 V/V, No Load (referenced to DC  
restored input)  
60  
mV  
VDET_LSB  
VDET  
Video Detection Threshold LSB  
Video Detection Threshold Offset  
85  
95  
105  
mV  
mV  
Video detection threshold offset  
measured above sync tip level of DC  
restored input  
±50  
AC Specifications  
BWSS  
BWLS  
tr/tf  
Small Signal Bandwidth (−3 dB)  
VOUT = 20 mVPP  
66  
29  
35  
5
MHz  
MHz  
ns  
Large Signal Bandwidth (−3 dB)  
Rise/Fall Time  
VOUT = 1.5 VPP  
10% to 90%, VOUT = 2 VPP  
50% to 50%, VOUT = 2 VPP  
50% to 50%, VOUT = 2 VPP  
tp  
Propagation Delay  
ns  
tpCh-Ch  
Ch-Ch Propagation Delay  
5
ns  
(1) All voltages are measured with respect to GND, unless otherwise specified.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
Submit Documentation Feedback  
7
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Electrical Characteristics(1) (continued)  
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, VREF_CLAMP = 300 mV, RL =  
150Ω, CL = 12 pF.  
Symbol  
CT  
Parameter  
Adjacent CH Crosstalk  
Conditions  
f = 6 MHz, AV = 2 V/V  
Min  
Typ  
−58  
−70  
0.05  
0.05  
Max  
Units  
dB  
Off Iso  
DG  
Input-Output Off-Isolation  
f = 6 MHz, AV = 2 V/V  
AV = 2 V/V, 3.5 MHz  
AV = 2 V/V, 3.5 MHz  
dB  
Differential Gain Error for NTSC  
Differential Phase Error for NTSC  
%
DP  
deg  
I2C Interface and Digital Pin Logic Levels  
VIL  
VIH  
IIN  
Low Input Voltage  
High Input Voltage  
Input Current  
1.5  
V
V
3.3  
±1  
µA  
V
VOL  
Low Output Voltage  
IOL = 3 mA  
0.5  
8
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
 
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
V
DD  
OTHER_INPUTS  
VIDEO_INPUT  
V
SS  
OTHER INPUT CIRCUIT DIAGRAM  
V
SS  
VIDEO INPUT CIRCUIT DIAGRAM  
V
DD  
V
DD  
VIDEO_SYNC_DETECT  
CROSSPOINT_OUTPUT  
V
SS  
V
SS  
VIDEO OUTPUT CIRCUIT DIAGRAM  
VIDEO SYNC DETECT CIRCUIT DIAGRAM  
SDA  
SCL  
V
V
SS  
SS  
2
2
I C CLOCK CIRCUIT DIAGRAM  
I C DATA CIRCUIT DIAGRAM  
Figure 2. Logic Diagram  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Typical Performance Characteristics  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Small Signal Bandwidth  
Small Signal Bandwidth  
4
2
8
6
4
0
-2  
-4  
-6  
2
0
-8  
-10  
-2  
-4  
-6  
-12  
-14  
-16  
A
= 1V/V  
A
= 2V/V  
V
V
R
= 150W  
R
= 150W  
L
L
10k  
100k  
1M  
10M  
100M  
10k  
100k  
1M  
10M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 3.  
Figure 4.  
Medium Signal Bandwidth  
Medium Signal Bandwidth  
4
2
8
6
4
0
-2  
-4  
2
-6  
0
-8  
-10  
-12  
-14  
-16  
-2  
-4  
-6  
A
= 1V/V  
V
A
= 2V/V  
V
R
= 150W  
L
R
= 150W  
L
10k  
100k  
1M  
10M  
100M  
10k  
100k  
1M  
10M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 5.  
Figure 6.  
Large Signal Bandwidth  
Large Signal Bandwidth  
1
-3  
8
6
4
2
-7  
0
-11  
-15  
-19  
-23  
-2  
-4  
-6  
-8  
-10  
-12  
A
= 2V/V  
A
= 1V/V  
V
V
R
= 150W  
R
= 150W  
L
L
10k  
100k  
1M  
10M  
100M  
10k  
100k  
1M  
10M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 7.  
Figure 8.  
10  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Small Signal Gain Flatness  
Small Signal Gain Flatness  
0.1  
0.05  
0
6.1  
6.05  
6
A
= 2V/V  
A
= 1V/V  
V
V
R
= 150W  
R
= 150W  
L
L
-0.05  
-0.1  
-0.15  
-0.2  
-0.25  
-0.3  
5.95  
5.9  
5.85  
5.8  
5.75  
100k  
1M  
10k  
10k  
100k  
1M  
FREQUENCY (Hz)  
Figure 9.  
FREQUENCY (Hz)  
Figure 10.  
Small Signal Gain Peaking  
Small Signal Gain Peaking  
3
2.5  
2
6.8  
6.6  
A
= 1V/V  
V
A
= 2V/V  
V
R
= 150W  
L
R
= 150W  
L
6.4  
6.2  
6
1.5  
1
0.5  
0
-0.5  
-1  
5.8  
5.6  
-1.5  
-2  
10k  
100k  
1M  
10M  
100M  
10k  
100k  
1M  
10M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 11.  
Figure 12.  
Large Signal Gain Flatness  
Large Signal Gain Flatness  
0.05  
0
6.05  
6
A
= 1V/V  
V
A
= 2V/V  
V
R
= 150W  
L
R
= 150W  
L
-0.05  
-0.1  
5.95  
5.9  
-0.15  
5.85  
10k  
100k  
1M  
10k  
100k  
1M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 13.  
Figure 14.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Large Signal Gain Peaking  
Large Signal Gain Peaking  
6.15  
6.1  
6.05  
6
0.15  
A
= 2V/V  
A
= 1V/V  
V
V
R
= 150W  
R
= 150W  
L
L
0.1  
0.05  
0
-0.05  
-0.1  
-0.15  
-0.2  
5.95  
5.9  
5.85  
10k  
100k  
1M  
10M  
100M  
100M  
100M  
10M  
10k  
100k  
1M  
100M  
100M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 15.  
Figure 16.  
Adjacent Channel Crosstalk  
Adjacent Channel Crosstalk  
0
-20  
0
-20  
A
= 1V/V  
A
= 2V/V  
V
V
R
= 150W  
R
= 150W  
L
L
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-100  
-120  
-120  
10k  
100k  
1M  
10M  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (HZ)  
Figure 17.  
Figure 18.  
All Hostile Crosstalk  
All Hostile Crosstalk  
0
-20  
0
-10  
-20  
A
= 2V/V  
A
= 1V/V  
V
V
R
= 150W  
R
= 150W  
L
L
-40  
-30  
-40  
-50  
-60  
-80  
-60  
-100  
-70  
-80  
-120  
10k  
100k  
1M  
10M  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 19.  
Figure 20.  
12  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Off Isolation  
Small Signal Pulse Response  
-20  
-30  
A
= 1V/V  
V
A
= 2V/V  
V
R
= 1 kW  
L
R
= 150W  
L
INPUT  
10 mV/DIV  
-40  
-50  
-60  
-70  
-80  
OUTPUT  
-90  
10 mV/DIV  
-100  
-110  
10  
100  
1M  
10M  
100M  
25 ns/DIV  
FREQUENCY (Hz)  
Figure 21.  
Figure 22.  
Small Signal Pulse Response  
Small Signal Pulse Response  
A
V
= 2V/V  
A
= 1V/V  
V
R
L
= 1 kW  
R
= 150W  
L
INPUT  
10 mV/DIV  
INPUT  
10 mV/DIV  
OUTPUT  
20 mV/DIV  
OUTPUT  
10 mV/DIV  
25 ns/DIV  
25 ns/DIV  
Figure 24.  
Figure 23.  
Small Signal Pulse Response  
Small Signal Pulse Response with Capacitive Load  
A
= 1V/V  
V
A
= 2V/V  
V
C
= 30 pF  
L
R
= 150W  
L
INPUT  
10 mV/DIV  
INPUT  
10 mV/DIV  
OUTPUT  
10 mV/DIV  
OUTPUT  
20 mV/DIV  
25 ns/DIV  
25 ns/DIV  
Figure 25.  
Figure 26.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Small Signal Pulse Response with Capacitive Load  
Medium Signal Pulse Response  
A
= 2V/V  
V
A
V
= 1V/V  
C
= 30 pF  
L
R
L
= 1 kW  
INPUT  
10 mV/DIV  
INPUT  
50 mV/DIV  
OUTPUT  
10 mV/DIV  
OUTPUT  
50 mV/DIV  
25 ns/DIV  
25 ns/DIV  
Figure 28.  
Figure 27.  
Medium Signal Pulse Response  
= 2V/V  
Medium Signal Pulse Response  
= 1V/V  
A
V
A
V
R
L
= 1 kW  
R
= 150W  
L
INPUT  
INPUT  
50 mV/DIV  
50 mV/DIV  
OUTPUT  
OUTPUT  
100 mV/DIV  
50 mV/DIV  
25 ns/DIV  
Figure 30.  
25 ns/DIV  
Figure 29.  
Medium Signal Pulse Response  
Medium Signal Pulse Response with Capacitive Load  
A
V
= 2V/V  
A
= 1V/V  
V
R
L
= 150W  
C
= 30 pF  
L
INPUT  
50 mV/DIV  
INPUT  
50 mV/DIV  
OUTPUT  
100 mV/DIV  
OUTPUT  
50 mV/DIV  
25 ns/DIV  
Figure 31.  
25 ns/DIV  
Figure 32.  
14  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Medium Signal Pulse Response with Capacitive Load  
Large Signal Pulse Response  
A = 1V/V  
V
A
= 2V/V  
V
R = 1 kW  
L
C
= 30 pF  
L
INPUT  
200 mV/DIV  
INPUT  
50 mV/DIV  
OUTPUT  
200 mV/DIV  
OUTPUT  
100 mV/DIV  
25 ns/DIV  
Figure 34.  
25 ns/DIV  
Figure 33.  
Large Signal Pulse Response  
Large Signal Pulse Response  
A
= 2V/V  
V
A
V
= 1V/V  
R
= 1 kW  
L
R
L
= 150W  
INPUT  
INPUT  
200 mV/DIV  
200 mV/DIV  
OUTPUT  
OUTPUT  
500 mV/DIV  
200 mV/DIV  
25 ns/DIV  
Figure 36.  
25 ns/DIV  
Figure 35.  
Large Signal Pulse Response  
= 2V/V  
Large Signal Pulse Response with Capacitive Load  
A
= 1V/V  
A
V
V
C
= 30 pF  
R
= 150W  
L
L
INPUT  
INPUT  
200 mV/DIV  
200 mV/DIV  
OUTPUT  
OUTPUT  
500 mV/DIV  
200 mV/DIV  
25 ns/DIV  
Figure 37.  
25 ns/DIV  
Figure 38.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Large Signal Pulse Response with Capacitive Load  
Differential Phase  
A
= 2V/V  
A
V
= 1V/V  
V
C
= 30 pF  
R
L
= 1 kW  
L
INPUT  
200 mV/DIV  
REF  
OUTPUT  
500 mV/DIV  
0.6 0.7 0.8 0.9  
1
1.1 1.2 1.3  
25 ns/DIV  
OUTPUT VIDEO LEVEL (V)  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
Figure 39.  
Figure 40.  
Differential Phase  
Differential Phase  
A
V
= 2V/V  
REF  
R
L
= 1 kW  
REF  
A
= 1V/V  
V
R
= 150W  
L
0.6 0.7 0.8  
0.9  
1
1.1 1.2 1.3  
0.6 0.7 0.8  
0.9  
1
1.1 1.2 1.3  
OUTPUT VIDEO LEVEL (V)  
OUTPUT VIDEO LEVEL (V)  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
Figure 41.  
Figure 42.  
Differential Phase  
Differential Gain  
A
V
= 2V/V  
A
V
= 1V/V  
R
L
= 150W  
R
= 1 kW  
L
REF  
REF  
0.6 0.7 0.8 0.9  
1
1.1 1.2 1.3  
0.6 0.7 0.8 0.9  
1
1.1 1.2 1.3  
OUTPUT VIDEO LEVEL (V)  
OUTPUT VIDEO LEVEL (V)  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
Figure 43.  
Figure 44.  
16  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Typical Performance Characteristics (continued)  
Unless otherwise specified, TA = 25°C, VDD = 5V, REXT = 10 kΩ 1%, RL = 150Ω, CL = 12 pF. Small Signal Input Signal = 20  
mVPP, Medium Signal Input Signal = 200 mVPP , Large Signal Input Signal = 750 mVPP  
Differential Gain  
Differential Gain  
REF  
REF  
A
= 1V/V  
V
A
= 2V/V  
V
R
= 150W  
L
R
= 1 kW  
L
0.6 0.7 0.8  
0.9  
1
1.1 1.2 1.3  
0.6 0.7 0.8  
0.9  
1
1.1 1.2 1.3  
OUTPUT VIDEO LEVEL (V)  
OUTPUT VIDEO LEVEL (V)  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
Figure 45.  
Figure 46.  
Differential Gain  
Harmonic Distortion  
-40  
-50  
REF  
A
V
= 1V/V  
R
L
= 150W  
-60  
-70  
-80  
-90  
A
= 2V/V  
V
R
= 150W  
L
-100  
0.6 0.7 0.8 0.9  
1
1.1 1.2 1.3  
1M  
10M  
OUTPUT VIDEO LEVEL (V)  
FREQUENCY (Hz)  
0.6V Output Level = 0 IRE  
1.3V Output Level = 100 IRE  
Figure 47.  
Figure 48.  
Harmonic Distortion  
-40  
-50  
A
V
= 2V/V  
R
L
= 150W  
-60  
-70  
-80  
-90  
-100  
1M  
10M  
FREQUENCY (Hz)  
Figure 49.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
APPLICATION INFORMATION  
FUNCTIONAL OVERVIEW  
The LMH6586 is a non-blocking, analog video crosspoint switch with 32 input channels and 16 output channels.  
The inputs have integrated DC restore clamp circuits for biasing the AC-coupled video inputs. The fully buffered  
outputs have selectable gain and can drive one back-terminated video load (150Ω). The LMH6586 includes an  
extra output (VOUT_16) with 1X fixed gain that can be used to feed any input's video signal to an external video  
sync separator, such as the LMH1980 or LMH1981.  
Each input and each output can be individually placed in shutdown mode by programming the input shutdown  
and output shutdown registers, respectively. Additionally, the PWDN pin (pin 70) can be set high to enable Power  
Down mode, which shuts down all input and output video channels while preserving all register settings.  
The LMH6586 also features both video detection and sync detection functions on each input channel. Additional  
flexibility is provided by user-defined threshold levels for both video and sync detection features. The status of  
both detection schemes can be read from the video and sync detection status registers. Additionally, the FLAG  
output (pin 75) can be used to indicate if video detection or sync detection is triggered on any combination of  
input channels and detection types enabled by the user.  
OUTPUT BUFFER GAIN  
The LMH6586 has an output buffer with a selectable gain of 1X or 2X. When the GAIN_SEL input (pin 61) is set  
low, output channels 0–15 will have a gain of 1X. When it is set high, they will have a gain of 2X. Regardless of  
the gain select setting, output channel 16 has 1X fixed gain since the output is intended to drive an optional  
external sync separator through a 0.1 µF capacitor and no load termination.  
VIDEO DETECTION  
This type of detection can be configured to indicate when an input's video signal is detected above the threshold  
level (“presence of video” ) or below the threshold level (“loss of video”). The video threshold voltage level is  
common to all 32 input channels and is selectable by programming register 0x1D. As shown in Table 1, the three  
LSBs (bits 2:0) of this register can be used to set the threshold level in 95 mV steps (typical) above to the sync  
tip level of the DC-restored input. Additionally, to prevent undesired triggering on high-frequency picture content,  
such as on-screen display (OSD) or text, the detection circuit actually analyzes a low-pass-filtered version of the  
video signal. The first-order RC filter is included on-chip and has a corner frequency of about 1 kHz.  
Registers 0x04 to 0x07 (read-only) contain the video detection status bits for all 32 input channels. Any input (m)  
has a video detection status bit (VD_m) that can flag high when either loss of video or presence of video is  
detected, depending on the respective invert control bit. Registers 0x0C to 0x0F contain the video detection  
invert control bits for all input channels. When the invert bit (VD_INV_m) is set to 0 (default setting), the  
respective status bit (VD_m) will flag high when loss of video is detected on the input; otherwise, when the invert  
bit is set to 1, the status bit will flag high when presence of video is detected.  
Table 1. Video Detect Threshold Voltage(1)  
Register  
0x1D [2:0]  
Threshold level above the  
sync tip level  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
491 mV  
587 mV  
683 mV  
778 mV  
873 mV  
968 mV  
1062 mV  
1156 mV  
(1) See Video Detect parameters in Electrical Characteristics  
18  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
 
 
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
The following example illustrates a practical use of video detection in a real-world system. A bank's ATM  
surveillance system could consist of a video camera, a LMH6586 crosspoint switch, a video recorder, and control  
system. When no one is using the ATM, the area being monitored by the camera could have strong backlighting,  
so the camera would output a normally high video level. When a person approaches the area, most of the  
backlighting would be blocked by the person and cause a measurable decrease in the video level. This change  
in camera's video level could be detected by the LMH6586, which could then flag the security system to begin  
recording of the activity. Once the person leaves the area, the LMH6586 could clear the flag.  
SYNC DETECTION  
The LMH6586 also features a sync detection circuit that can indicate when an input's negative-going sync pulse  
is not detected below the threshold level (“loss of sync”). The sync threshold voltage level is common to all 32  
input channels and is defined by the bias voltage on the VREF_SYNC input (pin 65), which may be set using a  
simple voltage divider circuit. The recommended voltage level at the VREF_SYNC pin is 350 mV to ensure  
proper operation.  
Registers 0x00 to 0x03 (read-only) contain the sync detection status bits for all 32 input channels. Any input (m)  
has a sync detection status bit (SD_m) that can flag high when a loss of sync is detected; otherwise, the status  
bit will be low to indicate presence of sync.  
DETECTION FLAG OUTPUT  
The FLAG output (pin 75) can flag high if either video detection or sync detection is triggered based on the user-  
defined enable settings for the video and sync detection status bits. Any of the input's video detection status bits  
(VD_m) and sync detection status bits (SD_m) can be logically OR-ed into this single FLAG output pin. Registers  
0x10 to 0x13 contain the video detection enable bits and registers 0x14 to 0x17 contain the sync detection  
enable bits for all input channels. Any input (m) has both a video detection enable bit (VD_EN_m) and a sync  
detection enable bit (SD_EN_m). When any enable bit is set low, the respective status bit will be excluded from  
the OR-ing function used to set the FLAG output; otherwise, when the enable bit is set high, the respective status  
bit will be included in the FLAG output function. Therefore, the FLAG will only logical-OR the status bits of the  
channel(s) and type(s) of detection that are specifically enabled by the user.  
SWITCH MATRIX  
The LMH6586 uses 512 CMOS analog switches to form a 32 x 16 crosspoint switch. The LMH6586 is a non-  
blocking crosspoint switch which means that any one of the 32 inputs can be routed to any of the 16 outputs.  
The switch can only be configured by programming through the I2C bus interface.  
DC RESTORATION  
Because the LMH6586 uses a single 5V supply and typical composite video signals contain signal components  
both above and below 0V (video blanking level), proper input signal biasing is required to ensure the video signal  
is within the operating range of the amplifier. To simplify the external biasing circuitry, each input of the LMH6586  
has a dedicated DC restore clamp circuit to allow AC-coupled input operation using a 0.1 uF coupling capacitor.  
Please refer to AC COUPLING for details on how the coupling capacitor value was determined.  
AC COUPLING  
Each video input uses an integrated DC restore clamp circuit to servo the sync tip of the AC-coupled video input  
signal to the DC voltage received at the VREF_CLAMP input (pin 66). For proper AC-coupled operation, the  
LMH6586 requires video signals with negative sync pulses. The VREF_CLAMP level can be set in range of 300  
mV to 1.0V using a voltage divider network. For optimum performance and reduced power consumption, it is  
recommended to set VREF_CLAMP to 300 mV. Therefore, assuming a video input amplitude of 1VPP, the bottom  
of the sync tip level would be clamped to 300 mV above ground and the peak white video level would be at 1.3V.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
19  
Product Folder Links: LMH6586  
 
 
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Figure 50. Input Video Signal Before DC Restore Clamp  
Figure 51. Input Video Signal After DC Restore Clamp  
The equivalent DC restore clamp circuit is shown below.  
+5V  
V_CLAMP  
300 mV  
7.8 mA  
+
-
VIN  
1.37 mA  
C
75W  
CLAMP CIRCUIT  
Figure 52. Clamp Circuit  
20  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Typically the clamp voltage is set to 300 mV. During the sync pulse period, the clamp circuit amplifier sources  
current and the coupling capacitor will not discharge. However, during the active video period, the clamp  
amplifier will sink current and cause the coupling capacitor to discharge through the 75Ω resistor. To limit this  
discharge to an acceptable value we must choose an appropriate value of the AC coupling capacitor. The value  
of the AC coupling capacitor can be calculated as follows:  
Cap Discharge Time T = Line Period – Sync Period  
T = 63.5 µs – 4.7 µs  
T= 58.8 µs  
Discharge current I = 1.37 µA  
Charge Q = I*T  
Q = 1.37 µA * 58.8 µs  
Q = 80.55 pC  
Q = C*V  
C = Q/V  
Typical acceptable voltage drop V = 0.1% of 700 mV  
V = 0.7 mV  
Capacitor Value C = 80.55 pC/ 0.7 mV  
C = 0.115 µF  
Thus the suggested AC coupling capacitor value is 0.1 µF. A larger value will reduce line droop at the expense of  
longer input settling time.  
VIDEO INPUTS AND OUTPUTS  
The LMH6586 has 32 inputs which accept standard NTSC or PAL composite video signals. The input video  
signal should be AC coupled through a 0.1 µF coupling capacitor for proper operation. Each input is buffered  
before the switch matrix, which provides high input impedance. Input buffering enables any single output to be  
broadcasted to all 16 outputs at a time without loading of the input source. Each input buffer can be individually  
shut down using the input shutdown registers. When shutdown the input buffers are high impedance, which  
reduces power consumption and crosstalk.  
The LMH6586 has 16 video outputs each of which is buffered through a programmable 1X or 2X gain output  
buffer. The outputs are capable of driving 150Ω loads. When the output gain is set to 1X (GAIN_SEL = 0), the  
output signal sync tip is set to the VREF_CLAMP voltage level; otherwise, when the gain is set to 2X (GAIN_SEL  
= 1), the output signal sync tip is set to twice the VREF_CLAMP level. Each output can be individually shut down  
using the output shutdown registers. When shutdown the outputs are high impedance, which reduces power  
consumption and crosstalk, and also enables multiple outputs to be connected together for expanding the matrix  
array size. Note that output short circuit protection is not provided, so care must be taken to ensure only one  
output is active when output channels are tied together in expansion configurations.  
INPUT EXPANSION  
The LMH6586 has the capability for creating larger switching matrices. Depending on the number of input and  
output channels required, the number of devices required can be calculated. To implement a 128 x 16 non-  
blocking matrix arrange the building blocks in a grid. The inputs are connected in parallel while the outputs are  
wired-or together. When using this configuration care must be taken to ensure that only one of the four outputs is  
active. The other three outputs should be placed in shutdown mode by using the appropriate shutdown bit in the  
output shutdown registers. This reduces output loading and the risk of output short circuit conditions, which can  
lead to device overheating and even damage to the channel or device.  
The figure below shows the 128 input x 16 output switching matrix using four LMH6586 devices. To construct  
larger matrices use the same technique with more devices.  
Because the LMH6586 has 2-bit configurable slave address inputs, up to four LMH6586 devices can be  
connected to a common I2C bus. For more devices additional I2C buses may be required.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
75W  
INPUT  
(0-31)  
LMH6586  
LMH6586  
LMH6586  
LMH6586  
16  
32  
75W  
75W  
75W  
INPUT  
(32-63)  
32  
32  
16  
16  
OUTPUT  
(0-15)  
INPUT  
(64-95)  
INPUT  
(96-127)  
32  
16  
Figure 53. 128 x 16 Crosspoint Array  
DRIVING CAPACITIVE LOAD  
When many outputs are wired together, as in the case of expansion, each output buffer sees the normal load  
impedance as well as the impedance the other shutdown outputs. This impedance has a resistive and a  
capacitive component. The resistive components reduce the total effective load for the driving output. Total  
capacitance is the sum of the capacitance of all the outputs and depends on the size of the matrix. As the size of  
the matrix increases, the length of the PC board traces also increases, adding more capacitance. The output  
buffers have been designed to drive more than 30 pF of capacitance while still maintaining a good AC response.  
If the output capacitance exceeds this amount then the AC response will be degraded. To prevent this, one  
option is to reduce the number of output wired-or together by using more LMH6586 device. Another option is to  
put a resistor in series with the output before the capacitive load to limit excessive ringing and oscillations.  
A low pass filter is created from the series resistor (R) and parasitic capacitance (C) to ground. A single R-C  
does not affect the performance at video frequencies, however, in large system, there may be many such R-Cs  
cascaded in series. This may result in high frequency roll-off resulting in “softening of the picture”. There are two  
solutions to improve performance in this case. One way is to design the PC board traces with some inductance  
between the R and C elements. By routing the traces in a repeating “S” configuration, the traces that are nearest  
each other will exhibit a mutual inductance increasing the total inductance. This series inductance causes the  
amplitude response to increase or peak at higher frequencies, offsetting the roll-off from the parasitic  
capacitance. Another solution is to add a small-value inductor between the R and C elements to add peaking to  
the frequency response.  
THERMAL MANAGEMENT  
The LMH6586 operates on a 5V supply and draws a load current of approximately 300 mA. Thus it dissipates  
approximately 1.75W of power. In addition, each equivalent video load (150Ω) connected to the outputs should  
be budgeted 30 mW of power consumption.  
The following calculations show the thermal resistance, θJA, required, to ensure safe operation and to prevent  
exceeding the maximum junction temperature, given the maximum power dissipation.  
PDMAX = (TJMAX – TAMAX)/θJA  
where  
•
•
•
TJMAX = Maximum junction temperature = 150°C  
TAMAX = Maximum ambient temperature = +85°C  
θJA = Thermal resistance of the package  
(1)  
22  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total  
power supply voltage, plus the power in the IC due to the load, or:  
n
VOUTi  
RLi  
(VS œ VOUTi) x  
PDMAX = VS x ISMAX  
+
S
i = 1  
where  
•
VS = Supply voltage = 5V  
•
•
•
•
ISMAX = Maximum quiescent supply current = 300 mA  
VOUT = Maximum output voltage of the application = 2.6V  
RL = Load resistance tied to ground = 150Ω  
n = 1 to 16 channels  
(2)  
Calculating:  
PDMAX = 2.2656  
The required θJA to dissipate PDMAX is = (TJMAX – TAMAX)/PDMAX  
The table below shows the θJA values with airflow and different heatsinks.  
LMH6586VS 80-Pin TQFT  
LMHXPT  
0 LFPM  
@ 0.50 watt  
0 LFPM  
@ 1.0 watt  
0 LFPM  
@ 2.0 watt  
0 LFPM @2.8 225 LFPM @ 500 LFPM @  
watt  
2.8 watt  
2.8 watt  
Analog Video Crosspoint Board  
NO Heat Sink  
32.2  
25.5  
30.9  
24.6  
29.4  
23.6  
28.6  
22.9  
26.8  
19.2  
25.3  
15.9  
Small Tower  
x y = 9.57x9.69 mm/ht. 6.28 mm  
Aluminum 12 rail  
x y = 9.82x10.73 mm/ht.10.07 mm  
25.2  
24.4  
24.2  
24.1  
23.3  
23.9  
23.0  
22.1  
22.9  
22.2  
21.3  
22.4  
16.4  
15.6  
18.2  
14.2  
13.6  
15.4  
Anodized 9 rail  
x y = 6.10x7.30 mm/ht. 13.67 mm  
Round Tower  
diameter = 14.35 mm/ht. 4.47 mm  
REXT RESISTOR  
The REXT external resistor (pin 67) establishes the internal bias current and precise reference voltage for the  
LMH6586. For optimal performance, REXT should be a 10 kΩ 1% precision resistor with a low temperature  
coefficient to ensure proper operation over a wide temperature range. Using a REXT resistor with less precision  
may result in reduced performance against temperature, supply voltage, input signal, or part-to-part variations.  
SYNC SEPARATOR OUTPUT  
In addition to the 16 video outputs, the LMH6586 has an extra output (V_OUT16) which can select any input  
channel. This channel's output buffer only has a gain of 1 since it is not meant to drive a 150Ω video load.  
Instead, this video output can be AC coupled to a non-terminated input of an external video sync separator, such  
as TI's LMH1980 or LMH1981. The sync separator can extract the synchronization (sync) timing signals, which  
can be useful for video triggering or phase-locked loop (PLL) clock generation circuits. Refer to the LMH1980 or  
LMH1981 datasheet for more information about these sync separator devices.  
I2C INTERFACE  
A microcontroller can be used to configure the LMH6586 via the I2C interface. The protocol of the interface  
begins with a start pulse followed by a byte comprised of a seven-bit slave device address and a read/write bit as  
the LSB. The two lowest bits of the seven-bit slave address are defined by the external connections of inputs  
ADDR[1] (pin 72) and ADDR[0] (pin 71), where ADDR[0] is the least significant bit. Because there are four  
different combinations of the two ADDR pins, it's possible to have up to four different LMH6586 devices with  
unique slave addresses on a common I2C bus. See I2C Device Slave Address Lookup Table.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
23  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Table 2. I2C Device Slave Address Lookup Table  
ADDR[1]  
(pin 72)  
ADDR[0]  
(pin 71)  
7-bit I2C Slave Address (binary)  
0
0
1
1
0
1
0
1
0000 000x  
0000 001x  
0000 010x  
0000 011x  
For example, if ADDR[1] is set low and ADDR[0] is set high, then the 7-bit slave address would be “0000 001” in  
binary. Therefore, the address byte for write sequences is 0x02 (“0000 0010”) and the address byte read  
sequences is 0x03 (“0000 0011”). Figure 54 and Figure 55 show write and read sequences across the I2C  
interface.  
WRITE SEQUENCE  
The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is held  
high. The slave device address is sent next. The address byte is made up of an address of seven bits (7:1) and  
the read/write bit (0). Bit 0 is low to indicate a write operation. Each byte that is sent is followed by an  
acknowledge (ACK) bit. When SCL is high the master will release the SDA line. The slave must pull SDA low to  
acknowledge. The address of the register to be written to is sent next. Following the register address and the  
ACK bit, the data byte for the register is sent. When more than one data byte is sent, the register pointer is  
automatically incremented to write to the next address location. Note that each data byte is followed by an ACK  
bit until a stop condition is encountered, indicating the end of the sequence.  
The timing diagram for the write sequence is shown in Figure 54, which uses the 7-bit slave device address from  
the previous example above.  
SCL  
SDA  
A7 A6 A5 A4 A3 A2 A1 A0  
0
0
0
0
0
0
1
0
0
0
Start  
Condition  
Write Address Byte (0 x 02)  
Address  
Acknowledge  
SCL  
SDA  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
0
0
0
Stop  
Condition  
Data Byte 1  
Data Byte 2  
Data Byte n  
Acknowledge  
Figure 54. LMH6586 Write Sequence  
24  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
 
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
READ SEQUENCE  
Read sequences are comprised of two I2C transfers shown. The first is the address access transfer, which  
consists of a write sequence that transfers only the address to be accessed. The second is the data read  
transfer, which starts at the address accessed in the first transfer and increments to the next address per data  
byte read until a stop condition is encountered.  
The address access transfer consists of a start condition, the slave device address including the read/write bit (a  
zero, indicating a write), and the ACK bit. The next byte is the address to be accessed, followed by the ACK bit  
and the stop condition to indicate the end of the address access transfer.  
The subsequent read data transfer consists of a start condition, the slave device address including the read/write  
bit (a one, indicating a read), and the ACK bit. The next byte is the data read from the initial access address.  
Subsequent read data bytes will correspond to the next increment address locations. Note that each data byte is  
followed by an ACK bit until a stop condition is encountered, indicating the end of the sequence.  
The timing diagram for the read sequence is shown in Figure 55, which uses the 7-bit slave address from the  
previous examples.  
SCL  
SDA  
A7 A6 A5 A4 A3 A2 A1 A0  
0
0
0
0
0
0
1
0
0
0
Start  
Condition  
Write Address Byte (0 x 02)  
Address  
Acknowledge  
SCL  
SDA  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
0
0
0
0
0
0
1
1
0
0
0
Start  
Condition  
Stop  
Condition  
Read Address Byte (0 x 03)  
Data Byte 1  
Data Byte n  
Acknowledge  
Figure 55. LMH6586 Read Sequence  
REGISTER DESCRIPTIONS  
Video and Sync Detection Status Registers  
Registers 0x00 to 0x03 (read-only) contain the sync detection status bits for all 32 input channels. Any input (m)  
has a sync detection status bit (SD_m) that can flag high when a loss of sync is detected; otherwise, the status  
bit will be low to indicate presence of sync.  
Registers 0x04 to 0x07 (read-only) contain the video detection status bits for all 32 input channels. Any input (m)  
has a video detection status bit (VD_m) that can flag high when either loss of video or presence of video is  
detected, depending on the respective invert control bit (see Video Detection Invert Registers). Assuming the  
default setting for the invert control bit, the status bit (VD_m) will flag high when loss of video is detected on the  
input; otherwise, the status bit will be low indicating presence of video.  
Video and Sync Detection Control Registers  
Video Detection Invert Registers  
Registers 0x0C to 0x0F contain the video detection invert control bits for all input channels. Any input (m) has a  
invert control bit that can invert the polarity of the video detection status bit (VD_INV_m). When the invert bit  
(VD_INV_m) is set to 0 (default), the respective status bit (VD_m) will flag high to indicate loss of video on the  
input; otherwise, when the invert bit is set to 1, the status bit will flag high to indicate presence of video.  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
25  
Product Folder Links: LMH6586  
 
 
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Video and Sync Detection Enable Registers:  
Registers 0x10 to 0x13 contain the video detection enable bits and registers 0x14 to 0x17 contain the sync  
detection enable bits for all input channels. Any input (m) has both a video detection enable bit (VD_EN_m) and  
a sync detection enable bit (SD_EN_m). When any enable bit is set low, the respective status bit will be excluded  
from the OR-ing function used to set the FLAG output; otherwise, when the enable bit is set high, the respective  
status bit will be included in the FLAG output function. Therefore, the FLAG will only logical-OR the status bits of  
the channel(s) and type(s) of detection that are specifically enabled by the user as described in DETECTION  
FLAG OUTPUT.  
Video Detection Threshold Control Register  
The video threshold voltage level is common to all 32 input channels and is selectable by programming VDT[2:0]  
in register 0x1D. As shown in Table 1, the three LSBs (bits 2:0) of this register can be used to set the threshold  
level in 95 mV steps (typical) above to the sync tip level of the DC-restored input. Refer to VIDEO DETECTION  
for more information.  
Input and Output Shutdown Registers  
Each input channel and each output channel can be individually placed in shutdown (power save) mode to  
reduce power consumption. Registers 0x18 to 0x1B contain the input shutdown bits (IN_PS_m) and registers  
0x1E and 0x1F contain the output shutdown bits (OUT_PS_n), where “m” is any input channel and “n” is any  
output channel. To place any input or output channel in shutdown mode, the respective bit should be set high;  
otherwise, it should be set low for normal input or output operation. When in shutdown mode, the buffer (input or  
output) will be placed in a high-impedance state.  
Note: To put the entire device in power save mode, the PWDN input (pin 70) should be set high; otherwise, it  
should be set low for normal operation.  
Video Input Selection Registers  
Registers 0x20 to 0x30 are used to control the routing of the crosspoint switch. Each output has a dedicated  
input selection register, which can be programmed to select any input channel for routing to its respective output.  
LMH6586 REGISTER MAP  
Table 3. Video and Sync Detection Status Registers  
Register  
Address  
R/W  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SYNC DETECT OUT  
(CH 0-7)  
0x00h  
R
SD_7  
SD_6  
SD_5  
SD_4  
SD_3  
SD_2  
SD_1  
SD_0  
SYNC DETECT OUT  
(CH 8-15)  
0x01h  
0x02h  
0x03h  
0x04h  
0x05h  
0x06h  
0x07h  
R
R
R
R
R
R
R
SD_15 SD_14 SD_13 SD_12 SD_11 SD_10  
SD_9  
SD_8  
SYNC DETECT OUT  
(CH 16-23)  
SD_23 SD_22 SD_21 SD_20 SD_19 SD_18 SD_17 SD_16  
SD_31 SD_30 SD_29 SD_28 SD_27 SD_26 SD_24 SD_24  
SYNC DETECT OUT  
(CH 24-31)  
VIDEO DETECT OUT  
(CH 0-7)  
VD_7  
VD_6  
VD_5  
VD_4  
VD_3  
VD_2  
VD_1  
VD_9  
VD_0  
VD_8  
VIDEO DETECT OUT  
(CH 8-15)  
VD_15 VD_14 VD_13 VD_12 VD_11 VD_10  
VIDEO DETECT OUT  
(CH 16-23)  
VD_23 VD_22 VD_21 VD_20 VD_19 VD_18 VD_17 VD_16  
VD_31 VD_30 VD_29 VD_28 VD_27 VD_26 VD_24 VD_24  
VIDEO DETECT OUT  
(CH 24-31)  
26  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
 
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
Table 4. Video and Sync Detection Control Registers  
Register  
Address  
R/W  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
RESERVED  
0x08h  
0x0Bh  
R/W  
0x00  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
VIDEO DETECT  
INVERT (CH 0-7)  
0x0Ch  
0x0Dh  
0x0Eh  
0x0Fh  
0x10h  
0x11h  
0x12h  
0x13h  
0x14h  
0x15h  
0x16h  
0x17h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
VD_  
INV_7  
VD_  
INV_6  
VD_  
INV_5  
VD_  
INV_4  
VD_  
INV_3  
VD_  
INV_2  
VD_  
INV_1  
VD_  
INV_0  
VIDEO DETECT  
INVERT (CH 8-15)  
VD_  
INV_15  
VD_  
INV_14  
VD_  
INV_13  
VD_  
INV_12  
VD_  
INV_11  
VD_  
INV_10  
VD_  
INV_9  
VD_  
INV_8  
VIDEO DETECT  
INVERT (CH 16-23)  
VD_  
INV_23  
VD_  
INV_22  
VD_  
INV_21  
VD_  
INV_20  
VD_  
INV_19  
VD_  
INV_18  
VD_  
INV_17  
VD_  
INV_16  
VIDEO DETECT  
INVERT (CH 24-31)  
VD_  
INV_31  
VD_  
INV_30  
VD_  
INV_29  
VD_  
INV_28  
VD_  
INV_27  
VD_  
INV_26  
VD_  
INV_24  
VD_  
INV_24  
SYNC DETECT  
ENABLE (CH 0-7)  
SD_  
EN_7  
SD_  
EN_6  
SD_  
EN_5  
SD_  
EN_4  
SD_  
EN_3  
SD_  
EN_2  
SD_  
EN_1  
SD_  
EN_0  
SYNC DETECT  
ENABLE (CH 8-15)  
SD_  
EN_15  
SD_  
EN_14  
SD_  
EN_13  
SD_  
EN_12  
SD_  
EN_11  
SD_  
EN_10  
SD_  
EN_9  
SD_  
EN_8  
SYNC DETECT  
ENABLE (CH 16-23)  
SD_  
EN_23  
SD_  
EN_22  
SD_  
EN_21  
SD_  
EN_20  
SD_  
EN_19  
SD_  
EN_18  
SD_  
EN_17  
SD_  
EN_16  
SYNC DETECT  
ENABLE (CH 24-31)  
SD_  
EN_31  
SD_  
EN_30  
SD_  
EN_29  
SD_  
EN_28  
SD_  
EN_27  
SD_  
EN_26  
SD_  
EN_25  
SD_  
EN_24  
VIDEO DETECT  
ENABLE (CH 0-7)  
VD_  
EN_7  
VD_  
EN_6  
VD_  
EN_5  
VD_  
EN_4  
VD_  
EN_3  
VD_  
EN_2  
VD_  
EN_1  
VD_  
EN_0  
VIDEO DETECT  
ENABLE (CH 8-15)  
VD_  
EN_15  
VD_  
EN_14  
VD_  
EN_13  
VD_  
EN_12  
VD_  
EN_11  
VD_  
EN_10  
VD_  
EN_9  
VD_  
EN_8  
VIDEO DETECT  
ENABLE (CH 16-23)  
VD_  
EN_23  
VD_  
EN_22  
VD_  
EN_21  
VD_  
EN_20  
VD_  
EN_19  
VD_  
EN_18  
VD_  
EN_17  
VD_  
EN_16  
VIDEO DETECT  
VD_  
VD_  
VD_  
VD_  
VD_  
VD_  
VD_  
SD_  
ENABLE (CH 24-31)  
EN_31  
EN_30  
EN_29  
EN_28  
EN_27  
EN_26  
EN_25  
EN_24  
Table 5. Video Detection Threshold Control Registers  
Register  
Address  
R/W  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
VIDEO DETECT  
THRESHOLD  
0x1Dh  
R/W  
0x00  
RSV  
VDT[2:0]  
Table 6. Input and Output Shutdown Registers  
Register  
Address  
R/W  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
INPUT SHUTDOWN  
(CH 0-7)  
0x18h  
R/W  
0x00  
IN_  
PS_7  
IN_  
PS_6  
IN_  
PS_5  
IN_  
PS_4  
IN_  
PS_3  
IN_  
PS_2  
IN_  
PS_1  
IN_  
PS_0  
INPUT SHUTDOWN  
(CH 8-15)  
0x19h  
0x1Ah  
0x1Bh  
0x1Eh  
R/W  
R/W  
R/W  
R/W  
0x00  
0x00  
0x00  
0x00  
IN_  
PS_15  
IN_  
PS_14  
IN_  
PS_13  
IN_  
PS_12  
IN_  
PS_11  
IN_  
PS_10  
IN_  
PS_9  
IN_  
PS_8  
INPUT SHUTDOWN  
(CH 16-23)  
IN_  
PS_23  
IN_  
PS_22  
IN_  
PS_21  
IN_  
PS_20  
IN_  
PS_19  
IN_  
PS_18  
IN_  
PS_17  
IN_  
PS_16  
INPUT SHUTDOWN  
(CH 24-31)  
IN_  
PS_31  
IN_  
PS_30  
IN_  
PS_29  
IN_  
PS_28  
IN_  
PS_27  
IN_  
PS_26  
IN_  
PS_25  
IN_  
PS_24  
OUTPUT  
SHUTDOWN  
(CH 0-7)  
OUT_  
PS_7  
OUT_  
PS_6  
OUT_  
PS_5  
OUT_  
PS_4  
OUT_  
PS_3  
OUT_  
PS_2  
OUT_  
PS_1  
OUT_  
PS_0  
OUTPUT  
SHUTDOWN  
(CH 8-15)  
0x1Fh  
R/W  
0x00  
OUT_  
PS_15  
OUT_  
PS_14  
OUT_  
PS_13  
OUT_  
PS_12  
OUT_  
PS_11  
OUT_  
PS_10  
OUT_  
PS_9  
OUT_  
PS_8  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
27  
Product Folder Links: LMH6586  
LMH6586  
SNCS105D –JULY 2008–REVISED MARCH 2013  
www.ti.com  
Table 7. Video Input Selection Registers  
Register  
CH 0 OUTPUT  
Address  
0x20h  
0x21h  
0x22h  
0x23h  
0x24h  
0x25h  
0x26h  
0x27h  
0x28h  
0x29h  
0x2Ah  
0x2Bh  
0x2Ch  
0x2Dh  
0x2Eh  
0x2Fh  
0x30h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Default  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
Bit 7  
Bit 6  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
Bit 5  
Bit 4  
Bit 3  
Bit 2 Bit 1 Bit 0  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
SELECTED INPUT CH[4:0]  
CH 1 OUTPUT  
CH 2 OUTPUT  
CH 3 OUTPUT  
CH 4 OUTPUT  
CH 5 OUTPUT  
CH 6 OUTPUT  
CH 7 OUTPUT  
CH 8 OUTPUT  
CH 9 OUTPUT  
CH 10 OUTPUT  
CH 11 OUTPUT  
CH 12 OUTPUT  
CH 13 OUTPUT  
CH 14 OUTPUT  
CH 15 OUTPUT  
CH 16 OUTPUT (extra)  
28  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: LMH6586  
LMH6586  
www.ti.com  
SNCS105D –JULY 2008–REVISED MARCH 2013  
REVISION HISTORY  
Changes from Revision C (March 2013) to Revision D  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 26  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
29  
Product Folder Links: LMH6586  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LMH6586VS/NOPB  
ACTIVE  
TQFP  
PFC  
80  
119  
RoHS & Green  
NIPDAU  
Level-3-260C-168 HR  
-40 to 85  
LMH6586VS  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TRAY  
Chamfer on Tray corner indicates Pin 1 orientation of packed units.  
*All dimensions are nominal  
Device  
Package Package Pins SPQ Unit array  
Max  
matrix temperature  
(°C)  
L (mm)  
W
K0  
P1  
CL  
CW  
Name  
Type  
(mm) (µm) (mm) (mm) (mm)  
LMH6586VS/NOPB  
PFC  
TQFP  
80  
119  
7X17  
150  
322.6 135.9 7620 17.9  
14.3 13.95  
Pack Materials-Page 1  
PACKAGE OUTLINE  
PFC0080A  
TQFP - 1.2 mm max height  
SCALE 1.250  
PLASTIC QUAD FLATPACK  
12.2  
11.8  
B
PIN 1 ID  
80  
61  
A
1
60  
12.2  
11.8  
14.2  
TYP  
13.8  
20  
41  
40  
21  
76X 0.5  
0.27  
80X  
0.17  
4X 9.5  
0.08  
C A B  
1.2 MAX  
C
(0.13) TYP  
SEATING PLANE  
0.08  
SEE DETAIL A  
0.25  
GAGE PLANE  
(1)  
0.05 MIN  
0.75  
0.45  
0 -7  
DETAIL  
SCALE: 14  
A
DETAIL A  
TYPICAL  
4215165/B 06/2017  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Reference JEDEC registration MS-026.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
PFC0080A  
TQFP - 1.2 mm max height  
PLASTIC QUAD FLATPACK  
SYMM  
80  
61  
80X (1.5)  
1
60  
80X (0.3)  
SYMM  
(13.4)  
76X (0.5)  
(R0.05) TYP  
20  
41  
21  
40  
(13.4)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:6X  
0.05 MAX  
ALL AROUND  
EXPOSED METAL  
METAL  
0.05 MIN  
ALL AROUND  
EXPOSED METAL  
SOLDER MASK  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4215165/B 06/2017  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
PFC0080A  
TQFP - 1.2 mm max height  
PLASTIC QUAD FLATPACK  
SYMM  
80  
61  
80X (1.5)  
1
60  
80X (0.3)  
SYMM  
(13.4)  
76X (0.5)  
(R0.05) TYP  
20  
41  
21  
40  
(13.4)  
SOLDER PASTE EXAMPLE  
BASED ON 0.1 mm THICK STENCIL  
SCALE:6X  
4215165/B 06/2017  
NOTES: (continued)  
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
8. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2022, Texas Instruments Incorporated  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明