LMH6609MA [TI]
900MHz 电压反馈运算放大器 | D | 8 | -40 to 85;
| 型号： | LMH6609MA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 900MHz 电压反馈运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总30页 (文件大小：1634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6609
www.ti.com
SNOSA84F –AUGUST 2003–REVISED MARCH 2013
LMH6609 900MHz Voltage Feedback Op Amp
Check for Samples: LMH6609
1
FEATURES
DESCRIPTION
23
•
900MHz −3dB bandwidth (AV = 1)
The LMH6609 is an ultra wideband, unity gain stable,
low power, voltage feedback op amp that offers
900MHz bandwidth at a gain of 1, 1400V/μs slew rate
and 90mA of linear output current.
•
Large signal bandwidth and slew rate 100%
tested
•
•
•
•
•
•
•
•
•
•
280MHz −3dB bandwidth (AV = +2, VOUT = 2VPP
90mA linear output current
1400V/μs slew rate
)
The LMH6609 is designed with voltage feedback
architecture for maximum flexibility especially for
active filters and integrators. The LMH6609 has
balanced, symmetrical inputs with well-matched bias
currents and minimal offset voltage.
Unity gain stable
<1mV input Offset voltage
7mA Supply current (no load)
6.6V to 12V supply voltage range
0.01%/0.026° differential gain/phase PAL
3.1nV√Hz voltage noise
With Differential Gain of 0.01% and Differential Phase
of 0.026° the LMH6609 is suited for video
applications. The 90mA of linear output current
makes the LMH6609 suitable for multiple video loads
and cable driving applications as well.
Improved replacement for CLC440, CL420,
CL426
The supply voltage is specified at 6.6V and 10V. A
low supply current of 7mA (at 10V supply) makes the
LMH6609 useful in a wide variety of platforms,
including portable or remote equipment that must run
from battery power.
APPLICATIONS
•
•
•
•
•
•
•
Test equipment
IF/RF amplifier
The LMH6609 is available in the industry standard 8-
pin SOIC package and in the space-saving 5-pin
SOT-23 package. The LMH6609 is specified for
operation over the -40°C to +85°C temperature
range. The LMH6609 is manufactured in state-of-the-
art VIP10™ technology for high performance.
A/D Input driver
Active filter
Integrator
DAC output buffer
TI's Transimpedance amplifier
Typical Application
C
2
m R
R
RF
V
IN
m
1
+
-
w
=
o
K =1+
RG
Q=
1+m2 2- K
mRC
(
)
V
C
O
Q, K ARE UNITLESS.
O IS RELATED TO BANDWIDTH AND IS IN UNITS OF
w
RADIANS/SEC. DIVIDE wO BY 2p TO GET IT IN Hz.
REFER TO OA-26 FOR MORE INFORMATION.
R
F
R
G
Figure 1. Sallen Key Low Pass Filter with Equal C Value
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VIP10 is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6609
SNOSA84F –AUGUST 2003–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
VS (V+ - V−)
±6.6V
(2)
IOUT
Common Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature Range
V+ to V−
+150°C
−65°C to +150°C
+300°C
(3)
ESD Tolerance
Human Body Model
Machine Model
2000V
200V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional. For specifications, see the Electrical Characteristics tables.
(2) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Section for more details.
(3) Human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω In series with 200pF.
(1)
Operating Ratings
Thermal Resistance
Package
(θJC
)
(θJA)
8-Pin SOIC
5-Pin SOT23
65°C/W
120°C/W
−40°C
145°C/W
187°C/W
+85°C
Operating Temperature
Nominal Supply Voltage
(2)
±3.3V
±6V
(1) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Section for more details.
(2) Nominal Supply voltage range is for supplies with regulation of 10% or better.
±5V Electrical Characteristics
Unless specified, AV = +2, RF = 250Ω: VS = ±5V, RL = 100Ω; unless otherwise specified. Boldface limits apply over
(1)
temperature Range.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
SSBW
LSBW
−3dB Bandwidth
−3dB Bandwidth
VOUT = 0.5VPP
260
170
MHz
MHz
MHz
MHz
%
VOUT = 4.0VPP
150
SSBWG1 −3dB Bandwidth AV = 1
VOUT = 0.25VPP
900
GFP
DG
DP
.1dB Bandwidth
Differential Gain
Differential Phase
Gain is Flat to .1dB
RL = 150Ω, 4.43MHz
RL = 150Ω, 4.43MHz
130
0.01
0.026
deg
Time Domain Response
TRS
TRL
ts
Rise and Fall Time
1V Step
4V Step
2V Step
1.6
2.6
ns
ns
Settling Time to 0.05%
Slew Rate
15
ns
(2)
SR
4V Step
1200
1400
V/µs
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Applications Section for information on temperature derating of this device.
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Slew rate is Average of Rising and Falling 40-60% slew rates.
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±5V Electrical Characteristics (continued)
Unless specified, AV = +2, RF = 250Ω: VS = ±5V, RL = 100Ω; unless otherwise specified. Boldface limits apply over
temperature Range. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Distortion and Noise Response
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
Equivalent Input Noise
Voltage Noise
2VPP, 20MHz
−63
−57
dBc
dBc
2VPP, 20MHz
VN
CN
>1MHz
>1MHz
3.1
1.6
nV/√Hz
pA/√Hz
Current Noise
Static, DC Performance
±2.5
±3.5
VIO Input Offset Voltage
±0.8
4
mV
μV/°C
µA
Input Voltage Temperature Drift
Input Bias Current
±5
±8
IBN
−2
11
Bias Current Temperature Drift
Input Offset Current
nA/°C
µA
±1.5
±3
IBI
0.1
67
65
PSRR
CMRR
ICC
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current
DC, 1V Step
DC, 2V Step
RL = ∞
73
73
dB
dB
67
65
7.8
8.5
7.0
mA
Miscellaneous Performance
RIN
Input Resistance
Input Capacitance
Output Resistance
1
MΩ
pF
Ω
CIN
1.2
0.3
ROUT
Closed Loop
±3.6
±3.3
VO
RL = ∞
±3.9
±3.5
±3.0
±90
V
V
Output Voltage Range
±3.2
±3.0
VOL
CMIR
IO
RL = 100Ω
±2.8
±2.5
Input Voltage Range
Linear Output Current
Common Mode, CMRR > 60dB
V
±60
±50
mA
VOUT
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±3.3V Electrical Characteristics
Unless specified, AV = +2, RF = 250Ω: VS = ±3.3V, RL = 100Ω; unless otherwise specified. Boldface limits apply over
(1)
temperature Range.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
SSBW
LSBW
−3dB Bandwidth
−3dB Bandwidth
VOUT = 0.5VPP
180
110
450
40
MHz
MHz
MHz
MHz
%
VOUT = 3.0VPP
SSBWG1 −3dB Bandwidth AV = 1
VOUT = 0.25VPP
VOUT = 1VPP
GFP
DG
DP
.1dB Bandwidth
Differential Gain
Differential Phase
RL = 150Ω, 4.43MHz
RL = 150Ω, 4.43MHz
.01
.06
deg
Time Domain Response
TRL
1V Step
2.2
ns
(2)
SR
Slew Rate
2V Step
800
V/µs
Distortion and Noise Response
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
Equivalent Input Noise
2VPP, 20MHz
2VPP, 20MHz
−63
−43
dBc
dBc
nV/
pA/√Hz
VN
CN
Voltage Noise
>1MHz
>1MHz
3.7
1.1
Current Noise
pA/√Hz
Static, DC Performance
±2.5
±3.5
VIO
IBN
IBI
Input Offset Voltage
0.8
mV
µA
µA
−1
±3
±6
Input Bias Current
Input Offset Current
0
±1.5
±3
PSRR
CMRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
DC, .5V Step
DC, 1V Step
RL = ∞
67
67
73
75
dB
dB
3.6
5
6
mA
ICC
Supply Current
Miscellaneous Performance
ROUT
VO
Input Resistance
Close Loop
RL = ∞
.05
±2.3
±2.0
±1.3
±45
Ω
V
±2.1
±1.9
Output Voltage Range
VOL
CMIR
IO
RL = 100Ω
Common Mode
VOUT
V
Input Voltage Range
Linear Output Current
V
±30
mA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Applications Section for information on temperature derating of this device.
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Slew rate is Average of Rising and Falling 40-60% slew rates.
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SNOSA84F –AUGUST 2003–REVISED MARCH 2013
CONNECTION DIAGRAM
8-Pin SOIC
(Top View)
5-Pin SOT-23
(Top View)
1
8
N/C
N/C
1
5
+
V
OUT
7
2
3
+
-IN
V
-
-
2
6
5
V
OUTPUT
+IN
+
-
+
4
-
N/C
V
4
3
-IN
+IN
See Package Number DBV0005A
See Package Number D0008A
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Typical Performance Characteristics
Small Signal Non-Inverting Frequency Response
Large Signal Non-Inverting Frequency Response
3
3
A
= 1, R = 0W
F
V
A
= 1, R = 0W
V
F
1
1
A
= 2
V
A
V
= 2
-1
-1
A
= 10
V
A
= 4
V
A
= 6
V
-3
-5
-7
-9
-3
-5
-7
-9
A
= 6
V
A
= 4
V
A
= 10
V
V
= ±5V
V
= ±5V
S
S
R
= 250W
R
= 250W
F
F
V
= 0.5V
V
OUT
= 4V
PP
OUT
PP
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 2.
Figure 3.
Small Signal Inverting Frequency Response
Large Signal Inverting Frequency Response
3
3
A
V
= -1, R = 250W
F
A
V
= -1, R = 250W
F
1
1
-1
-1
A
= -5, R = 250W
F
V
-3
-5
-7
-9
A
= -5, R = 250W
-3
-5
-7
-9
V
F
A
= -10, R = 500W
V
F
A
= -10, R = 500W
V
F
V
= ±5V
S
V
V
= ±5V
S
V
= 4V
PP
OUT
= 0.5V
PP
OUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4.
Figure 5.
Frequency Response
vs.
Frequency Response
vs.
VOUT AV = 2
VOUT AV = 2
3
3
V
= 2V
PP
OUT
V
= 1V
PP
OUT
1
-1
-3
-5
-7
-9
1
V
V
= 1V
PP
-1
OUT
OUT
V
= 0.5V
PP
OUT
= 0.5V
PP
-3
-5
-7
-9
V
= 4V
PP
OUT
V
= 2V
PP
OUT
V
= ±5V
V
= ±3.3V
= 250W
= 2V/V
S
S
R
= 250W
R
F
V
F
V
A
= 2V/V
A
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Frequency Response
vs.
Frequency Response
vs.
VOUT AV = 1
VOUT AV = −1
3
3
V
OUT
= 0.25V
PP
V
OUT
= 1V
PP
1
1
-1
-1
V
= 0.25V
PP
OUT
V
= 2V
PP
OUT
V
= 0.5V
PP
OUT
V
= 1V
PP
OUT
-3
-5
-7
-9
-3
-5
-7
-9
V
= 2V
PP
OUT
V
= 0.5V
PP
OUT
V
= ±3.3V
= 0W
S
V
= ±3.3V
= 250W
= -1V/V
S
R
F
V
R
F
V
A
= 1V/V
A
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8.
Figure 9.
Frequency Response
vs.
Frequency Response
vs.
VOUT AV = −1
Cap Load
2
3
1
C
L
= 10pF, R = 55W
OUT
V
= 2V
OUT
PP
V
= 1V
PP
OUT
0
-2
-1
-3
-5
V
= 0.25V
OUT
PP
C
= 100pF, R
= 17W
= 32W
L
OUT
-4
-6
C
= 33pF, R
= ±3.3V
L
OUT
V
= 4V
PP
OUT
V
= ±5V
V
S
S
-8
-7
-9
R
= 250W
= -1V/V
LOAD = 1kW||C
L
F
A
V
OUT
= 1V
PP
V
-10
1
10
100
1000
100
1000
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10.
Figure 11.
Frequency Response
Suggested ROUT
vs.
vs.
Cap Load
Cap Load
2
70
C
L
= 10pF, R = 55W
OUT
LOAD = 1kW || C
L
60
50
0
-2
C
= 100pF, R
= 17W
L
OUT
40
30
20
10
0
-4
-6
C
= 33pF, R = 32W
OUT
L
V
S
= ±5V
-8
LOAD = 1kW||C
L
V
OUT
= 1V
PP
-10
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
CMRR
vs.
Frequency
PSRR
vs.
Frequency
90
80
90
80
70
PSRR-
70
60
50
40
30
20
10
PSRR+
V
S
= ±5V
60
50
40
V
= ±3.3V
S
30
20
10
V
S
= ±3.3V
0.01
0
1
0.001 0.01
0.1
10
100
1
0.1
10
100
0.001
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14.
Figure 15.
PSRR
vs.
Frequency
Pulse Response
90
0.75
PSRR-
A
V
= +2
80
70
0.5
PSRR+
0.25
60
50
40
V
= 1V
PP
OUT
0
-0.25
-0.5
V
= ±3.3V
S
30
20
10
V
= ±5V
0.01
A
= -1
S
V
0
-0.75
0
5
10 15 20 25 30 35 40 45
TIME (ns)
1
0.1
10
100
0.001
FREQUENCY (MHz)
Figure 16.
Figure 17.
Pulse Response
Large Signal Pulse Response
2.5
2
0.75
0.5
1.5
1
A
V
= +2
0.25
0
A
= +2
V
0.5
0
V
V
= 4V
OUT
PP
= ±5V
S
-0.5
-1
V
V
+ 1V
PP
OUT
A
= -1
V
-0.25
= ±5V
S
A
= -1
V
-1.5
-2
-0.5
-2.5
-0.75
0
5
10 15 20 25 30 35 40 45
TIME (ns)
0
5
10 15 20 25 30 35 40
TIME (ns)
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Noise
vs.
HD2
vs.
VOUT
Frequency
100
10
1
100
10
1
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
V
= ±3.3V
S
20MHz
10MHz
VOLTAGE NOISE
2MHz
CURRENT NOISE
1k
100k
1
100
10k
1M
10
0
1
2
3
4
V
(V
)
FREQUENCY (Hz)
OUT PP
Figure 20.
Figure 21.
HD3
vs.
VOUT
HD2
vs.
VOUT
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
V
= ±5V
S
20MHz
10MHz
20MHz
2MHz
2MHz
V
= ±3.3V
S
10MHz
0
1
2
3
4
5
6
7
0
1
2
3
4
V
(V )
OUT PP
V
(V
)
OUT PP
Figure 22.
Figure 23.
HD3
vs.
VOUT
HD2 & HD3
vs.
Frequency
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-40
-50
-60
-70
V
= ±3.3V
S
20MHz
V
= 2V
OUT
PP
10MHz
HD3
HD2
2MHz
-80
-90
V
S
= ±5V
6
-100
7
0
1
2
3
4
5
1
10
100
FREQUENCY (MHz)
VOUT (V )
PP
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
HD2 & HD3
vs.
Frequency
Differential Gain & Phase
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
0.015
0.01
0.06
0.04
0.02
0
V
= ±3.3V
S
V
V
= ±5V
S
= 2V
PP
OUT
PHASE
0.005
0
HD3
HD2
-0.02
-0.04
-0.06
-0.005
-0.01
-0.015
GAIN
1
10
-0.75 -0.5 -0.25
0
0.25
0.5 0.75
100
FREQUENCY (MHz)
V
(V) 100IRE = 714mV
OUT
Figure 26.
Figure 27.
Differential Gain & Phase
Open Loop Gain & Phase
0.012
0.009
0.03
80
70
60
50
40
30
20
10
0
180
V = ±3.3V
S
V
= ±5V
S
GAIN
0.0225
0.015
0.0075
0
135
90
0.006
0.003
0
PHASE
45
0
PHASE
-45
-0.003
-0.006
-0.009
-0.012
-0.0075
-0.015
-0.0225
-0.03
-90
GAIN
-135
-180
100 1k 10k 100k 1M 10M 100M 1G
-0.75 -0.5 -0.25
0.25
0.5 0.75
0
FREQUENCY (Hz)
V
OUT
(V) 100IRE = 714mV
Figure 28.
Figure 29.
Open Loop Gain & Phase
Closed Loop Output Resistance
180
135
90
80
70
60
50
40
30
20
10
0
100
10
V
S
= ±5V
GAIN
V = ±3.3V
S
45
0
1
PHASE
0.1
-45
V = ±5V
S
-90
0.01
-135
-180
0.001
100 1k 10k 100k 1M 10M 100M 1G
0.001
0.01
0.1
1
100
10
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 30.
Figure 31.
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APPLICATION INFORMATION
GENERAL DESIGN EQUATION
The LMH6609 is a unity gain stable voltage feedback amplifier. The matched input bias currents track well over
temperature. This allows the DC offset to be minimized by matching the impedance seen by both inputs.
GAIN
The non-inverting and inverting gain equations for the LMH6609 are as follows:
R
F
NON-INVERTING GAIN : 1+
R
G
R
R
F
INVERTING GAIN : -
G
(1)
Figure 32. Typical Non-Inverting Application
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Figure 33. Typical Inverting Application
Figure 34. Single Supply Inverting
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Figure 35. AC Coupled Non-Inverting
GAIN BANDWIDTH PRODUCT
The LMH6609 is a voltage feedback amplifier, whose closed-loop bandwidth is approximately equal to the gain-
bandwidth product (GBP) divided by the gain (AV). For gains greater than 5, AV sets the closed-loop bandwidth of
the LMH6609.
GBP
CLOSED LOOP BANDWIDTH =
AV
(RF +RG)
AV =
RG
GBP = 240MHz
(2)
For Gains less than 5, refer to the frequency response plots to determine maximum bandwidth. For large signal
bandwidth the slew rate is a more accurate predictor of bandwidth.
SR
fMAX
=
2p VP
(3)
Where fMAX = bandwidth, SR = Slew rate and VP = peak amplitude.
OUTPUT DRIVE AND SETTLING TIME PERFORMANCE
The LMH6609 has large output current capability. The 100mA of output current makes the LMH6609 an excellent
choice for applications such as:
•
•
Video Line Drivers
Distribution Amplifiers
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When driving a capacitive load or coaxial cable, include a series resistance ROUT to back match or improve
settling time. Refer to the Driving Capacitive Loads section for guidance on selecting an output resistor for driving
capacitive loads.
EVALUATION BOARDS
TI offers the following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization. Many of the data sheet plots were measured with these boards.
Device
Package
SOIC
Board Part #
LMH730227
LMH730216
LMH6609MA
LMH6609MF
SOT-23
CIRCUIT LAYOUT CONSIDERATION
A proper printed circuit layout is essential for achieving high frequency performance. TI provides evaluation
boards for the LMH6609 as shown above. These boards were laid out for optimum, high-speed performance.
The ground plane was removed near the input and output pins to reduce parasitic capacitance. Also, all trace
lengths were minimized to reduce series inductances.
Supply bypassing is required for the amplifiers performance. The bypass capacitors provide a low impedance
return current path at the supply pins. They also provide high frequency filtering on the power supply traces.
10μF tantalum and .01μF capacitors are recommended on both supplies (from supply to ground). In addition, a
0.1μF ceramic capacitor can be added from V+ to V− to aid in second harmonic suppression.
R
51W
OUT
+
-
+
-
C
L
R
IN
51W
R
L
1kW
R
G
10pF
R
F
Figure 36. Driving Capacitive Loads with ROUT for Improved Stability
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 36 shows
the use of a series output resistor, ROUT as it might be applied when driving an analog to digital converter. The
charts "Suggested RO vs. Cap Load" in the Typical Performance Section give a recommended value for
mitigating capacitive loads. The values suggested in the charts are selected for .5dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of RO can be reduced slightly
from the recommended values. There will be amplitude lost in the series resistor unless the gain is adjusted to
compensate; this effect is most noticeable with heavy resistive loads.
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COMPONENT SELECTION AND FEEDBACK RESISTOR
Surface mount components are highly recommended for the LMH6609. Leaded components will introduce
unpredictable parasitic loading that will interfere with proper device operation. Do not use wire wound resistors.
The LMH6609 operates best with a feedback resistor of approximately 250Ω for all gains of +2 and greater and
for −1 and less. With lower gains in particular, large value feedback resistors will exaggerate the effects of
parasitic capacitances and may lead to ringing on the pulse response and frequency response peaking. Large
value resistors also add undesirable thermal noise. Feedback resistors that are much below 100Ω will load the
output stage, which will reduce voltage output swing, increase device power dissipation, increase distortion and
reduce current available for driving the load.
In the buffer configuration the output should be shorted directly to the inverting input. This feedback does not
load the output stage because the inverting input is a high impedance point and there is no gain set resistor to
ground.
OPTIMIZING DC ACCURACY
The LMH6609 offers excellent DC accuracy. The well-matched inputs of this amplifier allows even better
performance if care is taken to balance the impedances seen by the two inputs. The parallel combination of the
gain setting RG and feedback RF resistors should be equal to RSEQ, the resistance of the source driving the op
amp in parallel with any terminating Resistor (See Figure 32). Combining this with the non inverting gain equation
gives the following parameters:
RF = AVRSEQ
RG = RF/(AV−1)
For Inverting gains the bias current cancellation is accomplished by placing a resistor RB on the non-inverting
input equal in value to the resistance seen by the inverting input (See Figure 33). RB = RF || (RG + RS)
The additional noise contribution of RB can be minimized by the use of a shunt capacitor (not shown).
POWER DISSIPATION
The LMH6609 has the ability to drive large currents into low impedance loads. Some combinations of ambient
temperature and device loading could result in device overheating. For most conditions peak power values are
not as important as RMS powers. To determine the maximum allowable power dissipation for the LMH6609 use
the following formula:
PMAX = (150º - TAMB)/θJA
(4)
Where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction to ambient, for a given
package (°C/W). For the SOIC package θJA is 148°C/W, for the SOT-23 it is 250°C/W. 150ºC is the absolute
maximum limit for the internal temperature of the device.
Either forced air cooling or a heat sink can greatly increase the power handling capability for the LMH6609.
VIDEO PERFORMANCE
The LMH6609 has been designed to provide good performance with both PAL and NTSC composite video
signals. The LMH6609 is specified for PAL signals. NTSC performance is typically marginally better due to the
lower frequency content of the signal. Performance degrades as the loading is increased, therefore best
performance will be obtained with back-terminated loads. The back termination reduces reflections from the
transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier
output stage. This means that the device should be configured for a gain of 2 in order to have a net gain of 1
after the terminating resistor. (See Figure 37)
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6.8mF
C2
10nF
R
S
C1
75W
R
OUT
75W
+
R
IN
75W
V
S
+
V
OUT
-
R
G
R
F
250W
250W
10nF
C3
6.8mF
C4
Figure 37. Typical Video Application
ESD PROTECTION
The LMH6609 is protected against electrostatic discharge (ESD) on all pins. The LMH6609 will survive 2000V
Human Body model or 200V Machine model events.
Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions,
however, when the ESD diodes may be evident. For instance, if the amplifier is powered down and a large input
signal is applied the ESD diodes will conduct.
TRANSIMPEDANCE AMPLIFIER
The low input current noise and unity gain stability of the LMH6609 make it an excellent choice for
transimpedance applications. Figure 38 illustrates a low noise transimpedance amplifier that is commonly
implemented with photo diodes. RF sets the transimpedance gain. The photo diode current multiplied by RF
determines the output voltage.
C
F
PHOTO DIODE
PRESENTATION
R
F
-
V
OUT
I
IN
C
D
+
V
= -I * R
IN
OUT
F
Figure 38. Transimpedance Amplifier
The capacitances are defined as:
•
•
CD = Equivalent Diode Capacitance
CF = Feedback Capacitance
The feedback capacitor is used to give optimum flatness and stability. As a starting point the feedback
capacitance should be chosen as ½ of the Diode capacitance. Lower feedback capacitors will peak frequency
response.
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LMH6609
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SNOSA84F –AUGUST 2003–REVISED MARCH 2013
Rectifier
The large bandwidth of the LMH6609 allows for high-speed rectification. A common rectifier topology is shown in
Figure 39. R1 and R2 set the gain of the rectifier.
D
1
D
2
R
2
R
1
V
OUT
V
IN
-
+
Figure 39. Rectifier Topology
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SNOSA84F –AUGUST 2003–REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6609 MDC
LMH6609MA
ACTIVE
NRND
DIESALE
SOIC
Y
D
0
8
400
95
RoHS & Green
Call TI
Level-1-NA-UNLIM
-40 to 85
-40 to 85
Non-RoHS
& Green
Call TI
SN
Level-1-235C-UNLIM
LMH66
09MA
LMH6609MA/NOPB
LMH6609MAX/NOPB
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LMH66
09MA
2500 RoHS & Green
SN
LMH66
09MA
LMH6609MF/NOPB
LMH6609MFX/NOPB
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
1000 RoHS & Green
3000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
A89A
A89A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6609MAX/NOPB
LMH6609MF/NOPB
LMH6609MFX/NOPB
SOIC
D
8
5
5
2500
1000
3000
330.0
178.0
178.0
12.4
8.4
6.5
3.2
3.2
5.4
3.2
3.2
2.0
1.4
1.4
8.0
4.0
4.0
12.0
8.0
Q1
Q3
Q3
SOT-23
SOT-23
DBV
DBV
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6609MAX/NOPB
LMH6609MF/NOPB
LMH6609MFX/NOPB
SOIC
D
8
5
5
2500
1000
3000
367.0
208.0
208.0
367.0
191.0
191.0
35.0
35.0
35.0
SOT-23
SOT-23
DBV
DBV
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6609MA
LMH6609MA
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
LMH6609MA/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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SI9122E
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