LMH6628MA/NOPB [TI]
双路宽带、低噪声、电压反馈运算放大器 | D | 8 | -40 to 85;
| 型号： | LMH6628MA/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路宽带、低噪声、电压反馈运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总24页 (文件大小：1312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6628
www.ti.com
SNOSA02D –MAY 2002–REVISED MARCH 2013
LMH6628 Dual Wideband, Low Noise, Voltage Feedback Op Amp
Check for Samples: LMH6628
1
FEATURES
DESCRIPTION
The Texas Instruments LMH6628 is a high speed
dual op amp that offers a traditional voltage feedback
topology featuring unity gain stability and slew
enhanced circuitry. The LMH6628's low noise and
very low harmonic distortion combine to form a wide
dynamic range op amp that operates from a single
(5V to 12V) or dual (±5V) power supply.
23
•
Wide Unity Gain Bandwidth: 300MHz
Low Noise: 2nV/√hZ
•
•
•
•
•
•
Low Distortion: −65/−74dBc (10MHz)
Settling Time: 12ns to 0.1%
Wide Supply Voltage Range: ±2.5V to ±6V
High Output Current: ±85mA
Each of the LMH6628's closely matched channels
provides a 300MHz unity gain bandwidth and low
input voltage noise density (2nV/√hZ). Low 2nd/3rd
harmonic distortion (−65/−74dBc at 10MHz) make the
LMH6628 a perfect wide dynamic range amplifier for
matched I/Q channels.
Improved Replacement for CLC428
APPLICATIONS
•
•
•
•
•
•
High Speed Dual Op Amp
Low Noise Integrators
With its fast and accurate settling (12ns to 0.1%), the
LMH6628 is also an excellent choice for wide
dynamic range, anti-aliasing filters to buffer the inputs
of hi resolution analog-to-digital converters.
Combining the LMH6628's two tightly matched
amplifiers in a single 8-pin SOIC package reduces
cost and board space for many composite amplifier
applications such as active filters, differential line
Low Noise Active Filters
Driver/receiver for Transmission Systems
High Speed Detectors
I/Q Channel Amplifiers
drivers/receivers,
fast
peak
detectors
and
instrumentation amplifiers.
The LMH6628 is fabricated using TI’s VIP10™
complimentary bipolar process.
To reduce design times and assist in board layout,
the LMH6628 is supported by an evaluation board
(CLC730036).
Connection Diagram
Figure 1. 8-Pin SOIC, Top View
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VIP10 is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
LMH6628
SNOSA02D –MAY 2002–REVISED MARCH 2013
www.ti.com
Figure 2. Inverting Frequency Response
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Human Body Model
Machine Model
2kV
200V
ESD Tolerance(3)
Supply Voltage
13.5
Short Circuit Current
See(4)
Common-Mode Input Voltage
Differential Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering 10 sec)
V+ - V−
V+ - V−
+150°C
−65°C to +150°C
+300°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω In series with 200pF.
(4) Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA.
Operating Ratings(1)
Thermal Resistance(2)
Package
(θJC
)
(θJA
)
SOIC
65°C/W
145°C/W
Temperature Range
Nominal Supply Voltage
−40°C to +85°C
±2.5V to ±6V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX)-TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
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Electrical Characteristics(1)
VCC = ±5V, AV = +2V/V, RF = 100Ω, RG = 100Ω, RL = 100Ω; unless otherwise specified. Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
GB
Gain Bandwidth Product
VO < 0.5VPP
200
300
100
MHz
MHz
MHz
SSBW
SSBW
GFL
-3dB Bandwidth, AV = +1
-3dB Bandwidth, AV = +2
Gain Flatness
VO < 0.5VPP
VO < 0.5VPP
VO< 0.5VPP
180
GFP
GFR
LPD
Peaking
DC to 200MHz
DC to 20MHz
DC to 20MHz
0.0
.1
dB
dB
Rolloff
Linear Phase Deviation
.1
deg
Time Domain Response
TR
TS
OS
SR
Rise and Fall Time
1V Step
4
12
1
ns
ns
Settling Time
Overshoot
Slew Rate
2V Step to 0.1%
1V Step
%
4V Step
300
550
V/µs
Distortion And Noise Response
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
Equivalent Input Noise
Voltage
1VPP, 10MHz
1VPP, 10MHz
−65
−74
dBc
dBc
VN
1MHz to 100MHz
2
2
nV/√Hz
pA/√Hz
dB
IN
Current
1MHz to 100MHz
XTLKA
Crosstalk
Input Referred, 10MHz
−62
Static, DC Performance
GOL
Open-Loop Gain
56
63
dB
53
VIO
Input Offset Voltage
±.5
±2
mV
±2.6
DVIO
IBN
Average Drift
5
µV/°C
µA
Input Bias Current
±.7
±20
±30
DIBN
IOS
Average Drift
150
0.3
5
nA/°C
µA
Input Offset Current
Average Drift
±6
IOSD
PSRR
nA/°C
dB
Power Supply Rejection Ratio
60
70
46
CMRR
ICC
Common-Mode Rejection Ratio
Supply Current
57
54
62
9
dB
Per Channel, RL = ∞
7.5
12
mA
7.0
12.5
Miscellaneous Performance
RIN
Input Resistance
Input Capacitance
Output Resistance
Common-Mode
Differential-Mode
Common-Mode
Differential-Mode
Closed-Loop
500
200
1.5
1.5
.1
kΩ
kΩ
pF
pF
Ω
CIN
ROUT
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Note 6 for information on temperature de-rating of this device." Min/Max ratings
are based on product characterization and simulation. Individual parameters are tested as noted.
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Electrical Characteristics(1) (continued)
VCC = ±5V, AV = +2V/V, RF = 100Ω, RG = 100Ω, RL = 100Ω; unless otherwise specified. Boldface limits apply at the
temperature extremes.
Symbol
VO
Parameter
Output Voltage Range
Conditions
Min
Typ
±3.8
±3.5
Max
Units
RL = ∞
V
V
VOL
RL = 100Ω
±3.2
±3.1
CMIR
IO
Input Voltage Range
Output Current
Common- Mode
±3.7
±85
V
±50
mA
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Typical Performance Characteristics
(TA = +25°, AV = +2, VCC = ±5V, Rf =100Ω, RL = 100Ω, unless specified)
Non-Inverting Frequency Response
Inverting Frequency Response
Figure 3.
Figure 4.
Frequency Response
vs.
Load Resistance
Frequency Response
vs.
Output Amplitude
Figure 5.
Figure 6.
Frequency Response
vs.
Capacitive Load
Gain Flatness & Linear Phase
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
(TA = +25°, AV = +2, VCC = ±5V, Rf =100Ω, RL = 100Ω, unless specified)
Channel Matching
Channel to Channel Crosstalk
Figure 9.
Figure 10.
Pulse Response (VO = 2V)
Pulse Response (VO = 100mV)
Figure 11.
Figure 12.
2nd Harmonic Distortion
vs.
3rd Harmonic Distortion
vs.
Output Voltage
Output Voltage
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
(TA = +25°, AV = +2, VCC = ±5V, Rf =100Ω, RL = 100Ω, unless specified)
2nd & 3rd Harmonic Distortion
vs.
Frequency
PSRR and CMRR (±5V)
Figure 15.
Figure 16.
PSRR and CMRR (±2.5V)
Closed Loop Output Resistance (±2.5V)
Figure 17.
Figure 18.
Closed Loop Output Resistance (±5V)
Open Loop Gain & Phase (±2.5V)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
(TA = +25°, AV = +2, VCC = ±5V, Rf =100Ω, RL = 100Ω, unless specified)
Recommended RS
vs.
CL
Open Loop Gain & Phase (±5V)
Figure 21.
Figure 22.
DC Errors
vs.
Temperature
Maximum VO
vs.
RL
4
0.5
0.4
0.3
0.2
0.1
0.8
0.6
V
= ±5V
S
0.4
3.5
0.2
0
V
IO
-0.2
-0.4
0
3
I
BN
-0.1
-0.6
I
BI
-0.2
-0.3
-0.8
-1
2.5
50
75
100
125
150
25
-40
0
40
80
120
160
LOAD RESISTANCE (W)
TEMPERATURE (°)
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
(TA = +25°, AV = +2, VCC = ±5V, Rf =100Ω, RL = 100Ω, unless specified)
Voltage & Current Noise
vs.
2-Tone, 3rd Order Intermodulation Intercept
Frequency
50
1000
100
10
1000
40
30
20
10
100
CURRENT NOISE
10
VOLTAGE NOISE
1
1
10M
1
10
100
100
FREQUENCY (Hz)
Figure 26.
1
10
1k 10k 100k 1M
FREQUENCY (MHz)
Figure 25.
Settling Time
vs.
Accuracy
1
V
O
= 2V
PP
0.1
0.01
5
10
15
20
25
30
35
TIME (ns)
Figure 27.
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APPLICATION SECTION
LOW NOISE DESIGN
Ultimate low noise performance from circuit designs using the LMH6628 requires the proper selection of external
resistors. By selecting appropriate low valued resistors for RF and RG, amplifier circuits using the LMH6628 can
achieve output noise that is approximately the equivalent voltage input noise of 2nV/
gain (AV).
multiplied by the desired
DC BIAS CURRENTS AND OFFSET VOLTAGES
Cancellation of the output offset voltage due to input bias currents is possible with the LMH6628. This is done by
making the resistance seen from the inverting and non-inverting inputs equal. Once done, the residual output
offset voltage will be the input offset voltage (VOS) multiplied by the desired gain (AV). Application Note OA-7
(SNOA365) offers several solutions to further reduce the output offset.
OUTPUT AND SUPPLY CONSIDERATIONS
With ±5V supplies, the LMH6628 is capable of a typical output swing of ±3.8V under a no-load condition.
Additional output swing is possible with slightly higher supply voltages. For loads of less than 50Ω, the output
swing will be limited by the LMH6628's output current capability, typically 85mA.
Output settling time when driving capacitive loads can be improved by the use of a series output resistor. See
Figure 22.
LAYOUT
Proper power supply bypassing is critical to insure good high frequency performance and low noise. De-coupling
capacitors of 0.1μF should be placed as close as possible to the power supply pins. The use of surface mounted
capacitors is recommended due to their low series inductance.
A good high frequency layout will keep power supply and ground traces away from the inverting input and output
pins. Parasitic capacitance from these nodes to ground causes frequency response peaking and possible circuit
oscillation. See OA-15 (SNOA367) for more information. Texas Instruments suggests the CLC730036 (SOIC)
dual op amp evaluation board as a guide for high frequency layout and as an aid in device evaluation.
ANALOG DELAY CIRCUIT (ALL-PASS NETWORK)
The circuit in Figure 28 implements an all-pass network using the LMH6628. A wide bandwidth buffer (LM7121)
drives the circuit and provides a high input impedance for the source. As shown in Figure 29, the circuit provides
a 13.1ns delay (with R = 40.2Ω, C = 47pF). RF and RG should be of equal and low value for parasitic insensitive
operation.
499W
499W
V
IN
499W
+
LM7121
-
499W
½
LMH6628
-
-
V
OUT
½
LMH6628
+
+
R
f
C
C
R
R
Figure 28. Circuit That Implements an All-pass Network Using the LMH6628
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V
IN
V
OUT
TIME (10 ns/DIV)
Figure 29. Delay Circuit Response to 0.5V Pulse
The circuit gain is +1 and the delay is determined by the following equations.
(1)
(2)
1
d f
Td
=
;
3 6 0 d f
where Td is the delay of the op amp at AV = +1.
The LMH6628 provides a typical delay of 2.8ns at its −3dB point.
FULL DUPLEX DIGITAL OR ANALOG TRANSMISSION
Simultaneous transmission and reception of analog or digital signals over a single coaxial cable or twisted-pair
line can reduce cabling requirements. The LMH6628's wide bandwidth and high common-mode rejection in a
differential amplifier configuration allows full duplex transmission of video, telephone, control and audio signals.
In the circuit shown in Figure 30, one of the LMH6628's amps is used as a "driver" and the other as a difference
"receiver" amplifier. The output impedance of the "driver" is essentially zero. The two R's are chosen to match
the characteristic impedance of the transmission line. The "driver" op amp gain can be selected for unity or
greater.
Receiver amplifier A2 (B2) is connected across R and forms differential amplifier for the signals transmitted by
driver A2 (B2). If RF equals RG, receiver A2 (B1) will then reject the signals from driver A1 (B1) and pass the
signals from driver B1 (A1).
V
in
V
in
B
1
Coax Cable
+
-
+
-
R
R
R
R
in
R
in
g
R
g
R
f
R
f
V
V
out
out
-
-
+
+
A
B
2
2
Figure 30. Full Duplex Transmit and Receive Using the LMH6628
The output of the receiver amplifier will be:
(3)
11
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Care must be given to layout and component placement to maintain a high frequency common-mode rejection.
The plot of Figure 31 shows the simultaneous reception of signals transmitted at 1MHz and 10MHz.
Figure 31. Simultaneous Reception of Signals Transmitted at 1MHz and 10MHz
POSITIVE PEAK DETECTOR
The LMH6628's dual amplifiers can be used to implement a unity-gain peak detector circuit as shown in
Figure 32.
Figure 32. LMH6628's Dual Amplifiers Used to Implement a Unity-Gain Peak Detector Circuit
The acquisition speed of this circuit is limited by the dynamic resistance of the diode when charging Chold. A plot
of the circuit's performance is shown in Figure 33 with a 1MHz sinusoidal input.
Figure 33. Circuit's Performance With a 1MHz Sinusoidal Input
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A current source, built around Q1, provides the necessary bias current for the second amplifier and prevents
saturation when power is applied. The resistor, R, closes the loop while diode D2 prevents negative saturation
when VIN is less than VC. A MOS-type switch (not shown) can be used to reset the capacitor's voltage.
The maximum speed of detection is limited by the delay of the op amps and the diodes. The use of Schottky
diodes will provide faster response.
ADJUSTABLE OR BANDPASS EQUALIZER
A "boost" equalizer can be made with the LMH6628 by summing a bandpass response with the input signal, as
shown in Figure 34.
Figure 34. "Boost" Equalizer Made With the LMH6628 by Summing a Bandpass Response With the Input
Signal
The overall transfer function is shown in Equation 4.
(4)
To build a boost circuit, use the design equations Equation 5 and Equation 6.
(5)
(6)
Select R2 and C using Equation 5. Use reasonable values for high frequency circuits - R2 between 10Ω and 5kΩ,
C between 10pF and 2000pF. Use Equation 6 to determine the parallel combination of Ra and Rb. Select Ra and
Rb by either the 10Ω to 5kΩ criteria or by other requirements based on the impedance Vin is capable of driving.
Finish the design by determining the value of K from Equation 7.
(7)
Figure 35 shows an example of the response of the circuit of Figure 34, where fo is 2.3MHz. The component
values are as follows: Ra=2.1kΩ, Rb = 68.5Ω, R2 = 4.22kΩ, R = 500Ω, KR = 50Ω, C = 120pF.
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Figure 35. Example of Response of Circuit of Figure 34, Where fo is 2.3MHz
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SNOSA02D –MAY 2002–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6628MA
NRND
SOIC
SOIC
SOIC
D
D
D
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMH66
28MA
LMH6628MA/NOPB
LMH6628MAX/NOPB
ACTIVE
ACTIVE
95
RoHS & Green
SN
SN
LMH66
28MA
2500 RoHS & Green
LMH66
28MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6628MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMH6628MAX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6628MA
LMH6628MA
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
LMH6628MA/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2022, Texas Instruments Incorporated
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