LMH6703MFX/NOPB [TI]
1.2 GHz, Low Distortion Op Amp with Shutdown;
| 型号： | LMH6703MFX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.2 GHz, Low Distortion Op Amp with Shutdown 放大器 光电二极管 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6703
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SNOSAF2D –FEBRUARY 2005–REVISED MARCH 2013
LMH6703 1.2 GHz, Low Distortion Op Amp with Shutdown
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1
FEATURES
DESCRIPTION
The LMH™6703 is a very wideband, DC coupled
monolithic operational amplifier designed specifically
for ultra high resolution video systems as well as wide
dynamic range systems requiring exceptional signal
23
•
−3 dB bandwidth (VOUT = 0.5 VPP, AV = +2)
1.2 GHz
•
2nd/3rd harmonics (20 MHz, SOT-23)
−69/−90 dBc
fidelity.
Benefitting
from
current
feedback
architecture, the LMH6703 offers a practical gain
range of ±1 to ±10 while providing stable operation
without external compensation, even at unity gain. At
a gain of +2 the LMH6703 supports ultra high
resolution video systems with a 750 MHz 2 VPP −3 dB
Bandwidth. With 12-bit distortion levels through 10
MHz (RL = 100Ω), and a 2.3nV/√Hz input referred
noise, the LMH6703 is the ideal driver or buffer for
high speed flash A/D and D/A converters. Wide
dynamic range systems such as radar and
•
•
•
•
•
Low noise 2.3nV/√Hz
Fast slew rate 4500 V/μs
Supply current 11 mA
Output current 90 mA
Low differential gain and phase 0.01%/0.02°
APPLICATIONS
•
•
•
•
•
•
•
•
RGB video driver
communication receivers requiring
a
wideband
High resolution projectors
Flash A/D driver
amplifier offering exceptional signal purity will find the
LMH6703 low input referred noise and low harmonic
distortion an attractive solution.
D/A transimpedance buffer
Wide dynamic range IF amp
Radar/communication receivers
DDS post-amps
Line driver
CONNECTION DIAGRAMS
6 Pin SOT-23
Top View
8-pin SOIC
Top View
6
5
+
1
V
OUTPUT
1
8
7
6
5
N/C
SD
SD
-
2
3
2
3
+
V
-
-IN
V
-
+
OUTPUT
+
+IN
4
-IN
+IN
4
-
N/C
V
See Package Number D0008A
See Package Number D0008A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LMH6703
SNOSAF2D –FEBRUARY 2005–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Human Body Model
2000V
200V
(2)
ESD Tolerance
Machine Model
VS
±6.75V
(3)
IOUT
Common Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
V− to V+
+150°C
−65°C to +150°C
235°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Soldering Information
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 200 pF.
(3) The maximum output current (IOUT) is determined by device power dissipation limitations.
Operating Ratings(1)
Operating Temperature Range
−40°C to +85°C
Supply Voltage Range
±4V to ±6V
208°C/W
160°C/W
6 Pin SOT-23
8 Pin SOIC
(2)
Package Thermal Resistance (θJA
)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
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(1)
Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, AV = +2, VS = ±5V, RL = 100Ω, RF = 560Ω, SD = Floating.
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Performance
SSBW
LSBW
GF
-3 dB Bandwidth
VOUT = 0.5 VPP, AV = +1
VOUT = 0.5 VPP, AV = +2
VOUT = 2 VPP
1800
1200
750
MHz
MHz
VOUT = 4 VPP
500
0.1 dB Gain Flatness
VOUT = 0.5 VPP
150
VOUT = 2 VPP
150
DG
DP
Differential Gain
RL = 150Ω, 4.43 MHz
RL = 150Ω, 4.43 MHz
0.01
0.02
%
Differential Phase
deg
Time Domain Response
tr
Rise Time
2V Step, 10% to 90%
6V Step, 10% to 90%
2V Step, 10% to 90%
6V Step, 10% to 90%
0.5
1.05
0.5
ns
ns
tf
Fall Time
ns
1.05
4200
4500
10
ns
(4)
SR
ts
Slew Rate
Settling Time
4V Step, 10% to 90%
V/µs
V/µs
ns
(4)
6V Step, 10% to 90%
2V Step, VOUT within 0.1%
Distortion And Noise Response
HD2
2nd Harmonic Distortion
2 VPP, 5 MHz, SOT-23-6
2 VPP, 20 MHz, SOT-23-6
2 VPP, 50 MHz, SOT-23-6
2 VPP, 5 MHz, SOT-23-6
2 VPP, 20 MHz, SOT-23-6
2 VPP, 50 MHz, SOT-23-6
50 MHz, PO = 5 dBm/ tone
>1 MHz
−87
−69
−60
−100
−90
−70
−80
2.3
dBc
dBc
HD3
3rd Harmonic Distortion
IMD
en
3rd Order Intermodulation Products
Input Referred Voltage Noise
Input Referred Noise Current
dBc
nV/√Hz
pA/√Hz
in
Inverting Pin
>1 MHz
18.5
Input Referred Noise Current
Non-Inverting Pin
>1 MHz
3
pA/√Hz
Static, DC Performance
VOS
Input Offset Voltage
±1.5
±7
±9
mV
(5)
TCVOS
Input Offset Voltage Average Drift
Input Bias Current
22
µV/°C
(6)
Non-Inverting
−7
±20
±23
IB
µA
(6)
Inverting
−2
±35
±44
(5)
Non-Inverting
+30
TCIB
Input Bias Current Average Drift
nA/°C
(5)
Inverting
−70
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. Parametric performance is indicated in the electrical tables under conditions of
internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
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Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, AV = +2, VS = ±5V, RL = 100Ω, RF = 560Ω, SD = Floating.
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Symbol
VO
Parameter
Conditions
Min
±3.3
Typ
Max
Units
Output Voltage Range
RL = ∞
±3.45
±3.4
V
RL = 100Ω
±3.2
±3.14
PSRR
CMRR
IS
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current (Enabled)
VS = ± 4.0V to ±6.0V
VCM = −1.0V to +1.0V
SD = 2V, RL = ∞
48
46
52
47
11
0.2
dB
dB
45
44
12.5
15.0
mA
mA
Supply Current (Disabled)
SD = 0.8V, RL = ∞
0.900
0.935
Miscellaneous Performance
RIN+
RIN−
CIN
Non-Inverting Input Resistance
1
MΩ
Ω
Inverting Input Resistance
Non-Inverting Input Capacitance
Output Resistance
Output Impedance of Input Buffer
30
0.8
0.05
pF
Ω
RO
Closed Loop
CMVR
IO
Input Common Mode Voltage Range
Linear Output Current
CMRR ≥ 40 dB
±1.9
±55
V
VIN = 0V, VOUT ≤ ±80 mV
±90
mA
Enable/Disable Performance (Disabled Low)
TON
Enable Time
10
10
50
ns
ns
TOFF
Disable Time
Output Glitch
mVPP
V
VIH
VIL
IIH
Enable Voltage
SD ≥ VIH
SD ≤ VIL
SD = V+(7)
2.0
Disable Voltage
0.8
±70
V
Disable Pin Bias Current, High
Disable Pin Bias Current, Low
Disabled Output Leakage Current
−7
µA
µA
(7)
IIL
SD = 0V
−50
−240
0.07
−400
IOZ
VOUT = ±1.8V
±25
±40
µA
(7) Negative input current implies current flowing out of the device.
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Typical Performance Characteristics
(AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25°C, SOT-23-6; unless otherwise specified).
Large Signal Frequency Response
Small Signal Non-Inverting Frequency Response (SOT-23)
(SOT-23)
4
4
3
V
= 0.5 V
PP
A
= +2
OUT
V
3
R
= 560W
A
= +2, R = 560W
F
F
V
2
2
V
OUT
= 0.5 V
PP
1
1
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
V
= 4 V
A
= +10, R = 300W
OUT
PP
V
F
V
= 2 V
PP
A
= +5, R = 390W
OUT
V
F
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1.
Figure 2.
Large Signal Frequency Response
(SOT-23)
Small Signal Inverting Frequency Response
(SOT-23)
4
4
3
2
3
A
= -10, R = 390W
F
V
2
1
V
= 0.5 V
PP
OUT
1
A
V
= -5, R = 470W
F
0
0
V
V
= 4 V
= 2 V
OUT
PP
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
A
= -1, R = 560W
F
V
OUT
PP
A
= +10
V
V = 0.5 V
OUT PP
R
= 300W
F
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
Small Signal Non-Inverting Frequency Response
(SOIC)
Large Signal Frequency Response
(SOIC)
4
4
V
OUT
= 0.5 V
PP
A
= +2
V
3
2
3
2
R
= 390W
F
A
= +2, R = 390W
F
V
= 0.5 V
PP
V
OUT
1
1
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
A
= +10, R = 180W
F
V
= 4 V
PP
V
OUT
V
= 2 V
PP
A
= +5, R = 200W
F
OUT
V
100
10
1000
1
10
100
1000
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
(AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25°C, SOT-23-6; unless otherwise specified).
Large Signal Frequency Response
(SOIC)
Small Signal Pulse Response
0.5
0.4
0.3
0.2
0.1
0
4
3
2
V
= 0.5 V , 2 V , and 4 V
PP PP
OUT
PP
1
0
-1
-2
-3
-4
-5
-6
-0.1
-0.2
-0.3
-0.4
-0.5
A
= +10
V
R
= 180W
F
1
10
100
1000
TIME (2 ns/DIV)
FREQUENCY (MHz)
Figure 7.
Figure 8.
Harmonic Distortion
vs.
Large Signal Pulse Response
Frequency
5
-50
V
= 2 V
PP
OUT
4
3
-60
-70
2ND, SOT23-6
2ND, SOIC
2
1
-80
-90
0
-1
-2
-3
-4
-5
-100
-110
-120
3RD, SOIC
10
3RD, SOT23-6
0.1
1
100
TIME (2 ns/DIV)
FREQUENCY (MHz)
Figure 9.
Figure 10.
Harmonic Distortion
vs.
Output Voltage
Harmonic Distortion
vs.
Load
-45
-55
-50
-60
f = 10 MHz
f = 10 MHz
R
= 100W
V
OUT
= 2 V
PP
L
2ND
2ND
-65
-70
-75
-80
-90
-85
-95
3RD
-100
-110
-105
-115
3RD
400
0
1
2
3
4
5
6
7
0
200
600
800
1000
OUTPUT VOLTAGE PEAK TO PEAK
LOAD RESISTANCE (W)
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
(AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25°C, SOT-23-6; unless otherwise specified).
2-Tone 3rd Order Intermodulation
Differential Gain
0.03
0.02
0.01
0
-60
-65
R
= 75W
LOAD
R
L
= 100W
R
= 150W
-70
LOAD
50 MHz
-75
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-80
-85
R
= 37.5
LOAD
-90
10 MHz
-95
-100
-105
-110
R
= 50W
LOAD
f = 4.43 MHz
-5
-2.5
0
2.5
5
7.5
-1.5
-1
-0.5
V
0
0.5
)
1
1.5
(V
OUT DC
TEST TONE POWER INTO 100W LOAD (dBm)
Figure 13.
Figure 14.
Noise
Differential Phase
1000
0.1
0.08
0.06
0.04
0.02
0
R
= 75W
LOAD
R
= 150W
LOAD
100
10
1
INVERTING CURRENT
-0.02
-0.04
-0.06
-0.08
-0.1
NON-INVERTING
CURRENT
R
= 37.5W
LOAD
VOLTAGE
R
= 50W
LOAD
f = 4.43 MHz
100
1k
10k
100k
1M
10M
-1.5
-1
-0.5
0
0.5
)
1
1.5
FREQUENCY (Hz)
V
(V
OUT DC
Figure 15.
Figure 16.
CMRR
vs.
Frequency
PSRR
vs.
Frequency
60
50
40
30
20
70
PSRR+
PSRR-
60
50
40
30
20
10
0
10M
1M
100
10k
100k
1G
10M
10k 100k
1M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
(AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25°C, SOT-23-6; unless otherwise specified).
Disable Timing
Disable Output Glitch
50 mV
0V
1V
0V
-50 mV
-1V
3V
3V
2V
1V
0V
2V
1V
0V
TIME (20 ns/DIV)
TIME (20 ns/DIV)
Figure 19.
Figure 20.
RISO
vs.
Non-Inverting Input Bias
vs.
CLOAD (See Applications Section)
Temperature
70
60
50
-4
-5
-6
-7
-8
40
30
20
10
0
-9
-50
0
25
50
100
125 150
75
-25
0
25
50
75 100 125
CAPACITIVE LOAD (pF)
TEMPERATURE (°C)
Figure 21.
Figure 22.
Inverting Input Bias
vs.
Input Offset
vs.
Temperature
Temperature
0
-4
5
4
3
2
1
-8
-12
-16
-20
0
-25
0
25
50
75 100 125
-25
0
25
50
75 100 125
-50
-50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
(AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25°C, SOT-23-6; unless otherwise specified).
Supply Current
Voltage Swing
vs.
vs.
Temperature
Temperature
4
3.75
3.5
14
13
3.25
3
12
11
10
9
ö
-3
-3.25
-3.5
-3.75
-4
-50 -25
0
25
50
75 100 125
-25
0
25
50
75 100 125
-50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25.
Figure 26.
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APPLICATION INFORMATION
+5V
+5V
6.8 mF
6.8 mF
0.1 mF
R
R
V
OUT
F
A
V
= 1 +R /R = V
/V
OUT IN
F
G
0.1 mF
A
V
=
=
V
IN
G
V
IN
C
C
POS
7
POS
7
3
2
3
2
+
LMH6703
V
+
LMH6703
V
OUT
OUT
6
6
C
SS
C
SS
0.01 mF
R
IN
25W
0.01 mF
-
-
C
C
NEG
NEG
4
4
R
R
F
R
G
F
V
IN
0.1 mF
6.8 mF
0.1 mF
6.8 mF
R
G
SELECT R TO
T
R
T
YIELD DESIRED
-5V
-5V
R
= R ||R
T G
IN
Figure 27. Recommended Non-Inverting Gain
Figure 28. Recommended Inverting Gain Circuit
(SOIC Pinout Shown)
Circuit
(SOIC Pinout Shown)
GENERAL DESCRIPTION
The LMH6703 is a high speed current feedback amplifier, optimized for excellent bandwidth, gain flatness, and
low distortion. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly
set by the feedback resistor value. The LMH6703 in the SOT-23-6 package is optimized for use with a 560Ω
feedback resistor. The LMH6703 in the SOIC package is optimized for use with a 390Ω feedback resistor. Using
lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth.
Application Note OA-13 (SNOA366) discusses this in detail along with the occasions where a different RF might
be advantageous.
EVALUATION BOARDS
Device
Package
SOT-23-6
SOIC
Evaluation Board Part Number
CLC730216
LMH6703MF
LMH6703MA
CLC730227
FEEDBACK RESISTOR SELECTION
One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency
response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical
Characteristics and Typical Performance plots specify an RF of 560Ω (390Ω for the SOIC package), a gain of +2
V/V and ±5V power supplies (unless otherwise specified). Generally, lowering RF from it’s recommended value
will peak the frequency response and extend the bandwidth while increasing the value of RF will cause the
frequency response to roll off faster. Reducing the value of RF too far below it’s recommended value will cause
overshoot, ringing and, eventually, oscillation.
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800
700
600
500
400
INVERTING (SOT23-6)
300
200
100
G (SOIC)
NON-INVERTIN
1
2
3
4
5
6
7
8
9
10
GAIN (V/V)
Figure 29. Recommended RF vs. Gain
Since a current feedback amplifier is dependant on the value of RF to provide frequency compensation and since
the value of RF can be used to optimize the frequency response, different packages use different RF values. As
shown in Figure 29, Recommended RF vs. Gain, the SOT-23-6 and the SOIC package use different values for
the feedback resistor, RF. Since each application is slightly different, it is worth some experimentation to find the
optimal RF for a given circuit. In general, a value of RF that produces ≈0.1 dB of peaking is the best compromise
between stability and maximum bandwidth. Note that it is not possible to use a current feedback amplifier with
the output shorted directly to the inverting input. The buffer configuration of the LMH6703 requires a 560Ω (390Ω
for SOIC package) feedback resistor for stable operation.
The LMH6703 was optimized for high speed operation. As shown in Figure 29, the suggested value for RF
decreases for higher gains. Due to the output impedance of the input buffer, there is a practical limit for how
small RF can go, based on the lowest practical value of RG. This limitation applies to both inverting and non
inverting configurations. For the LMH6703 the input resistance of the inverting input is approximately 30Ω and
20Ω is a practical (but not hard and fast) lower limit for RG. The LMH6703 begins to operate in a gain bandwidth
limited fashion in the region when RG is nearly equal to the input buffer impedance. Note that the amplifier will
operate with RG values well below 20Ω, however results may be substantially different than predicted from ideal
models. In particular the voltage potential between the Inverting and Non-Inverting inputs cannot be expected to
remain small.
Inverting gain applications that require impedance matched inputs may limit gain flexibility somewhat (especially
if maximum bandwidth is required). The impedance seen by the source is RG || RT (RT is optional). The value of
RG is RF /Gain. Thus for a SOT-23 in a gain of —5V/V, an RF of 460Ω is optimum and RG is 92Ω. Without a
termination resistor, RT, the input impedance would equal RG, 92Ω. Using an RT of 109Ω will set the input
resistance to match a 50Ω source. Note that source impedances greater then RG cannot be matched in the
inverting configuration.
For more information see Application Note OA-13 (SNOA366) which describes the relationship between RF and
closed-loop frequency response for current feedback operational amplifiers. The value for the inverting input
impedance for the LMH6703 is approximately 30Ω. The LMH6703 is designed for optimum performance at gains
of +1 to +10 V/V and −1 to −9 V/V. Higher gain configurations are still useful, however, the bandwidth will fall as
gain is increased, much like a typical voltage feedback amplifier.
The LMH6703 data sheet shows both SOT-23-6 and SOIC data in the Electrical Characteristic section to aid in
selecting the right package. The Typical Performance Characteristics section shows SOT-23-6 package plots
only.
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CAPACITIVE LOAD DRIVE
X1
R
ISO
51W
+
-
V
IN
+
-
CL
10 pF
R
L
R
IN
R
G
1 kW
51W
560W
R
F
560W
Figure 30. Decoupling Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor RISO. Figure 30 shows
the use of a series output resistor, RISO, to stabilize the amplifier output under capacitive loading. Capacitive
loads from 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible
oscillation. The chart “Suggested RISO vs. Cap Load” gives a recommended value for selecting a series output
resistor for mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of
peaking in the frequency response. This produces a good compromise between settling time and bandwidth. For
applications where maximum frequency response is needed and some peaking is tolerable, the value of RISO can
be reduced slightly from the recommended values.
DC ACCURACY AND NOISE
Example below shows the output offset computation equation for the non-inverting configuration (see Figure 27)
using the typical bias current and offset specifications for AV = + 2:
Output Offset : VO = (IBN · RIN ± VOS) (1 + RF/RG) ± IBI · RF
Where RIN is the equivalent input impedance on the non-inverting input.
Example computation for AV = +2, RF = 560Ω, RIN = 25Ω:
VO = (7 μA · 25Ω ± 1.5 mV) (1 + 560/560) ± 2μA · 560≈ −3.7 mV to 4.5 mV
A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet
tables, in order to ensure "worst case" operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA-07 (SNOA365). The two input bias currents are physically unrelated in both magnitude and
polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the
source impedance for the two inputs (as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12
(SNOA375) for a full discussion of noise calculations for current feedback amplifiers.
PRINTED CIRCUIT LAYOUT
Whenever questions about layout arise, use the evaluation board as a guide. The CLC730216 is the evaluation
board for SOT-23-6 samples of the LMH6703 and the CLC730227 is the evaluation board for SOIC samples of
the LMH6703.
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins.
Components in the feedback path should be placed as close to the device as possible to minimize parasitic
capacitance. For long signal paths controlled impedance lines should be used, along with impedance matching
elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each voltage rail
to ground are applied in pairs. The larger electrolytic bypass capacitors can be located further from the device,
the smaller ceramic bypass capacitors should be placed as close to the device as possible. In Figure 27 and
Figure 28 CSS is optional, but is recommended for best second order harmonic distortion.
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LMH6703
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SNOSAF2D –FEBRUARY 2005–REVISED MARCH 2013
VIDEO PERFORMANCE
6.8 mF
C2
0.01 mF
+5V
C1
X1
R
IN
75W
+
-
V
IN
+
-
V
OUT
R
OUT
75W
R
G
560W
R
F
560W
0.01 mF
-5V
C3
6.8 mF
C4
Figure 31. Typical Video Application
The LMH6703 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless
with DG of 0.01% and DP of 0.02°. Best performance will be obtained with back terminated loads. The back
termination reduces reflections from the transmission line and effectively masks transmission line and other
parasitic capacitance from the amplifier output stage. Figure 31 shows a typical configuration for driving 75Ω
cable. The amplifier is configured for a gain of two compensating for the 6 dB loss due to ROUT
.
ENABLE/DISABLE
PIN 6
+
V
20 kW
SUPPLY
MID-POINT
PULL-UP
20 kW
BIAS CIRCUITRY
RESISTOR
PIN 5
SD
Q
Q
1
2
+
-
V
- V
20 kW
2
I TAIL
PIN 2
-
V
NOTE: PINS 2, 5, 6 ARE EXTERNAL
Figure 32. SD Pin Simplified Schematic
(SOT-23 Pinout Shown)
For ±5V supplies only the LMH6703 has a TTL logic compatible disable function. Apply a logic low (< 0.8V) to
the SD pin and the LMH6703 is disabled. Apply a logic high (> 2.0V), or let the pin float and the LMH6703 is
enabled. Voltage, not current, at the Shutdown pin (SD) determines the enable/disable state. Care must be
exercised to prevent the shutdown pin voltage from going more than 0.8V below the midpoint of the supply
voltages (0V with split supplies, V+/2 with single supply biasing). Doing so could cause transistor Q1 to Zener
resulting in damage to the disable circuit (See Figure 32). The core amplifier is unaffected by this, but the
shutdown operation could become permanently slower as a result.
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Disabled, the LMH6703 inputs and output become high impedances. While disabled the LMH6703 quiescent
current is approximately 200 µA. Because of the pull up resistor on the shutdown circuit, the ICC and IEE currents
(positive and negative supply currents respectively) are not balanced in the disabled state. The positive supply
current (ICC) is approximately 300 µA while the negative supply current (IEE) is only 200 µA. The remaining IEE
current of 100 µA flows through the shutdown pin.
The disable function can be used to create analog switches or multiplexers. Implement a single analog switch
with one LMH6703 positioned between an input and output. Create an analog multiplexer with several
LMH6703’s and tie the outputs together.
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SNOSAF2D –FEBRUARY 2005–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMH6703MA/NOPB
LMH6703MAX/NOPB
LMH6703MF/NOPB
LMH6703MFX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
6
6
95
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LMH67
03MA
ACTIVE
ACTIVE
ACTIVE
D
2500
1000
3000
Green (RoHS
& no Sb/Br)
-40 to 85
LMH67
03MA
SOT-23
SOT-23
DBV
DBV
Green (RoHS
& no Sb/Br)
-40 to 85
AR1A
Green (RoHS
& no Sb/Br)
-40 to 85
AR1A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6703MAX/NOPB
LMH6703MF/NOPB
LMH6703MFX/NOPB
SOIC
D
8
6
6
2500
1000
3000
330.0
178.0
178.0
12.4
8.4
6.5
3.2
3.2
5.4
3.2
3.2
2.0
1.4
1.4
8.0
4.0
4.0
12.0
8.0
Q1
Q3
Q3
SOT-23
SOT-23
DBV
DBV
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6703MAX/NOPB
LMH6703MF/NOPB
LMH6703MFX/NOPB
SOIC
D
8
6
6
2500
1000
3000
367.0
210.0
210.0
367.0
185.0
185.0
35.0
35.0
35.0
SOT-23
SOT-23
DBV
DBV
Pack Materials-Page 2
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