LMH6882SQE/NOPB [TI]
具有增益控制的 2.4GHz 双路可编程差动放大器 | NJK | 36 | -40 to 85;
| 型号： | LMH6882SQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有增益控制的 2.4GHz 双路可编程差动放大器 | NJK | 36 | -40 to 85 放大器 信息通信管理 |
| 文件： | 总38页 (文件大小：1027K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
LMH6882 直流至 2.4GHz、高线性度、双路可编程差分放大器
1 特性
3 说明
1
•
小信号带宽：2400MHz
100MHz 时的 OIP3：42dBm
LMH6882 是一款高速、高性能、可编程的差分放大
器。 该器件具有 2.4GHz 的带宽和 42dBm OIP3 的高
线性度，适合各类信号调节应用。
•
•
•
•
•
•
•
•
100MHz 时的 HD3：-100dBc
噪声系数：9.7dB
LMH6882 可编程差分放大器完美结合了全差分放大器
和可变增益放大器的优点。 此器件无需外部电阻即可
在整个增益范围内提供优异的抗噪声和失真性能，因此
只需使用一个器件和一种设计就能满足需要不同增益设
置的多种应用的要求。
电压增益范围：6dB 至 26dB
电压增益步长：0.25dB
输入阻抗：100Ω
并行和串行增益控制
断电功能
LMH6882 是一款易于使用的放大器，既可以替代全差
分、固定增益放大器，也可以替代可变增益放大器。
LMH6882 无需任何外部增益设置元件，并且支持在
6dB 到 26dB 范围内进行增益设置（增益步长为
0.25dB，小而精确）。 如左侧的电压增益图所示，增
益步长在整个增益范围内都非常精确。 LMH6882 的输
入阻抗为 100Ω，可轻松驱动混频器或滤波器等各类
源。 LMH6882 还支持 50Ω 单端信号源，并且支持直
流和交流耦合应用。
2 应用
•
•
•
•
•
•
微波回程音频接收器
零中频 (IF) 采样
同相/正交 (I/Q) 采样
医疗成像
射频 (RF)/IF 与基带增益块
差分电缆驱动器
OIP3 与电压增益间的关系
凭借并行增益控制，可将 LMH6882 以固定增益进行焊
接，因此无需任何控制电路。 如果需要进行动态增益
控制，则可以通过 串行外设接口 (SPI)™ 串行命令或
并行引脚来更改 LMH6881。
50
45
40
35
30
25
20
LMH6882 由德州仪器 (TI) 的 CBiCMOS8 专有硅锗互
补工艺制成，并且采用节省空间的散热增强型 36 引脚
超薄型四方扁平无引线 (WQFN) 封装。 此放大器还提
供了单路封装型号 LMH6881。
f = 100 MHz
= 4dBm / Tone
器件信息(1)
P
OUT
器件型号
LMH6882
封装
封装尺寸（标称值）
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
WQFN (36)
6.00mm x 6.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNOSC84
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 15
7.5 Programming........................................................... 16
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 26
Power Supply Recommendations...................... 29
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics .......................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
10.3 Thermal Considerations........................................ 31
11 器件和文档支持 ..................................................... 32
11.1 文档支持................................................................ 32
11.2 商标....................................................................... 32
11.3 静电放电警告......................................................... 32
11.4 术语表 ................................................................... 32
12 机械封装和可订购信息 .......................................... 32
7
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D
Page
•
已添加 引脚配置和功能部分，ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，
布局部分，器件和文档支持部分以及机械、封装和可订购信息部分........................................................................................ 1
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 29
2
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
5 Pin Configuration and Functions
NJK Package
36-Pins WQFN
Top View
10
NC
INMSA
OUTPA
OUTMA
NC
INMDA
INPDA
INPSA
D0
NC
NC
GND
INPSB
OUTMB
OUTPB
28 NC
INPDB
INMDB
INMSB
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
ANALOG I/O
INPD, INMD
INPS, INMS
OUTP, OUTM
POWER
11, 12, 16, 17
10, 13, 15, 18
35, 34, 30, 29
Analog Input
Differential inputs 100 Ω
Analog Input
Single ended inputs 50 Ω
Analog Output
Differential outputs, low impedance
GND
5, 6, 22, 23
Ground
Ground pins. Connect to low-impedance ground plane.
All pin voltages are specified with respect to the voltage
on these pins. The exposed thermal pad is internally
bonded to the ground pins.
VCC
3, 4, 24, 25
Power
Power supply pins. Valid power supply range is 4.75 V to
5.25 V.
Exposed Center Pad Thermal/ Ground
Thermal management/ Ground
DIGITAL INPUTS
SPI
27
Digital Input
0 = Parallel Mode, 1 = Serial Mode
PARALLEL MODE DIGITAL PINS, SPI = LOGIC LOW
D0, D1, D2, D3, D4, D5, D6 14, 7, 8, 9, 21, 29, 19 Digital Input
Attenuator control, D0 = 0.25 dB, D6 = 16 dB
Shutdown 0 = amp on, 1 = amp off
SD
1
Digital Input
SERIAL MODE DIGITAL PINS, SPI = LOGIC HIGH (SPI COMPATIBLE)
CS
9
8
Digital Input
Digital Input
Chip Select (active low)
Clock
CLK
SDO
14
Digital Output- Open
Emitter
Serial Data Output (Requires external bias.)
SDI
7
Digital Input
Serial Data In
Copyright © 2012–2015, Texas Instruments Incorporated
3
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN
MAX
5.5
UNIT
V
Positive supply voltage (VCC)
Differential voltage between any two grounds
Analog input voltage
−0.6
< 200
5.5
mV
V
−0.6
−0.6
Digital input voltage
5.5
V
Output short circuit duration (one pin to ground)
Junction temperature
Infinite
+150
260
°C
°C
°C
Soldering information: infrared or convection (30 sec)
Storage temperature, Tstg
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.25
< 10
UNIT
V
Supply voltage (VCC)
4.75
Differential voltage between any two grounds
mV
Analog input voltage,
AC coupled
0
VCC
85
V
(1)
Temperature range
–40
°C
(1) The maximum power dissipation is a function of TJ(MAX), θJA and the ambient temperature TA. The maximum allowable power dissipation
at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.4 Thermal Information
LMH6882
THERMAL METRIC(1)
NJK (WQFN)
36 PINS
33.6
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
16.9
7.8
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
7.7
RθJC(bot)
3.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
6.5 Electrical Characteristics
The following specifications apply for single supply with VCC = 5 V, Maximum Gain (26 dB), RL = 200 Ω.(1)(2)(3)
TEST CONDITIONS
MIN(4)
TYP(5)
MAX(4)
UNIT
DYNAMIC PERFORMANCE
3dBBW
NF
−3-dB Bandwidth
VOUT = 2 VPPD
Source Resistance (Rs) = 100 Ω
2.4
9.7
42
GHz
dB
Noise Figure
OIP3
Output Third Order Intercept Point(6) f = 100 MHz, POUT = 4 dBm per tone, tone
spacing = 1 MHz
dBm
f = 200 MHz, POUT = 4 dBm per tone, tone
spacing = 2 MHz
40
76
OIP2
IMD3
Output Second Order Intercept Point POUT= 4 dBm per Tone, f1 = 112.5 MHz,
f2=187.5 MHz
dBm
dBc
Third Order Intermodulation
Products
f = 100 MHz, VOUT = 4 dBm per tone, tone
spacing = 1 MHz
−76
−72
f = 200 MHz, POUT = 4 dBm per tone, tone
spacing = 2 MHz
P1dB
HD2
HD3
CMRR
SR
1-dB Compression Point
Output power
17
−70
−76
−40
6000
47
dBm
dBc
Second Order Harmonic Distortion
Third Order Harmonic Distortion
f = 200 MHz, VOUT = 4 dBm
f = 200 MHz, POUT = 4 dBm
Pin = −15 dBm, f = 100 MHz
dBc
(7)
Common Mode Rejection Ratio
dBc
Slew Rate
V/us
Output Voltage Noise
Input Referred Voltage Noise
Maximum Gain f > 1 MHz
Maximum Gain f > 1 MHz
nV/√Hz
nV/√Hz
2.3
ANALOG I/O
RIN
RIN
Input Resistance
Input Resistance
Differential, INPD to INMD
100
50
Ω
Ω
Single Ended, INPS or INMS, 50-Ω
termination on unused input
VICM
Input Common Mode Voltage
Maximum Input Voltage Swing
Self Biased
2.5
2
V
Volts peak to peak, differential
VPPD
VPPD
Maximum Differential Output Voltage Differential, f < 10 MHz
Swing
6
ROUT
Output Resistance
Differential, f = 100 MHz
0.4
Ω
GAIN PARAMETERS
Maximum Voltage Gain
Parallel Inputs (INPD and INMD), Rs =
26
100 Ω
dB
dB
Single ended input (INMS or INPS), 50 Ω
Rs and 50 Ω termination on unused input.
26.6
Minimum Gain
Gain Steps
Gain Code = 80d or 50h
6
80
Gain Step Size
Gain Step Error
Gain Step Phase Shift
0.25
±0.125
±3
dB
dB
Any two adjacent steps over entire range
Any two adjacent steps over entire range
Degrees
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance
is indicated in the electrical tables under conditions different than those tested
(2) Negative input current implies current flowing out of the device.
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(4) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(5) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(6) OIP3 is the third order intermodulation intercept point. In this data sheet OIP3 numbers are single power measurements where OIP3 =
IMD3 / 2 + POUT (per tone). OIP2 is the second order intercept point where OIP2 = IMD2 + POUT (per tone). HD2 is the second order
harmonic distortion and is a single tone measurement. HD3 is the third order harmonic distortion and is a single tone measurement.
Power measurements are made at the amplifier output pins.
(7) CMRR is defined as the differential response at the output in response to a common mode signal at the input.
Copyright © 2012–2015, Texas Instruments Incorporated
5
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
Electrical Characteristics (continued)
The following specifications apply for single supply with VCC = 5 V, Maximum Gain (26 dB), RL = 200 Ω.(1)(2)(3)
TEST CONDITIONS
MIN(4)
TYP(5)
MAX(4)
UNIT
dB
Channel to Channel Gain Matching
f = 100 MHz, over entire gain range
0.2
Channel to Channel Phase Matching f= 100 MHz, over entire gain range
Gain Step Switching Time
1.5
Degrees
ns
20
Enable/ Disable Time
POWER REQUIREMENTS
Settled to 90% level
15
ns
ICC
P
Supply Current
Power
200
1
270
mA
W
ICC
Disabled Supply Current
25
mA
ALL DIGITAL INPUTS
Logic Compatibility
TTL, 2.5 V CMOS, 3.3 V CMOS, 5 V CMOS
VIL
VIH
IIH
IIL
Logic Input Low Voltage
0.4
2.0-5.0
−9
V
V
Logic Input High Voltage
Logic Input High Input Current
Logic Input Low Input Current
μA
μA
−47
PARALLEL MODE TIMING
tGS
tGH
Setup Time
Hold Time
3
3
ns
ns
SERIAL MODE
fCLK SPI Clock Frequency
50% duty cycle, ATE tested @ 10 MHz
10
50
MHz
6
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
6.6 Typical Characteristics
(Unless otherwise specified, the following conditions apply: TA = 25°C, VCC = 5 V, RL = 200 Ω, Maximum Gain,
Differential Input.)(8)
35
50
30
45
40
35
30
25
20
25
20
15
10
5
0
-5
f = 100 MHz
= 4dBm / Tone
-10
-15
4dB Step
10
P
OUT
1
100
1k
10k
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
FREQUENCY (MHz)
Figure 1. Frequency Response Over Gain Range
Figure 2. OIP3 vs Voltage Gain
50
50
45
40
35
30
25
20
15
10
5
20
18
16
14
12
10
8
45
40
35
DRF = IIP3 - NF
6
4
f = 100MHz
Tone Spacing = 1 MHz
OIP3
2
Noise Figure
Dynamic Range Figure
30
0
0
-4
-2
0
2
4
6
8
10
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
OUTPUT POWER FOR EACH TONE (dBm)
Figure 3. OIP3 vs Output Power
Figure 4. Dynamic Range Figure vs Voltage Gain
50
50
f = 100 MHz
P
= 4dBm / Tone
OUT
45
40
35
30
25
20
45
40
35
30
Voltage Gain
Voltage Gain
26 dB
26 dB
16 dB
6 dB
16 dB
6 dB
0
50 100 150 200 250 300 350 400
FREQUENCY (MHz)
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
Figure 5. OIP3 vs Frequency
Figure 6. OIP3 vs Supply Voltage
(8) LMH6881 devices have been used for some typical performance plots.
Copyright © 2012–2015, Texas Instruments Incorporated
7
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
Typical Characteristics (continued)
50
90
85
80
75
70
65
60
55
50
f = 100 MHz
P
= 4dBm
OUT
45
40
35
30
25
Temperature
- 40 °C
f = 187.5 MHz
1
f = 112.5 MHz
2
25 °C
P
= 4dBm / Tone
OUT
85 °C
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
Figure 7. OIP3 vs Temperature
Figure 8. OIP2 vs Voltage Gain
100
99
98
97
96
95
94
93
92
91
90
27.0
26.5
26.0
25.5
25.0
24.5
24.0
f = 100 MHz
P
= 4.5dBm
OUT
-45 -30 -15
0
15 30 45 60 75 90
-45 -30 -15
0
15 30 45 60 75 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Supply Current vs Temperature
Figure 10. Maximum Gain vs Temperature
-30
-40
-50
-60
-70
-80
-90
-100
-30
-40
-50
-60
-70
-80
-90
-100
Voltage Gain
26 dB
16 dB
Voltage Gain
26 dB
16 dB
6 dB
6 dB
0
50
100
150
Frequency (MHz)
200
250
300
350
400
0
50
100
150
Frequency (MHz)
200
250
300
350
400
D001
D002
Pout = 4 dBm
Pout = 4 dBm
Figure 11. HD2 vs Frequency
Figure 12. HD3 vs Frequency
8
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
Typical Characteristics (continued)
-40
-20
HD2
Voltage Gain
-30
-40
-50
-60
HD3
26 dB
21 dB
10 dB
-50
f = 100 MHz
-70
POUT = 4dBm
-60
-80
-70
-80
-90
-90
-100
-110
-100
-110
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
0
2
4
6
8
10 12 14 16
OUTPUT POWER (dBm)
C001
Figure 13. HD2 & HD3 vs Voltage Gain
Figure 14. HD2 vs Output Power
-10
-20
20
15
10
5
Voltage Gain
26 dB
f = 100 MHz
Voltage Gain = 26dB
-30
-40
21 dB
10 dB
-50
-60
-70
-80
-90
0
-100
-110
-5
0
2
4
6
8
10 12 14 16
-25
-20
-15
-10
-5
0
OUTPUT POWER (dBm)
INPUT POWER (dBm)
Figure 15. HD3 vs Output Power
Figure 16. Output Power vs Input Power
1.0
0.2
0.1
50 MHz
200 MHz
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0.0
-0.1
-0.2
50 MHz
200 MHz
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
Figure 17. Gain Step Amplitude Error
Figure 18. Gain Step Phase Error
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LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
Typical Characteristics (continued)
0.6
3
2
50 MHz
200 MHz
0.5
0.4
0.3
1
0
0.2
-1
-2
-3
-4
-5
0.1
0.0
-0.1
-0.2
-0.3
50 MHz
200 MHz
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
Figure 19. Cumulative Amplitude Error
30
Figure 20. Cumulative Phase Error
14
13
12
11
10
9
25
20
15
10
5
8
7
0
6
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
0
200
400
600
800
1000
FREQUENCY (MHz)
Figure 21. Noise Figure vs Voltage Gain
Figure 22. Noise Figure vs Frequency
5
4
4
5
4
4
3
Enable Control
Output Voltage
16dB Gain Control
Ouptut Voltage
3
2
3
3
2
2
1
2
1
1
0
1
0
0
-1
-2
0
-1
-2
-1
-1
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
Figure 23. Channel Enable Control Timing Behavior
Figure 24. 16-dB Gain Control Timing Behavior
10
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
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ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
Typical Characteristics (continued)
0
5
4
3
8 dB Gain Control
Output Voltage
4
-10
-20
-30
-40
-50
-60
3
2
2
1
1
0
0
-1
-2
-1
1
10
100
1k
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
FREQUENCY (MHz)
Figure 26. Common Mode Rejection (Sdc21) vs Frequency
Figure 25. 8-dB Gain Control Timing Behavior
125
50
40
100
Impedance = R + j X
R
X
30
20
75
R
X
Impedance = R + j X
10
50
25
0
0
-10
-20
-30
-40
-50
-25
-50
0
400
800
1200 1600 2000
0
400
800
1200 1600 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. Differential Input Impedance
Figure 28. Differential Output Impedance
0
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.00
1.75
Gain
Phase
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1.50
1.25
1.00
0.75
f = 100 MHz
CHA - CHB
0.50
0.25
0.00
10
100
1k
10k
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
FREQUENCY (MHz)
Figure 29. Crosstalk
Figure 30. Channel A to Channel B Gain and Phase
Matching
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Typical Characteristics (continued)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
50
45
40
35
30
Gain
Phase
f = 100 MHz
CHA - CHB
25
20
f = 100 MHz
= 4dBm / Tone
P
OUT
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
Figure 31. OIP3 Overvoltage Gain Range
Figure 32. Channel A to Channel B Gain and Phase
Matching
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6.6.1 Single-Ended Input
(Unless otherwise specified, the following conditions apply: TA = 25°C, VCC = 5 V, RL = 200Ω, Maximum Gain,
Differential Input).
-30
50
Volt Gain
26 dB
-40
16 dB
6 dB
45
-50
-60
40
-70
-80
35
Single Ended Input
f = 100 MHz, 1MHz Spacing
-90
P
= 4dBm / Tone
OUT
0
50
100
150
200
250
Frequency (MHz)
300
350
400
D001
30
Pout = 4 dBm
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
Figure 34. HD2 vs Frequency Across Gain Settings
Figure 33. OIP3 vs Voltage Gain
-30
-40
-50
-60
-70
-80
-90
-100
-30
Volt Gain
26 dB
16 dB
6 dB
HD2
HD3
-40
-50
-60
-70
-80
-90
-100
-110
0
50
100
150
Frequency (MHz)
200
250
300
350
400
6
8
10
12
14
Voltage Gain (dB)
16
18
20
22
24
26
D002
D003
Pout = 4 dBm
f = 100 MHz
Figure 36. HD2 & HD3 vs Voltage Gain
60
Pout = 4 dBm
Figure 35. HD3 vs Frequency Across Gain Settings
20
f = 100 MHz
18
50
40
30
20
10
0
R
X
16
14
12
10
8
Impedance = R + j X
-10
-20
6
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
0
400
800
1200 1600 2000
FREQUENCY (MHz)
Figure 37. Noise Figure vs Voltage Gain
Figure 38. Input Impedance
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7 Detailed Description
7.1 Overview
The LMH6882 has been designed to replace traditional, fixed-gain amplifiers, as well as variable-gain amplifiers,
with an easy-to-use device which can be flexibly configured to many different gain settings while maintaining
excellent performance over the entire gain range. Many systems can benefit from this programmable-gain, DC-
capable, differential amplifier. Last minute design changes can be implemented immediately, and external
resistors are not required to set the gain. Gain control is enabled with a parallel- or a serial-control interface and
as a result, the amplifier can also serve as a digitally controlled variable-gain amplifier (DVGA) for automatic gain
control applications. Figure 50 and Figure 53 show typical implementations of the amplifier.
The LMH6882 is a fully differential amplifier optimized for signal path applications up to 1000 MHz. The
LMH6882 has a 100-Ω input impedance and a low (less than 0.5 Ω) impedance output. The gain is digitally
controlled over a 20 dB range from 26 dB to 6 dB. The LMH6882 is designed to replace fixed-gain differential
amplifiers with a single, flexible-gain device. It has been designed to provide good noise figure and OIP3 over the
entire gain range. This design feature is highlighted by the Dynamic Range Figure of merit (DRF). Traditional
variable gain amplifiers generally have the best OIP3 and NF performance at maximum gain only.
7.2 Functional Block Diagram
SD
SPI
Power Down A
INPSA
INPDA
OUTPA
AMP_In
AMP_Out
OUTMA
INMDA
INMSA
ATTEN
Decode
X 2
OCMA
Power Down A
Power Down B
SPI
SPI
D0 - D6
Parallel
Decode
ATTEN
INMSB
OCMB
X 2
INMDB
INPDB
OUTMB
OUTPB
AMP_In
AMP_Out
INPSB
Power Down B
SPI
SD
7.3 Feature Description
The LMH6882 has three functional stages, a low-noise amplifier, followed by a digital attenuator, and a low-
distortion, low-impedance output amplifier. The amplifier has four signal input pins to accommodate both
differential signals and single-ended signals. The amplifier has an OCM pin used to set the output common-mode
voltage. There is a gain of 2 on this pin so that 1.25 V applied on that pin will place the output common mode at
2.5 V.
14
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Feature Description (continued)
+5V
0.01 PF
SOURCE
LOAD
VCC
INMS
49.9:
50:
OUT+
INMD
2.5V
V
CM
2.5V
V
AC
CM
LMH6882
100:
INPD
OUT-
50:
49.9:
INPS
OCM
0.01 PF
1.25V
Figure 39. Typical Implementation With a Differential Input Signal
+5V
0.01 PF
SOURCE
LOAD
VCC
50:
V
IN
2.5V INMS
INMD
49.9:
OUT+
AC
V
2.5V
CM
LMH6882
100:
INPD
INPS
OUT-
49.9:
50:
0.01 PF
OCM
0.01 PF
2.5V
1.25V
Figure 40. Typical Implementation With a Single-Ended Input Signal
7.4 Device Functional Modes
The LMH6882 will support two modes of control for its gain: a parallel mode and a serial mode (SPI compatible).
Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with
existing SPI-compatible systems. The device has gain settings covering a range of 20 dB. In parallel mode, only
2-dB steps are available. The serial interface should be used for finer gain control of 0.25 dB for a gain between
6 dB and 26 dB of voltage gain. If fixed gain is desired, the digital pins can be strapped to ground or VCC, as
required.
The device also supports two modes of power down control to enable power savings when the amplifier is not
being used: using the SD pin (when SPI pin = Logic 0) and the power-down register (when SPI pin = Logic 1).
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7.5 Programming
7.5.1 Digital Control of the Gain and Power-Down Pins
The LMH6882 was designed to interface with 2.5-V to 5-V CMOS logic circuits. If operation with 5-V logic is
required care should be taken to avoid signal transients exceeding the amplifier supply voltage. Long,
unterminated digital signal traces should be avoided. Signal voltages on the logic pins that exceed the device
power-supply voltage may trigger ESD protection circuits and cause unreliable operation. Some digital input-
output pins have different functions depending on the digital control mode. Table 1 shows the mapping of the
digital pins. These functions for each pin will be described in the sections Parallel Interface and SPI-Compatible
Serial Interface.
While the full gain range is available in parallel mode both channels must be set to the same gain. If independent
channel control is desired, SPI mode must be used.
Table 1. Pins With Dual Functions
PIN
7
SPI = 0
D1
SPI = 1
SDI
(1)
14
8
D0
SDO
D2
CLK
9
D3
CS (active low)
(1) Pin 14 requires external bias. See SPI-Compatible Serial Interface for details.
7.5.2 Parallel Interface
Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space
dedicated to control lines. To place the LMH6882 into parallel mode the SPI pin (pin 27) is set to the logical zero
state. Alternately, the SPI pin can be connected directly to ground. The SPI pin has a weak internal resistor to
ground. If left unconnected, the amplifier will operate in parallel mode.
In parallel mode the gain can be changed in 0.25-dB steps with a 7-bit gain control bus. The attenuator control
pins are internally biased to logic high state with weak pull-up resistors, with the exception of D0 (pin 14) which is
biased low due to the shared SDO function. If the control bus is left unconnected, the amplifier gain will be set to
6 dB. Table 2 shows the gain of the amplifier when controlled in parallel mode.
The LMH6882 has a 7-bit gain control bus. Data from the gain control pins is immediately sent to the gain circuit
(that is, gain is changed immediately). To minimize gain change glitches all gain pins should change at the same
time. Gain glitches could result from timing skew between the gain set bits. This is especially the case when a
small gain change requires a change in state of three or more gain control pins. If necessary the PDA could be
put into a disabled state while the gain pins are reconfigured and then brought active when they have settled.
Table 2. Gain Change Values for the Parallel-Gain Pins
PIN
14
7
NAME
D0
GAIN STEP SIZE (dB)
0.25
0.5
1
D1
8
D2
9
D3
2
21
20
19
D4
4
D5
8
D6
16
Gain combinations that exceed 80 will result in minimum gain of 6 dB.
16
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Table 3. Amplifier Gain for Selected Control Pin Combinations
CONTROL PINS LOGICAL LEVEL IN PARALLEL MODE. (X = DON'T
CARE)
GAIN = 26 - 0.25 × DECIMAL VALUE AND GAIN
≥ 6 dB
Decimal/
Hex
D6
D5
D4
D3
D2
D1
D0
Amplifier Voltage Gain (dB)
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
X
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
X
X
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
X
X
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
X
X
0 / 0
1 / 1
26
25.75
25.5
25.25
25
2 / 2
3 / 3
4 / 4
5 / 5
24.75
24.5
24.25
24
6 / 5
7 / 7
8 / 8
16 / 10
24 / 18
32 / 20
40 / 28
48 / 30
56 / 38
64 / 40
72 / 48
80 / 50
> 80 / 50
> 80 / 50
22
20
18
16
14
12
10
8
6
6
6
For fixed-gain applications the attenuator control pins should be connected to the desired logic state instead of
relying on the weak internal bias. Data from the gain-control pins directly drive the amplifier gain circuits. To
minimize gain change glitches all gain pins should be driven with minimal skew. If gain-pin timing is uncertain,
undesirable transients can be avoided by using the shutdown pin to disable the amplifier while the gain is
changed. Gain glitches are most likely to occur when multiple bits change value for a small gain change, such as
the gain change from 10 dB to 12 dB which requires changing all 4 gain control pins.
A shutdown pin (SD == 0, amplifier on, SD == 1, amplifier off) is provided to reduce power consumption by
disabling the highest power portions of the amplifier. The digital control circuit is not shut down and will preserve
the last active gain setting during the disabled state. See the Typical Characteristics section for disable and
enable timing information. The SD pin is functional in parallel mode only and disabled in serial mode.
LMH6882
CONTROL LOGIC
Shutdown
0.25 dB Step
0.5 dB Step
1 dB Step
SD
D0
D1
D2
D3
2 dB Step
4 dB Step
D4
D5
D6
8 dB Step
16 dB Step
Figure 41. Parallel Mode Connection
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7.5.3 SPI-Compatible Serial Interface
The serial interface allows a great deal of flexibility in gain programming and reduced board complexity. The
LMH6882 serial interface is a generic 4-wire synchronous interface compatible with SPI type interfaces that are
used on many microcontrollers and DSP controllers. Using only 4 wires, the SPI mode offers access to the 0.25-
dB gain steps of the amplifier.
For systems where gain is changed only infrequently, or where only slower gain changes are required, serial
mode is the best choice. To place the LMH6882 into serial mode the SPI pin (Pin 27) should be put into the logic
high state. Alternatively the SPI pin can be connected directly to the 5-V supply bus. In this configuration the pins
function as shown in Table 2. The SPI interface uses the following signals: clock input (CLK); serial data in (SDI);
serial data out (SDO); and serial chip select (CS). The chip-select pin is active low meaning the device is
selected when the pin is low.
The SD pin is inactive in the serial mode. This pin can be left disconnected for serial mode. The SPI interface
has the ability to shutdown the amplifier without using the SD pin.
The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the
rising edge and to source the output data on the SDO pin on the falling edge. The user may disable clock and
hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is
enabled or disabled. The clock pulse-width minimum is equal to one setup plus one hold time, or 6 ns.
The CS pin is the chip-select pin. This pin is active low; the chip is selected in the logic low state. Each assertion
starts a new register access - i.e., the SDATA field protocol is required. The user is required to de-assert this
signal after the 16th clock. If the CS pin is de-asserted before the 16th clock, no address or data write will occur.
The rising edge captures the address just shifted in and, in the case of a write operation, writes the addressed
register. There is a minimum pulse-width requirement for the deasserted pulse - which is specified in the
Electrical Characteristics section.
The SDI pin is the input pin for the serial data. It must observe setup / hold requirements with respect to the
SCLK. Values can be found in the Electrical Characteristics table (refer to electrical table of the DS). Each write
cycle is 16-bit long.
The SDO pin is the data output pin. This output is normally at a high-impedance state, and is driven only when
CS is asserted. Upon CS assertion, contents of the register addressed during the first byte are shifted out with
the second 8 SCLK falling edges. The SDO pin is a current output and requires external bias resistor to develop
the correct logic voltage. See Figure 43 for details on sizing the external bias resistor. Resistor values of 180 Ω
to 400 Ω are recommended. The SDO pin can source 10 mA in the logic high state. With a bias resistor of 250 Ω
the logic 1 voltage would be 2.5 V. In the logic 0 state, the SDO output is off, and no current flows, so the bias
resistor will pull the voltage to 0 V.
Each serial interface access cycle is exactly 16 bits long as shown in Figure 42. Each signal's function is
described below. the read timing is shown in Figure 44.
The external bias resistor means that in the high impedance state the SDO pin impedance is equal to the
external bias resistor value. If bussing multiple SPI devices make sure that the SDO pins of the other devices
can drive the bias resistor.
The serial interface has 6 registers with address [0] to address [6]. Table 4 shows the content of each SPI
register. Registers 0 and 1 are read only. Registers 2 through 6 are read/write and control the gain and power of
the amplifier. Register contents and functions are detailed below.
Table 4. SPI Registers by Address and Function
Address
R/W
R
Name
Default Value Hex (Dec)
0
1
2
3
4
5
Revision ID
Product ID
1 (1)
R
21 (33)
0 (0)
R/W
R/W
R/W
R/W
Power Control
Attenuation A
Attenuation B
Channel Control
50 (80)
50 (80)
3 (3)
18
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Table 5. Serial Word Format for Register 2: Power Control
7
6
5
4
3
2
1
0
RES
RES
CHA1
CHB1
CHA2
CHB2
RES
RES
CHA1 and CHA2 = 0 for ON, CHA1 and CHA2 = 1 for OFF
CHB1 and CHB2 = 0 for ON, CHB1 and CHB2 = 1 for OFF
Table 6. Serial Word Format for Registers 3, 4: Gain Control
7
6
5
4
3
2
1
0
RES
Gain = 26 — (register value * 0.25) valid range is 0 to 80
Table 7. Serial Word Format for Register 5: Channel Control
7
6
5
4
3
2
1
1
RES
SYNC
Load A
Load B
The Channel Control register controls how registers 3 and 4 work. When the SYNC bit is set to 1 both channel A
and channel B are set to the gain indicated in register 3. When the SYNC bit is set to zero, register 3 controls
channel A, and register 4 controls channel B. When the Load A bit is zero data written to register 3 does not
transfer to channel A. When the Load A bit is set to 1 the gain of channel A is set equal to the value indicated in
register 3. The Load B bit works the same for channel B and register 4.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
SCSb
COMMAND FIELD
DATA FIELD
D4 D3
C7
C6
0
C5
0
C4
0
C3
A3
C2
A2
C1
A1
C0
A0
D7
(MSB)
D6
D5
D2
D1
D0
(LSB)
R/Wb
Write DATA
SDI
Reserved (3-bits)
Address (4-bits)
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
Hi-Z
Read DATA
Data (8-bits)
SDO
Single Access Cycle
Figure 42. Serial Interface Protocol (SPI Compatible)
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Control Logic
Clock out
Chip Select out
Data Out (MOSI)
Data In (MISO)
LMH6882
CLK
CS
SDI
SDO
R
10 mA
Typ
For SDO (MISO) pin only:
V
= R x 0.010A,
OH
V
= 0V
OL
Recommended:
R = 250: to 400:
Figure 43. Internal Operation of the SDO Pin
R/Wb
Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write
operation.
Reserved
ADDR:
DATA
Not used. Must be set to 0.
Address of register to be read or written.
In a write operation the value of this field will be written to the addressed register when the chip-
select pin is deasserted. In a read operation this field is ignored.
st
th
th
16 clock
1
clock
8 clock
SCLK
CSb
t
t
CSS
CSH
t
t
CSH
CSS
ODZ
t
t
OZD
t
OD
SDO
D7
D1
D0
Figure 44. Read Timing
20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input Characteristics
The LMH6882 has internally terminated inputs. The INMD and INPD pins are intended to be the differential input
pins and have an internal 100-Ω resistive termination. An example differential circuit is shown in Figure 39. When
using the differential inputs, the single-ended inputs should be left disconnected.
The INMS and INPS pins are intended for use as single-ended inputs and have been designed to support single-
ended termination of 50 Ω working as an active termination. For single-ended signals an external 50-Ω resistor is
required as shown in Figure 40. When using the single-ended inputs, the differential inputs should be left
disconnected.
All of the input pins are self biased to 2.5 V. When using the LMH6882 for DC-coupled applications, it is possible
to externally bias the input pins to voltages from 1.5 V to 3.5 V. Performance is best at the 2.5-V level specified.
Performance will degrade slightly as the common mode shifts away from 2.5 V.
The first stage of the LMH6882 is a low-noise amplifier that can accommodate a maximum input signal of 2 Vppd
on the differential input pins and 1 Vpp on either of the single-ended pins. Signals larger than this will cause
severe distortion. Although the inputs are protected against ESD, sustained electrical overstress will damage the
part. Signal power over 13 dBm should not be applied to the amplifier differential inputs continuously. On the
single-ended pins the power limit is 10 dBm for each pin.
8.1.2 Output Characteristics
The LMH6882 has a low-impedance output very similar to a traditional Op-amp output. This means that a wide
range of loads can be driven with good performance. Matching load impedance for proper termination of filters is
as easy as inserting the proper value of resistor between the filter and the amplifier (See Figure 50 for example.)
This flexibility makes system design and gain calculations very easy. By using a differential output stage the
LMH6882 can achieve large voltage swings on a single 5-V supply. This is illustrated in Figure 45. This figure
shows how a voltage swing of 4 Vppd is realized while only swinging 2 Vpp on each output. A 1-Vp signal on one
branch corresponds to 2 Vpp on that branch and 4 Vppd when looking at both branches (positive and negative).
5.0
4.5
4V
PPD
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2V
PP
Out Plus
Out Minus
Differential Vout
0.0 0.9 1.8 2.7 3.6 4.5 5.4
PHASE ANGLE (Radians)
Figure 45. Differential Output Voltage
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Application Information (continued)
The LMH6882 has been designed for both AC-coupled and DC-coupled applications. To give more flexibility in
DC-coupled applications, the common-mode voltage of the output pins is set by the OCM pin. The OCM pin
needs to be driven from an external low-noise source. If the OCM pin is left floating, the output common-mode is
undefined, and the amplifier will not operate properly.
There is a DC gain of 2 between the OCM pin and the output pins so that the OCM voltage should be between 1
V and 1.5 V. This will set the output common mode voltage between 2 V and 3 V. Output common-mode
voltages outside the recommended range will exhibit poor voltage swing and distortion performance. The
amplifier will give optimum performance when the output common mode is set to half of the supply voltage (2.5 V
or 1.25 V at the OCM pin).
The ability of the LMH6882 to drive low-impedance loads while maintaining excellent OIP3 performance creates
an opportunity to greatly increase power gain and drive low-impedance filters. This gives the system designer
much needed flexibility in filter design. In many cases using a lower impedance filter will provide better
component values for the filter. Another benefit of low-impedance filters is that they are less likely to be
influenced by circuit board parasitic reactances such as pad capacitance or trace inductance. The output stage is
a low-impedance voltage amplifier, so voltage gain is constant over different load conditions. Power gain will
change based on load conditions. See Figure 46 for details on power gain with respect to different load
conditions. The graph was prepared for the 26 dB voltage gain. Other gain settings will behave similarly.
All measurements in this data sheet, unless specified otherwise, refer to voltage or power at the device output
pins. For instance, in an OIP3 measurement the power out will be equal to the output voltage at the device pins
squared, divided by the total load voltage. In back-terminated applications, power to the load would be 3 dB less.
Common back-terminated applications include driving a matched filter or driving a transmission line.
24
22
20
18
16
14
12
0
100
200
300
400
LOAD IMPEDANCE (ꢀ)
Figure 46. Power Gain as a Function of the Load
Printed circuit board (PCB) design is critical to high-frequency performance. In order to ensure output stability the
load-matching resistors should be placed as close to the amplifier output pins as possible. This allows the
matching resistors to mask the board parasitics from the amplifier output circuit. An example of this is shown in
Figure 50. Also note that the low-pass filters in Figure 48 and Figure 49 use center-tapped capacitors. Having
capacitors to ground provides a path for high-frequency, common-mode energy to dissipate. This is equally
valuable for the ADC, so there are also capacitors to ground on the ADC side of the filter. The LMH6882EVAL
evaluation board is available to serve a guide for system board layout. See also application note AN-2235
(SNOA869) for more details.
8.1.3 Interfacing to an ADC
The LMH6882 is an excellent choice for driving high-speed ADCs such as the ADC12D1800RF,
ADC12D1600RF or the ADS5400. The following sections will detail several elements of ADC system design,
including noise filters, AC, and DC coupling options.
22
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
Application Information (continued)
8.1.3.1 ADC Noise Filter
When connecting a broadband amplifier to an analog to digital converter it is nearly always necessary to filter the
signal before sampling it with the ADC. Figure 47 shows a schematic of a second order Butterworth filter and
Table 8 shows component values for some common IF frequencies. These filters, shown in Table 8, offer a good
compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on the
ADC14V155KDRB High IF Receiver reference design board. This filter topology is adequate for reducing aliasing
of broadband noise and will also provide rejection of harmonic distortion and many of the images that are
commonly created by mixers.
C1
R1
L1
L5
AMP V
OUT
-
ADC V
+
IN
C2
L2
ADC V
-
IN
AMP V
OUT
+
R2
ADC V
CM
Figure 47. Sample Filter
Table 8. Filter Component Values(1)
CENTER
FREQUENCY
BANDWIDTH R1, R2
L1, L2
C1, C2
C3
L5
R3, R4
75 MHz
40 MHz
60 MHz
75 MHz
100 MHz
90 Ω
90 Ω
90 Ω
90 Ω
390 nH
370 nH
300 nH
225 nH
10 pF
3 pF
22 pF
19 pF
15 pF
11 pF
220 nH
62 nH
54 nH
36 nH
100 Ω
100 Ω
100 Ω
100 Ω
150 MHz
180 MHz
250 MHz
2.7 pF
1.9 pF
(1) Resistor values are approximate, but have been reduced due to the internal 10 Ω of output resistance per pin.
8.1.3.2 AC Coupling to an ADC
AC coupling is an effective method for interfacing to an ADC for many communications systems. In many
applications this will be the best choice. The LMH6882 evaluation board is configured for AC coupling as shipped
from the factory. Coupling with capacitors is usually the most cost-effective method. Transformers can provide
both AC coupling and impedance transformation as well as single-ended-to-differential conversion. One of the
key benefits of AC coupling is that each stage of the system can be biased to the ideal DC operating point. Many
systems operate with lower overall power dissipation when DC bias currents are eliminated between stages.
8.1.3.3 DC Coupling to an ADC
The LMH6882 supports DC-coupled signals. In order to successfully implement a DC-coupled signal chain the
common-mode voltage requirements of every stage need to be met. This requires careful planning, and in some
cases there will be signal-level, gain or termination compromises required to meet the requirements of every part.
Shown in Figure 48 and Figure 49 is a method using resistors to change the 2.5-V common mode of the
amplifier output to a common mode compatible for the input of a low-input voltage ADC such as the
ADC12D1800RF. This DC level shift is achieved while maintaining an AC impedance match with the filter in
Figure 48 while in Figure 49 there is a small mismatch between the amplifier termination resistors and the ADC
input. Because there is no universal ADC input common mode, and some ADC’s have impedance controlled
input, each design will require a different resistor ratio. For high-speed data-conversion systems it is very
important to keep the physical distance between the amplifier and the ADC electrically short. When connections
between the amplifier and the ADC are electrically short, termination mismatches are not critical.
Copyright © 2012–2015, Texas Instruments Incorporated
23
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
LMH6882
50:
INPS
RIN = 50:
RT
ROUT
75:
LPF
N/C
N/C
INPD
INMD
50:
VCM = 2.5V
VCM =1.5V
ADC
300:
RL
50:
ROUT
75:
RT
INMS
+1.25V
OCM
50:
Parallel termination = 2* RT || RL = 150 || 300 =
100:
VCM voltage divider = 2.5V * RT/(ROUT + RT) =
2.5 * 75/125 = 1.5 V
+2.5V
Figure 48. DC-Coupled ADC Driver Example 1, High Input Impedance ADC
LMH6882
N/C
INSP
ROUT
100:
RT
OUTM
OUTP
INDP
INDM
INSM
100:
ADC
100:
V=1.25V
V =2.5V
100:
CM
ROUT
RT
100:
+1.25V
N/C
OCM
Figure 49. DC-Coupled ADC Driver Example 2, ADC12D1800RF with Terminated Input
8.1.4 Figure of Merit: Dynamic Range Figure
The dynamic range figure (DRF) as illustrated in Figure 4, is defined as the input third order intercept point (IIP3)
minus the noise figure (NF). The combination of noise figure and linearity gives a good proxy for the total
dynamic range of an amplifier. In some ways this figure is similar to the SFDR of an analog to digital converter.
In contrast to an ADC, however, an amplifier will not have a full-scale input to use as a reference point. With
amplifiers, there is no one point where signal amplitude hits “full scale”. Yet, there are real limitations to how
large a signal the amplifier can handle. Normally, the distortion products produced by the amplifier will determine
the upper limit to signal amplitude. The intermodulation intercept point is an imaginary point that gives a well-
understood figure of merit for the maximum signal an amplifier can handle. For low-amplitude signals the noise
figure gives a threshold of the lowest signal that the amplifier can reproduce. By combining the third-order input
intercepts point and the noise figure the DRF gives a very good indication of the available dynamic range offered.
24
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
Table 9. Compatible High-Speed Analog-to-Digital Converters
PRODUCT NUMBER
MAX SAMPLING RATE (MSPS)
RESOLUTION
CHANNELS
ADC12D1800RF
ADC12D1600RF
ADC12D1000RF
ADS5400
1800
1600
1000
1000
1800
1600
1000
1000
1500
105
12
12
12
12
12
12
12
10
10
12
12
12
14
14
14
14
14
16
16
8
DUAL
DUAL
DUAL
SINGLE
DUAL
ADC12D1800
ADC12D1600
ADC12D1000
ADC10D1000
ADC10D1500
ADC12C105
ADC12C170
ADC12V170
ADC14C080
ADC14C105
ADC14DS105
ADC14155
DUAL
DUAL
DUAL
DUAL
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
DUAL
170
170
80
105
105
155
SINGLE
SINGLE
SINGLE
DUAL
ADC14V155
ADC16V130
ADC16DV160
ADC08D500
ADC08500
155
130
160
500
DUAL
500
8
SINGLE
DUAL
ADC08D1000
ADC081000
ADC08D1500
ADC081500
ADC08(B)3000
ADC08100
1000
1000
1500
1500
3000
100
8
8
SINGLE
DUAL
8
8
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
SINGLE
8
8
ADCS9888
170
8
ADC08(B)200
ADC11C125
ADC11C170
200
8
125
11
11
170
Copyright © 2012–2015, Texas Instruments Incorporated
25
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
8.2 Typical Applications
8.2.1 LMH6882 Typical Application
+5V
100:
100:
FILTER
FILTER
0.01 PF
0.01 PF
49.9:
2.5V
RF
LMH6882
100:
ADS5400
49.9:
LO
7
OCM 1.25V
GAIN 0-6
SD
Figure 50. LMH6882 Typical Application
8.2.1.1 Design Requirements
Figure 50 shows a design example for an IF amplifier in a typical direct-IF receiver application and LMH6881
meets these requirements.
Table 10. Example Design Requirement for an IF Receiver Application
SPECIFICATION
EXAMPLE DESIGN REQUIREMENT
Supply Voltage and Current
4.75V to 5.25V, with a minimum 150-mA supply current
DC coupled Single-ended or Differential with 100Ω input differential
Input structure and Impedance
impedance
Output control
DC coupled with output common mode control capability
RF input frequency range
Voltage Gain Range
DC to 250MHz
26dB to 6dB
OIP3 in RF input frequency range for Pout = 4dBm/tone with
> 38 dBm at 200MHz for Max Gain
RL = 200Ω
Noise Figure
< 12dB at Max Gain across RF input frequency
Parallel control as well as SPI control
Attenuation Control
8.2.1.2 Detailed Design Procedure
The LMH6882 device can be included in most receiver applications by following these basic procedures:
•
Select an appropriate input drive circuitry to the LMH6882 by frequency planning the signal chain properly
such that the down-converted input signal is within the input frequency specifications of the device. Identify
whether dc-or ac-coupling is required or filtering is needed to optimize the system. Follow the guidelines
mentioned in Input Characteristics for interfacing the LMH6882 inputs.
•
Choose the right speed grade ADC that meets the signal bandwidth application. Based upon the noise
filtering and anti-aliasing requirement , determine the right order & type for the anti-aliasing filter. Follow the
guidelines mentioned in Output Characteristics and Interfacing to an ADC when interfacing the device to an
anti-aliasing filter.
•
•
•
Optimize the signal chain gain leading up to the ADC for best SNR and SFDR performance by employing the
device in automatic gain control (AGC) loop using serial or parallel digital interface.
While interfacing the digital inputs, verify the electrical and functional compatibility of the LMH6882 digital
input pins with the external micro-controller (µC).
Choose the appropriate power-supply architecture and supply bypass filtering devices to provide stable, low
noise supplies as mentioned in the Power Supply Recommendations.
26
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LMH6882
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ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
8.2.1.3 Application Curves
50
45
40
35
30
25
20
15
10
5
30
Voltage Gain
25
26 dB
16 dB
6 dB
20
0
0
50 100 150 200 250 300 350 400
6
8
10 12 14 16 18 20 22 24 26
VOLTAGE GAIN (dB)
FREQUENCY (MHz)
Figure 51. OIP3 vs Frequency
Figure 52. Noise Figure vs Voltage Gain
8.2.2 LMH6882 Used as Twisted Pair Cable Driver
V
CC
ꢀꢁ:
ꢀꢁ:
0.01 PF
49.9:
49.9:
CAT5
Rx
LMH6882
100:
100:
0.01 PF
5
1.25V
GAIN 0-3
SD
OCM
Figure 53. LMH6882 Used as Twisted Pair Cable Driver
8.2.2.1 Design Requirements
Table 11 shows a design example for LMH6882 used as cable driver for driving un-shielded twisted pair (UTP)
CAT-5 cables.
Table 11. Example Design Requirement for a Cable Driver
SPECIFICATION
Supply Voltage and Current
Input to Output Device Configuration
Input frequency range
EXAMPLE DESIGN REQUIREMENT
4.75 V to 5.25 V, with a minimum 150-mA supply current
Single-ended input to differential output
0.1 to 100 MHz
Voltage Gain Range
26-dB to 6-dB gain range
Output voltage swing
4 Vppdiff into a 200-Ω load at the output
300 to 400 feet
Cable length to be driven
8.2.2.2 Detailed Design Procedure
The LMH6882 device can be used as a cable driver to drive (UTP) CAT-5 cable by following these basic
procedures:
•
Select an appropriate input buffer or drive circuitry to the LMH6882 that provides pre-equalization in the
frequency range of interest that needs to be driven down the CAT-5 cable. The cable usually presents
attenuation of the signal at the receive end which is proportional to the length of the cable and the frequency
being transmitted. In some cases, use of the pre-equalization buffer is not possible which mandates the use
of a post-equalizer at the receive end to gain up the received signal.
Copyright © 2012–2015, Texas Instruments Incorporated
27
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
•
Determine the maximum output swing required to be transmitted in-order to receive the signal with good
signal integrity. When driving long cable lengths, there is a possibility of corruption of differential signals due
to common mode signals which requires the use of devices that offer good common mode rejection. Also,
care must be taken to match the source impedance with the characteristic impedance of the CAT-5 cable to
minimize signal reflections at higher frequencies. The LMH6882 offers low differential output resistance that
makes source matching of driven cable very convenient.
•
•
Verify the electrical and functional compatibility when interfacing LMH6882 digital input pins with the external
micro-controller (µC).
Also, use appropriate power-supply architecture and supply bypass filtering devices to provide stable, low
noise supplies as mentioned in the Power Supply Recommendations.
8.2.2.3 Application Curves
0
20
f = 100 MHz
Voltage Gain = 26dB
-10
-20
-30
-40
-50
-60
15
10
5
0
-5
1
10
100
1k
-25
-20
-15
-10
-5
0
FREQUENCY (MHz)
INPUT POWER (dBm)
Figure 55. Common Mode Rejection (Sdc21) vs Frequency
Figure 54. Output Power vs Input Power
28
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
9 Power Supply Recommendations
The LMH6882 was designed to be operated on 5-V power supplies. The voltage range for VCC is 4.75 V to 5.25
V. Power supply accuracy of 5% or better is advised. When operated on a board with high-speed digital signals it
is important to provide isolation between digital-signal noise and the analog input pins. The SP16160CH1RB
reference board provides an example of good board layout.
Each power supply pin should be decoupled with a low inductance, surface-mount ceramic capacitor of
approximately 10 nF as close to the device as possible. When vias are used to connect the bypass capacitors to
a ground plane the vias should be configured for minimal parasitic inductance. One method of reducing via
inductance is to use multiple vias. For broadband systems two capacitors per supply pin are advised.
To avoid undesirable signal transients the LMH6882 should not be powered on with large inputs signals present.
Careful planning of system power-on sequencing is especially important to avoid damage to ADC inputs when an
ADC is used in the application.
10 Layout
10.1 Layout Guidelines
It is very important to employ good high-speed layout techniques when dealing with devices having relatively
high gain bandwidth in excess of 1GHz to ensure stability and optimum performance. The LMH6882 evaluation
board provides a good reference for suggested layout techniques. The LMH6882 evaluation board was designed
for both good signal integrity and thermal dissipation using higher performance (Rogers) dielectric on the top
layer. The high performance dielectric provides well matched impedance and low loss to frequencies beyond
1GHz.
TI recommends that the LMH6882 board be multi-layered to improve thermal performance, grounding and
power-supply decoupling. The LMH6882 evaluation board is an 8-layered board with the supply sandwiched in-
between the GND layers for decoupling and having the stack up as Top layer - GND - GND - GND - Supply -
GND - GND - Bottom layer. All signal paths are routed on the top layer on the higher performance (Rogers)
dielectric, while the remainder signal layers are conventional FR4.
10.1.1 Uncontrolled Impedance Traces
It is important to pay careful attention while routing high-frequency signal traces on the PCB to maintain signal
integrity. A good board layout software package can simplify the trace thickness design to maintain controlled
characteristic impedances for high-frequency signals. Eliminating copper (the ground and power plane) from
underneath the input and output pins of the device also helps in minimizing parasitic capacitance affecting the
high frequency signals near the PCB and package junctions. The LMH6882 evaluation board has copper keep-
out areas under both the input and the output traces for this purpose. It is recommended that the application
board also follow these keep-out areas to avoid any performance degradation.
Copyright © 2012–2015, Texas Instruments Incorporated
29
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
10.2 Layout Example
Stitched GND vias
across signal traces
provide GND shielding
Supply bypass
Capacitor pads
Rout pads closer to
device output pins
Signal trace line widths chosen
based upon 50-Ω characteristic
impedance and Rogers RO4350
dielectric used on the top layer
Figure 56. Top Layer
30
Copyright © 2012–2015, Texas Instruments Incorporated
LMH6882
www.ti.com.cn
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
Layout Example (continued)
A GND layer cut out is beneath
the signal traces to reduce
reduce parasitic capacitance at
the input and outptut pins
Figure 57. GND Layer
10.3 Thermal Considerations
The LMH6882 is packaged in a thermally enhanced package. The exposed pad on the bottom of the package is
the primary means of removing heat from the package. It is recommended, but not necessary, that the exposed
pad be connected to the supply ground plane. In any case, the thermal dissipation of the device is largely
dependent on the attachment of the exposed pad to the system printed circuit board (PCB). The exposed pad
should be attached to as much copper on the PCB as possible, preferably external layers of copper.
版权 © 2012–2015, Texas Instruments Incorporated
31
LMH6882
ZHCSDC9D –AUGUST 2012–REVISED FEBRUARY 2015
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
《AN-2235 LMH6517/21/22 和其它高速 IF/RF 反馈放大器的电路板设计》，SNOA869
11.2 商标
串行外设接口 (SPI) is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6882SQ/NOPB
LMH6882SQE/NOPB
LMH6882SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
NJK
NJK
NJK
36
36
36
1000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
LMH6882
SN
SN
LMH6882
LMH6882
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6882SQ/NOPB
LMH6882SQE/NOPB
LMH6882SQX/NOPB
WQFN
WQFN
WQFN
NJK
NJK
NJK
36
36
36
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6882SQ/NOPB
LMH6882SQE/NOPB
LMH6882SQX/NOPB
WQFN
WQFN
WQFN
NJK
NJK
NJK
36
36
36
1000
250
356.0
208.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
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