LMK00334-Q1_技术文档

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

LMK00334-Q1 四路输出 PCIe 第 1 代至第 5 代时钟缓冲器和电平转换器

1 特性

3 说明

•

符合面向汽车应用的 AEC-Q100 标准：

– 器件温度等级 2：-40°C 至 105°C 环境运行温度

范围

– 器件 HBM ESD 分类等级 2

– 器件 CDM ESD 分类等级 C5

– 器件 MM ESD 分类等级 M2

3:1 输入多路复用器

LMK00334-Q1 器件是一款 4 路输出 HCSL 扇出缓

冲器，旨在用于高频、低抖动时钟、数据分配和电平转

换。它能够为 ADC、DAC、多千兆以太网、XAUI、光

纤通道、SATA/SAS、SONET/SDH、CPRI 和高频背

板分配参考时钟。

可从两个通用输入或一个晶振输入中选择输入时钟。所

选择的输入时钟被分配到由两个 HCSL 输出和一个

LVCMOS 输出组成的两个组。LVCMOS 输出具有

同步使能输入，在使能或禁用后可实现无短脉冲运行。

LMK00334-Q1 由一个 3.3V 内核电源和三个独立的

3.3V 或 2.5V 输出电源供电运行。

– 两个通用输入运行频率高达 400MHz，且接受

LVPECL、LVDS、CML、SSTL、HSTL、HCSL

或单端时钟

– 单个晶体输入可接受 10MHz 至 40MHz 的晶体

或单端时钟

LMK00334-Q1 具有高性能、多用途和高功效特性，因

此堪称替代固定输出缓冲器器件的理想选择，同时还能

增加系统中的时序余裕。

分为两组，每组具有两路差分输出

– HCSL 或 Hi-Z（可选）

– 100MHz 时 PCIe 第 3 代/第 4 代的附加 RMS 相

位抖动：

器件信息⁽¹⁾

•

30fs RMS（典型值）

器件型号

封装

封装尺寸（标称值）

•

高 PSRR：156.25MHz 时为 -72 dBc

通过同步使能输入提供 LVCMOS 输出

由引脚控制的配置

LMK00334-Q1

WQFN (32)

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_CC内核电源：3.3V ± 5%

三个独立的 V_CCO输出电源：3.3V、2.5V ± 5%

工业温度范围：-40°C 至 +105°C

32 引脚 WQFN (5 mm × 5 mm)

CLKout_EN

2 应用

•

信息娱乐系统：远程信息处理

信息娱乐系统控制单元：音响主机

ADAS：自主驾驶控制器

CLKout_EN

LMK00334-Q1 功能框图

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS760

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Propagation Delay and Output Skew..........................8

6.7 Typical Characteristics................................................9

7 Parameter Measurement Information.......................... 11

7.1 Differential Voltage Measurement Terminology.........11

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................14

9 Application and Implementation..................................15

9.1 Application Information............................................. 15

9.2 Typical Application.................................................... 15

10 Power Supply Recommendations..............................20

10.1 Current Consumption and Power Dissipation

Calculations.................................................................20

10.2 Power Supply Bypassing........................................ 22

11 Layout...........................................................................23

11.1 Layout Guidelines................................................... 23

11.2 Layout Example...................................................... 23

11.3 Thermal Management.............................................24

12 Device and Documentation Support..........................25

12.1 Documentation Support.......................................... 25

12.2 接收文档更新通知................................................... 25

12.3 支持资源..................................................................25

12.4 Trademarks.............................................................25

12.5 Electrostatic Discharge Caution..............................25

12.6 术语表..................................................................... 25

13 Mechanical, Packaging, and Orderable

Information.................................................................... 25

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (April 2018) to Revision A (January 2022)

Page

•

更改了数据表标题...............................................................................................................................................1

在数据表中添加了 PCIe 第 5.0 代.......................................................................................................................1

添加了指向应用部分的链接................................................................................................................................1

向说明部分添加了文本.......................................................................................................................................1

Added example board layout to Packaging Information section.......................................................................25

2

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

5 Pin Configuration and Functions

32

31

30

29

28

27

26

25

GND

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

GND

V

CCOA

CCOB

CLKoutA0

CLKoutA0*

CLKoutB0

CLKoutB0*

Top Down View

V

CCOA

CCOB

CLKoutA1

CLKoutA1*

GND

CLKoutB1

CLKoutB1*

GND

DAP

9

10

11

12

13

14

15

16

图 5-1. RTV Package 32-Pin WQFN Top View

表 5-1. Pin Functions⁽³⁾

I/O

DESCRIPTION

NAME

NO.

DAP

GND

Die Attach Pad. Connect to the PCB ground plane for heat dissipation.

Clock input selection pins ⁽²⁾

CLKin_SEL0

CLKin_SEL1

CLKin0

13

I

16

I

Clock input selection pins ⁽²⁾

14

I

Universal clock input 0 (differential/single-ended)

Universal clock input 1 (differential/single-ended)

Bank A and Bank B low active output buffer enable. ⁽²⁾

Differential clock output A0.

CLKin0*

15

CLKin1

27

I

CLKin1*

26

I

CLKout_EN

CLKoutA0

CLKoutA0*

CLKoutA1

CLKoutA1*

CLKoutB1

CLKoutB1*

CLKoutB0

CLKoutB0*

GND

9

I

3

O

GND

4

Differential clock output A0.

6

Differential clock output A1.

7

Differential clock output A1.

19

Differential clock output B1.

18

22

Differential clock output B1.

Differential clock output B0.

21

Differential clock output B0.

1, 8 17, 24

Ground

Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential

within the Supply Voltage range stated in the Absolute Maximum Ratings.

NC

25

—

OSCin

11

12

29

31

I

Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.

Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.

LVCMOS reference output. Enable output by pulling REFout_EN pin high.

OSCout

REFout

O

I

REFout_EN

REFout enable input. Enable signal is internally synchronized to selected clock input. ⁽²⁾

Submit Document Feedback

3

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

表 5-1. Pin Functions⁽³⁾(continued)

I/O

DESCRIPTION

NAME

NO.

Power supply for Core and Input Buffer blocks. The V_CCsupply operates from 3.3 V. Bypass

with a 0.1-µF, low-ESR capacitor placed very close to each V_CCpin.

V_CC

10, 28, 32

PWR

Power supply for Bank A Output buffers. V_CCOAoperates from 3.3 V or 2.5 V. The V_CCOA

pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close

to each V_CCOpin. ⁽¹⁾

V_CCOA

2, 5

Power supply for Bank B Output buffers. V_CCOBoperates from 3.3 V or 2.5 V. The V_CCOB

pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close

to each V_CCOpin. ⁽¹⁾

V_CCOB

20, 23

30

PWR

Power supply for REFout buffer. V_CCOCoperates from 3.3 V or 2.5 V. Bypass with a 0.1-µF,

low-ESR capacitor placed very close to each V_CCOpin. ⁽¹⁾

V_CCOC

(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCOin general when no distinction is needed, or when

the output supply can be inferred from the output bank/type.

(2) CMOS control input with internal pulldown resistor.

(3) Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if

connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration and Termination and Use of

Clock Drivers for output interface and termination techniques.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

MAX

3.6

UNIT

V

V_CC, V_CCO

Supply voltages

V_IN

T_L

Input voltage

(V_CC+ 0.3)

260

V

Lead temperature (solder 4 s)

Junction temperature

Storage temperature

°C

T_J

150

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Machine model (MM)

V_(ESD)

V

±150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX UNIT

T_A

Ambient temperature

Junction temperature

Core supply voltage

–40

25

105

125

°C

V

T_J

V_CC

3.15

3.3 – 5%

2.5 – 5%

3.3

3.45

3.3-V range

2.5-V range

3.3 3.3 + 5%

2.5 2.5 + 5%

V_CCO

Output supply voltage^{(1) (2)}

V

(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCOin general when no distinction is needed, or when

the output supply can be inferred from the output bank/type.

(2) V_CCOfor any output bank should be less than or equal to V_CC(V_CCO≤ V_CC).

6.4 Thermal Information

LMK00334-Q1 ⁽²⁾

THERMAL METRIC⁽¹⁾

RTV (WQFN)

UNIT

32 PINS

38.1

7.2

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

12

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

11.9

4.5

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Specification assumes 5 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board.

These vias play a key role in improving the thermal performance of the package. TI recommends using the maximum number of vias in

the board layout.

6.5 Electrical Characteristics

Unless otherwise specified: V_CC= 3.3 V ± 5%, V_CCO= 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ T_A≤ 105°C, CLKin driven

differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at V_CC= 3.3 V, V_CCO= 3.3

V, T_A= 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical

values are not ensured. ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT CONSUMPTION ⁽¹⁾

CLKinX selected

8.5

10

10.5

13.5

58.5

5.5

mA

Core supply current, all outputs

disabled

ICC_CORE

OSCin selected

ICC_HCSL

ICC_CMOS

50

3.5

Additive output supply current,

HCSL banks enabled

Includes output bank bias and load currents

for both banks, R_T= 50 Ω on all outputs

ICCO_HCSL

ICCO_CMOS

65

81.5

mA

V_CCO= 3.3 V ±5%

200 MHz, C_L= 5 pF

9

7

10

8

mA

Additive output supply current,

LVCMOS output enabled

V_CCO= 2.5V ± 5%

Submit Document Feedback

5

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

Unless otherwise specified: V_CC= 3.3 V ± 5%, V_CCO= 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ T_A≤ 105°C, CLKin driven

differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at V_CC= 3.3 V, V_CCO= 3.3

V, T_A= 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical

values are not ensured. ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLY RIPPLE REJECTION (PSRR)

Ripple-induced phase spur level⁽²⁾

PSRR_HCSL

156.25 MHz

312.5 MHz

–72

–63

dBc

Differential HCSL Output

CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN)

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

1.6

V_CC

0.4

50

V

GND

V_IH= V_CC, internal pulldown resistor

V_IL= 0 V, internal pulldown resistor

μA

I_IL

–5

0.1

CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)

Functional up to 400 MHz

Output frequency range and timing specified

per output type (refer to LVCMOS output

specifications)

f_CLKin

Input frequency range⁽⁸⁾

DC

400 MHz

V_IHD

V_ILD

V_ID

Differential input high voltage

Differential input low voltage

Differential input voltage swing⁽³⁾

Vcc

V

CLKin driven differentially

GND

0.15

0.25

1.3

V_CC– 1.2

V_CC– 1.1

V_CC– 0.9

V_CC

V_ID= 150 mV

V_ID= 350 mV

V_ID= 800 mV

Differential input CMD common-

mode voltage

V_CMD

V

V_IH

Single-ended input high voltage

Single-ended input low voltage

Single-ended input voltage swing⁽⁸⁾

V

V_IL

GND

0.3

CLKinX driven single-ended (AC- or DC-

coupled), CLKinX* AC-coupled to GND or

externally biased within V_CMrange

V_{I_SE}

2

Vpp

Single-ended input CM common-

mode voltage

V_CM

0.25

V_CC– 1.2

V

f_CLKin0= 100 MHz

–84

–82

–71

–65

f_CLKin0= 200 MHz

f_CLKin0= 500 MHz

f_CLKin0= 1000 MHz

f_OFFSET> 50 kHz,

P_CLKinX= 0 dBm

ISO_MUX

Mux isolation, CLKin0 to CLKin1

dBc

CRYSTAL INTERFACE (OSCin, OSCout)

F_CLK

F_XTAL

C_IN

External clock frequency range⁽⁸⁾

OSCin driven single-ended, OSCout floating

250 MHz

40 MHz

pF

Fundamental mode crystal ESR ≤ 200 Ω (10

to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)⁽⁴⁾

Crystal frequency range

10

OSCin input capacitance

1

6

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

Unless otherwise specified: V_CC= 3.3 V ± 5%, V_CCO= 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ T_A≤ 105°C, CLKin driven

differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at V_CC= 3.3 V, V_CCO= 3.3

V, T_A= 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical

values are not ensured. ⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

f_CLKout

Output frequency range⁽⁸⁾

R_L= 50 Ω to GND, C_L≤ 5 pF

DC

400 MHz

Additive RMS phase jitter for PCIe

5.0

CLKin: 100 MHz,

slew rate ≥ 0.5 V/ns

Jitter_{ADD_PCle}

PCIe Gen 5 filter

0.015

0.03

ps

PCIe Gen 4,

PLL BW = 2–5 MHz,

CDR = 10 MHz

Additive RMS phase jitter for PCIe

4.0

CLKin: 100 MHz,

slew rate ≥ 1.8 V/ns

Jitter_{ADD_PCle}

PCIe Gen 3,

PLL BW = 2–5 MHz,

CDR = 10 MHz

Additive RMS phase jitter for PCIe

3.0

CLKin: 100 MHz,

slew rate ≥ 0.6 V/ns

Jitter_{ADD_PCle}

0.03

ps

Additive RMS jitter integration

bandwidth 12 MHz to 20 MHz⁽⁵⁾

V_CCO= 3.3 V,

R_T= 50 Ω to GND

CLKin: 100 MHz,

slew rate ≥ 3 V/ns

Jitter_ADD

77

fs

V_CCO= 3.3 V,

R_T= 50 Ω to GND

CLKin: 100 MHz,

slew rate ≥ 3 V/ns

Noise Floor

Noise floor f_OFFSET≥ 10 MHz^{(6) (7)}

–161.3

dBc/Hz

DUTY

V_OH

Duty cycle⁽⁸⁾

50% input clock duty cycle

45%

520

55%

920

150

Output high voltage

Output low voltage

Absolute crossing voltage⁽⁹⁾

810

0.5

mV

ps

T_A= 25°C, DC measurement,

R_T= 50 Ω to GND

V_OL

–150

V_CROSS

t_R

R_L= 50 Ω to GND, C_L≤ 5 pF

350

225

Output rise time 20% to 80%^{(9) (12)}250 MHz, uniform transmission line up to 10

in. with 50-Ω characteristic impedance, R_L=

400

t_F

Output fall time 80% to 20%^{(9) (12)}

50 Ω to GND, C_L≤ 5 pF

225

ps

LVCMOS OUTPUT (REFout)

f_CLKout

Output frequency range⁽⁸⁾

C_L≤ 5 pF

DC

250 MHz

fs

Additive RMS jitter integration

bandwidth 1 MHz to 20 MHz⁽⁵⁾

V_CCO= 3.3 V,

C_L≤ 5 pF

100 MHz, input slew

rate ≥ 3 V/ns

Jitter_ADD

95

V_CCO= 3.3 V,

C_L≤ 5 pF

100 MHz, input slew

rate ≥ 3 V/ns

Noise Floor

DUTY

Noise floor f_OFFSET≥ 10 MHz^{(6) (7)}

Duty cycle⁽⁸⁾

–159.3

dBc/Hz

50% input clock duty cycle

45%

55%

V_CCO

–

V_OH

Output high voltage

V

0.1

1-mA load

V_OL

I_OH

Output low voltage

0.1

V

Output high current (source)

V_CCO= 3.3 V

28

20

mA

V_CCO= 2.5 V

V_CCO= 3.3 V

V_CCO= 2.5 V

V_O= V_CCO/ 2

I_OL

Output low current (sink)

28

mA

20

t_R

t_F

Output rise time 20% to 80%⁽⁹⁾

Output fall time 80% to 20%⁽¹⁰⁾

250 MHz, uniform transmission line up to 10

in. with 50-Ω characteristic impedance, R_L=

50 Ω to GND, C_L≤ 5 pF

225

ps

225

t_EN

Output enable time⁽¹⁰⁾

Output disable time⁽¹⁰⁾

3

cycles

C_L≤ 5 pF

t_DIS

(1) See Power Supply Recommendations and Thermal Management for more information on current consumption and power dissipation

calculations.

(2) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output

when a single-tone sinusoidal signal (ripple) is injected onto the V_CCOsupply. Assuming no amplitude modulation effects and small

index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level

(PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10^{(PSRR / 20)}) / (π × f_CLK) ] × 1E12

(3) See Differential Voltage Measurement Terminology for definition of V_IDand V_ODvoltages.

(4) The ESR requirements stated must be met to ensure that the oscillator circuitry has no start-up issues. However, lower ESR values for

the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal

Interface for crystal drive level considerations.

Submit Document Feedback

7

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

(5) For the 100-MHz and 156.25-MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD

=

SQRT(J_OUT²- J_SOURCE²), where J_OUTis the total RMS jitter measured at the output driver and J_SOURCEis the RMS jitter of the

clock source applied to CLKin. For the 625-MHz clock input condition, Additive RMS Jitter is approximated using Method #2: J_ADD

=

SQRT(2 × 10^dBc/10) / (2 × π × f_CLK), where dBc is the phase noise power of the Output Noise Floor integrated from 12-kHz to 20-MHz

bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10 × log₁₀(20 MHz – 12 kHz).

(6) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(7) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common-mode noise rejection.

However, TI recommends using the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at

the device outputs.

(8) Specification is ensured by characterization and is not tested in production.

(9) AC timing parameters for HCSL or LVCMOS are dependent on output capacitive loading.

(10) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly,

Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The

REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.

(11) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while

operating at the same supply voltage and temperature conditions.

(12) Parameter is specified by design, not tested in production.

6.6 Propagation Delay and Output Skew

MIN

TYP

590

MAX UNIT

t_{PD_HCSL}Propagation delay CLKin-to-HCSL ⁽¹⁾

t_{PD_CMOS}Propagation delay CLKin-to-LVCMOS⁽¹⁾

R_T= 50 Ω to GND, C_L≤ 5 pF

V_CCO= 3.3 V

V_CCO= 2.5 V

ps

1475

1550

30

C_L≤ 5 pF

ps

t_SK(O)

Output skew^{(11) (9)}

Skew specified between any two CLKouts.

Load conditions are the same as

propagation delay specifications.

ps

t_SK(PP)

Part-to-part output skew^{(1) (2)}

80

(1) AC timing parameters for HCSL or LVCMOS are dependent on output capacitive loading.

(2) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while

operating at the same supply voltage and temperature conditions.

8

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

6.7 Typical Characteristics

Unless otherwise specified: V_CC= 3.3 V, V_CCO= 3.3 V, T_A= 25°C, CLKin driven differentially, input slew rate ≥ 3 V/ns.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

1.00

0.75

0.50

0.25

0.00

-0.25

-0.50

-0.75

-1.00

Vcco=3.3 V, AC coupled, 50ꢀ load

Vcco=2.5 V, AC coupled, 50ꢀ load

0

1

2

3

4

5

0

1

2

3

4

5

6

TIME (ns)

图 6-1. HCSL Output Swing at 250 MHz

TIME (ns)

图 6-2. LVCMOS Output Swing at 250 MHz

-140

-135

HCSL

LVCMOS

CLKin Source

HCSL

CLKin Source

-145

-150

-155

-160

-165

-170

-140

-145

-150

-155

-160

-165

0.5

1.0

Differential Input Slew Rate (V/ns)

F_clk= 100 MHz F_offset= 20 MHz

1.5

2.0

2.5

3.0

3.5

0.5

1.0

Differential Input Slew Rate (V/ns)

F_clk= 156.25 MHz F_offset= 20 MHz

1.5

2.0

2.5

3.0

3.5

图 6-3. Noise Floor vs. CLKin Slew Rate at 100 MHz

图 6-4. Noise Floor vs. CLKin Slew Rate at 156.25 MHz

500

400

HCSL

CLKin Source

HCSL

LVCMOS

CLKin Source

450

400

350

300

250

200

150

100

50

350

300

250

200

150

100

50

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Differential Input Slew Rate (V/ns)

F_clk= 156.25 MHz

Int. BW = 1 to 20 MHz

F_clk= 100 MHz

Int. BW = 1 to 20 MHz

图 6-6. RMS Jitter vs. CLKin Slew Rate at 156.25 MHz

图 6-5. RMS Jitter vs. CLKin Slew Rate at 100 MHz

Submit Document Feedback

9

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

6.7 Typical Characteristics (continued)

Unless otherwise specified: V_CC= 3.3 V, V_CCO= 3.3 V, T_A= 25°C, CLKin driven differentially, input slew rate ≥ 3 V/ns.

-50

-55

-60

-65

-70

-75

-80

-85

-90

-50

-55

-60

-65

-70

-75

-80

-85

-90

HCSL

.1

1

10

.1

1

10

Ripple Frequency (MHz)

F_clk= 312.5 MHz

Vccco Ripple = 100 mV_pp

F_clk= 156.25 MHz

Vccco Ripple = 100 mV_pp

图 6-8. PSRR vs. Ripple Frequency at 312.5 MHz

图 6-7. PSRR vs. Ripple Frequency at 156.25 MHz

850

750

650

550

450

350

250

1950

1850

1750

1650

1550

1450

1350

200

20 MHz Crystal

40 MHz Crystal

HCSL (0.35 ps/°C)

LVCMOS (2.2 ps/°C)

175

150

125

100

75

Right Y-axis plot

50

25

0

500 1k 1.5k 2k 2.5k 3k 3.5k 4k

R_LIM(ꢁ)

-50 -25

0

25

Temperature (°C)

图 6-9. Propagation Delay vs. Temperature

50

75 100

图 6-10. Crystal Power Dissipation vs. R_LIM

图 6-11. HCSL Phase Noise at 100 MHz

10

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

7 Parameter Measurement Information

7.1 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions, causing confusion

when reading data sheets or communicating with other engineers. This section will address the measurement

and description of a differential signal so that the reader will be able to understand and discern between the two

different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V_IDor V_ODdepending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting

signal with respect to the inverting signal. The symbol for this second measurement is V_SSand is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground; it only exists in reference to its

differential pair. V_SScan be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V_ODas described in the first description.

图 7-1 illustrates the two different definitions side-by-side for inputs and 图 7-2 illustrates the two different

definitions side-by-side for outputs. The V_ID(or V_OD) definition show the DC levels, V_IHand V_OL(or V_OHand

V_OL), that the noninverting and inverting signals toggle between with respect to ground. V_SSinput and output

definitions show that if the inverting signal is considered the voltage potential reference, the noninverting signal

voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the

peak-to-peak voltage of the differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

V

ID

Definition

V

Definition for Input

SS

Non-Inverting Clock

V

IH

V

SS

V

ID

CM

V

IL

Inverting Clock

V

= | V œ V

IH IL

|

V

SS

= 2·V

ID

GND

图 7-1. Two Different Definitions for Differential Input Signals

V

Definition

V

Definition for Output

SS

OD

Non-Inverting Clock

V

OH

V

OS

SS

OD

V

OL

Inverting Clock

= | V - V

V

OD

|

V

SS

= 2·V

OD

OH OL

GND

图 7-2. Two Different Definitions for Differential Output Signals

Refer to Common Data Transmission Parameters and their Definitions (SNLA036) for more information.

Submit Document Feedback

11

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

8 Detailed Description

8.1 Overview

The LMK00334-Q1 is a 4-output HCSL clock fanout buffer with low additive jitter that can operate up to 400

MHz. It features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of two HCSL outputs,

one LVCMOS output, and three independent output buffer supplies. The input selection and output buffer modes

are controlled through pin strapping. The device is offered in a 32-pin WQFN package and leverages much of

the high-speed, low-noise circuit design employed in the LMK04800 family of clock conditioners.

8.2 Functional Block Diagram

CLKout_EN

8.3 Feature Description

8.3.1 Crystal Power Dissipation vs. R_LIM

For 图 6-10, the following applies:

•

The typical RMS jitter values in the plots show the total output RMS jitter (J_OUT) for each output buffer type

and the source clock RMS jitter (J_SOURCE). From these values, the Additive RMS Jitter can be calculated as:

J_ADD= SQRT(J_OUT²– J_SOURCE²).

•

20-MHz crystal characteristics: Abracon ABL series, AT cut, C_L= 18 pF, C₀= 4.4 pF measured (7 pF

maximum), ESR = 8.5 Ω measured (40 Ω maximum), and Drive Level = 1 mW maximum (100 µW typical).

40-MHz crystal characteristics: Abracon ABLS2 series, AT cut, C_L= 18 pF, C₀= 5 pF measured (7 pF

maximum), ESR = 5 Ω measured (40 Ω maximum), and Drive Level = 1 mW maximum (100 µW typical).

12

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

8.3.2 Clock Inputs

The input clock can be selected from CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin. Clock input selection is

controlled using the CLKin_SEL[1:0] inputs as shown in 表 8-1. Refer to Driving the Clock Inputs for clock input

requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected,

the crystal oscillator circuit will start up and its clock will be distributed to all outputs. Refer to Crystal Interface

for more information. Alternatively, OSCin may be driven by a single-ended clock (up to 250 MHz) instead of a

crystal.

表 8-1. Input Selection

CLKin_SEL1

CLKin_SEL0

SELECTED INPUT

CLKin0, CLKin0*

CLKin1, CLKin1*

OSCin

0

1

0

1

X

表 8-2 shows the output logic state vs. input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected.

When OSCin is selected, the output state will be an inverted copy of the OSCin input state.

表 8-2. CLKin Input vs. Output States

STATE OF

SELECTED CLKin

ENABLED OUTPUTS

CLKinX and CLKinX* inputs floating

CLKinX and CLKinX* inputs shorted together

CLKin logic low

Logic low

Logic high

CLKin logic high

8.3.3 Clock Outputs

The HCSL output buffer for both Bank A and B outputs are can be disabled to Hi-Z using the CLKout_EN [1:0]

as shown in 表 8-3. For applications where all differential outputs are not needed, any unused output pin should

be left floating with a minimum copper length (see note below) to minimize capacitance and potential coupling

and reduce power consumption. If all differential outputs are not used, TI recommends disabling (Hi-Z) the banks

to reduce power. Refer to Termination and Use of Clock Drivers for more information on output interface and

termination techniques.

备注

For best soldering practices, the minimum trace length for any unused pin should extend to include

the pin solder mask. This way during reflow, the solder has the same copper area as connected pins.

This allows for good, uniform fillet solder joints helping to keep the IC level during reflow.

表 8-3. Differential Output Buffer Type Selection

CLKoutX BUFFER TYPE

CLKout_EN

(BANK A AND B)

0

1

HCSL

Disabled (Hi-Z)

Submit Document Feedback

13

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

8.3.3.1 Reference Output

The reference output (REFout) provides a LVCMOS copy of the selected input clock. The LVCMOS output

high level is referenced to the V_CCOvoltage. REFout can be enabled or disabled using the enable input pin,

REFout_EN, as shown in 表 8-4.

表 8-4. Reference Output Enable

REFout_EN

REFout STATE

Disabled (Hi-Z)

Enabled

0

1

The REFout_EN input is internally synchronized with the selected input clock by the SYNC block. This

synchronizing function prevents glitches and runt pulses from occurring on the REFout clock when enabled

or disabled. REFout will be enabled within three cycles (t_EN) of the input clock after REFout_EN is toggled high.

REFout will be disabled within three cycles (t_DIS) of the input clock after REFout_EN is toggled low.

When REFout is disabled, the use of a resistive loading can be used to set the output to a predetermined level.

For example, if REFout is configured with a 1-kΩ load to ground, then the output will be pulled to low when

disabled.

8.4 Device Functional Modes

8.4.1 V_CCand V_CCOPower Supplies

The LMK00334-Q1 has separate 3.3-V core supplies (V_CC) and three independent 3.3-V or 2.5-V output power

supplies (V_CCOA, V_CCOB, V_CCOC). Output supply operation at 2.5 V enables lower power consumption and

output-level compatibility with 2.5-V receiver devices. The output levels for HCSL are relatively constant over

the specified V_CCOrange. Refer to Power Supply Recommendations for additional supply related considerations,

such as power dissipation, power supply bypassing, and power supply ripple rejection (PSRR).

备注

Take care to ensure the V_CCOvoltages do not exceed the V_CCvoltage to prevent turning-on the

internal ESD protection circuitry.

14

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

9 Application and Implementation

备注

以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

A common automotive PCIe application, such as ADAS (Advanced Driver Assistance Systems), requires several

clocks and timing sources to drive the building blocks of the system. In a common ADAS system, the clock is

distributed to an SoC, PCIe Switch, WiFi Controller, and Gigabit Ethernet to transmit high-speed video data from

the IP-Based Cameras on the vehicle. The LMK00334-Q1 provides an automotive qualified solution that saves

cost and space. When transmitting high-speed video data, the additive jitter of the buffer clock may noticeably

impact performance. In order to optimize signal speed and cable length, system designs must account for this

additive jitter. The LMK00334-Q1 is an ultra-low-jitter PCIe clock buffer suitable for current and future automotive

PCIe applications.

9.2 Typical Application

图 9-1. Example Automotive Application

Submit Document Feedback

15

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

9.2.1 Design Requirements

9.2.1.1 Driving the Clock Inputs

The LMK00334-Q1 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept DC-

coupled, 3.3-V or 2.5-V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet

the input requirements specified in Electrical Characteristics. The device can accept a wide range of signals due

to its wide input common-mode voltage range (V_CM) and input voltage swing (V_ID) / dynamic range. For 50%

duty cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the

V_CMrange. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques.

To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have high slew

rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.

For this reason, a differential signal input is recommended over single-ended because it typically provides higher

slew rate and common-mode rejection. Refer to the Noise Floor vs. CLKin Slew Rate and RMS Jitter vs. CLKin

Slew Rate plots in Typical Characteristics.

While TI recommends driving the CLKin/CLKin* pair with a differential signal input, it is possible to drive it with

a single-ended clock provided it conforms to the single-ended input specifications for CLKin pins listed in the

Electrical Characteristics. For large single-ended input signals, such as 3.3-V or 2.5-V LVCMOS, a 50-Ω load

resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line

termination to minimize reflections. Again, the single-ended input slew rate should be as high as possible to

minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V, so the input can

be AC coupled as shown in 图 9-2. The output impedance of the LVCMOS driver plus Rs should be close to 50

Ω to match the characteristic impedance of the transmission line and load termination.

0.1 mF

R_S

50W Trace

CMOS

Driver

LMK

Input

0.1 mF

图 9-2. Single-Ended LVCMOS Input, AC Coupling

A single-ended clock may also be DC-coupled to CLKinX as shown in 图 9-3. A 50-Ω load resistor should be

placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing

of the driver (V_O,PP/ 2) drives CLKinX, CLKinX* should be externally biased to the midpoint voltage of the

attenuated input swing ((V_O,PP/ 2) × 0.5). The external bias voltage should be within the specified input common

voltage (V_CM) range. This can be achieved using external biasing resistors in the kΩ range (R_B1and R_B2) or

another low-noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point

where the input slew rate is the highest.

V_O,PP

Rs

V_O,PP/2

V_CC

50W Trace

CMOS

Driver

50W

LMK

Input

V_BB~ (V_O,PP/2) x 0.5

R_B1

V_CC

R_B2

0.1 mF

图 9-3. Single-Ended LVCMOS Input, DC Coupling With Common-Mode Biasing

16

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external

clock as shown in 图 9-4. The input clock should be AC coupled to the OSCin pin, which has an internally-

generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative

input to multiplex an external clock, TI recommends using either universal input (CLKinX) because it offers

higher operating frequency, better common-mode and power supply noise rejection, and greater performance

over supply voltage and temperature variations.

0.1 mF

R_S

50W Trace

CMOS

Driver

OSCin

OSCout

图 9-4. Driving OSCin With a Single-Ended Input

9.2.1.2 Crystal Interface

The LMK00334-Q1 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal.

The crystal interface is shown in 图 9-5.

C₁

OSCin

XTAL

R_LIM

OSCout

C₂

图 9-5. Crystal Interface

The load capacitance (C_L) is specific to the crystal, but usually on the order of 18 to 20 pF. While C_Lis specified

for the crystal, the OSCin input capacitance (C_IN= 1 pF typical) of the device and PCB stray capacitance

(C_STRAYis approximately around 1 to 3 pF) can affect the discrete load capacitor values, C₁and C₂.

For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:

C_L= (C₁× C₂) / (C₁+ C₂) + C_IN+ C_STRAY

Typically, C₁= C₂for optimum symmetry, so 方程式 1 can be rewritten in terms of C₁only:

C_L= C₁²/ (2 × C₁) + C_IN+ C_STRAY

(1)

(2)

(3)

Finally, solve for C₁:

C₁= (C_L– C_IN– C_STRAY) × 2

Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the

crystal, but it does not specify crystal power dissipation. The designer must ensure the crystal power dissipation

Submit Document Feedback

17

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can

cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level

necessary to start up and maintain steady-state operation.

The power dissipated in the crystal, P_XTAL, can be computed by:

P_XTAL= I_RMS²× R_ESR× (1 + C₀/C_L)²

(4)

where

•

I_RMSis the RMS current through the crystal.

R_ESRis the maximum equivalent series resistance specified for the crystal

C_Lis the load capacitance specified for the crystal

C₀is the minimum shunt capacitance specified for the crystal

I_RMScan be measured using a current probe (Tektronix CT-6 or equivalent, for example) placed on the leg of the

crystal connected to OSCout with the oscillation circuit active.

As shown in 图 9-5, an external resistor, R_LIM, can be used to limit the crystal drive level, if necessary. If the

power dissipated in the selected crystal is higher than the drive level specified for the crystal with R_LIMshorted,

then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the

crystal is less than the drive level with R_LIMshorted, then a zero value for R_LIMcan be used. As a starting point, a

suggested value for R_LIMis 1.5 kΩ.

9.2.2 Detailed Design Procedure

9.2.2.1 Termination and Use of Clock Drivers

When terminating clock drivers, keep these guidelines in mind for optimum phase noise and jitter performance:

•

Transmission line theory should be followed for good impedance matching to prevent reflections.

Clock drivers should be presented with the proper loads.

– HCSL drivers are switched current outputs and require a DC path to ground through 50-Ω termination.

Receivers should be presented with a signal biased to their specified DC bias level (common-mode voltage)

for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage

level; in this case, the signal should normally be AC coupled.

•

9.2.2.2 Termination for DC-Coupled Differential Operation

For DC-coupled operation of an HCSL driver, terminate with 50 Ω to ground near the driver output as shown

in 图 9-6. Series resistors, Rs, may be used to limit overshoot due to the fast transient current. Because HCSL

drivers require a DC path to ground, AC coupling is not allowed between the output drivers and the 50-Ω

termination resistors.

Rs

CLKoutX

HCSL

Driver

HCSL

Receiver

50W Traces

Rs

CLKoutX*

图 9-6. HCSL Operation, DC Coupling

18

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

9.2.2.3 Termination for AC-Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common-mode voltage) when driving different receiver

standards. Because AC-coupling prevents the driver from providing a DC bias voltage at the receiver, it is

important to ensure the receiver is biased to its ideal DC level.

9.2.3 Application Curve

图 9-7. HCSL Phase Noise at 100 MHz

Submit Document Feedback

19

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

10 Power Supply Recommendations

10.1 Current Consumption and Power Dissipation Calculations

The current consumption values specified in Electrical Characteristics can be used to calculate the total power

dissipation and IC power dissipation for any device configuration. The total V_CCcore supply current (I_{CC_TOTAL}

)

can be calculated using 方程式 5:

I_{CC_TOTAL}= I_{CC_CORE}+ I_{CC_BANKS}+ I_{CC_CMOS}

(5)

where

•

I_{CC_CORE}is the V_CCcurrent for core logic and input blocks and depends on selected input (CLKinX or OSCin).

I_{CC_HCSL}is the V_CCcurrent for Banks A and B

I_{CC_CMOS}is the V_CCcurrent for the LVCMOS output (or 0 mA if REFout is disabled).

Because the output supplies (V_CCOA, V_CCOB, V_CCOC) can be powered from three independent voltages, the

respective output supply currents (I_{CCO_BANK_A}, I_{CCO_BANK_B}, and I_{CCO_CMOS}) should be calculated separately.

I_{CCO_BANK}for either Bank A or B may be taken as 50% of the corresponding output supply current specified for

two banks (I_{CCO_HCSL}) provided the output loading matches the specified conditions. Otherwise, I_{CCO_BANK}

should be calculated per bank as shown in 方程式 6:

I_{CCO_BANK}= I_{BANK_BIAS}+ (N × I_{OUT_LOAD}

)

(6)

where

•

I_{BANK_BIAS}is the output bank bias current (fixed value).

I_{OUT_LOAD}is the DC load current per loaded output pair.

N is the number of loaded output pairs (N = 0 to 2).

表 10-1 shows the typical I_{BANK_BIAS}values and I_{OUT_LOAD}expressions for HCSL.

表 10-1. Typical Output Bank Bias and Load Currents

CURRENT PARAMETER

HCSL

I_{BANK_BIAS}

2.4 mA

V_OH/R_T

I_{OUT_LOAD}

Once the current consumption is known for each supply, the total power dissipation (P_TOTAL) can be calculated

by 方程式 7:

P_TOTAL= (V_CC× I_{CC_TOTAL}) + (V_CCOA× I_{CCO_BANK}) + (V_CCOB× I_{CCO_BANK}) + (V_CCOC× I_{CCO_CMOS}

)

(7)

If the device is configured with HCSL outputs, then it is also necessary to calculate the power dissipated in any

termination resistors (P_{RT_HCSL}). The external power dissipation values can be calculated by 方程式 8:

P_{RT_HCSL}(per HCSL pair) = V_OH²/ R_T

(8)

Finally, the IC power dissipation (P_DEVICE) can be computed by subtracting the external power dissipation values

from P_TOTALas shown in 方程式 9:

P_DEVICE= P_TOTAL– N × P_{RT_HCSL}

(9)

where

•

N is the number of HCSL output pairs with termination resistors to GND.

20

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

10.1.1 Power Dissipation Example: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power

dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical

Characteristics are used:

•

Max V_CC= V_CCO= 3.465 V. Max I_CCand I_CCOvalues.

CLKin0/CLKin0* input is selected.

Banks A and B are enabled, and all outputs are terminated with 50 Ω to GND.

REFout is enabled with 5-pF load.

T_A=105°C

Using the power calculations from the previous section and maximum supply current specifications, the user can

compute P_TOTALand P_DEVICE

.

•

From 方程式 5: I_{CC_TOTAL}= 10.5 mA + 58.5 mA + 5.5 mA = 74.5 mA

From I_{CCO_HCSL}max spec: I_{CCO_BANK}= 50% of I_{CCO_HCSL}= 40.75 mA

From 方程式 7: P_TOTAL= (3.465 V × 74.5 mA) + (3.465 V × 40.75 mA) + (3.465 V × 40.75 mA) + (3.465 V ×

10 mA) = 575.2 mW

•

From 方程式 8: P_{RT_HCSL}= (0.92 V)²/ 50 Ω = 16.9 mW (per output pair)

From 方程式 9: P_DEVICE= 575.2 mW – (4 × 16.9 mW) = 510.4 mW

In this worst-case example, the IC device will dissipate about 510.4 mW or 88.7% of the total power (575.2 mW),

while the remaining 11.3% will be dissipated in the termination resistors (64.8 mW for 4 pairs). Based on R_θJAof

38.1°C/W, the estimate die junction temperature would be about 19.4°C above ambient, or 104.4°C when T_A=

85°C.

Submit Document Feedback

21

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

10.2 Power Supply Bypassing

The V_CCand V_CCOpower supplies should have a high-frequency bypass capacitor, such as 0.1 µF or 0.01

µF, placed very close to each supply pin. 1-µF to 10-µF decoupling capacitors should also be placed nearby

the device between the supply and ground planes. All bypass and decoupling capacitors should have short

connections to the supply and ground plane through a short trace or via to minimize series inductance.

10.2.1 Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies,

digital ASICs or FPGAs, and so forth. While power supply bypassing will help filter out some of this noise, it

is important to understand the effect of power supply ripple on the device performance. When a single-tone

sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00334-Q1, it can

produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the

single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level

relative to the carrier (measured in dBc).

For the LMK00334-Q1, power supply ripple rejection, or PSRR, was measured as the single-sideband phase

spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the V_CCOsupply. The

PSRR test setup is shown in 图 10-1.

Ripple

Source

Power

Supplies

Bias-Tee

Vcc

Vcco

OUT+

IN+

IN-

Clock

Source

Limiting

Amp

IC

OUT-

DUT Board

OUT

Phase Noise

Analyzer

Scope

Measure 100 mV

Measure single

sideband phase spur

power in dBc

PP

ripple on Vcco at IC

图 10-1. PSRR Test Setup

A signal generator was used to inject a sinusoidal signal onto the V_CCOsupply of the DUT board, and the

peak-to-peak ripple amplitude was measured at the V_CCOpins of the device. A limiting amplifier was used to

remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the

phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and

312.5 MHz under the following power supply ripple conditions:

•

Ripple amplitude: 100 mVpp on V_CCO= 2.5 V

Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ)

can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

DJ (ps pk-pk) = [(2 × 10^{(PSRR / 20)}) / (π × f_CLK)] × 10¹²

(10)

The PSRR vs. Ripple Frequency plots in Typical Characteristics show the ripple-induced phase spur levels at

156.25 MHz and 312.5 MHz. The LMK00334-Q1 exhibits very good and well-behaved PSRR characteristics

across the ripple frequency range. The phase spur levels for HCSL are below –72 dBc at 156.25 MHz and below

–63 dBc at 312.5 MHz. Using 方程式 10, these phase spur levels translate to Deterministic Jitter values of 1.02

ps pk-pk at 156.25 MHz and 1.44 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the

device improves for V_CCO= 3.3 V under the same ripple amplitude and frequency conditions.

22

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

For this device, consider the following guidelines:

•

For DC-coupled operation of an HCSL driver, terminate with 50 Ω to ground near the driver output as shown

in 图 11-1.

Keep the connections between the bypass capacitors and the power supply on the device as short as

possible.

•

Ground the other side of the capacitor using a low impedance connection to the ground plane.

If the capacitors are mounted on the back side, 0402 components can be employed. However, soldering to

the Thermal Dissipation Pad can be difficult.

•

For component side mounting, use 0201 body size capacitors to facilitate signal routing.

11.2 Layout Example

图 11-1. LMK00334-Q1 Layout Example

Submit Document Feedback

23

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

11.3 Thermal Management

Power dissipation in the LMK00334-Q1 device can be high enough to require attention to thermal management.

For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is,

as an estimate, T_A(ambient temperature) plus device power dissipation times R_θJAshould not exceed 125°C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent

electrical grounding to the printed-circuit board. To maximize the removal of heat from the package, a thermal

land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in 图 11-2. More information on soldering WQFN packages can

be obtained at: https://www.ti.com/packaging.

3.1 mm, min

0.2 mm, typ

1.27 mm, typ

图 11-2. Recommended Land and Via Pattern

To minimize junction temperature, TI recommends building a simple heat sink into the PCB (if the ground plane

layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of

the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not

have conformal coating (if possible), which could provide thermal insulation. The vias shown in 图 11-2 should

connect these top and bottom copper layers and to the ground layer. These vias act as heat pipes to carry the

thermal energy away from the device side of the board to where it can be more effectively dissipated.

24

Submit Document Feedback

Product Folder Links: LMK00334-Q1

LMK00334-Q1

ZHCSI14A – APRIL 2018 – REVISED JANUARY 2022

www.ti.com.cn

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documents, see the following:

•

Absolute Maximum Ratings for Soldering (SNOA549)

Common Data Transmission Parameters and their Definitions (SNLA036)

"How to Optimize Clock Distribution in PCIe Applications" on the Texas Instruments E2E community forum

LMK00338EVM User's Guide (SNAU155)

Semiconductor and IC Package Thermal Metrics (SPRA953).

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

25

Product Folder Links: LMK00334-Q1

PACKAGE OUTLINE

RTV0032A

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

A

B

PIN 1 INDEX AREA

5.15

4.85

0.8

0.7

C

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

SYMM

EXPOSED

THERMAL PAD

(0.1) TYP

9

16

8

17

SYMM

33

2X 3.5

3.1 0.1

28X 0.5

1

24

0.30

32X

0.18

32

25

PIN 1 ID

0.1

C A B

0.5

0.3

32X

0.05

4224386/B 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTV0032A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.1)

SYMM

SEE SOLDER MASK

DETAIL

32

25

32X (0.6)

1

24

32X (0.24)

28X (0.5)

(3.1)

33

SYMM

(4.8)

(1.3)

8

17

(R0.05) TYP

(

0.2) TYP

VIA

9

16

(1.3)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224386/B 04/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTV0032A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.775) TYP

25

32

32X (0.6)

1

32X (0.24)

28X (0.5)

24

(0.775) TYP

(4.8)

33

SYMM

(R0.05) TYP

4X (1.35)

17

8

9

16

4X (1.35)

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 33

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224386/B 04/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMK00334-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 4 路输出 PCIe® 第 1 代/第 2 代/第 3 代/第 4 代/第 5 代时钟缓冲器和电平转换器时钟 PC 转换器电平转换器
文件：	总31页 (文件大小：2040K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK00334-Q1 [TI]

相关型号：

LMK00334RTVR

LMK00334RTVRQ1

LMK00334RTVT

LMK00334RTVTQ1

LMK00334_14

LMK00338

LMK00338RTAR

LMK00338RTAT

LMK00338_14

LMK00725

LMK00725PW

LMK00725PWR