LMK00334_14 [TI]

Four-Output PCIe/Gen1/Gen2/Gen3 Clock Buffer/Level Translator;


型号：	LMK00334_14
厂家：	TEXAS INSTRUMENTS
描述：	Four-Output PCIe/Gen1/Gen2/Gen3 Clock Buffer/Level Translator PC
文件：	总25页 (文件大小：1406K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK00334

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SNAS635 –DECEMBER 2013

LMK00334 4-Output PCIe/Gen1/Gen2/Gen3 Clock Buffer/Level Translator

Check for Samples: LMK00334

FEATURES

APPLICATIONS

•

3:1 Input Multiplexer

•

Clock Distribution and Level Translation for

ADCs, DACs, Multi-Gigabit Ethernet, XAUI,

Fibre Channel, SATA/SAS, SONET/SDH, CPRI,

High-Frequency Backplanes

–

Two Universal Inputs Operate up to 400

MHz and Accept LVPECL, LVDS, CML,

SSTL, HSTL, HCSL, or Single-Ended Clocks

•

Switches, Routers, Line Cards, Timing Cards

Servers, Computing, PCI Express (PCIe 3.0)

Remote Radio Units and Baseband Units

–

One Crystal Input Accepts a 10 to 40 MHz

Crystal or Single-Ended Clock

•

Two Banks with 2 Differential Outputs Each

–

HCSL, or Hi-Z (Selectable)

DESCRIPTION

Additive RMS Phase Jitter for PCIe Gen3 at

100MHz:

The LMK00334 is a 4-output HCSL fanout buffer

intended for high-frequency, low-jitter clock/data

distribution and level translation. The input clock can

be selected from two universal inputs or one crystal

input. The selected input clock is distributed to two

banks of 2 HCSL outputs and one LVCMOS output.

The LVCMOS output has a synchronous enable input

for runt-pulse-free operation when enabled or

disabled. The LMK00334 operates from a 3.3 V core

–

30 fs RMS (typical)

•

High PSRR: -72 dBc at 156.25 MHz

LVCMOS Output with Synchronous Enable

Input

•

Pin-Controlled Configuration

V_CCCore Supply: 3.3 V ± 5%

supply and

supplies.

3 independent 3.3 V/2.5 V output

3 Independent V_CCOOutput Supplies: 3.3 V/2.5

V ± 5%

The LMK00334 provides high performance,

versatility, and power efficiency, making it ideal for

replacing fixed-output buffer devices while increasing

timing margin in the system.

•

Industrial Temperature Range: -40°C to +85°C

32-lead WQFN (5 mm x 5 mm)

FUNCTIONAL BLOCK DIAGRAM

CLKout_EN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMK00334

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Connection Diagram

GND

CCOA

CCOB

CLKoutA0

CLKoutA0*

CLKoutB0

CLKoutB0*

Top Down View

CCOA

CCOB

CLKoutA1

CLKoutA1*

GND

CLKoutB1

CLKoutB1*

GND

DAP

Figure 1. 32-Pin Package

RTV0032A Package

Application Diagram

Mainboard

MAC

100MHz

Reference

Oscillator

PCI Express®

PHY

E.g.: XIO1100

Fan Out Buffer

E.g.: LMK00334

PCI Express®

fan-out switch

E.g.: XIO3130

Connector

FPGA with

PCI Express®

Core

PCI Express®

device

Add-In Card

Data

Clock

Figure 2. Example PCI Express Application

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Pin Descriptions⁽¹⁾

Pin #

DAP

Pin Name(s)

DAP

Type

Description

GND

Die Attach Pad. Connect to the PCB ground plane for heat dissipation.

Ground

1, 8 17, 24

GND

Power supply for Bank A Output buffers. V_CCOAoperates from 3.3 V or 2.5

V. The V_CCOApins are internally tied together. Bypass with a 0.1 uF low-

ESR capacitor placed very close to each Vcco pin.

2, 5

V_CCOA

PWR

(2)

3, 4

6, 7

CLKoutA0, CLKoutA0*

CLKoutA1, CLKoutA1*

CLKout_EN

Differential clock output A0.

Differential clock output A1.

(3)

Bank A and Bank B low active output buffer enable.

Power supply for Core and Input Buffer blocks. The Vcc supply operates

from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to

each Vcc pin.

Vcc

PWR

Input for crystal. Can also be driven by a XO, TCXO, or other external

single-ended clock.

OSCin

Output for crystal. Leave OSCout floating if OSCin is driven by a single-

ended clock.

OSCout

(3)

13, 16

14, 15

18, 19

CLKin_SEL0, CLKin_SEL1

CLKin0, CLKin0*

Clock input selection pins

Universal clock input 0 (differential/single-ended)

Differential clock output B1.

CLKoutB1*, CLKoutB1

Power supply for Bank B Output buffers. V_CCOBoperates from 3.3 V or 2.5

V. The V_CCOBpins are internally tied together. Bypass with a 0.1 uF low-

ESR capacitor placed very close to each Vcco pin.

20, 23

21, 22

V_CCOB

CLKoutB0*, CLKoutB0

PWR

(2)

Differential clock output B0.

Not connected internally. Pin may be floated, grounded, or otherwise tied to

any potential within the Supply Voltage range stated in the Absolute

Maximum Ratings.

—

26, 27

CLKin1*, CLKin1

REFout

Universal clock input 1 (differential/single-ended)

LVCMOS reference output. Enable output by pulling REFout_EN pin high.

Power supply for REFout buffer. V_CCOCoperates from 3.3 V or 2.5 V.

Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco

pin.

V_CCOC

PWR

(2)

REFout enable input. Enable signal is internally synchronized to selected

REFout_EN

(3)

clock input.

(1) Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if

connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration and Termination and Use of

Clock Drivers for output interface and termination techniques.

(2) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCOin general when no distinction is needed, or when the

output supply can be inferred from the output bank/type.

(3) CMOS control input with internal pull-down resistor.

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Functional Description

The LMK00334 is a 4-output HCSL clock fanout buffer with low additive jitter that can operate up to 400 MHz. It

features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of 2 HCSL outputs, one

LVCMOS output, and 3 independent output buffer supplies. The input selection and output buffer modes are

controlled via pin strapping. The device is offered in a 32-pin WQFN package and leverages much of the high-

speed, low-noise circuit design employed in the LMK04800 family of clock conditioners.

V_CCand V_CCOPower Supplies

The LMK00334 has separate 3.3 V core supply (V_CC) and 3 independent 3.3 V/2.5 V output power supplies

(V_CCOA, V_CCOB, V_CCOC). Output supply operation at 2.5 V enables lower power consumption and output-level

compatibility with 2.5 V receiver devices. The output levels for HCSL are relatively constant over the specified

Vcco range. Refer to Power Supply and Thermal Considerations for additional supply related considerations,

such as power dissipation, power supply bypassing, and power supply ripple rejection (PSRR).

NOTE

Care should be taken to ensure the Vcco voltages do not exceed the Vcc voltage to

prevent turning-on the internal ESD protection circuitry.

Clock Inputs

The input clock can be selected from CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin. Clock input selection is

controlled using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer to Driving the Clock Inputs for clock input

requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected,

the crystal oscillator circuit will start-up and its clock will be distributed to all outputs. Refer to Crystal Interface for

more information. Alternatively, OSCin may be driven by a single-ended clock (up to 250 MHz) instead of a

crystal.

Table 1. Input Selection

CLKin_SEL1

CLKin_SEL0

Selected Input

CLKin0, CLKin0*

CLKin1, CLKin1*

OSCin

Table 2 shows the output logic state vs. input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected.

When OSCin is selected, the output state will be an inverted copy of the OSCin input state.

Table 2. CLKin Input vs. Output States

State of

Selected CLKin

Enabled Outputs

CLKinX and CLKinX* inputs floating

CLKinX and CLKinX* inputs shorted together

CLKin logic low

Logic low

Logic high

CLKin logic high

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Clock Outputs

The HCSL output buffer for both Bank A and B outputs are can be disabled to Hi-Z using the CLKout_EN [1:0] as

shown in Table 3. For applications where all differential outputs are not needed, any unused output pin should be

left floating with a minimum copper length (see note below) to minimize capacitance and potential coupling and

reduce power consumption. If all differential outputs are not used, it is recommended to disable (Hi-Z) the banks

to reduce power. Refer to Termination and Use of Clock Drivers for more information on output interface and

termination techniques.

NOTE

For best soldering practices, the minimum trace length for any unused pin should extend

to include the pin solder mask. This way during reflow, the solder has the same copper

area as connected pins. This allows for good, uniform fillet solder joints helping to keep

the IC level during reflow.

Table 3. Differential Output Buffer Type Selection

CLKoutX Buffer Type

CLKout_EN

(Bank A and B)

HCSL

Disabled (Hi-Z)

Reference Output

The reference output (REFout) provides a LVCMOS copy of the selected input clock. The LVCMOS output high

level is referenced to the Vcco voltage. REFout can be enabled or disabled using the enable input pin,

REFout_EN, as shown in Table 4.

Table 4. Reference Output Enable

REFout_EN

REFout State

Disabled (Hi-Z)

Enabled

The REFout_EN input is internally synchronized with the selected input clock by the SYNC block. This

synchronizing function prevents glitches and runt pulses from occurring on the REFout clock when enabled or

disabled. REFout will be enabled within 3 cycles (t_EN) of the input clock after REFout_EN is toggled high. REFout

will be disabled within 3 cycles (t_DIS) of the input clock after REFout_EN is toggled low.

When REFout is disabled, the use of a resistive loading can be used to set the output to a predetermined level.

For example, if REFout is configured with a 1 kΩ load to ground, then the output will be pulled to low when

disabled.

ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)

Parameter

Symbol

V_CC, V_CCO

V_IN

Ratings

-0.3 to 3.6

-0.3 to (V_CC+ 0.3)

-65 to +150

+260

Units

Supply Voltages

Input Voltage

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

T_STG

°C

T_L

T_J

+150

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see ELECTRICAL CHARACTERISTICS. The ensured specifications apply only to the test conditions listed.

(2) This device is a high-performance integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and

up to 750 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free

workstations.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

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RECOMMENDED OPERATING CONDITIONS

Parameter

Ambient Temperature Range

Junction Temperature

Symbol

Min

Typ

Max

Units

°C

T_A

-40

T_J

125

3.45

°C

Core Supply Voltage Range

V_CC

3.15

3.3

3.3 – 5%

2.5 – 5%

3.3

2.5

3.3 + 5%

2.5 + 5%

(1)(2)

Output Supply Voltage Range

V_CCO

(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCOin general when no distinction is needed, or when the

output supply can be inferred from the output bank/type.

(2) Vcco for any output bank should be less than or equal to Vcc (Vcco ≤ Vcc).

PACKAGE THERMAL RESISTANCE

Package

θ_JA

θ_{JC (DAP)}

(1)

32-Lead WQFN

38.1 °C/W

7.2 °C/W

(1) Specification assumes 5 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board.

These vias play a key role in improving the thermal performance of the package. It is recommended that the maximum number of vias

be used in the board layout.

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ELECTRICAL CHARACTERISTICS

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A≤ 85 °C, CLKin driven

differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A

(1)

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

SYMBOL

PARAMETER

CONDITIONS

Current Consumption⁽²⁾

CLKinX selected

MIN

TYP

MAX UNIT

8.5

10.5

Core Supply Current, All Outputs

Disabled

ICC_CORE

OSCin selected

13.5

58.5

5.5

ICC_HCSL

ICC_CMOS

3.5

Additive Output Supply Current,

HCSL Banks Enabled

Includes Output Bank Bias and Load Currents

ICCO_HCSL

ICCO_CMOS

81.5

for both banks, RT = 50 Ω on all outputs

Vcco = 3.3 V ±5%

200 MHz, C_L= 5 pF

Additive Output Supply Current,

LVCMOS Output Enabled

Vcco = 2.5V ± 5%

Power Supply Ripple Rejection (PSRR)

Ripple-Induced Phase Spur Level⁽³⁾

Differential HCSL Output

156.25 MHz

312.5 MHz

-72

-63

PSRR_HCSL

dBc

CMOS Control Inputs (CLKin_SELn, CLKout_TYPEn, REFout_EN)

High-Level Input Voltage

V_IH

V_IL

I_IH

1.6

Vcc

0.4

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

GND

V_IH= V_cc, Internal pull-down resistor

V_IL= 0 V, Internal pull-down resistor

μA

I_IL

-5

0.1

Clock Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)

Functional up to 400 MHz

Output frequency range and timing specified

per output type (refer to LVCMOS output

specifications)

f_CLKin

Input Frequency Range⁽⁴⁾

400

Vcc

1.3

MHz

V_IHD

V_ILD

V_ID

Differential Input High Voltage

Differential Input Low Voltage

Differential Input Voltage Swing⁽⁵⁾

CLKin driven differentially

GND

0.15

Vcc -

1.2

V_ID= 150 mV

V_ID= 350 mV

V_ID= 800 mV

0.25

Differential Input CMD Common

Mode Voltage

Vcc -

1.1

V_CMD

Vcc -

0.9

V_IH

V_IL

Single-Ended Input IH High Voltage

Single-Ended Input IL Low Voltage

Single-Ended Input Voltage Swing⁽⁴⁾

VCC

GND

0.3

CLKinX driven single-ended (AC or DC

coupled), CLKinX* AC coupled to GND or

externally biased within V_CMrange

V_{I_SE}

Vpp

Single-Ended Input CM Common

Mode Voltage

VCC -

1.2

V_CM

0.25

(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCOin general when no distinction is needed, or when the

output supply can be inferred from the output bank/type.

(2) See Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations.

(3) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output

when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index

modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as

follows: DJ (ps pk-pk) = [ (2 * 10(^PSRR/ 20)) / (π * f_CLK) ] * 1E12

(4) Specification is ensured by characterization and is not tested in production.

(5) See Differential Voltage Measurement Terminology for definition of V_IDand V_ODvoltages.

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A≤ 85 °C, CLKin driven

differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A

(1)

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

SYMBOL

PARAMETER

CONDITIONS

f_CLKin0= 100 MHz

MIN

TYP

-84

MAX UNIT

f_CLKin0= 200 MHz

f_CLKin0= 500 MHz

f_CLKin0= 1000 MHz

-82

-71

-65

f_OFFSET> 50 kHz,

P_CLKinX= 0 dBm

ISO_MUX

Mux Isolation, CLKin0 to CLKin1

dBc

Crystal Interface (OSCin, OSCout)

F_CLK

F_XTAL

C_IN

External Clock Frequency Range⁽⁶⁾

OSCin driven single-ended, OSCout floating

250

MHz

Fundamental mode crystal ESR ≤ 200 Ω (10

to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)⁽⁷⁾

Crystal Frequency Range

OSCin Input Capacitance

HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

Output Frequency Range⁽⁶⁾

R_L= 50 Ω to GND, C_L≤ 5 pF

f_CLKout

400

MHz

PCIe Gen 3, PLL BW

Additive RMS Phase Jitter for PCIe

3.0⁽⁶⁾

CLKin: 100 MHz,

Jitter_{ADD_PCle}

= 2–5 MHz, CDR = 10

MHz

0.03

0.15

Slew rate ≥ 0.6 V/ns

CLKin: 100 MHz,

Slew rate ≥ 3 V/ns

Additive RMS Jitter Integration

Bandwidth 1 MHz to 20 MHz⁽⁸⁾

Vcco = 3.3 V, RT = 50

Jitter_ADD

Ω to GND

CLKin: 156.25 MHz,

Slew rate ≥ 2.7 V/ns

CLKin: 100 MHz,

Slew rate ≥ 3 V/ns

-161.3

-156.3

Vcco = 3.3 V, RT = 50

Noise Floor

Noise Floor f_OFFSET≥ 10 MHz^(9)(10)

dBc/Hz

Ω to GND

CLKin: 156.25 MHz,

Slew rate ≥ 2.7 V/ns

DUTY

V_OH

Duty Cycle⁽⁶⁾

Output High Voltage

50% input clock duty cycle

520

810

0.5

920

T_A= 25 °C, DC Measurement, R_T= 50 Ω to

GND

-150

250

150

460

140

V_OL

Output Low Voltage

Absolute Crossing Voltage^(6)(11)

350

V_CROSS

ΔV_CROSS

R_L= 50 Ω to GND, C_L≤ 5 pF

(6)(11)

Total Variation of V_CROSS

Output Rise Time 20% to

80%^(11)(12)

Output Fall Time 80% to 20%^(11)(12)

250 MHz, Uniform transmission line up to 10

in. with 50-Ω characteristic impedance, RL =

50 Ω to GND, C_L≤ 5 pF

t_R

t_F

300

500

(6) Specification is ensured by characterization and is not tested in production.

(7) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for

the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal

Interface for crystal drive level considerations.

(8) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD= SQRT(J_OUT

- J_SOURCE²), where J_OUTis the total RMS jitter measured at the output driver and J_SOURCEis the RMS jitter of the clock source applied to

CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: J_ADD= SQRT(2*10^dBc/10) /

(2*π*f_CLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise

power can be calculated as: dBc = Noise Floor + 10*log₁₀(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz

using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer

to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in TYPICAL CHARACTERISTICS.

(9) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(10) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(11) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(12) Parameter is specified by design, not tested in production.

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A≤ 85 °C, CLKin driven

differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A

(1)

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

SYMBOL

PARAMETER

CONDITIONS

LVCMOS Output (REFout)

CL ≤ 5 pF

MIN

TYP

MAX UNIT

f_CLKout

Output Frequency Range⁽¹³⁾

250

MHz

Additive RMS Jitter Integration

Bandwidth 1 MHz to 20 MHz⁽¹⁴⁾

Vcco = 3.3 V, CL ≤ 5 100 MHz, Input Slew

Jitter_ADD

Vcco = 3.3 V, CL ≤ 5 100 MHz, Input Slew

pF rate ≥ 3 V/ns

rate ≥ 3 V/ns

Noise Floor Noise Floor f_OFFSET≥ 10 MHz^{(15) (16)}

-159.3

dBc/Hz

DUTY

V_OH

Duty Cycle⁽¹³⁾

50% input clock duty cycle

Vcco -

0.1

Output High Voltage

Output Low Voltage

1 mA load

V_OL

0.1

Vcco = 3.3 V

Vcco = 2.5 V

Vcco = 3.3 V

I_OH

Output High Current (Source)

Output Low Current (Sink)

Vo = Vcco / 2

Vcco = 2.5 V

I_OL

t_R

Output Rise Time 20% to 80%⁽¹⁷⁾

250 MHz, Uniform transmission line up to 10

in. with 50-Ω characteristic impedance, RL =

50 Ω to GND, CL ≤ 5 pF

225

400

(18)

t_F

Output Fall Time 80% to 20%^(19)(18)

Output Enable Time⁽¹⁹⁾

400

t_EN

t_DIS

cycles

C_L≤ 5 pF

Output Disable Time⁽¹⁹⁾

Propagation Delay and Output Skew

Propagation Delay CLKin-to-HCSL

t_{PD_HCSL}

t_{PD_CMOS}

R_T= 50 Ω to GND, C_L≤ 5 pF

295

590

885

(17)(18)

Vcco = 3.3 V

Vcco = 2.5 V

900

1475

1550

2300

2700

Propagation Delay CLKin-to-

LVCMOS^(17)(18)

CL ≤ 5 pF

1000

t_SK(O)

Output Skew^(20)(17)(13)

Skew specified between any two CLKouts.

Load conditions are the same as propagation

delay specifications.

t_SK(PP)

Part-to-Part Output Skew^(17)(18)(20)

120

(13) Specification is ensured by characterization and is not tested in production.

(14) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD= SQRT(J_OUT

- J_SOURCE²), where J_OUTis the total RMS jitter measured at the output driver and J_SOURCEis the RMS jitter of the clock source applied to

CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: J_ADD= SQRT(2*10^dBc/10) /

(2*π*f_CLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise

power can be calculated as: dBc = Noise Floor + 10*log₁₀(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz

using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer

to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in TYPICAL CHARACTERISTICS.

(15) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(16) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(17) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(18) Parameter is specified by design, not tested in production.

(19) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly,

Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The

REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.

(20) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while

operating at the same supply voltage and temperature conditions.

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MEASUREMENT DEFINITIONS

Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading datasheets or communicating with other engineers. This section will address the measurement and

description of a differential signal so that the reader will be able to understand and discern between the two

different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and non-inverting signal. The symbol for this first measurement is typically V_IDor V_ODdepending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal

with respect to the inverting signal. The symbol for this second measurement is V_SSand is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V_SScan be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V_ODas described in the first description.

Figure 3 illustrates the two different definitions side-by-side for inputs and Figure 4 illustrates the two different

definitions side-by-side for outputs. The V_ID(or V_OD) definition show the DC levels, V_IHand V_OL(or V_OHand V_OL),

that the non-inverting and inverting signals toggle between with respect to ground. V_SSinput and output

definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal

voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-

to-peak voltage of the differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

Definition

Definition for Input

Non-Inverting Clock

Inverting Clock

= | V ± V

= 2·V

GND

Figure 3. Two Different Definitions for Differential Input Signals

Definition

Definition for Output

Non-Inverting Clock

Inverting Clock

= | V - V

= 2·V

GND

Figure 4. Two Different Definitions for Differential Output Signals

Refer to Application Note AN-912 (literature number SNLA036), Common Data Transmission Parameters and

their Definitions, for more information.

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TYPICAL CHARACTERISTICS

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, T_A= 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns.

HCSL Output Swing @ 250 MHz

LVCMOS Output Swing @ 250 MHz

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

1.00

0.75

0.50

0.25

0.00

-0.25

-0.50

-0.75

-1.00

Vcco=3.3 V, AC coupled, 50ꢀꢀload

Vcco=2.5 V, AC coupled, 50ꢀꢀload

TIME (ns)

Figure 5.

Figure 6.

Noise Floor vs. CLKin Slew Rate @ 100 MHz

-140

Noise Floor vs. CLKin Slew Rate @ 156.25 MHz

-135

Fclk=100 MHz

HCSL

LVCMOS

CLKin Source

Fclk=156.25 MHz

Foffset=20 MHz

HCSL

CLKin Source

-140

-145

-150

-155

-160

-165

-145

-150

-155

-160

-165

-170

Foffset=20 MHz

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Figure 7.

Figure 8.

RMS Jitter vs. CLKin Slew Rate @ 100 MHz

400

RMS Jitter vs. CLKin Slew Rate @ 156.25 MHz

500

450

400

350

300

250

200

150

100

Fclk=156.25 MHz

Int. BW=1-20 MHz

Fclk=100 MHz

Int. BW=1-20 MHz

350

HCSL

LVCMOS

CLKin Source

HCSL

CLKin Source

300

250

200

150

100

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

DIFFERENTIAL INPUT SLEW RATE (V/ns)

Figure 9.

Figure 10.

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TYPICAL CHARACTERISTICS (continued)

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, T_A= 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns.

PSRR vs. Ripple Frequency @ 156.25 MHz

-50

PSRR vs. Ripple Frequency @ 312.5 MHz

-50

Fclk=156.25 MHz

Vcco Ripple=100 mVpp

Fclk=312.5 MHz

Vcco Ripple=100 mVpp

-55

-60

-65

-70

-75

-80

-85

-90

-55

-60

-65

-70

-75

-80

-85

-90

HCSL

RIPPLE FREQUENCY (MHz)

Figure 11.

Figure 12.

Propagation Delay vs. Temperature

1950

HCSL Phase Noise @ 100 MHz

850

HCSL (0.35 ps/°C)

1850

750

650

550

450

350

250

LVCMOS (2.2 ps/°C)

Right Y-axis plot

1750

1650

1550

1450

1350

-50 -25

75 100

TEMPERATURE (°C)

Figure 13.

Figure 14.

(1) The typical RMS jitter values in the plots show the total output RMS jitter (J_OUT) for each output buffer type and the

source clock RMS jitter (J_SOURCE). From these values, the Additive RMS Jitter can be calculated as: J_ADD

SQRT(J_OUT²- J_SOURCE²).

(2) 20 MHz crystal characteristics: Abracon ABL series, AT cut, C_L= 18 pF , C₀= 4.4 pF measured (7 pF max), ESR =

8.5 Ω measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).

(3) 40 MHz crystal characteristics: Abracon ABLS2 series, AT cut, C_L= 18 pF , C₀= 5 pF measured (7 pF max), ESR =

5 Ω measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).

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TYPICAL CHARACTERISTICS (continued)

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, T_A= 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns.

Crystal Power Dissipation vs. R_LIM

200

20 MHz Crystal

40 MHz Crystal

175

150

125

100

500 1k 1.5k 2k 2.5k 3k 3.5k 4k

(ꢁ)

LIM

Figure 15.

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APPLICATION INFORMATION

Driving the Clock Inputs

The LMK00334 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept DC-coupled

3.3V/2.5V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the input

requirements specified in ELECTRICAL CHARACTERISTICS. The device can accept a wide range of signals

due to its wide input common mode voltage range (V_CM) and input voltage swing (V_ID) / dynamic range. For 50%

duty cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the

V_CMrange. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques.

To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have high slew

rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.

For this reason, a differential signal input is recommended over single-ended because it typically provides higher

slew rate and common-mode-rejection. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin

Slew Rate” plots in TYPICAL CHARACTERISTICS.

While it is recommended to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive it

with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in

the ELECTRICAL CHARACTERISTICS. For large single-ended input signals, such as 3.3V or 2.5V LVCMOS, a

50 Ω load resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for

line termination to minimize reflections. Again, the single-ended input slew rate should be as high as possible to

minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V, so the input can

be AC coupled as shown in Figure 16. The output impedance of the LVCMOS driver plus Rs should be close to

50 Ω to match the characteristic impedance of the transmission line and load termination.

0.1 PF

50:ꢀTrace

CMOS

Driver

LMK

Input

0.1 PF

Figure 16. Single-Ended LVCMOS Input, AC Coupling

A single-ended clock may also be DC coupled to CLKinX as shown in Figure 17. A 50-Ω load resistor should be

placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of

the driver (V_O,PP/ 2) drives CLKinX, CLKinX* should be externally biased to the midpoint voltage of the

attenuated input swing ((V_O,PP/ 2) × 0.5). The external bias voltage should be within the specified input common

voltage (V_CM) range. This can be achieved using external biasing resistors in the kΩ range (R_B1and R_B2) or

another low-noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point

where the input slew rate is the highest.

V_O,PP

V_O,PP/2

50:ꢀTrace

CMOS

Driver

50:

LMK

Input

V_BB~ (V_O,PP/2) x 0.5

0.1 PF

Figure 17. Single-Ended LVCMOS Input, DC Coupling

with Common Mode Biasing

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If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external

clock as shown in Figure 18. The input clock should be AC coupled to the OSCin pin, which has an internally-

generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative

input to multiplex an external clock, it is recommended to use either universal input (CLKinX) since it offers

higher operating frequency, better common mode and power supply noise rejection, and greater performance

over supply voltage and temperature variations.

0.1 PF

50:ꢀTrace

OSCin

CMOS

Driver

OSCout

Figure 18. Driving OSCin with a Single-Ended Input

Crystal Interface

The LMK00334 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The

crystal interface is shown in Figure 19.

OSCin

XTAL

LIM

OSCout

Figure 19. Crystal Interface

The load capacitance (C_L) is specific to the crystal, but usually on the order of 18 - 20 pF. While C_Lis specified

for the crystal, the OSCin input capacitance (C_IN= 1 pF typical) of the device and PCB stray capacitance (C_STRAY

~ 1~3 pF) can affect the discrete load capacitor values, C₁and C₂.

For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:

C_L= (C₁* C₂) / (C₁+ C₂) + C_IN+ C_STRAY

(1)

(2)

(3)

Typically, C₁= C₂for optimum symmetry, so Equation 1 can be rewritten in terms of C₁only:

C_L= C₁²/ (2 * C₁) + C_IN+ C_STRAY

Finally, solve for C₁:

C₁= (C_L- C_IN- C_STRAY)*2

ELECTRICAL CHARACTERISTICS provides crystal interface specifications with conditions that ensure start-up

of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power

dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the

crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient

level necessary to start-up and maintain steady-state operation.

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The power dissipated in the crystal, P_XTAL, can be computed by:

P_XTAL= I_RMS²* R_ESR*(1 + C₀/C_L)²

where

•

I_RMSis the RMS current through the crystal.

R_ESRis the max. equivalent series resistance specified for the crystal

C_Lis the load capacitance specified for the crystal

C₀is the min. shunt capacitance specified for the crystal

(4)

I_RMScan be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal

connected to OSCout with the oscillation circuit active.

As shown in Figure 19, an external resistor, R_LIM, can be used to limit the crystal drive level, if necessary. If the

power dissipated in the selected crystal is higher than the drive level specified for the crystal with R_LIMshorted,

then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the

crystal is less than the drive level with R_LIMshorted, then a zero value for R_LIMcan be used. As a starting point, a

suggested value for R_LIMis 1.5 kΩ.

Termination and Use of Clock Drivers

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

•

Transmission line theory should be followed for good impedance matching to prevent reflections.

Clock drivers should be presented with the proper loads.

–

HCSL drivers are switched current outputs and require a DC path to ground via 50 Ω termination.

•

Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage)

for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage

level; in this case, the signal should normally be AC coupled.

Termination for DC Coupled Differential Operation

For DC coupled operation of an HCSL driver, terminate with 50 Ω to ground near the driver output as shown in

Figure 20. Series resistors, Rs, may be used to limit overshoot due to the fast transient current. Because HCSL

drivers require a DC path to ground, AC coupling is not allowed between the output drivers and the 50 Ω

termination resistors.

CLKoutX

HCSL

Driver

HCSL

Receiver

50:ꢀTraces

CLKoutX*

Figure 20. HCSL Operation, DC Coupling

Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver

standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver, it is important

to ensure the receiver is biased to its ideal DC level.

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Power Supply and Thermal Considerations

Current Consumption and Power Dissipation Calculations

The current consumption values specified in ELECTRICAL CHARACTERISTICS can be used to calculate the

total power dissipation and IC power dissipation for any device configuration. The total V_CCcore supply current

(I_{CC_TOTAL}) can be calculated using Equation 5:

I_{CC_TOTAL}= I_{CC_CORE}+ I_{CC_BANKS}+ I_{CC_CMOS}

where

•

I_{CC_CORE}is the V_CCcurrent for core logic and input blocks and depends on selected input (CLKinX or OSCin).

I_{CC_HCSL}is the V_CCcurrent for Banks A & B

I_{CC_CMOS}is the V_CCcurrent for the LVCMOS output (or 0 mA if REFout is disabled).

(5)

Since the output supplies (V_CCOA, V_CCOB, V_CCOC) can be powered from 3 independent voltages, the respective

output supply currents (I_{CCO_BANK_A}, I_{CCO_BANK_B}, and I_{CCO_CMOS}) should be calculated separately.

I_{CCO_BANK}for either Bank A or B may be taken as 50% of the corresponding output supply current specified for

two banks (I_{CCO_HCSL}) provided the output loading matches the specified conditions. Otherwise, I_{CCO_BANK}

should be calculated per bank as follows:

I_{CCO_BANK}= I_{BANK_BIAS}+ (N * I_{OUT_LOAD}

)

where

•

I_{BANK_BIAS}is the output bank bias current (fixed value).

I_{OUT_LOAD}is the DC load current per loaded output pair.

N is the number of loaded output pairs (N = 0 to 2).

(6)

Table 5 shows the typical I_{BANK_BIAS}values and I_{OUT_LOAD}expressions for HCSL.

Table 5. Typical Output Bank Bias and Load Currents

Current Parameter

I_{BANK_BIAS}

HCSL

2.4 mA

V_OH/R_T

I_{OUT_LOAD}

Once the current consumption is known for each supply, the total power dissipation (P_TOTAL) can be calculated:

P_TOTAL= (V_CC*I_{CC_TOTAL}) + (V_CCOA*I_{CCO_BANK}) + (V_CCOB*I_{CCO_BANK}) + (V_CCOC*I_{CCO_CMOS}

)

(7)

If the device is configured with HCSL outputs, then it is also necessary to calculate the power dissipated in any

termination resistors (P_{RT_HCSL}). The external power dissipation values can be calculated as follows:

P_{RT_HCSL}(per HCSL pair) = V_OH²/ R_T

(8)

Finally, the IC power dissipation (P_DEVICE) can be computed by subtracting the external power dissipation values

from P_TOTALas follows:

P_DEVICE= P_TOTAL- N*P_{RT_HCSL}

where

•

N is the number of HCSL output pairs with termination resistors to GND.

(9)

Power Dissipation Example: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power

dissipation. In this case, the maximum supply voltage and supply current values specified in ELECTRICAL

CHARACTERISTICS are used.

•

Max V_CC= V_CCO= 3.465 V. Max I_CCand I_CCOvalues.

CLKin0/CLKin0* input is selected.

Banks A and B are enabled, and all outputs are terminated with 50 Ω to GND.

REFout is enabled with 5 pF load.

T_A= 85 °C

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Using the power calculations from the previous section and maximum supply current specifications, we can

compute P_TOTALand P_DEVICE

•

From Equation 5: I_{CC_TOTAL}= 10.5 mA + 58.5 mA + 5.5 mA = 74.5 mA

From I_{CCO_HCSL}max spec: I_{CCO_BANK}= 50% of I_{CCO_HCSL}= 40.75 mA

From Equation 7: P_TOTAL= (3.465 V * 74.5 mA) + (3.465 V * 40.75 mA)+ (3.465 V * 40.75 mA) + (3.465 V *

10 mA) = 575.2 mW

From Equation 8: P_{RT_HCSL}= (0.92V)²/ 50Ω = 16.9 mW (per output pair)

•

From Equation 9: P_DEVICE= 575.2 mW - (4 * 16.9 mW) = 510.4 mW

In this worst-case example, the IC device will dissipate about 510.4 mW or 88.7% of the total power (575.2 mW),

while the remaining 11.3% will be dissipated in the termination resistors (64.8 mW for 4 pairs). Based on θ_JAof

38.1 °C/W, the estimate die junction temperature would be about 19.4 °C above ambient, or 104.4 °C when T_A=

85 °C.

Power Supply Bypassing

The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF,

placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the

device between the supply and ground planes. All bypass and decoupling capacitors should have short

connections to the supply and ground plane through a short trace or via to minimize series inductance.

Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies,

digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to

understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is

applied to the power supply of a clock distribution device, such as LMK00334, it can produce narrow-band phase

modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise

spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in

dBc).

For the LMK00334, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur

level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vcco supply. The

PSRR test setup is shown in Figure 21.

Ripple

Source

Power

Supplies

Bias-Tee

Vcco

Vcc

OUT+

IN+

IN-

Clock

Source

Limiting

Amp

OUT-

DUT Board

OUT

Phase Noise

Analyzer

Scope

Measure 100 mV

Measure single

sideband phase spur

power in dBc

ripple on Vcco at IC

Figure 21. PSRR Test Setup

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A signal generator was used to inject a sinusoidal signal onto the Vcco supply of the DUT board, and the peak-

to-peak ripple amplitude was measured at the Vcco pins of the device. A limiting amplifier was used to remove

amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise

analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz

under the following power supply ripple conditions:

•

Ripple amplitude: 100 mVpp on Vcco = 2.5 V

Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ)

can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_CLK)] * 10¹²

(10)

The “PSRR vs. Ripple Frequency” plots in TYPICAL CHARACTERISTICS show the ripple-induced phase spur

levels at 156.25 MHz and 312.5 MHz. The LMK00334 exhibits very good and well-behaved PSRR characteristics

across the ripple frequency range. The phase spur levels for HCSL are below -72 dBc at 156.25 MHz and below

-63 dBc at 312.5 MHz. Using Equation 10, these phase spur levels translate to Deterministic Jitter values of 1.02

ps pk-pk at 156.25 MHz and 1.44 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the

device improves for Vcco = 3.3 V under the same ripple amplitude and frequency conditions.

Thermal Management

Power dissipation in the LMK00334 device can be high enough to require attention to thermal management. For

reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an

estimate, T_A(ambient temperature) plus device power dissipation times θ_JAshould not exceed 125 °C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent

electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal

land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 22. More information on soldering WQFN packages can

be obtained at: http://www.ti.com/packaging.

3.1 mm, min

0.2 mm, typ

1.27 mm,

typ

Figure 22. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground

plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite

side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but

should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in

Figure 22 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat

pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively

dissipated.

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PACKAGE OPTION ADDENDUM

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22-Dec-2013

PACKAGING INFORMATION

Orderable Device

LMK00334RTVR

LMK00334RTVT

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

WQFN

RTV

1000

Green (RoHS

& no Sb/Br)

CU SN

Level-3-260C-168 HR

K00334

ACTIVE

RTV

250

Green (RoHS

& no Sb/Br)

CU SN

Level-3-260C-168 HR

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

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Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Dec-2013

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMK00334RTVR

LMK00334RTVT

WQFN

RTV

1000

250

178.0

12.4

5.3

1.3

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMK00334RTVR

LMK00334RTVT

WQFN

RTV

1000

250

213.0

191.0

55.0

Pack Materials-Page 2

MECHANICAL DATA

RTV0032A

SQA32A (Rev B)

www.ti.com

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LMK00334_14 [TI]

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