LMK00804BPWR [TI]

低偏斜、1 至 4、多路复用差动/LVCMOS 至 LVCMOS/TTl 扇出缓冲器 | PW | 16 | -40 to 85;


型号：	LMK00804BPWR
厂家：	TEXAS INSTRUMENTS
描述：	低偏斜、1 至 4、多路复用差动/LVCMOS 至 LVCMOS/TTl 扇出缓冲器 \| PW \| 16 \| -40 to 85
文件：	总35页 (文件大小：2903K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMK00804B

ZHCSCY6A –JUNE 2014–REVISED JULY 2014

LMK00804B 低偏移 1 到 4 多路复用

差动/LVCMOS 到 LVCMOS/TTL 扇出缓冲器

1 特性

2 应用

•

4 个具有 7Ω 输出阻抗的 LVCMOS/LVTTL 输出

•

无线和有线基础设施

网络和数据通信

服务器和计算

医疗成像

–

附加抖动：125MHz 时为 0.04ps RMS（典型

值）

–

噪底：125MHz 时为 –166dBc/Hz（典型值）

输出频率：350MHz（最大值）

输出偏移：35ps（最大值）

便携式测试和测量

高端 A/V

部件间偏移：700ps（最大值）

3 说明

•

两个可选输入

LMK00804B 是一款低偏移、高性能时钟扇出缓冲器，

可通过两个可选输入（可接受差分输入或单端输入）之

一分配至多 4 个 LVCMOS/LVTTL 输

–

CLK、nCLK 对接受

LVPECL、LVDS、HCSL、SSTL、LVHSTL 或

LVCMOS/LVTTL

–

LVCMOS_CLK 接受 LVCMOS/LVTTL

出（3.3V、2.5V、1.8V 或 1.5V 四种电平）。时钟使

能输入在内部同步，以便在时钟使能端子被置为有效或

置为无效时消除输出上的欠幅脉冲或毛刺脉冲。禁用

时钟后，输出将保持逻辑低电平状态。单独的输出使

能端子可控制输出处于激活状态或高阻态。

•

同步时钟启用

内核/输出电源：

–

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

3.3V/1.5V

LMK00804B 具有低附加抖动和相位噪底，且兼具可靠

的输出和部件间偏移特性，因此非常适合对高性能和可

重复性有严格要求的应用。

•

封装：16 引线薄型小尺寸封装 (TSSOP)

工业温度范围：-40ºC 至 +85ºC

有关 CDCLVC1310 和 LMK00725 部件的介绍，另请

参见Device Comparison Table。

器件信息

部件号

封装

封装尺寸（标称值）

LMK00804B

TSSOP (16)

5.00mm x 4.40mm

1. 如需了解所有可用封装，请见数据表末尾的可订购

产品附录。

附加抖动与 VDDO 电源和温度间的关系

4 简化电路原理图

0.10

±40C

25°C

85°C

f_CLK= 125 MHz

Input Slew Rate = 3 V/ns

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0.00

R_PU

CLK_EN

R_PD

LVCMOS

_CLK

CLK

R_PU

nCLK

R_PD

R_PU

CLK_SEL

R_PU= Pullup

R_PD= Pulldown

1.5

1.8

2.5

3.3

VDDO Supply (V)

C002

R_PU

(1) R_PU= 51kΩ（上拉电阻），R_PD

51kΩ（下拉电阻）。请参见Figure 10

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNAS642

LMK00804B

ZHCSCY6A –JUNE 2014–REVISED JULY 2014

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

8.1 Pin Characteristics .................................................... 4

8.2 Absolute Maximum Ratings ...................................... 4

8.3 Handling Ratings....................................................... 4

8.4 Recommended Operating Conditions....................... 4

8.5 Thermal Information.................................................. 5

8.6 Power Supply Characteristics ................................... 5

8.7 LVCMOS / LVTTL DC Characteristics...................... 5

8.8 Differential Input DC Characteristics......................... 6

8.9 Electrical Characteristics (VDDO = 3.3 V ± 5%)....... 6

8.10 Electrical Characteristics (VDDO = 2.5 V ± 5%)..... 7

8.11 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V) 8

8.12 Electrical Characteristics (VDDO = 1.5 V ± 5%)..... 9

8.13 Typical Characteristics.......................................... 10

Parameter Measurement Information ................ 11

10 Detailed Description ........................................... 12

10.1 Overview ............................................................... 12

10.2 Functional Block Diagram ..................................... 12

10.3 Feature Description............................................... 13

10.4 Device Functional Modes...................................... 13

11 Applications and Implementation...................... 14

11.1 Application Information.......................................... 14

11.2 Output Clock Interface Circuit............................... 14

11.3 Input Detail............................................................ 14

11.4 Input Clock Interface Circuits................................ 15

11.5 Typical Applications .............................................. 18

11.6 Do's and Don'ts..................................................... 21

12 Power Supply Recommendations ..................... 23

12.1 Power Supply Considerations............................... 23

13 Layout................................................................... 24

13.1 Layout Guidelines ................................................. 24

13.2 Layout Example .................................................... 25

14 器件和文档支持 ..................................................... 26

14.1 器件支持................................................................ 26

14.2 商标....................................................................... 26

14.3 静电放电警告......................................................... 26

14.4 术语表 ................................................................... 26

15 机械封装和可订购信息 .......................................... 26

5 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (June 2014) to Revision A

Page

•

Added Device Comparison Table .......................................................................................................................................... 3

Changed Human Body Model (HBM) value from 2000 to 1000 ............................................................................................ 4

Changed Charged Device Model (CDM) value from 750 to 250 .......................................................................................... 4

LMK00804B

www.ti.com.cn

ZHCSCY6A –JUNE 2014–REVISED JULY 2014

6 Device Comparison Table

PART NUMBER

CDCLVC1310

LMK00725

DESCRIPTION

10 outputs LVCMOS fanout buffer with Diff, Single-Ended, or Crystal Input

5 output LVPECL fanout buffer with Differential or Single-Ended Input

7 Pin Configuration and Functions

16 Pin

PW Package

Top View

GND

VDD

VDDO

CLK_EN

CLK

GND

nCLK

VDDO

CLK_SEL

LVCMOS_CLK

GND

Pin Functions

TERMINAL

NUMBER

TYPE⁽¹⁾

DESCRIPTION

NAME

GND

1, 9, 13

Power supply ground

Output enable input.

I, R_PU

0 = Outputs in Hi-Z state

1 = Outputs in active state

VDD

Power supply terminal

Synchronous clock enable input.

CLK_EN

I, R_PU

0 = Outputs are forced to logic low state

1 = Outputs are enabled with LVCMOS/LVTT levels

CLK

I, R_PD

Non-inverting differential clock input 0.

nCLK

I, R_PD/R_PU

Inverting differential clock input 0. Internally biased to VDD/2 when left floating

Clock select input.

CLK_SEL

I, R_PU

0 = Select LVCMOS_CLK

1 = Select CLK, nCLK

LVCMOS_CLK

Q3, Q2, Q1, Q0

VDDO

I, R_PD

Single-ended clock input. Accepts LVCMOS/LVTTL levels.

Single-ended clock outputs with LVCMOS/LVTTL levels, 7Ω output impedance

Output supply terminals

10, 12, 14, 16

11, 15

(1) G = Ground, I = Input, O = Output, P = Power, R_PU= 51 kΩ pullup, R_PD= 51 kΩ pulldown.

LMK00804B

ZHCSCY6A –JUNE 2014–REVISED JULY 2014

www.ti.com.cn

8 Specifications

8.1 Pin Characteristics

MIN

TYP

MAX

UNIT

C_IN

Input Capacitance

R_PU

R_PD

C_PD

R_OUT

Input Pullup Resistance

kΩ

Input Pulldown Resistance

Power Dissipation Capacitance (per output)

Output impedance

8.2 Absolute Maximum Ratings⁽¹⁾⁽²⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

TYP

MAX

3.6

UNIT

VDD

Core Supply Voltage

Output Supply Voltage

VDDO

3.6

VDD

+0.3

V_IN

T_J

Input Voltage Range

Junction Temperature

–0.3

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

8.3 Handling Ratings

MIN

MAX

150

UNIT

T_stg

Storage temperature range

–65

°C

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001, all

pins⁽²⁾

1000

V_(ESD)

Electrostatic discharge⁽¹⁾

Charged device model (CDM), per

JEDEC specification JESD22-C101,

all pins⁽³⁾

250

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

3.135

2.375

1.65

TYP

3.3

2.5

1.8

1.5

MAX

3.465

2.625

1.95

1.575

UNIT

VDD

Core Supply Voltage

Output Supply Voltage

VDDO

1.425

-40

T_A

T_J

Ambient Temperature

Junction Temperature

°C

125

LMK00804B

www.ti.com.cn

ZHCSCY6A –JUNE 2014–REVISED JULY 2014

8.5 Thermal Information

Over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC⁽¹⁾

MIN

TYP

MAX

UNIT

R _θJA

Package Thermal Impedance, Junction to Air (0 LFPM)

116

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.6 Power Supply Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

Power Supply Current through VDD

Power Supply Current through VDDO

MIN

TYP

MAX

UNIT

IDD

IDDO

8.7 LVCMOS / LVTTL DC Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

CLK_EN,

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD +

0.3

CLK_SEL, OE

V_IH

V_IL

I_IH

Input High Voltage

Input Low Voltage

Input High Current

VDD +

0.3

LVCMOS_CLK

CLK_EN,

–0.3

0.8

1.3

CLK_SEL, OE

LVCMOS_CLK

CLK_EN,

VDD = 3.465 V,

V_IN= 3.465 V

CLK_SEL, OE

µA

VDD = 3.465 V,

V_IN= 3.465 V

LVCMOS_CLK

150

CLK_EN,

VDD = 3.465 V,

V_IN= 0 V

–150

–5

CLK_SEL, OE

I_IL

Input Low Current

VDD = 3.465 V,

V_IN= 0 V

LVCMOS_CLK

VDDO = 3.3 V ± 5%

VDDO = 2.5 V ± 5%

VDDO = 1.8 V ± 0.15 V

2.6

1.8

1.5

V_OH

Output High Voltage⁽¹⁾

VDDO –

0.3

VDDO = 1.5 V ± 5%

VDDO = 3.3 V ± 5%

VDDO = 2.5 V ± 5%

VDDO = 1.8 V ± 0.15 V

VDDO = 1.5 V ± 5%

0.5

V_OL

Output Low Voltage⁽¹⁾

0.4

0.35

I_OZL

I_OZH

Output Hi-Z Current Low

Output Hi-Z Current High

–5

µA

(1) Outputs terminated with 50 Ω to VDDO/2.

LMK00804B

ZHCSCY6A –JUNE 2014–REVISED JULY 2014

www.ti.com.cn

8.8 Differential Input DC Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential Input Voltage Swing,

(V_IH-V_IL)⁽¹⁾

V_ID

0.15

1.3

VDD –

0.85

V_ICM

Input Common Mode Voltage⁽¹⁾⁽²⁾

0.5

VDD = 3.465 V,

V_IN= 3.465 V

nCLK

Input High Current⁽³⁾

CLK

150

I_IH

µA

VDD = 3.465 V,

V_IN= 3.465 V

VDD = 3.465 V ,

V_IN= 0 V

nCLK

Input Low Current⁽³⁾

CLK

-150

-5

I_IL

µA

VDD = 3.465 V,

V_IN= 0 V

(1) V_ILshould not be less than -0.3 V.

(2) Input common mode voltage is defined as V_IH

(3) For I_IHand I_ILmeasurements on CLK or nCLK, one must comply with V_IDand V_ICMspecifications by using the appropriate bias on nCLK

or CLK.

8.9 Electrical Characteristics (VDDO = 3.3 V ± 5%)

Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3V ± 5%,

All AC parameters measured at ≤ 350 MHz unless otherwise noted.

PARAMETER

Maximum Output Frequency⁽¹⁾⁽²⁾

Propagation Delay,

TEST CONDITIONS

MIN

TYP

MAX

350

2.1

UNIT

MHz

f_OUT

LVCMOS_CLK⁽⁴⁾

0°C to 70°C

1.1

t_PDLH

CLK/nCLK⁽⁵⁾

Low to High⁽³⁾

–40°C to 85°C

0.95

2.2

t_SK(O)

t_SK(PP)

t_R/t_F

Output Skew^(2)(6)(7)

Part-to-Part Skew^(3)(7)(8)

Output Rise/Fall Time⁽³⁾

Measured on rising edge

700

20% to 80%

f=125 MHz,

Input slew rate ≥ 3 V/ns,

12 kHz to 20 MHz

integration band

J_ADD

Additive Jitter⁽⁹⁾

0.04

ps RMS

(1) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.

(2) These AC parameters are specified by characterization. Not tested in production.

(3) These AC parameters are specified by design. Not tested in production

(4) Measured from the VDD/2 of the input to the VDDO/2 of the output.

(5) Measured from the differential input crossing point to VDDO/2 of the output.

(6) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.

(7) Parameter is defined in accordance with JEDEC Standard 65.

(8) Calculation for part-to-part skew is the difference between the fastest and slowest t_PDacross multiple devices, operating at the same

supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.

(9) Buffer Additive Jitter: J_ADD= SQRT(J_SYSTEM²- J_SOURCE²), where J_SYSTEMis the RMS jitter of the system output (source+buffer) and

J_SOURCEis the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should

be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN_FLOOR). This is usually the case for

high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and

measurement details.

LMK00804B

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ZHCSCY6A –JUNE 2014–REVISED JULY 2014

Electrical Characteristics (VDDO = 3.3 V ± 5%) (continued)

Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3V ± 5%,

All AC parameters measured at ≤ 350 MHz unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 125 MHz,

Input slew rate ≥ 3 V/ns

10 kHz offset

100 kHz offset

1 MHz offset

-155

-162

-166

Phase Noise Floor⁽¹⁰⁾

dBc/Hz

PN_FLOOR

10 MHz offset

20 MHz offset

REF = CLK/nCLK

45%

55%

ODC

Output Duty Cycle^(3)(11)

REF = LVCMOS_CLK,

f ≤ 300 MHz

t_EN

Output Enable Time

Output Disable Time

t_DIS

(10) Buffer Phase Noise Floor: PN_FLOOR(dBc/Hz) = 10 x log10[10^(PN_SYSTEM/10) – 10^(PN_SOURCE/10)], where PN_SYSTEMis the phase noise

floor of the system output (source+buffer) and PN_SOURCEis the phase noise floor of the input source. Buffer Phase Noise Floor should

be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN_FLOOR). This is usually the case for

high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and

measurement details.

(11) 50% Input duty cycle

8.10 Electrical Characteristics (VDDO = 2.5 V ± 5%)

Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%,

All AC parameters measured at ≤ 350 MHz unless otherwise noted.

PARAMETER

Maximum Output Frequency^{(1) (2)}

TEST CONDITIONS

MIN

TYP

MAX

350

2.1

UNIT

MHz

f_OUT

t_PDLH

Propagation Delay,

Low to High⁽³⁾

LVCMOS_CLK⁽⁴⁾

0°C to 70°C

1.1

CLK/nCLK⁽⁵⁾

–40°C to 85°C

0.95

2.2

t_SK(O)

t_SK(PP)

t_R/t_F

Output Skew^(2)(6)(7)

Part-to-Part Skew^(3)(7)(8)

Output Rise/Fall Time⁽³⁾

Additive Jitter⁽⁹⁾

Measured on rising edge

700

20% to 80%

J_ADD

f=125 MHz,

0.04

ps RMS

Input slew rate ≥ 3 V/ns,

12 kHz to 20 MHz

integration band

ODC

Output Duty Cycle^(3)(10)

REF = CLK/nCLK

45%

55%

REF = LVCMOS_CLK,

f ≤ 300 MHz

t_EN

Output Enable Time

Output Disable Time

t_DIS

(1) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.

(2) These AC parameters are specified by characterization. Not tested in production.

(3) These AC parameters are specified by design. Not tested in production.