LMK04002BISQ/NOPB_技术文档

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs

Check for Samples: LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033

1

FEATURES

23

•

Cascaded PLLatinum™ PLL Architecture

•

Support Clock Rates up to 1080 MHz

–

PLL1

Default Clock Output (CLKout2) at power up

–

Phase Detector Rate of up to 40 MHz

Five Dedicated Channel Divider and Delay

Blocks

Integrated Low-Noise Crystal Oscillator

Circuit

•

Pin Compatible Family of Clocking Devices

Industrial Temperature Range: -40 to 85 °C

3.15 V to 3.45 V Operation

–

Dual Redundant Input Reference Clock

with LOS

–

PLL2

Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)

–

Normalized [1 Hz] PLL Noise Floor of -

224 dBc/Hz

APPLICATIONS

–

Phase Detector Rate up to 100 MHz

Input Frequency-Doubler

Integrated Low-Noise VCO

•

Data Converter Clocking

Wireless Infrastructure

Networking, SONET/SDH, DSLAM

Medical

•

Ultra-Low RMS Jitter Performance

–

150 fs RMS Jitter (12 kHz – 20 MHz)

200 fs RMS Jitter (100 Hz – 20 MHz)

Military / Aerospace

Test and Measurement

Video

LVPECL/2VPECL, LVDS, and LVCMOS outputs

DESCRIPTION

The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and

distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a

cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family

provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal

oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-

noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured

to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and

a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise

(offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as

the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be

optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the

VCXO module or crystal used in PLL1.

The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon

power up. The input block is equipped with loss of signal detection and automatic or manual selection of the

reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a

programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on

CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or

microcontroller that programs the jitter cleaner during the system power up sequence.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PLLatinum is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Crystal or

VCXO

CLKout0

CLKout1

CLKout2A

CLKout4

Recovered

—dirty“ clock or

clean clock

Serializer/

Deserializer

LMK040xx

Precision Clock

Conditioner

CLKin0

CLKin1

LMX2531

PLL+VCO

FPGA

Fout

> 1 Gsps

Backup

Reference

Clock

Multiple —clean“ clocks at

different frequencies

DAC

ADC

Table 1. Device Configuration Information

2VPECL / LVPECL

NSID

PROCESS

LVDS OUTPUTS

LVCMOS OUTPUTS

VCO

OUTPUTS

LMK04000BISQ

LMK04001BISQ

LMK04002BISQ

LMK04010BISQ

LMK04011BISQ

LMK04031BISQ

LMK04033BISQ

BiCMOS

3

5

2

4

1185 to 1296 MHz

1430 to 1570 MHz

1600 to 1750 MHz

1185 to 1296 MHz

1430 to 1570 MHz

1840 to 2160 MHz

2

NSID

CLKout0

2VPECL / LVPECL

LVDS

CLKout1

CLKout2

LVCMOS x 2

CLKout3

CLKout4

2VPECL / LVPECL

LVDS

LMK04000BISQ

LMK04001BISQ

LMK04002BISQ

LMK04010BISQ

LMK04011BISQ

LMK04031BISQ

LMK04033BISQ

LVCMOS x 2

2VPECL / LVPECL

LVCMOS x 2

2VPECL / LVPECL

LVCMOS x 2

LVDS

LVCMOS x 2

LVDS

2

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Functional Block Diagram

LOS

LOS0

CLKin0

CLKin0*

Mux

R1 Divider

N1 Divider

Phase

Detector

PLL1

CLKin1

CLKin1*

LOS

LOS1

2X

Partially

Integrated

Mux

Loop Filter

Internal VCO

OSCin

OSCin*

R2 Divider

Phase

Detector

PLL2

Fout

N2 Divider

VCO

Divider

Distribution

Path

CLKout4

CLKout4*

Divider

Mux

Delay

GOE

LD

Device

Control

CLKout3B

CLKout3A

SYNC*

CLK

CLKout2B

CLKout2A

mWire

Port

Control

Registers

DATA

LE

CLKout1

CLKout1*

CLKout0

CLKout0*

Clock Buffers

Submit Documentation Feedback

3

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Connection Diagram

48

47

46

45

44

43

42

41

40

39

38

37

GND

Fout

1

2

36

35

34

33

32

31

30

29

28

27

26

25

Bias

CLKin1_LOS

CLKin0_LOS

Vcc10

Vcc1

3

CLKuWire

DATAuWire

LEuWire

NC

4

5

CPout2

Vcc9

6

7

Vcc8

Vcc2

8

OSCin*

OSCin

LDObyp1

LDObyp2

GOE

9

10

11

12

SYNC*

CLKin1*

CLKin1

DAP

LD

13

14

15

16

17

18

19

20

21

22

23

24

Figure 1. 48-Pin WQFN Package

Top View

PIN DESCRIPTIONS

Pin Number

Name(s)

GND

I/O

Type

Description

1

2

GND

Ground (For Fout Buffer)

VCO Frequency Output Port

Power Supply for VCO Output Buffer

Microwire Clock Input

Fout

O

ANLG

PWR

3

V_CC1

4

CLKuWire

DATAuWire

LEuWire

NC

I

CMOS

5

Microwire Data Input

6

Microwire Latch Enable Input

No Connection

7

8

V_CC

2

PWR

ANLG

Power Supply for VCO

9

LDObyp1

LDObyp2

LDO Bypass, bypassed to ground with a 10 µF capacitor

10

LDO Bypass, bypassed to ground with a 0.1 µF

capacitor

11

12

13

14

15

16

GOE

LD

I

CMOS

Global Output Enable

O

Lock Detect and PLL multiplexer Output

Power Supply for CLKout0

Clock Channel 0 Output

V_CC3

PWR

CLKout0

CLKout0*

DLD_BYP

O

LVDS/LVPECL

ANLG

Clock Channel 0* Output

DLD Bypass, bypassed to ground with a 0.47 µF

capacitor

17

18

GND

PWR

Ground (Digital)

V_CC4

Power Supply for Digital

4

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

PIN DESCRIPTIONS (continued)

Pin Number

Name(s)

V_CC

I/O

Type

PWR

ANLG

Description

19

20

5

Power Supply for CLKin buffers and PLL1 R-divider

Reference Clock Input Port for PLL1 - AC or DC

CLKin0

I

(1)

Coupled

21

22

CLKin0*

ANLG

PWR

Reference Clock Input Port for PLL1 (complimentary) -

AC or DC Coupled

(1)

V_CC6

Power Supply for PLL1 Phase Detector and Charge

Pump

23

24

25

CPout1

V_CC

O

ANLG

PWR

Charge Pump1 Output

7

Power Supply for PLL1 N-Divider

Reference Clock Input Port for PLL1 - AC or DC

CLKin1

I

ANLG

(1)

Coupled

26

CLKin1*

ANLG

Reference Clock Input Port for PLL1 (complimentary) -

(1)

AC or DC Coupled

27

28

29

30

31

SYNC*

OSCin

OSCin*

I

CMOS

ANLG

PWR

Global Clock Output Synchronization

Reference oscillator Input for PLL2 - AC Coupled

Power Supply for OSCin Buffer and PLL2 R-Divider

V_CC8

9

V_CC

PWR

Power Supply for PLL2 Phase Detector and Charge

Pump

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

DAP

CPout2

V_CC10

O

ANLG

PWR

Charge Pump2 Output

Power Supply for VCO Divider and PLL2 N-Divider

Status of CLKin0 reference clock input

Status of CLKin1 reference clock input

Bias Bypass. AC coupled with 1 µF capacitor to Vcc1

Power Supply for CLKout1

CLKin0_LOS

CLKin1_LOS

Bias

O

I

LVCMOS

ANLG

V_CC11

PWR

CLKout1

CLKout1*

V_CC12

O

LVPECL/LVCMOS

PWR

Clock Channel 1 Output

Clock Channel 1* Output

Power Supply for CLKout2

CLKout2

CLKout2*

V_CC13

O

LVPECL/LVCMOS

PWR

Clock Channel 2 Output

Clock Channel 2* Output

Power Supply for CLKout3

CLKout3

CLKout3*

V_CC14

O

LVPECL

Clock Channel 3 Output

LVPECL

Clock Channel 3* Output

PWR

Power Supply for CLKout4

CLKout4

CLKout4*

DAP

O

LVDS/LVPECL

Clock Channel 4 Output

Clock Channel 4* Output

DIE ATTACH PAD, connect to GND

(1) The reference clock inputs may be either AC or DC coupled.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Submit Documentation Feedback

5

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Absolute Maximum Ratings^(1)(2)(3)(4)

Parameter

Symbol

Ratings

-0.3 to 3.6

Units

(5)

Supply Voltage

Input Voltage

V_CC

V_IN

V

-0.3 to (V_CC+ 0.3)

-65 to 150

Storage Temperature Range

T_STG

T_L

°C

Lead Temperature (solder 4 sec)

+260

Differential Input Current (CLKinX/X*,

OSCin/OSCin*)

I_IN

± 5

mA

(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test

conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3) This device is a high performance RF integrated circuit with an ESD rating up to 8 KV Human Body Model, up to 300 V Machine Model

and up to 1,250 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free

workstations.

(4) Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress

ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation

sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

(5) Never to exceed 3.6 V.

Package Thermal Resistance

Package

θ_JA

θ_{J-PAD (Thermal Pad)}

(1)

48-Lead WQFN

27.4° C/W

5.8° C/W

(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These

vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in

the board layout.

Recommended Operating Conditions

Parameter

Symbol

Condition

Min

-40

Typical

25

Max

85

Unit

°C

Ambient

Temperature

T_A

V_CC= 3.3 V

Supply Voltage

V_CC

3.15

3.3

3.45

V

Electrical Characteristics

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Current Consumption

Min

Typ

Max

Units

I_{CC_PD}

Power Down Supply Current

1

mA

LMK04000, LMK04001,

LMK04002

380

435

(2)

Supply Current with all clocks

enabled, all delay bypassed,

Fout disabled.

I_{CC_CLKS}

LMK04010, LMK04011

mA

378

335

435

385

(1)

(2)

LMK04031, LMK04033

(2)

CLKin0/0* and CLKin1/1* Input Clock Specifications

Manual Select mode

Auto-Switching mode

0.001

1

400

Clock Input Frequency

f_CLKin

MHz

(3)

(1) Load conditions for output clocks: LVPECL: 50 Ω to V_CC-2 V. 2VPECL: 50 Ω to V_CC-2.36 V. LVDS: 100 Ω differential. LVCMOS: 10 pF.

(2) Additional test conditions for I_CClimits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 33 for more

information)

(3) CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz.

6

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Slew Rate on CLKin

SLEW_CLKin

20% to 80%

0.15

0.5

V/ns

(4)

AC coupled to CLKinX;

CLKinX* AC coupled to Ground

(CLKinX_TYPE=0)

Input Voltage Swing,

single-ended input

0.25

0.5

2.0

3.1

Vpp

mV

Vpp

V

V_CLKin(Bipolar input buffer

mode)

CLKinX and CLKinX* are both

driven, AC coupled.

(CLKinX_TYPE=0)

Input Voltage Swing,

differential input

DC offset voltage between

CLKinX/CLKinX*

|CLKinX-CLKinX*|

V_CLKin-offset(Bipolar input

buffer mode)

Each pin AC coupled

(CLKinX_TYPE=0)

44

AC coupled to CLKinX;

CLKinX* AC coupled to Ground

(CLKinX_TYPE=1)

Input Voltage Swing, single-

ended input

0.25

0.5

2.0

0.0

2.0

3.1

V_CC

0.4

V_CLKin(MOS input buffer

mode)

CLKinX and CLKinX* are both

driven, AC coupled.

(CLKinX_TYPE=1)

Input Voltage Swing,

differential input

DC coupled to CLKinX;

CLKinX* AC coupled to Ground

(CLKinX_TYPE=1)

V_CLKin-V_IH(MOS input buffer

mode)

Maximum input voltage

DC coupled to CLKinX;

CLKinX* AC coupled to Ground

(CLKinX_TYPE=1)

V_CLKin-V_IL(MOS input buffer

mode)

V

DC offset voltage between

CLKinX/CLKinX*

|CLKinX-CLKinX*|

V_CLKin-offset(MOS input

buffer mode)

Each pin AC coupled

(CLKinX_TYPE=1)

294

mV

PLL1 Specifications

PLL1 Phase Detector

Frequency

f_PD

40

MHz

V_CPout1= V_CC/2,

PLL1_CP_GAIN = 100b

25

50

V_CPout1= V_CC/2,

PLL1_CP_GAIN = 101b

V_CPout1= V_CC/2,

PLL1_CP_GAIN = 110b

100

400

V_CPout1= V_CC/2,

PLL1_CP_GAIN = 111b

PLL1 Charge Pump Source

Current

I_CPout1SOURCE

µA

(5)

PLL1_CP_GAIN = 000b

PLL1_CP_GAIN = 001b

NA

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 010b

20

80

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 011b

(4) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all

input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input

slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended

clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to

their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to

achieve optimal phase noise performance at the device outputs.

(5) This parameter is programmable

Submit Documentation Feedback

7

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 100b

-25

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 101b

-50

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 110b

-100

-400

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 111b

PLL1 Charge Pump Sink

Current

I_CPout1SINK

µA

(5)

PLL1_CP_GAIN = 000b

PLL1_CP_GAIN = 001b

NA

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 010b

-20

-80

3

V_CPout1=V_CC/2, PLL1_CP_GAIN

= 011b

Charge Pump Sink / Source

Mismatch

I_CPout1%MIS

V_CPout1= V_CC/2, T = 25 °C

10

%

Magnitude of Charge Pump

Current vs. Charge Pump

Voltage Variation

0.5 V < V_CPout1< V_CC- 0.5 V

T_A= 25 °C

I_CPout1V_TUNE

4

Charge Pump Current vs.

Temperature Variation

I_CPout1%TEMP

PLL1 I_CPout1TRI

%

Charge Pump TRI-STATE

Leakage Current

0.5 V < V_CPout< V_CC- 0.5 V

5

nA

PLL2 Reference Input (OSCin) Specifications

EN_PLL2_REF 2X = 0

250

50

(7)

PLL2 Reference Input

f_OSCin

MHz

V/ns

(6)

EN_PLL2_REF 2X = 1

20% to 80%

PLL2 Reference Clock

minimum slew rate on OSCin

SLEW_OSCin

0.15

0.5

AC coupled; Single-ended

(Unused pin AC coupled to

GND)

Input Voltage for OSCin or

OSCin*

V_OSCin(Single-ended)

V_OSCin(Differential)

0.2

0.4

2.0

3.1

Vpp

Differential voltage swing

AC coupled

Crystal Oscillator Mode Specifications

Crystal Frequency Range

f_XTAL

ESR

6

20

MHz

Crystal Effective Series

Resistance

6 MHz < F_XTAL< 20 MHz

100

Ohms

Vectron VXB1 crystal, 12.288

MHz, R_ESR< 40 Ω

(8)

P_XTAL

C_IN

Crystal Power Dissipation

200

6

µW

pF

Input Capacitance of

LMK040xx OSCin port

-40 to +85 °C

PLL2 Phase Detector and Charge Pump Specifications

Phase Detector Frequency

f_PD

100

MHz

(6) F_OSCinmaximum frequency guaranteed by characterization. Production tested at 200 MHz.

(7) The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.

(8) See Application Section discussion of Crystal Power Dissipation.

8

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 00b

100

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 01b

400

1600

3200

-100

-400

-1600

-3200

3

PLL2 Charge Pump Source

Current

I_CPoutSOURCE

µA

(9)

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 10b

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 11b

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 00b

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 01b

PLL2 Charge Pump Sink

I_CPoutSINK

µA

(9)

Current

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 10b

V_CPout2=V_CC/2, PLL2_CP_GAIN

= 11b

Charge Pump Sink/Source

Mismatch

I_CPout2%MIS

V_CPout2=V_CC/2, T_A= 25 °C

10

%

Magnitude of Charge Pump

Current vs. Charge Pump

Voltage Variation

0.5 V < V_CPout2< V_CC- 0.5 V

T_A= 25 °C

I_CPout2V_TUNE

4

Charge Pump Current vs.

Temperature Variation

I_CPout2%TEMP

I_CPout2TRI

%

Charge Pump Leakage

0.5 V < V_CPout2< V_CC- 0.5 V

nA

PLL 1/f Noise at 10 kHz offset PLL2_CP_GAIN = 400 µA

⁽¹⁰⁾. Normalized to

-117

-122

PN10kHz

PN1Hz

dBc/Hz

PLL2_CP_GAIN = 3200 µA

1 GHz Output Frequency

PLL2_CP_GAIN = 400 µA

PLL2_CP_GAIN = 3200 µA

Internal VCO Specifications

LMK040x0

-219

-224

Normalized Phase Noise

Contribution

(11)

1185

1430

1600

1840

1296

1570

1750

2160

LMK040x1

f_VCO

VCO Tuning Range

MHz

LMK040x2

LMK040x3

LMK040x0, T_A= 25 °C, single-

ended

3

LMK040x1, T_A= 25 °C, single-

ended

VCO Output power to a

50 Ω load driven by Fout

LMK040x2, T_A= 25 °C, single-

ended

P_VCO

2

dBm

LMK040x3, T_A= 25 °C, single-

ended 1840 MHz

0

LMK040x3, T_A= 25 °C, single-

ended 2160 MHz

-5

(9) This parameter is programmable

(10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker

noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10

kHz) - 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single side band phase noise of only the flicker noise's contribution to total noise,

L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean

crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference

oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of L_{PLL_flicker}(f)

and L_{PLL_flat}(f).

(11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as:

PN1HZ=L_{PLL_flat}(f)-20log(N)-10log(f_COMP). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz

bandwidth and f_COMPis the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

Submit Documentation Feedback

9

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

LMK040x0

Min

Typ

Max

Units

Fine Tuning Sensitivity

(The range displayed in the

typical column indicates the

lower sensitivity is typical at

the lower end of the tuning

range, and the higher tuning

sensitivity is typical at the

higher end of the tuning

range).

7 to 9

8 to 11

9 to 14

LMK040x1

LMK040x2

K_VCO

MHz/V

LMK040x3

14 to 26

After programming R15 for

lock, no changes to output

configuration are permitted to

guarantee continuous lock

Allowable Temperature Drift

|ΔT_CL

|

for Continuous Lock

125

°C

(12)

Internal VCO Open Loop Phase Noise and Jitter

Offset = 1 kHz

-66

-94

Offset = 10 kHz

LMK040x0

f_VCO= 1185 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 1 kHz

-119

-139

-158

-163

-64

dBc/Hz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 1 kHz

-91

LMK040x0

f_VCO= 1296 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-117

-138

-157

-161

-61

dBc/Hz

L(f)_Fout

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 1 kHz

-91

LMK040x1

f_VCO= 1440 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-117

-138

-158

-160

-58

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

-89

LMK040x1

f_VCO= 1560 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-115

-137

-157

-162

(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was

at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register,

even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if

the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to

ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the

frequency range of -40 °C to 85 °C without violating specifications.

10

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Offset = 1 kHz

Min

Typ

-63

Max

Units

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 1 kHz

-91

LMK040x2

f_VCO= 1600 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-115

-137

-156

-161

-61

dBc/Hz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 1 kHz

-90

LMK040x2

f_VCO= 1750 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-114

-136

-155

-160

-58

dBc/Hz

L(f)_Fout

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 1 kHz

-88

LMK040x3

f_VCO= 1840 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-113

-135

-155

-158

-54

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

-84

LMK040x3

f_VCO= 2160 MHz

SSB Phase Noise

PLL2 = Open Loop

Measured at Fout

-110

-132

-154

-157

Submit Documentation Feedback

11

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO

Offset = 1 kHz

-111

-119

-121

-133

-157

-162

-165

-110

-117

-120

-132

-156

-160

-163

-111

-118

-120

-132

-156

-162

-165

-107

-114

-117

-126

-152

-156

-160

Offset = 10kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 40 MHz

Offset = 1 kHz

(13)

LMK040x0

f_VCO= 1200 MHz

SSB Phase Noise

PLL2 = Closed Loop

Measured at Fout

dBc/Hz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 40 MHz

Offset = 1 kHz

(14)

LMK040x1

f_VCO= 1500 MHz

SSB Phase Noise

PLL2 = Closed Loop

Measured at Fout

dBc/Hz

L(f)_Fout

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 40 MHz

Offset = 1 kHz

(15)

LMK040x2

f_VCO= 1600 MHz

SSB Phase Noise

PLL2 = Closed Loop

Measured at Fout

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

Offset = 40 MHz

(16)

LMK040x3

f_VCO= 2000 MHz

SSB Phase Noise

PLL2 = Closed Loop

Measured at Fout

(13) For LMK040x0, f_VCO= 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

(14) For LMK040x1, f_VCO= 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

(15) For LMK040x2, f_VCO= 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 8, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

252 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

(16) For LMK040x3, f_VCO= 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW

= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

12

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(13)

LMK040x0

BW = 12 kHz to 20 MHz

105

f_VCO= 1200 MHz

Integrated RMS Jitter

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

110

100

105

95

(14)

LMK040x1

f_VCO= 1500 MHz

Integrated RMS Jitter

J_Fout

fs

(15)

LMK040x2

f_VCO= 1600 MHz

Integrated RMS Jitter

100

105

110

(16)

LMK040x3

f_VCO= 2000 MHz

Integrated RMS Jitter

CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset = 1 MHz

Offset = 10 MHz

-125

-130

-132

-148

-157

-126

-133

-136

-147

-156

-127

-133

-134

-145

-157

-125

-132

-135

-145

-156

(17)

LMK040x0

f_CLKout= 250 MHz

SSB Phase Noise

Measured at Clock Outputs

Value is average for all output

types

(18)

LMK040x1

f_CLKout= 250 MHz

SSB Phase Noise

Measured at Clock Outputs

Value is average for all output

types

L(f)_CLKout

dBc/Hz

(19)

LMK040x2

f_CLKout= 250 MHz

SSB Phase Noise

Measured at Clock Outputs

Value is average for all output

types

(20)

LMK040x3

f_CLKout= 250 MHz

SSB Phase Noise

Measured at Clock Outputs

Value Is average for all output

types

(17) For LMK040x0, f_VCO= 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

251 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = Bypass. CLKout_DLY = OFF.

(18) For LMK040x1, f_VCO= 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = 2. CLKout_DLY = OFF.

(19) For LMK040x2, f_VCO= 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

354 kHz, PM = 73°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = Bypass. CLKout_DLY = OFF.

(20) For LMK040x3, f_VCO= 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW

= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = 4. CLKout_DLY = OFF.

Submit Documentation Feedback

13

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(21)

LMK040x0

BW = 12 kHz to 20 MHz

130

f_CLKout= 250 MHz

Integrated RMS Jitter

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

135

115

120

130

135

125

130

140

145

110

115

130

135

120

125

(22)

LMK040x1

f_CLKout= 250 MHz

Integrated RMS Jitter

J_CLKout

LVPECL/2VPECL/LVDS

fs

(23)

LMK040x2

f_CLKout= 250 MHz

Integrated RMS Jitter

(24)

LMK040x3

f_CLKout= 250 MHz

Integrated RMS Jitter

(21)

LMK040x0

f_CLKout= 250 MHz

Integrated RMS Jitter

(22)

LMK040x1

f_CLKout= 250 MHz

Integrated RMS Jitter

J_CLKout

LVCMOS

fs

(23)

LMK040x2

f_CLKout= 250 MHz

Integrated RMS Jitter

(24)

LMK040x3

f_CLKout= 250 MHz

Integrated RMS Jitter

CLKout's Internal VCO Closed Loop Jitter Specifications using a Commercial Quality VCXO

(21) For LMK040x0, f_VCO= 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

251 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = Bypass. CLKout_DLY = OFF.

(22) For LMK040x1, f_VCO= 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = 2. CLKout_DLY = OFF.

(23) For LMK040x2, f_VCO= 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =

354 kHz, PM = 73°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = Bypass. CLKout_DLY = OFF.

(24) For LMK040x3, f_VCO= 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of

PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW

= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.

CLKoutX_DIV = 4. CLKout_DLY = OFF.

14

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(25) (26)

LMK040x0

BW = 12 kHz to 20 MHz

140

200

f_CLKout= 250 MHz

Integrated RMS Jitter

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

185

130

190

150

190

145

200

130

190

145

200

(27) (26)

LMK040x1

200

f_CLKout= 250 MHz

Integrated RMS Jitter

J_CLKout

LVPECL/2VPECL

fs

(28) (26)

LMK040x2

f_CLKout= 250 MHz

Integrated RMS Jitter

(29) (26)

LMK040x3

f_CLKout= 250 MHz

Integrated RMS Jitter

(30)

LMK040x1

f_CLKout= 250 MHz

Integrated RMS Jitter

J_CLKout

LVDS

fs

(31)

LMK040x3

f_CLKout= 250 MHz

Integrated RMS Jitter

(25) For LMK040x0, F_VCO= 1250 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2

= 1.8 kΩ, LBW = 254 kHz, PM = 81°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz:

-100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(26) Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production.

(27) For LMK040x1, F_VCO= 1500 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2

= 1.8 kΩ, LBW = 271 kHz, PM = 80°. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100

dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(28) For LMK040x2, F_VCO= 1750 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2

= 1.8 kΩ, LBW = 360 kHz, PM = 79°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz:

-100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(29) For LMK040x3, F_VCO= 2000 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF,

R2 = 1.8 kΩ, LBW = 445 kHz, PM = 76°. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -

100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(30) For LMK040x1, F_VCO= 1500 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2

= 1.8 kΩ, LBW = 271 kHz, PM = 80°. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100

dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(31) For LMK040x3, F_VCO= 2000 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, F_DET= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF,

R2 = 1.8 kΩ, LBW = 445 kHz, PM = 76°. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -

100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

Submit Documentation Feedback

15

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(32)

LMK040x0

BW = 12 kHz to 20 MHz

150

f_CLKout= 250 MHz

Integrated RMS Jitter

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

190

125

185

150

190

145

195

(30)

LMK040x1

f_CLKout= 250 MHz

Integrated RMS Jitter

J_CLKout

LVCMOS

fs

(33)

LMK040x2

f_CLKout= 250 MHz

Integrated RMS Jitter

(31)

LMK040x3

f_CLKout= 250 MHz

Integrated RMS Jitter

CLKout's Internal VCO Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit

(34)

LMK040x0

f_CLKout= 245.76 MHz

Integrated RMS Jitter

(35)

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

190

230

200

230

195

230

245

260

LMK040x1

f_CLKout= 245.76 MHz

Integrated RMS Jitter

J_CLKout

LVPECL/2VPECL/LVDS

fs

(36)

LMK040x2

f_CLKout= 245.76 MHz

Integrated RMS Jitter

(37)

LMK040x3

f_CLKout= 245.76 MHz

Integrated RMS Jitter

(32) For LMK040x0, F_VCO= 1250 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2

= 1.8 kΩ, LBW = 254 kHz, PM = 81°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz:

-100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(33) For LMK040x2, F_VCO= 1750 MHz. PLL1 parameters: F_DET= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives

the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, F_DET= 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2

= 1.8 kΩ, LBW = 360 kHz, PM = 79°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz:

-100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.

(34) For LMK040x0, F_VCO= 1228.8 MHz. PLL1 parameters: F_DET= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz

Vectron crystal (model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 5,

N2 = 10, EN_PLL2_REF2X = 1, F_DET= 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3

= 150 pF, C4 = 60 pF, LBW = 109 kHz, PM = 43°, CLKoutX_DIV = 2, CLKout_DLY = OFF.

(35) For LMK040x1, F_VCO= 1474.56 MHz. PLL1 parameters: F_DET= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz

Ecliptek crystal (model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 3, N2 = 20,

EN_PLL2_REF2X = 1, F_DET= 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150

pF, C4 = 60 pF, LBW = 103 kHz, PM = 44°, CLKoutX_DIV = 2, CLKout_DLY = OFF.

(36) For LMK040x2, F_VCO= 1720.32 MHz. PLL1 parameters: F_DET= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz

Vectron crystal (model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 7,

N2 = 10, EN_PLL2_REF2X = 1, F_DET= 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3

= 150 pF, C4 = 60 pF, LBW = 120 kHz, PM = 40°, CLKoutX_DIV = 2, CLKout_DLY = OFF.

(37) For LMK040x3, F_VCO= 1966.08 MHz. PLL1 parameters: F_DET= 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz

Ecliptek crystal (model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 4, N2 = 20,

EN_PLL2_REF2X = 1, F_DET= 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150

pF, C4 = 60 pF, LBW = 91 kHz, PM = 47°, CLKoutX_DIV = 2, CLKout_DLY = OFF.

16

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(34)

LMK040x0

BW = 12 kHz to 20 MHz

195

f_CLKout= 245.76 MHz

Integrated RMS Jitter

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

BW = 12 kHz to 20 MHz

BW = 100 Hz to 20 MHz

230

195

220

195

230

240

260

(35)

LMK040x1

f_CLKout= 245.76 MHz

Integrated RMS Jitter

J_CLKout

LVCMOS

fs

(36)

LMK040x2

f_CLKout= 245.76 MHz

Integrated RMS Jitter

(37)

LMK040x3

f_CLKout= 245.76 MHz

Integrated RMS Jitter

Digital Inputs (CLKuWire, DATAuWire, LEuWire)

High-Level Input Voltage

V_IH

V_IL

I_IH

1.6

V_CC

0.4

25

V

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

V_IH= V_CC

V_IL= 0

-5

µA

I_IL

-5.0

5.0

Digital Inputs (GOE, SYNC*)

V_IH

V_IL

I_IH

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

1.6

V_CC

0.4

5.0

V

V_IH= V_CC

V_IL= 0

-5.0

µA

I_IL

-40.0

Digital Outputs (CLKinX_LOS, LD)

V_OH

V_OL

High-Level Output Voltage

Low-Level Output Voltage

I_OH= -500 µA

I_OL= 500 µA

V_CC- 0.4

V

0.4

Default Power On Reset Clock Output Frequency

CLKout2, LM040x0

50

62

68

81

CLKout2, LM040x1

CLKout2, LM040x2

CLKout2, LM040x3

Default output clock frequency

at device power on

f_{CLKout-startup}

MHz

LVDS Clock Outputs (CLKoutX)

Maximum Frequency

f_CLKout

T_SKEW

V_OD

R_L= 100 Ω

1080

(38)

CLKoutX to CLKoutY

LVDS-LVDS, T = 25 °C,

F_CLK= 800 MHz, R_L= 100 Ω

30

ps

(39)

Differential Output Voltage

250

-50

350

450

mV

Change in Magnitude of V_OD

for complementary output

states

R = 100 Ω differential

termination, AC coupled to

receiver input,

ΔV_OD

50

mV

F_CLK= 800 MHz,

T = 25 °C

V_OS

Output Offset Voltage

1.125

1.25

1.375

35

V

Change in V_OSfor

complementary output states

ΔV_OS

|mV|

I_SA

I_SB

Output short circuit current -

single ended

Single-ended output shorted to

GND, T = 25 °C

-24

-12

24

12

mA

Output short circuit current -

differential

Complimentary outputs tied

together

I_SAB

(40)

LVPECL Clock Outputs (CLKoutX)

(38) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to ½ of a period, or, 0.5/F_CLKoutX

.

(39) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for

delay mode.

(40) LVPECL/2VPECL is programmable for all NSIDs.

Submit Documentation Feedback

17

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Maximum Frequency

f_CLKout

T_SKEW

V_OH

1080

MHz

(41)

LVPECL-to-LVPECL,

T = 25 °C, F_CLK= 800 MHz,

each output terminated with

120 Ω to GND.

CLKoutX to CLKoutY

40

ps

V

(42)

V_CC

0.93

-

Output High Voltage

F_CLK= 100 MHz, T = 25 °C

Termination = 50 Ω to

V_CC- 2 V

V_CC

1.82

-

V_OL

V_OD

Output Low Voltage

Output Voltage

V

660

890

965

40

mV

2VPECL Clock Outputs (CLKoutX)

Maximum Frequency

f_CLKout

T_SKEW

V_OH

1080

MHz

ps

(41)

2VPECL-2VPECL, T=25 °C,

F_CLK= 800 MHz, each output

terminated with 120 Ω to GND.

CLKoutX to CLKoutY

(42)

V_CC

0.95

-

Output High Voltage

V

F_CLK= 100 MHz, T = 25 °C

Termination = 50 Ω to

V_CC- 2 V

V_CC

1.98

-

V_OL

V_OD

Output Low Voltage

Output Voltage

V

800

1030

1200

0.1

mV

LVCMOS Clock Outputs (CLKoutX)

f_CLKout

V_OH

V_OL

I_OH

Maximum Frequency

Output High Voltage

Output Low Voltage

5 pF Load

1 mA Load

250

MHz

V

V_CC- 0.1

V

Output High Current (Source) V_CC= 3.3 V, V_O= 1.65 V

28

mA

I_OL

Output Low Current (Sink)

V_CC= 3.3 V, V_O= 1.65 V

Skew between any two

LVCMOS outputs, same

channel or different channel

R_L= 50 Ω, C_L= 10 pF,

T_SKEW

T = 25 °C, F_CLK= 100 MHz.

100

55

ps

(43)

V_CC/2 to V_CC/2, F_CLK= 100

DUTY_CLK

Output Duty Cycle

Output Rise Time

Output Fall Time

45

50

%

ps

(44)

MHz, T = 25 °C

20% to 80%, RL = 50 Ω,

CL = 5 pF

T_R

T_F

400

80% to 20%, RL = 50 Ω,

CL = 5 pF

Mixed Clock Skew

Same device, T = 25 °C,

250 MHz

LVPECL to LVDS skew

LVDS to LVCMOS skew

LVCMOS to LVPECL skew

-230

770

ps

Same device, T = 25 °C,

250 MHz

T_SKEWChanX - ChanY

Same device, T = 25 °C,

250 MHz

-540

Microwire Interface Timing

T_CS

T_CH

Data to Clock Set Up Time

Data to Clock Hold Time

See Microwire Input Timing

25

8

ns

(41) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to ½ of a period, or, 0.5/F_CLKoutX

.

(42) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for

delay mode.

(43) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for

delay mode.

(44) Guaranteed by characterization.

18

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Electrical Characteristics (continued)

(3.15 V ≤ V_CC≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C. Typical values represent most likely parametric norms at V_CC= 3.3 V, T_A= 25

°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)

Symbol

Parameter

Clock Pulse Width High

Clock Pulse Width Low

Conditions

Min

25

Typ

Max

Units

ns

T_CWH

T_CWL

See Microwire Input Timing

25

ns

Clock to Latch Enable

Set Up Time

T_ES

See Microwire Input Timing

25

ns

T_CES

T_EW

Clock to Enable Setup Time

Load Enable Pulse Width

See Microwire Input Timing

25

ns

Serial Data Timing Diagram

MSB

LSB

A0

DATAuWire

CLKuWire

LEuWire

D27

D26

D25

D24

D23

D0

A3

A2

A1

t

CWH

CS

t

ES

t

CH

CES

t

CWL

t

EWH

Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of

the CLKuWire signal. On the rising edge of the LEuWire signal, the register is sent from the shift register to the

register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is

complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. If the CLKuWire or

DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared

with other parts, the phase noise may be degraded during this programming.

Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V_CPout= V_CC- ΔV

I2 = Charge Pump Sink Current at V_CPout= V_CC/2

Submit Documentation Feedback

19

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= V_CC- ΔV

I5 = Charge Pump Source Current at V_CPout= V_CC/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage

Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch

Charge Pump Output Current Magnitude Variation vs. Temperature

20

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Typical Performance Characteristics

Clock Output AC Characteristics

LVDS V_OD

vs.

LVPECL V_OD

vs.

Frequency

1.0

2.5

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

2.0

LV2PECL Mode

1.5

1.0

0.5

0.0

NORMAL Mode

0

300

600

900 1.2k 1.5k 1.8k

0

400

800

1.2k

1.6k

2k

FREQUENCY (MHz)

Figure 2.

Figure 3.

LVCMOS Vpp

vs.

Frequency

Typical Dynamic I_CC, LVCMOS Driver, V_CC= 3.3 V,

Temp = 25 °C, CL= 5 pF

5

4

3

2

1

0

No Load

10 pF Load

40

35

30

25

20

15

10

5

22 pF Load

47 pF Load

0

100 pF Load

0

100

200

300

400

500

0

50 100 150 200 250 300 350 400

FREQUENCY (MHz)

Figure 4.

Figure 5.

Clock Channel Delay Noise Floor

Clock Output Noise Floor

vs.

Frequency

Delay = 2100 ps

Delay = 1800 ps

-130

-135

-140

-145

-150

-155

-160

-165

-170

-130

-135

-140

-145

-150

-155

-160

-165

-170

LVPECL (differential)

LVDS (differential)

Delay = 450 ps

Delay = 0 ps

Delay = 900 ps

LVCMOS

100

10

100

1000

10

1000

FREQUENCY (MHz)

Figure 6.

Figure 7.

To estimate this noise, only the output frequency is required. Divide value and input frequency are not relevant.

Submit Documentation Feedback

21

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Typical Performance Characteristics (continued)

The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor,

due to the distribution section accounting for the delay noise, can be calculated as: Total Output Noise = 10 x

log(10^{Output Buffer Noise/10}+ 10^{Delay Noise Floor/10}).

Typical LVDS Phase Noise, F_CLK= 250 MHz, RMS Jitter = 192 fs (100 Hz to 20 MHz)

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 8.

Typical LVPECL Phase Noise, F_CLK= 250 MHz, RMS Jitter = 196 fs (100 Hz to 20 MHz)

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 9.

Reference clock = 10 MHz, PLL1_R = 10, PLL1_N = 100, PLL1_CP_GAIN = 100 µA, PLL1 Loop BW = 20 Hz, VCXO

= 100 MHz Crystek CVPD-920-100, PLL2_R = 2, PLL2_N = 10, PLL2_CP_GAIN = 1600 µA, PLL2 Loop BW = 137

kHz, f_VCO= 1500 MHz, VCO_DIV = 3, CLKoutX_DIV = 2, CLK_DLY = OFF.

22

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Typical Performance Characteristics (continued)

Typical LVCMOS Phase Noise, F_CLK= 250 MHz, RMS Jitter = 188 fs (100 Hz to 20 MHz)

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 10.

Submit Documentation Feedback

23

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

FEATURES

System Architecture

The cascaded PLL architecture of the LMK040xx was chosen to provide the lowest jitter performance over the

widest range of output frequencies and phase noise offset frequencies. The first stage PLL (PLL1) is used in

conjunction with an external reference clock and an external VCXO to provide a frequency accurate, low phase

noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow

loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the

same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated

along its path or from other circuits. The “cleaned” reference clock frequency accuracy is combined with the low

phase noise of an external VCXO to provide the reference input to PLL2. The low phase noise reference

provided to PLL2 allows it to use wider loop bandwidths (50 kHz to 200 kHz). The chosen loop bandwidth for

PLL2 should take best advantage of the superior high offset frequency phase noise profile of the internal VCO

and the good low offset frequency phase noise of the reference VCXO for PLL2. Ultra low jitter is achieved by

allowing the external VCXO’s phase noise to dominate the final output phase noise at low offset frequencies and

the internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in

best overall phase noise and jitter performance.

Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)

The LMK040xx has two LVDS/LVPECL/LVCMOS compatible reference clock inputs for PLL1, CLKin0 and

CLKin1. The selection of the preferred input may be fixed to either CLKin0 or CLKin1, or may be configured to

employ one of two automatic switching modes when redundant clock signals are present. The PLL1 reference

clock input buffers may also be individually configured as either a CMOS buffered input or a bipolar buffered

input.

PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS)

When either of the two auto-switching modes is selected for the reference clock input mode, the signal status of

the selected reference clock input is indicated by the state of the CLKinX_LOS (loss-of-signal) output. These

outputs may be configured as either CMOS (active HIGH on loss-of-signal), NMOS open-drain or PMOS open-

drain. If PLL1 was originally locked and then both reference clocks go away, then the frequency accuracy of the

LMK04000 device will be set by the absolute tuning range of the VCXO used on PLL1. The absolute tuning

range of the VCXO can be determined by multiplying its' tuning constant by the charge pump voltage.

Integrated Loop Filter Poles

The LMK040xx features programmable 3rd and 4th order loop filter poles for PLL2. When enabled, internal

resistors and capacitor values may be selected from a fixed range of values to achieve either 3rd or 4th order

loop filter response. These programmable components compliment external components mounted near the chip.

Clock Distribution

The LMK040xx features a clock distribution block with a minimum of five outputs that are a mixture of LVPECL,

2VPECL, LVDS, and LVCMOS. The exact combination is determined by the part number. The 2VPECL is a

National Semiconductor proprietary configuration that produces a 2 Vpp differential swing for compatibility with

many data converters. More than five outputs may be available for device versions that offer dual LVCMOS

outputs.

CLKout Divide (CLKoutX_DIV, X = 0 to 4)

Each individual clock distribution channel includes a channel divider. The range of divide values is 2 to 510, in

steps of 2. “Bypass” mode operates as a divide-by-1.

CLKout Delay (CLKoutX_DLY, X = 0 to 4)

Each individual clock distribution channel includes a delay adjustment. Clock output delay registers

(CLKoutX_DLY) support a nominal 150 ps step size and range from 0 to 2250 ps of total delay.

24

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Global Clock Output Synchronization (Sync*)

The SYNC* input is used to synchronize the active clock outputs. When SYNC* is held in a logic low state, the

outputs are also held in a logic low state. When SYNC* goes high, the clock outputs are activated and will

transition to a high state simultaneously with one another.

SYNC* must be held low for greater than one clock cycle of the Clock Distribution Path. After this low event has

been registered, the outputs will not reflect the low state for four more cycles. Similarly after SYNC* becomes

high, the outputs will simultaneously transition high after four Clock Distribution Path cycles have passed. See

Figure 11 for further detail.

Distribution

Path

SYNC*

CLKout0

CLKout1

CLKout2

Figure 11. Clock Output synchronization using the SYNC* pin

Global Output Enable and Lock Detect

Each Clock Output Channel may be either enabled or put into a high impedance state via the Clock Output

Enable control bit (one for each channel). Each output enable control bit is gated with the Global Output Enable

input pin (GOE). The GOE pin provides an internal pull-up so that if it is un-terminated externally, then the clock

output states are determined by the Clock Channel Output Enable Register bits. All clock outputs can be

disabled simultaneously if the GOE pin is pulled low by an external signal.

Table 2. Clock Output Control

CLKoutX

_EN bit

EN_CLKout

_Global bit

CLKoutX Output State

GOE pin

1

Low

Off

Don't care

0

Don't care

1

Don't care

0

1

Don't care

Off

High / No Connect

Enabled

The Lock Detect (LD) signal can be connected to the GOE pin in which case all outputs are disabled

automatically if the synthesizer is not locked. See EN_CLKoutX: Clock Channel Output Enable and also System

Level Diagram for actual implementation details.

The Lock Detect (LD) pin can be programmed to output a ‘High’ when both PLL1 and PLL2 are locked, or only

when PLL1 is locked or only when PLL2 is locked.

FUNCTIONAL DESCRIPTION

Architectural Overview

The LMK040xx chip consists of two high performance synthesizer blocks (Phase Locked Loop, internal

VCO/VCO Divider, and loop filter), source selection, distribution system, and independent clock output channels.

The Phase Frequency Detector in PLL1 compares the divided (R Divider 1) system clock signal from the

selected CLKinX and CLKinX* input with the divided (N Divider 1) output of the external VCXO attached to the

PLL2 OSCin port. The external loop filter for PLL1 should be narrow to provide an ultra clean reference clock

from the external VCXO to the OSCin/OSCin* pins for PLL2.

Submit Documentation Feedback

25

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

The Phase Frequency Detector in PLL2 then compares the divided (R Divider 2) reference signal from the PLL2

OSCin port with the divided (N Divider 2 and VCO Divider) output of the internal VCO. The bandwidth of the

external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase

noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is passed through a

common VCO divider block and placed on a distribution path for the clock distribution section. It is also routed to

the PLL2_N counter. Each clock output channel allows the user to select a path with a programmable divider

block, a phase synchronization circuit, a programmable delay, and LVDS/LVPECL/2VPECL/LVCMOS compatible

output buffers.

Phase Detector 1 (PD1)

Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz. Since a narrow loop bandwidth should be used for

PLL1, the need to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary.

Phase Detector 2 (PD2)

Phase Detector 2 in PLL2 (PD2) supports a maximum comparison rate of 100 MHz, though the actual maximum

frequency at the input port (PLL2 OSCin/OSCin*) is 250 MHz. Operating at highest possible phase detector rate

will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter, as the in-band phase noise

from the reference input and PLL are proportional to N².

PLL2 Frequency Doubler

The PLL2 reference input at the OSCin port may be optionally routed through a frequency doubler function rather

than through the PLL2_R counter. The maximum phase comparison frequency of the PLL2 phase detector is 100

MHz, so the input to the frequency doubler is limited to a maximum of 50 MHz. The frequency doubler feature

allows the phase comparison frequency to be increased when a relative low frequency oscillator is driving the

OSCin port. By doubling the PLL2 phase comparison frequency, the in-band PLL2 noise is reduced by about 3

dB.

Inputs / Outputs

PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*)

The reference clock inputs for PLL1 may be selected from either CLKin0 and CLKin1. The user has the capability

to manually select one of the two inputs or to configure an automatic switching mode operation. A detailed

description of this function is described in the uWire programming section of this data sheet.

PLL2 OSCin / OSCin* Port

The feedback from the external oscillator being locked with PLL1 is injected to the PLL2 OSCin/OSCin* pins.

This input may be driven with either a single- ended or differential signal. If operated in single ended mode, the

unused input should be tied to GND with a 0.1 µF capacitor. Either AC or DC coupling is acceptable. Internal to

the chip, this signal is routed to the PLL1_N Counter and to the reference input for PLL2. The internal circuitry of

the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, varactor

diode and a small number of other external components may be used to implement the oscillator. The internal

oscillator circuit is enabled by setting the EN_PLL2_XTAL bit.

CPout1 / CPout2

The CPout1 pin provides the charge pump current output to drive the loop filter for PLL1. This loop filter should

be configured so that the total loop bandwidth for PLL1 is less than 200 Hz. When combined with an external

oscillator that has low phase noise at offsets close to the carrier, PLL1 generates a reference for PLL2 that is

frequency locked to the PLL1 reference clock but has the phase noise performance of the oscillator. The CPout2

pin provides the charge pump current output to drive the loop filter for PLL2. This loop filter should be configured

so that the total loop bandwidth for PLL2 is in the range of 50 kHz to 200 kHz. See the section on uWire device

control for a description of the charge pump current gain control.

26

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Fout

The buffered output of the internal VCO is available at the Fout pin. This is a single-ended output (sinusoid).

Each time the PLL2_N counter value is updated via the uWire interface, an internal algorithm is triggered that

optimizes the VCO performance.

Digital Lock Detect 1 Bypass

The VCO coarse tuning algorithm requires a stable OSCin clock (reference clock to PLL2) to frequency calibrate

the internal VCO correctly. In order to ensure a stable OSCin clock, the first PLL must achieve lock status. A

digital lock detect is used in PLL1 to monitor its lock status. After lock is achieved by PLL1, the coarse tuning

circuitry is enabled and frequency calibration for the internal VCO begins.

The (DLD_BYP) pin is provided to allow an external bypass cap to be connected to the digital lock detect 1. This

capacitor will eliminate potential glitches at initial startup of PLL1 due to unknown phase relationships between

the Ncntr1 and Rcntr1.

Bias

Proper bypassing of this pin by a 1 µF capacitor connected to V_CCis important for low noise performance.

General Programming Information

LMK040xx devices are programmed using several 32-bit registers. Each register consists of a 4-bit address field

and 28-bit data field. The address field is formed by bits 0 through 3 (LSBs) and the data field is formed by bits 4

through 31 (MSBs). The contents of each register are clocked in MSB first (bit 31), and the LSB (bit 0) last.

During programming, the LE signal should be held LOW. The serial data is clocked in on the rising edge of the

CLK signal. After the LSB (bit 0) is clocked in the LE signal should be toggled LOW-to-HIGH-to-LOW to latch the

contents into the register selected in the address field. Registers R0-R4, R7, and R8-R15 must be programmed

in order to achieve proper device operation. Figure 12 illustrates the serial data timing sequence.

MSB

D27

LSB

A0

DATAuWire

CLKuWire

LEuWire

D26

D25

D24

D23

D0

A3

A2

A1

t

CWH

CS

t

ES

t

CH

CES

t

CWL

t

EWH

Figure 12. uWire Timing Diagram

To achieve proper frequency calibration, the OSCin port must be driven with a valid signal before programming

Register 15. Changes to PLL2_R Counter or the OSCin port signal require Register 15 to be reloaded in order to

activate the frequency calibration process.

Recommended Programming Sequence

The recommended programming sequence involves programming R7 with the reset bit set to 1 (Reg. 7, bit 4) to

ensure the device is in a default state. If R7 is programmed again, the reset bit should be set to 0. Registers are

programmed in order with R15 being the last register programmed. An example programming sequence is

shown below:

•

Program R7 with the RESET bit = 1 (b4 = 1). This ensures that the device is configured with default settings.

When RESET = 1, all other R7 bits are ignored.

–

- If R7 is programmed again during the initial configuration of the device, the RESET bit should be cleared

(b4 = 0)

•

Program R0 through R4 as necessary to configure the clock outputs as desired. These registers configure

clock channel functions such as the channel multiplexer output selection, divide value, delay value, and

enable/disable bit.

Submit Documentation Feedback

27

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

•

Program R5 and R6 with the default values shown in the register map on the following pages.

Program R7 with RESET = 0.

Program R8 through R10 with the default values shown in the register map on the following pages.

Program R11 to configure the reference clock inputs (CLKin0 and CLKin1).

–

- type, LOS timeout, LOS type, and mode (manual or auto-switching)

Program R12 to configure PLL1.

- Charge pump gain, polarity, R counter and N counter

•

–

Program R13 through R15 to configure PLL2 parameters, crystal mode options, and certain globally asserted

functions.

The following table provides the register map for device programming:

28

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Default Device Register Settings After Power On/Reset

Table 4 illustrates the default register settings programmed in silicon for the LMK040xx after power on or

asserting the reset bit.

Table 4. Default Device Register Settings after Power On/Reset

Field Name

Default

Value

Default State

Field Description

Register

Bit Location

(MSB:LSB)

(decimal)

CLKoutX_PECL_LVL

0

2VPECL disabled This bit sets LVPECL clock level. Valid when

the clock channel is configured as

R0 to R4

23

LVPECL/2VPECL; otherwise, not relevant.

CLKoutXB_STATE

CLKoutXA_STATE

EN_CLKoutX

0

1

0

Inverted

This field sets the state of output B of an

LVCMOS Clock channel.

R1 to R3

R0 to R4

22:21

20:19

16

Non-Inverted

This field sets the state of output A of an

LVCMOS Clock channel.

OFF

Clock Channel enable bit. Note: The state of

CLKout2 is ON by default.

(1)

Reserved Registers

RC_DLD1_Start

R5,R6,R8

R9,R10

NA

1

Enabled

Forces the VCO tuning algorithm state

machine to wait until PLL1 is locked.

R10

29

CLKin1_BUFTYPE

CLKin0_BUFTYPE

LOS_TIMEOUT

1

MOS mode

3 MHz (min.)

CLKin1 Input Buffer Type

CLKin0 Input Buffer Type

R11

11

10

Selects Lower Reference Clock input

frequency for LOS Detection.

9:8

(2)

LOS_TYPE

3

0

1

CMOS

CLKin0

Selects LOS output type

R11

R12

7:6

5:4

31

CLKin_SEL

Selects Reference Clock source

PLL1 CP Polarity

Positive polarity

Selects the charge pump output polarity, i.e.,

the tuning slope of the external VCXO

PLL1_CP_GAIN

PLL1_R Counter

PLL1_N Counter

EN_PLL2_REF2X

6

1

0

100 µA

Divide = 1

Disabled

Sets the PLL1 Charge Pump Gain

Sets divide value for PLL1_R Counter

Sets divide value for PLL1_N Counter

R12

R13

30:28

27:16

15:4

16

Enables or disables the OSCin frequency

doubler path for the PLL2 reference input

EN_PLL2_XTAL

0

OFF

Enables or Disables internal circuits that

support an external crystal driving the OSCin

pins

R13

21

EN_Fout

0

1

0

OFF

Enables or disables the VCO output buffer

Global enable or disable for output clocks

R13

20

18

17

CLK Global Enable

POWER DOWN

Enabled

Disabled (device is Device power down control

active)

PLL2 CP TRI-STATE

PLL1 CP TRI-STATE

0

TRI-STATE

disabled

Enables or disables TRI-STATE for PLL2

Charge Pump

R13

15

14

TRI-STATE

disabled

Enables or disables TRI-STATE for PLL1

Charge Pump

OSCin_FREQ

PLL_MUX

200

31

1

200 MHz

Reserved

Divide = 1

1600 µA

Source frequency driving OSCin port

Selects output routed to LD pin

Sets Divide value for PLL2_R Counter

Sets PLL2 Charge Pump Gain

R14

R15

28:21

20:16

15:4

PLL2_R Counter

PLL2_CP_GAIN

VCO_DIV

2

27:26

25:22

21:4

2

Divide = 2

Divide = 1

Sets divide value for VCO output divider

Sets PLL2_N Counter value

PLL2_N Counter

1

(1) These registers are reserved. The Power On/Reset values for these registers are shown in the register map and should not be changed

during programming.

(2) If the CLKin_SEL value is set to either [0,0] or [0,1], the LOS_TYPE field should be set to [0,0].

Submit Documentation Feedback

31

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Register R0 To R4

Registers R0 through R4 control the five clock outputs. Register R0 controls CLKout0, Register R1 controls

CLKout1, and so on. Aside from this, the functions of the bits in these registers are identical. The X in

CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be

from 0 to 4.

CLKoutX_DIV: Clock Channel Divide Registers

Each of the five clock output channels (0 though 4) has a dedicated 8-bit divider followed by a fixed divide by 2

that is used to generate even integer related versions of the distribution path clock frequency (VCO Divider

output). If the VCO Divider value is even then the Channel Divider may be bypassed (See CLK Output Mux),

giving an effective divisor of 1 while preserving a 50% duty cycle output waveform.

Table 5. CLKoutX_DIV: Clock Channel Divide Values

CLKoutX_DIV [ 7:0 ]

Total Divide Value

b7

0

-

b6

0

-

b5

0

-

b4

0

-

b3

0

b2

0

1

-

b1

0

1

0

-

b0

0

1

0

1

0

1

-

invalid

0

2

4

0

6

0

8

0

10

-

--

1

510

EN_CLKoutX: Clock Channel Output Enable

Each Clock Output Channel may be either enabled or disabled via the Clock Output Enable control bits. Each

output enable control bit is gated with the Global Output Enable input pin (GOE) and Global Output Enable bit

(EN_CLKout_Global). The GOE pin provides an internal pull-up so that if it is unterminated externally, the clock

output states are determined by the Clock Output Enable Register bits. All clock outputs can be set to the low

state simultaneously if the GOE pin is pulled low by an external signal. If EN_CLKout_Global is programmed to 0

all outputs are turned off. If both GOE and EN_CLKout_Global are low the clock outputs are turned off.

Table 6. EN_CLKoutX: Clock Channel Output Enable Control Bits

BIT NAME

EN_CLKout0

EN_CLKout1

EN_CLKout2

EN_CLKout3

EN_CLKout4

EN_CLKout_Global

BIT = 1

ON

BIT = 0

DEFAULT

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

-

ON

According to individual channel

settings

All EN_CLKout X = OFF

Note the default state of CLKout2 is ON after power on or RESET assertion. The nominal frequency is 62 MHz

(LMK040x1) or 81 MHz (LMK040x3). This is based on a channel divide value of 12 and default VCO_DIV value

of 2. If an active CLKout2 at power on is inappropriate for the user’s application, the following method can be

employed to shut off CLKout2 during system initialization:

When the device is powered on, holding the GOE pin LOW will disable all clock outputs. The device can be

programmed while the GOE is held LOW. The state of CLKout2 can be altered during device programming

according to the user’s specific application needs. After device configuration is complete, the GOE pin should

be set HIGH to enable the active clock channels.

32

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

CLKoutX_DLY: Clock Channel Phase Delay Adjustment

Each output channel has an output delay register that can be used to introduce a lag relative to the distribution

path frequency (VCO Divider output). These registers support a 150 ps stepsize and range from 0 to 2.25 ns of

total delay. When the channel phase delay registers are enabled, a nominal fixed delay of 300 ps of delay is

incurred in addition to the programmed delay. The Channel Phase Delay Adjustment Registers are 4 bits wide

and are programmed as follows:

Table 7. CLKoutX_DLY: Clock Channel Delay Control Bit Values

CLKoutX_DLY [ 3:0 ]

DELAY (ps)

b3

0

1

b2

0

1

0

1

b1

0

1

0

1

0

1

0

1

b0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

150

300

450

600

750

900

1050

1200

1350

1500

1650

1800

1950

2100

2250

CLKoutX/CLKoutX* LVCMOS Mode Control

For clock outputs that are configured as LVCMOS, the LVCMOS CLKoutX/CLKoutX* outputs can be

independently configured by uWire CLKoutXA_STATE and CLKoutXB_STATE bits. The following choices are

available for LVCMOS outputs:

Table 8. CLKoutXA_STATE, CLKoutXB_STATE Control Bits for LVCMOS Modes

CLKoutXA_STATE

CLKoutXB_STATE

LVCMOS Modes

b1

0

b0

0

b1

0

b0

0

Inverted

Normal

0

1

0

1

0

1

0

Low

1

TRI-STATE

CLKoutX/CLKoutX* LVPECL Mode Control

Clock outputs designated as LVPECL can be configured in one of two possible output levels. The default mode

is the common LVPECL swing of 800 mVp-p single-ended (1.6 Vp-p differential). A second mode, 2VPECL, can

be enabled in which the swing is increased to 1000 mVp-p single-ended (2 Vp-p differential).

Table 9. LVPECL Output Format Control

CLKoutX_PECL_LVL

Output Format

LVPECL (800 mVpp)

2VPECL (1000 mVpp)

0

1

Submit Documentation Feedback

33

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

CLKoutX_MUX: Clock Output Mux

The output of each CLKoutX channel pair is controlled by its' channel multiplexer (mux). The mux can select

between several signals: bypassed, divided only, divided and delayed, or delayed only.

Table 10. CLKoutX_MUX: Clock Channel Multiplexer Control Bits

CLKout_MUX [1:0]

Clock Mode

b1

0

b0

0

Bypassed

Divided

0

1

0

Delayed

1

Divided and Delayed

Registers 5, 6

These registers are reserved. These register values should not be modified from the values shown in the register

map.

Register 7

Reset bit

This bit is only in register R7. The use of this bit is optional and it should be set to '0' if not used. Setting this bit

to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit.

Registers 8, 9

These registers are reserved. These register values should not be modified from the values shown in the register

map.

Register 10

RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit

This bit is used to control the state machine for the PLL2 VCO tuning algorithm. The following table describes the

function of this bit.

Table 11. RC_DLD1_Start bit States

RC_DLD1_Start

Description

1

0

The PLL2 VCO tuning algorithm trigger is delayed until PLL1 Digital Lock Detect is valid.

The PLL2 VCO tuning algorithm runs immediately after any PLL2_N counter update, despite the state of PLL1

Digital Lock Detect.

If the user is unsure of the state of the reference clock input at startup of the LMK040xx device, setting

RC_DLD1_Start = 0 will allow PLL2 to tune and lock the internal VCO to the oscillator attached to the OSCin

port. This ensures that the active clock outputs will start up at frequencies close to their desired values. The error

in clock output frequency will depend on the open loop accuracy of the oscillator driving the OSCin port. The

frequency of an active clock output is normally given by:

F_OSCin

N

R

À

F_CLK

=

(VCO_DIV À CLK_DIV)

If the open loop frequency accuracy of the external oscillator (either a VCXO or crystal based oscillator) is "X"

ppm, then the error in the output clock frequency (F_CLKerror) will be:

X À F_OSCin

N

R

À

F_CLKerror =

(VCO_DIV À CLK_DIV)

34

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Setting this bit to 0 does not prevent PLL1 from locking the external oscillator to the reference clock input after

the latter input becomes valid.

Register 11

CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control

The user may choose between one of two input buffer modes for the PLL1 reference clock inputs: either bipolar

junction differential or MOS. Both CLKinX and CLKinX* input pins must be AC coupled when driven differentially.

In single ended mode, the CLKinX* pin must be coupled to ground through a capacitor. The active CLKinX buffer

mode is selected by the CLKinX_TYPE bits programmed via the uWire interface.

Table 12. PLL1 CLKinX_BUFTYPE Mode Control Bits

b1

0

b0

0

CLKin1_TYPE

BJT Differential

MOS

CLKin0_TYPE

BJT Differential

MOS

0

1

0

BJT Differential

MOS

1

MOS

CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits

This register allows the user to set the reference clock input that is used to lock PLL1, or to select an auto-

switching mode. The automatic switching modes are revertive or non-revertive. In either revertive or non-

revertive mode, CLKin0 is the initial default reference source for the auto-switching mode. When revertive mode

is active, the switching control logic will always select CLKin0 as the reference if it is active, otherwise it selects

CLKin1. When non-revertive mode is active, the switching logic will only switch the reference input if the currently

selected input fails.

Table 13 illustrates the control modes. Modes [1,0] and [1,1] are the auto-switching modes. The behavior of both

modes is tied to the state of the LOS signals for the respective reference clock inputs.

If the reference clock inputs are active prior to configuration of the device, then the normal programming

sequence described under General Programming Information can be used without modification. If it cannot be

guaranteed that the reference clocks are active prior to device programming, then the device programming

sequence should be modified in order to ensure that CLKin0 is selected as the default. Under this scenario, the

device should be programmed as described in General Programming Information, with CLKin_SEL bits

programmed to [0,0] in register R11. The other R11 fields for clock type and LOS timeout should be programmed

with the appropriate values for the given application. After the reference clock inputs have started, register R11

should be programmed a second time with the CLKin_SEL field modified to the set the desired mode. The clock

type field and LOS field values should remain the same.

Table 13. CLKin_SEL: Reference Clock Selection Bits

CLKin_SEL [1:0]

Function

b1

0

b0

0

Force CLKin0 / CLKin0* as PLL1 reference

0

1

Force CLKin1 / CLKin1* as PLL1 reference

1

0

Non-revertive. Auto-switching. CLKin0 is the default reference clock. If CLKin0 fails, CLKin1

is automatically selected if active. If CLKin0 restarts, CLKin1 remains as the selected

reference clock unless it fails, then CLKin0 is re-selected.

1

Revertive. Auto-switching. CLKin0 is the preferred reference clock and is selected when

active.

CLKinX_LOS

The CLKin0_LOS and CLKin1_LOS pins indicate the state of the respective PLL1 CLKinX reference input when

the CLKin_SEL bits are set set to either [1,0] or [1,1]. The detection logic that determines the state of the

reference inputs is sensitive to the frequency of the reference inputs and must be configured to operate with the

appropriate frequency range of the reference inputs, as described in the next section.

Submit Documentation Feedback

35

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

PLL1 Reference Clock LOS Timeout Control

This register is used to tune the LOS timeout based upon the frequency of the reference clock input(s). The

register value controls the timeout setting for both CLKin0 and CLKin1. The value programmed in the

LOS_TIMEOUT register represents the minimum input frequency for which loss of signal can be detected. For

example, if the reference input frequency is 12.288 MHz, then either register values (0,0) or (0,1) will result in

valid loss of signal detection. If the reference input frequency is 1 MHz, then only the register value (0,0) will

result in valid detection of signal loss.

Table 14. Reference Clock LOS Timeout Control Bits

b1

0

b0

0

Corresponding Minimum Input Frequency

1 MHz

3.0 MHz

13 MHz

32 MHz

0

1

0

1

LOS Output Type Control

The output format of the LOS pins may be selected as active CMOS, open drain NMOS and open drain PMOS,

as shown in the following table.

Table 15. Loss of Signal (LOS) Output Pin Format Type

LOS_TYPE [1:0]

Functional Description

b1

0

b0

0

Reserved

0

1

NMOS open drain

PMOS open drain

Active CMOS

1

0

1

The LOS output signal is valid only when CLKin_SEL bits are set to either [1,0] or [1,1]. If the CLKin_SEL field is

programmed to either of the fixed inputs, [0,0] or [0,1], the LOS_TYPE bits should be set to [0,0].

Register 12

PLL1_N: PLL1_N Counter

The size of the PLL1_N counter is 12 bits. This counter will support a maximum divide ratio of 4095 and

minimum divide ratio of 1. The 12 bit resolution is sufficient to support minimum phase detector frequency

resolution of approximately 50 kHz when the VCXO frequency is 200 MHz.

For a 200 MHz external VCXO, the minimum phase detector rate will be PDmin = 200 MHz/4095 = 48.84 kHz

Table 16. PLL1_N Counter Values

N [17:0]

b5

VALUE

b11

0

b10

0

...

b6

0

.

b4

0

.

b3

0

.

b2

0

.

b1

0

1

.

b0

0

1

0

.

0

.

Not Valid

0

1

2

0

...

1

4095

36

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

PLL1_R: PLL1_R Counter

The size of the PLL1_R counter is 12 bits. This counter will support a maximum divide ratio of 4095 and

minimum divide ratio of 1.

Table 17. PLL1_R Counter Values

R [11:0]

VALUE

b11

b10

b9

0

.

b8

0

.

b7

0

.

b6

0

.

b5

0

.

b4

0

.

b3

0

.

b2

0

.

b1

0

.

b0

0

1

.

0

.

0

.

Not Valid

1

...

1

4095

PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL)

The Loop Band Width (LBW) on PLL1 should be narrow to suppress the noise from the system or input clocks at

CLKinX/CLKinX* port. This configuration allows the noise of the external VCXO to dominate at low offset

frequencies. Given that the noise of the external VCXO is far superior than the noise of PLL1, this setting

produces a very clean reference clock to PLL2 at the OSCin port.

In order to achieve a LBW as low as 10 Hz at the supported VCXO frequency (1 MHz to 200 MHz), a range of

charge pump currents in PLL1 is provided. The table below shows the available current gains. A small charge

pump current is required to obtain a narrow LBW at high phase detector rate (small N value).

Table 18. PLL1 Charge Pump Current Selections (PLL1_CP_GAIN)

PLL1_CP_GAIN [2:0]

PLL1 Charge Pump Current Magnitude (µA)

b2

0

b1

0

b0

0

RESERVED

0

1

RESERVED

0

1

0

20

80

0

1

0

25

1

0

1

50

1

0

100

400

1

The PLL1_CP_POL bit sets the PLL1 charge pump for operation with a positive or negative slope VCO/VCXO. A

positive slope VCO/VCXO increases frequency with increased tuning voltage. A negative slope VCO/VCXO

increases frequency with decreased tuning voltage.

Table 19. PLL1 Charge Pump Polarity Control Bits (PLL1_CP_POL)

PLL1_CP_POL

DESCRIPTION

0

1

Negative Slope VCO/VCXO

Positive Slope VCO/VCXO

Register 13

EN_PLL2_XTAL: Crystal Oscillator Option Enable

If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be

enabled in order to complete the oscillator circuit.

Submit Documentation Feedback

37

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Table 20. EN_PLL2_XTAL: External Crystal Option

EN_PLL2_XTAL

Oscillator Amplifier State

0

1

OFF

ON

EN_Fout: Fout Power Down Bit

The EN_Fout bit allows the Fout port to be enabled or disabled. By default EN_Fout = 0.

CLK Global Enable: Clock Global enable bit

In addition to the external GOE pin, an internal Register 13 bit (b18) can be used to globally enable/disable the

clock outputs via the uWire programming interface. The default value is 1. When CLK Global Enable = 1, the

active output clocks are enabled. The active output clocks are disabled if this bit is 0.

POWERDOWN Bit -- Device Power Down

This bit can power down the entire device. Enabling this bit powers down the entire device and all functional

blocks, regardless of the state of any of the other bits or pins.

Table 21. Power Down Bit Values

POWERDOWN Bit

Mode

0

1

Normal Operation

Entire device powered down

EN_PLL2 REF2X: PLL2 Frequency Doubler control bit

When F_OSCinis below 50 MHz, the PLL2 frequency doubler can be enabled by setting EN_PLL2_REF2X = 1. The

default value is 0. When EN_PLL2_REF2X = 1, the signal at the OSCin port bypasses the PLL2_R counter and

is passed through a frequency doubler circuit. The output of this circuit is then input to the PLL2 phase

comparator block. This feature allows the phase comparison frequency to be increased for lower frequency

OSCin sources (< 50 MHz), and can be used with either VXCOs or crystals. For instance, when using a pullable

crystal of 12.288 MHz to drive the OSCin port, the PLL2 phase comparison frequency is 24.576 MHz when

EN_PLL2_REF2X = 1. A higher PLL phase comparison frequency reduces PLL2 in-band phase noise and RMS

jitter. The PLL in-band phase noise can be reduced by approximately 2 to 3 dB. The on-chip loop filter typically is

enabled to reduce PLL2 reference spurs when EN_PLL2_REF2X is enabled. Suggested values in this case are:

R3 = 600 Ω, C3 = 50 pF, R4 = 10 kΩ, C4 = 60 pF.

PLL2 Internal Loop Filter Component Values

Internal loop filter components are available for PLL2, enabling the user to implement either 3rd or 4th order loop

filters without requiring external components. The user may select from a fixed set of values for both the resistors

and capacitors. Internal loop filter resistance values for R3 and R4 can be set individually according to Table 22

and Table 23.

Table 22. PLL2 Internal Loop Filter Resistor Values, PLL2_R3_LF

PLL2_R3_LF [2:0]

RESISTANCE

b2

0

b1

0

b0

0

< 600 Ω

10 kΩ

20 kΩ

30 kΩ

40 kΩ

Invalid

0

1

0

1

0

1

0

1

0

1

0

1

38

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Table 23. PLL2 Internal Loop Filter Resistor Values, PLL2_R4_LF

PLL2_R4_LF [2:0]

RESISTANCE

b2

0

b1

0

b0

0

< 200 Ω

10 kΩ

20 kΩ

30 kΩ

40 kΩ

Invalid

0

1

0

1

0

1

0

1

0

1

0

1

Internal loop filter capacitors for C3 and C4 can be set individually according to the following table.

Table 24. PLL2 Internal Loop Filter Capacitor Values

PLL2_C3_C4_LF [3:0]

Loop Filter Capacitance(pF)

b3

0

1

b2

0

1

0

1

b1

0

1

0

1

0

1

0

1

b0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C3 = 0, C4 = 10

C3 = 0, C4 = 60

C3 = 50, C4 = 10

C3 = 0, C4 = 110

C3 = 50, C4 = 110

C3 = 100, C4 = 110

C3 = 0, C4 = 160

C3 = 50, C4 = 160

C3 = 100, C4 = 10

C3 = 100, C4 = 60

C3 = 150, C4 = 110

C3 = 150, C4 = 60

Reserved

PLL1 CP TRI-STATE and PLL2 CP TRI-STATE

The charge pump output of either CPout1 or CPout2 may be placed in a TRI-STATE mode by setting the

appropriate PLLx CP TRI-STATE bit.

Table 25. PLL1 Charge Pump TRI-STATE bit values

PLL1 CP TRI-STATE

Description

1

0

PLL1 CPout1 is at TRI-STATE

PLL1 CPout1 is active

Table 26. PLL2 Charge Pump TRI-STATE bit values

PLL2 CP TRI-STATE

Description

1

0

PLL2 CPout2 is at TRI-STATE

PLL2 CPout2 is active

Submit Documentation Feedback

39

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Register 14

OSCin_FREQ: PLL2 Oscillator Input Frequency Register

The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be

programmed in order to support proper operation of the internal VCO tuning algorithm. This is an 8-bit register

that sets the frequency to the nearest 1-MHz increment.

Table 27. OSCin_FREQ Register Values

OSCin_FREQ [7:0]

VALUE

b7

0

b6

0

.

b5

0

.

b4

0

.

b3

0

.

b2

0

.

b1

0

1

.

b0

0

1

0

.

Not Valid

1 MHz

2 MHz

...

0

1

.

1

.

1

0

.

1

0

.

1

.

0

.

1

0

.

0

1

.

250 MHz

Not Valid

.

1

Not Valid

PLL2_R: PLL2_R Counter

The PLL2 R Counter is 12 bits wide. It divides the PLL2 OSCin/OSCin* clock and is connected to the PLL2

Phase Detector.

Table 28. PLL2_R: PLL2_R Counter Values

R [11:0]

VALUE

b11

0

b10

0

b9

0

b8

0

b7

0

b6

0

b5

0

b4

0

b3

0

b2

0

b1

0

b0

0

Not Valid

0

1

...

.

1

4095

PLL_MUX: LD Pin Selectable Output

The signal appearing on the LD pin is programmable via the uWire interface and provides access to several

internal signals which may be valuable for either status monitoring during normal operation or for debugging

during the hardware development phase. This pin may be forced to either a HIGH or LOW state, and may also

be configured as specified in Table 29.

40

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Table 29. PLL_MUX: LD Pin Selectable Outputs

PLL_MUX [4:0]

LD Output

b4

0

1

b3

0

1

0

1

b2

0

1

0

1

0

1

0

1

b1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

b0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HiZ

Logic High

Logic Low

PLL2 Digital Lock Detect Active High

PLL2 Digital Lock Detect Active Low

PLL2 Analog Lock Detect Push Pull

PLL2 Analog Lock Detect Open Drain NMOS

PLL2 Analog Lock Detect Open Drain PMOS

Reserved

PLL2_N Divider Output / 2

Reserved

PLL2_R Divider Output / 2

Reserved

PLL1 Digital Lock Detect Active HIGH

PLL1 Digital Lock Detect Active LOW

Reserved

PLL1_N Divider Output / 2

Reserved

PLL1_R Divider Output / 2

PLL1 and PLL2 Digital Lock Detect

Inverted PLL1 and PLL2 Digital Lock Detect

Reserved

Submit Documentation Feedback

41

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Register 15

PLL2_N: PLL2_N Counter

The PLL2_N Counter is 18 bits wide. It divides the output of the VCO Divider and is connected to the PLL2

Phase Detector. Each time the PLL2_N Counter value is updated via the uWire interface, an internal algorithm is

triggered that optimizes the VCO performance.

Table 30. PLL2_N: PLL2_N Counter Values

N [17:0]

VALUE

b17

0

b16

0

...

b6

0

.

b5

0

.

b4

0

.

b3

0

.

b2

0

.

b1

0

1

.

b0

0

1

0

.

Not Valid

0

1

0

2

...

1

262143

PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control

The PLL2 charge pump output current level is controlled with the PLL2_CP_GAIN register. The following table

presents the charge pump current control values.

Table 31. PLL2_CP_GAIN: PLL2 Charge Pump Current Selections

PLL2_CP_GAIN [1:0]

CP_TRI

Charge Pump Current (µA)

b1

X

0

b0

X

0

1

0

Hi-Z

100

0

1

400

1

0

1600

3200

1

VCO_DIV: PLL2 VCO Divide Register

A divider is provided on the output of the PLL2 VCO to enable a wide range of output clock frequencies. The

output of this divider is placed on the input path for the clock distribution section, which feeds each of the

individual clock channels. The divider provides integer divide ratios from 2 to 8.

Table 32. VCO_DIV: PLL2 VCO Divider Values

VCO_DIV [3:0]

Divide Value

b3

0

b2

0

b1

0

b0

0

Invalid

0

1

Invalid

0

1

0

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

42

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

APPLICATION INFORMATION

System Level Diagram

The following diagram illustrates the typical interconnection of the LMK040xx in a clocking application.

0.1 mF

120Ö

To

System

0.1 mF

120Ö

0.1 mF

To

System

To

System

120Ö

Vcc

1 mF

100 pF

Bias

Fout

To

System

PLL2 Loop Filter

CPout2

51Ö

LD

(optional)

GOE

0.1 uF

OSCin*

OSCin

LEuWire

CLKuWire

DATAuWire

To Host

LMK040xx

0.1 mF

R

term

VCXO

SYNC*

CLKin1*

CLKin1

To Host

0.1 mF

LDObyp1

100 Ö

LDObyp2

0.1 mF

Reference Clock #2

(Secondary)

0.1 mF

10 mF

PLL1 Loop Filter

0.1 mF

0.47 mF

100Ö

To

System

Reference Clock #1

(Primary)

Figure 13. Typical Application

Figure 13 shows an LMK04000 family device with external circuitry. The primary reference clock input is at

CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled differential

drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any

of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-

ended. These options are discussed later in the data sheet.

The diagram shows an optional connection between the LD pin and GOE. With this arrangement, the LD pin can

be programmed to output a lock detect signal that is active HIGH (see Table 29 for optional LD pin outputs). If

lock is lost, the LD pin will transition to a LOW, pulling GOE low and causing all clock outputs to be disabled.

This scheme should be used only if disabling the clock outputs is desirable when lock is lost.

Submit Documentation Feedback

43

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

The loop filter for PLL2 consists of three external components that implement two lower order poles, plus optional

internal integrated components if 3rd or 4th order poles are needed. The loop filter components for PLL1 must be

external components.

The VCO output buffer signal that appears at the Fout pin when enabled (EN_Fout = 1) should be AC coupled

using a 100 pF capacitor. This output is a single-ended signal by default. If a differential signal is required, a 50

Ω balun may be connected to this pin to convert it to differential.

The clock outputs are all AC coupled with 0.1 µF capacitors. CLKout1 and CLKout3 are depicted as LVPECL,

with 120 Ω emitter resistors as source termination. However, the output format of the clock channels will vary by

device part number, so the designer should use the appropriate source termination for each channel. Later

sections of this data sheet illustrate alternative methods for AC coupling, DC coupling and terminating the clock

outputs.

LDO Bypass And Bias Pin

The LDObyp1 and LDObyp2 pins should be connected to GND through external capacitors, as shown in the

diagram. Furthermore, the Bias pin should be connected to V_CCthrough a 1 µF capacitor in series.

Loop Filter

Each PLL of the LMK04000 family requires a dedicated loop filter. The loop filter for PLL1 must be connected to

the CPout1 pin. Figure 14 shows a simple 2-pole loop filter. The output of the filter drives an external VCXO

module or discrete implementation of a VCXO using a crystal resonator. Higher order loop filters may be

implemented using additional external R and C components. It is recommended the loop filter for PLL1 result in a

total closed loop bandwidth in the range of 10 Hz to 200 Hz. The design of the loop filter is application specific

and highly dependent on parameters such as the phase noise of the reference clock, VCXO phase noise, and

phase detector frequency for PLL1. National’s Clock Conditioner Owner’s Manual covers this topic in detail and

National’s Clock Design Tool can be used to simulate loop filter designs for both PLLs. These resources may be

found: http://www.national.com/timing/.

As shown in the diagram, the charge pump for PLL2 is directly connected to the optional internal loop filter

components, which are normally used only if either a third or fourth pole is needed. The first and second poles

are implemented with external components. The loop must be designed to be stable over the entire application-

specific tuning range of the VCO. The designer should note the range of K_VCOlisted in the table of Electrical

Characteristics and how this value can change over the expected range of VCO tuning frequencies. Because

loop bandwidth is directly proportional to K_VCO, the designer should model and simulate the loop at the expected

extremes of the desired tuning range, using the appropriate values for K_VCO

.

When designing with the integrated loop filter of the LMK04000 family, considerations for minimum resistor

thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4.

Both the integrated loop filter resistors and capacitors (C3 and C4) also restrict the maximum loop bandwidth.

However, these integrated components do have the advantage that they are closer to the VCO and can therefore

filter out some noise and spurs better than external components. For this reason, a common strategy is to

minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a

wide enough loop bandwidth. In situations where spurs requirements are very stringent and there is margin on

phase noise, it might make sense to design for a loop filter with integrated resistor values larger than their

minimum value.

44

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

LMK040xx

Internal VCO

PLL2 Internal Loop Filter

R3 R4

PLL2

Phase

Detector

C3

C4

C2

PLL2 External Loop

Filter

C1

R2

LMK040xx

External VCXO

PLL1

Phase

CPout1

Detector

C2

C1

R2

PLL1 External Loop

Filter

Figure 14. Loop Filter

Table 33. Typical Current Consumption for Selected Functional Blocks

Power

Dissipated in

LVPECL/2VPECL

Emitter

Typical I_CC

(Temp = 25 °C,

V_CC= 3.3 V)

(mA)

Power

Dissipated in

device

Block

Condition

(mW)

Resistors

(mW)

Single input clock (CLKIN_SEL = 0 or 1); LOS disabled;

PLL1 and PLL2 locked; All CLKouts are off; No LVPECL

emitter resistors connected

Entire device,

core current

115

380

-

REFMUX

LOS

Enable auto-switch mode (CLKIN_SEL = 2 or 3)

Enable LOS (LOS_TYPE = 1, or 2, or 3)

4.3

3.6

14

12

-

Low Channel

Internal Buffer

The low channel internal buffer is enabled when CLKout0 is

enabled

10

33

-

High Channel

Internal Buffer

The high channel internal buffer is enabled when one of

CLKout1 through CLKout4 is enabled

Divider bypassed (CLKout_MUX = 0, 2)

Divider enabled, divide = 2 (CLKout_MUX = 1, 3)

Divider enabled, divide > 2 (CLKout_MUX = 1, 3)

Delay bypassed (CLKout_MUX = 0, 1)

Delay enabled, delay < 8 (CLKout_MUX = 2, 3)

Delay enabled, delay > 7 (CLKout_MUX = 2, 3)

EN_Fout = 1

0

-

Divide circuitry

per output

5.3

8.5

0

17

28

0

Delay circuitry per

output

5.8

9.9

14.5

19.3

19

33

48

64

Fout Buffer

LVDS Buffer

LVDS buffer, enabled

Submit Documentation Feedback

45

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Power

Table 33. Typical Current Consumption for Selected Functional Blocks (continued)

Typical I_CC

(Temp = 25 °C,

V_CC= 3.3 V)

(mA)

Power

Dissipated in

device

Dissipated in

LVPECL/2VPECL

Emitter

Block

Condition

(mW)

Resistors

(mW)

LVPECL/2VPECL buffer (enabled and with 120 Ω emitter

resistors)

40

82

47

50

25

LVPECL/2VPECL

Buffer

LVPECL/2VPECL buffer (disabled and with 120 Ω emitter

resistors)

21.7

LVPECL/2VPECL (disabled and with no emitter resistors)

LVCMOS buffer static I_CC, C_L= 5 pF

0

-

4.5

15

LVCMOS Buffer

(1)

LVCMOS buffer dynamic I_CC, C_L= 5 pF, CLKout = 100

MHz

16

53

-

(2) (3)

Entire device

LMK0400x

379.5

377.5

1102

996

150

250

(Single input clock

(CLKIN_SEL = 0

or 1); LOS

(2) (3)

LMK0401x

(2) (3)

LMK0403x

disabled; PLL1

and PLL2 locked;

Fout disabled; All

CLKouts are on;

No delay); Divide

> 2 on each

337.1

1012

100

output.

(1) Dynamic power dissipation of LVCMOS buffer varies with output frequency and can be found in the LVCMOS dynamic I_CCvs frequency

plot, as shown in Typical Performance Characteristics. Total power dissipation of the LVCMOS buffer is the sum of static and dynamic

power dissipation. CLKoutXa and CLKoutXb are each considered an LVCMOS buffer.

(2) Assuming ThetaJ = 27.4 °C/W, the total power dissipated on chip must be less than 40/27.4 = 1450 mW to guarantee a junction

temperature is less than 125 °C.

(3) Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.2.

Current Consumption / Power Dissipation Calculations

Due to the myriad of possible configurations the following table serves to provide enough information to allow the

user to calculate estimated current consumption of the device. Unless otherwise noted V_CC= 3.3 V, T_A= 25 °C.

From Table 33 the current consumption can be calculated in any configuration. For example, the current for the

entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) output in bypassed mode can be calculated by

adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL

output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from

the current draw is dissipated in the external 120 Ω resistors which doesn't add to the power dissipation budget

for the device. If delays or divides are switched in, then the additional current for these stages needs to be added

as well.

For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device

minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter

resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of 1 LVDS

(CLKout0) & 1 LVPECL (CLKout1) operating at 3.3 V, we calculate 3.3 V × (115 + 10 + 10 + 19.3 + 40) mA = 3.3

V × 194.3 mA = 641.2 mW. Because the LVPECL output (CLKout1) has the emitter resistors hooked up and the

power dissipated by these resistors is 50 mW, the total device power dissipation is 641.2 mW - 50 mW = 591.2

mW.

When the LVPECL output is active, ~1.7 V is the average voltage on each output as calculated from the LVPECL

V_OH& V_OLtypical specification. Therefore the power dissipated in each emitter resistor is approximately (1.7 V)²/

120 Ω = 25 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the

power dissipated in each emitter resistor is approximately (1.07 V)²/ 120 Ω = 9.5 mW.

46

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Power Supply Conditioning

The recommended technique for power supply management is to connect the power pins for the clock outputs

(pins 13, 37, 40, 43, and 46) to a dedicated power plane and connect all other power pins on the device (pins 3,

8, 18, 19, 22, 24, 30, 31, and 33) to a second power plane. Note: the LMK04000 family has internal voltage

regulators for the PLL and VCO blocks to provide noise immunity.

Thermal Management

Power consumption of the LMK04000 family of devices can be high enough to require attention to thermal

management. For reliability and performance reasons the die temperature should be limited to a maximum of

125 °C. That is, as an estimate, T_A(ambient temperature) plus device power consumption times θ_JAshould not

exceed 125 °C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent

electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land

pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A

recommended land and via pattern is shown in Figure 15. More information on soldering WQFN packages can

be obtained: http://www.national.com/analog/packaging/.

5.0 mm, min

0.33 mm, typ

1.2 mm, typ

Figure 15. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground

plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite

side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but

should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in

Figure 15 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat

pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively

dissipated.

Submit Documentation Feedback

47

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

OSCin*

C

opt

C

C1

= 2.2 nF

R1 = 4.7k

SMV1249-074LF

R3 = 10k

LMK040xx

XTAL

1 nF

R2 = 4.7k

C

= 2.2 nF

C2

OSCin

C

opt

PLL1 Loop Filter

Figure 16. Reference Design Circuit for Crystal Oscillator Option

Optional Crystal Oscillator Implementation (OSCin/OSCin*)

The LMK04000 family features supporting circuitry for a discretely implemented oscillator driving the OSCin port

pins. Figure 16 illustrates a reference design circuit for a crystal oscillator:

This circuit topology represents a parallel resonant mode oscillator design. When selecting a crystal for parallel

resonance, the total load capacitance, C_L, must be specified. The load capacitance is the sum of the tuning

capacitance (C_TUNE), the capacitance seen looking into the OSCin port (C_IN), and stray capacitance due to PCB

parasitics (C_STRAY), and is given by:

C_STRAY

C_L= C_TUNE+ C_IN

+

2

C_TUNEis provided by the varactor diode shown in Figure 16, Skyworks model SMV1249-074. A dual diode

package with common cathode and provides the variable capacitance for tuning. The single diode capacitance

ranges from approximately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range of the dual package (anode to

anode) is approximately 15.5 pF at 3 V to 1.7 pF at 0.3 V. The desired value of V_TUNEapplied to the diode should

be V_CC/2, or 1.65 V for V_CC= 3.3 V. The typical performance curve from the data sheet for the SMV1249-074

indicates that the capacitance at this voltage is approximately 6 pF (12 pF/2).

The nominal input capacitance (C_IN) of the LMK04000 family OSCin pins is 6 pF. The stray capacitance (C_STRAY

)

of the PCB should be minimized by arranging the oscillator circuit layout to achieve trace lengths as short as

possible and as narrow as possible trace width (50 Ω characteristic impedance is not required). As an example,

assume that C_STRAYis 4 pF. The total load capacitance is nominally:

4

2

= 14 pF

C_L= 6 + 6 +

Consequently the load capacitance specification for the crystal in this case should be nominally 14 pF.

48

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

The 2.2 nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the

4.7 k and 10 k resistors. The value of these coupling capacitors should be large, relative to the value of C_TUNE

(C_C1= C_C2>> C_TUNE), so that C_TUNEbecomes the dominant capacitance.

For a specific value of C_L, the corresponding resonant frequency (F_L) of the parallel resonant mode circuit is:

1

+ 1

C₁

2(C₀+ C_L1

C₀

C_L

C₁

+ 1

= F_SÀ

≈

’

÷

◊

F_L= F_S

À

)

+

²∆_C

1

«

F_S= Series resonant frequency

C₁= Motional capacitance of the crystal

C_L= Load capacitance

C₀= Shunt capacitance of the crystal, specified on the crystal datasheet

The normalized tuning range of the circuit is closely approximated by:

1

-

F_CL1- F_CL2

C₁

2

1

2

1

DF

F

C₀C_L1

+

C₀C_L2

+

À

-

≈

∆

«

’ ≈

’

÷

◊

À

=

(C₀+ C_L1

)

(C₀+ C_L2)

F_FCL1

÷ ∆_C

C₁

1

◊ «

C_L1, C_L2= The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one

component of the load. F_CL1, F_CL2= parallel resonant frequencies at the extremes of the circuit’s load

capacitance range.

A common range for the pullability ratio, C₀/C₁, is 250 to 280. The ratio of the load capacitance to the shunt

capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning

range because this allows the scale factors related to the load capacitance to dominate.

Examples of the phase noise and jitter performance of the LMK04031 with a crystal oscillator are shown in

Table 34. This table illustrates the clock output phase noise when a 12.288 MHz crystal is paired with PLL1.

Table 34. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a

(1)

12.288 MHz Crystal Driving OSCin (T = 25 °C, V_CC= 3.3 V)

RMS Jitter (ps)

Integration Bandwidth

100 Hz – 20 MHz

Clock Output Type

PLL2 PDF = 12.288 MHz

(EN_PLL2_REF2X = 0)

PLL2 PDF = 24.576 MHz

(EN_PLL2_REF2X = 1)

F_CLK= 122.88 MHz

F_CLK= 153.6 MHz

0.263

F_CLK= 122.88 MHz

0.300

LVPECL

LVCMOS

LVDS

0.279

0.244

0.248

0.218

0.272

0.251

0.269

0.245

10 kHz – 20 MHz

LVPECL

LVCMOS

LVDS

0.234

0.284

0.211

0.215

0.193

0.236

0.235

0.217

Phase Noise (dBc/Hz)

Offset

Clock Output Type

PLL2 FPD = 12.288 MHz

(EN_PLL2_REF2X = 0)

PLL2 FPD = 24.576 MHz

(EN_PLL2_REF2X = 1)

F_CLK= 122.88 MHz

F_CLK= 153.6 MHz

F_CLK= 122.88 MHz

100 Hz

LVPECL

LVCMOS

LVDS

-107

-105

-106

-103

-104

-106

-104

-106

(1) Performance data and crystal specifications contained in this section are based on Ecliptek model ECX-6465, 12.288 MHz.

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

49

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Table 34. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a

12.288 MHz Crystal Driving OSCin (T = 25 °C, V_CC= 3.3 V) ⁽¹⁾(continued)

1 kHz

10 kHz

100 kHz

1 MHz

LVPECL

LVCMOS

LVDS

-126

-125

-126

-125

-127

-126

-134

-135

-134

-155

-157

-155

-158

-160

-158

-124

-123

-124

-125

-124

-133

-132

-154

-155

-153

-158

-159

-158

-130

-127

-126

-131

-128

-131

-134

-154

-155

-154

-158

-159

-157

LVPECL

LVCMOS

LVDS

LVPECL

LVCMOS

LVDS

LVPECL

LVCMOS

LVDS

10 MHz

LVPECL

LVCMOS

LVDS

Example crystal specifications are presented in Table 35.

Table 35. Example Crystal Specifications

Parameter

Value

Nominal Frequency (MHz)

12.288

Frequency Stability, T = 25 °C

Operating temperature range

Frequency Stability, -40 °C to +85 °C

Load Capacitance

± 10 ppm

-40 °C to +85 °C

± 15 ppm

14 pF

Shunt Capacitance (C₀)

Motional Capacitance (C₁)

Equivalent Series Resistance

Drive level

5 pF Maximum

20 fF ± 30%

25 Ω Maximum

2 mWatts Maximum

225 typical, 250 Maximum

C₀/C₁ratio

See Figure 17 for a representative tuning curve.

180

140

100

60

20

-20

-60

-100

-140

-180

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3

(VDC)

V

TUNE

Figure 17. Example Tuning Curve, 12.288 MHz Crystal

50

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

The tuning curve achieved in the user's application may differ from the curve shown above due to differences in

PCB layout and component selection.

This data is measured on the bench with the crystal integrated with the LMK04000 family. Using a voltmeter to

monitor the V_TUNEnode for the crystal, the PLL1 reference clock input frequency is swept in frequency and the

resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock

frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is

valid.

The curve shows over the tuning voltage range of 0.17 VDC to 3.0 VDC, the frequency range is ± 163 ppm; or

equivalently, a crystal frequency range of ± 2000 Hz. The measured tuning voltage at the nominal crystal

frequency (12.288 MHz) is 1.4 V. Using the diode data sheet tuning characteristics, this voltage results in a

tuning capacitance of approximately 6.5 pF.

The tuning curve data can be used to calculate the gain of the oscillator (K_VCO). The data used in the calculations

is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal

frequency (12.288 MHz). For a well designed circuit, this is the most likely operating range. In this case, the

tuning range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to

calculate the ratio:

DF₂- DF₁

≈

= ∆_V

«

’

DF

DV

MHz

V

÷^,

◊

K_VCO

=

_TUNE2- V_TUNE1

ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:

0.001 - (-0.001)

2.03 - 0.814

MHz

V

= 0.00164

A second method uses the tuning data in units of ppm:

F_NOMÀ (Dppm₂- Dppm₁)

DV À 10⁶

K_VCO

=

F_NOMis the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:

12.288 ^À(^{81.4 - (-81.4)})

MHz

= 0.00164,

(2.03 - 0.814) À 10⁶

V

In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal

should conform to the specifications listed in the table of Electrical Characteristics. It is also important to select a

crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator

exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and

possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the

crystal, voltage and equivalent series resistance (ESR). For more complete coverage of crystal oscillator design,

see

Application

Note

AN-1939

at

http://www.national.com/analog/timing/clocking

or

http://www.national.com/appnotes.

Termination and use of Clock Output (Drivers)

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

•

Transmission line theory should be followed for good impedance matching to prevent reflections.

Clock drivers should be presented with the proper loads. For example:

–

LVDS drivers are current drivers and require a closed current loop.

LVPECL drivers are open emitters and require a DC path to ground.

•

Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage)

for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage

level. In this case, the signal should normally be AC coupled.

Submit Documentation Feedback

51

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above

guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best

termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode

voltage). For example, when driving the OSCin/OSCin* input of the LMK04000 family, OSCin/OSCin* should be

AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 13) This is only slightly

different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the

DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains

the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage),

not the driver.

Termination for DC Coupled Differential Operation

For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as

shown in Figure 18.

CLKoutX

100W Trace

(Differential)

LVDS

Receiver

LVDS

Driver

CLKoutX*

Figure 18. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver

For DC coupled operation of an LVPECL driver, terminate with 50 Ω to V_CC- 2 V as shown in Figure 19.

Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to V_CCand an 82 Ω resistor

connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as shown in

Figure 20 for V_CC= 3.3 V.

Vcc - 2 V

CLKoutX

100W Trace

(Differential)

LVPECL

Driver

LVPECL

Receiver

CLKoutX*

Vcc - 2 V

Figure 19. Differential LVPECL Operation, DC Coupling

Vcc

CLKoutX

100W Trace

(Differential)

LVPECL

Driver

LVPECL

Receiver

CLKoutX*

Vcc

Figure 20. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent

52

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver

standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important

to ensure the receiver is biased to its ideal DC level.

When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC

blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do

this is with the termination circuitry in Figure 21.

0.1 mF

100W Trace

CLKoutX

(Differential)

LVDS

Receiver

LVDS

Driver

Vbias

CLKoutX*

0.1 mF

Figure 21. Differential LVDS Operation, AC Coupling, External Biasing at the Receiver

Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 21 is

modified by replacing the 50 Ω terminations to Vbias with a single 100 Ω resistor across the input pins of the

receiver, as shown in Figure 22. When using AC coupling with LVDS outputs, there may be a startup delay

observed in the clock output due to capacitor charging. The previous figures employ a 0.1 µF capacitor. This

value may need to be adjusted to meet the startup requirements for a particular application.

0.1 mF

100W Trace

(Differential)

LVDS

Receiver

LVDS

Driver

0.1 mF

Figure 22. LVDS Termination for a Self-Biased Receiver

LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors

close to the LVPECL driver to provide a DC path to ground as shown in Figure 23. For proper receiver operation,

the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical

DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor connected to V_CCand

a 120 Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is

a valid termination as shown in Figure 23 for V_CC= 3.3 V. Note this Thevenin circuit is different from the DC

coupled example in Figure 20.

Vcc

CLKoutX

0.1 mF

100W Trace

(Differential)

LVPECL

Receiver

LVPECL

Driver

0.1 mF

CLKoutX*

Vcc

Figure 23. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent, External Biasing at the

Receiver

Submit Documentation Feedback

53

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

Termination for Single-Ended Operation

A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an

unbalanced, single-ended signal.

It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL

driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. When DC coupling one of

the LMK04000 family clock LVPECL drivers, the termination should be 50 Ω to V_CC- 2 V as shown in Figure 24.

The Thevenin equivalent circuit is also a valid termination as shown in Figure 25 for Vcc = 3.3 V.

Vcc - 2V

CLKoutX

50W Trace

LVPECL

Driver

Vcc - 2V

Load

CLKoutX*

50W

Figure 24. Single-Ended LVPECL Operation, DC Coupling

Vcc

CLKoutX

Vcc

50W Trace

LVPECL

Driver

CLKoutX*

Load

Figure 25. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent

When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensure a

50 Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL

receivers is 2 V (See Driving CLKin Pins with a Single-Ended Source). If the companion driver is not used it

should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-

ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or

phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and

proper operation. The internal 50 Ω termination of the test equipment correctly terminates the LVPECL driver

being measured as shown in Figure 26.

CLKoutX

50W Trace

0.1 mF

LVPECL

Driver

0.1 mF

CLKoutX*

Load

Figure 26. Single-Ended LVPECL Operation, AC Coupling

54

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

DRIVING CLKin AND OSCin INPUTS

Driving CLKin Pins with a Differential Source

Both CLKin ports can be driven by differential signals. It is recommended that the input mode be set to bipolar

(CLKinX_TYPE = 0) when using differential reference clocks. The LMK04000 family internally biases the input

pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with

either LVDS or LVPECL are shown in Figure 27 and Figure 28.

Figure 27. CLKinX/X* Termination for an LVDS Reference Clock Source

Figure 28. CLKinX/X* Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sinewave output can drive the CLKin pins using the

following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in the Electrical

Characteristics table.

CLKinX

0.1 mF

100W Trace

LMK040XX

Input

(Differential)

0.1 mF

Differential

Sinewave Clock

Source

CLKinX*

Figure 29. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source

Driving CLKin Pins with a Single-Ended Source

The CLKin pins of the LMK04000 family can be driven using a single-ended reference clock source, for example,

either a sinewave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the

case of the sinewave source that is expecting a 50 Ω load, it is recommended that AC coupling be used as

shown in the circuit below with a 50 Ω termination..

NOTE

The signal level must conform to the requirements for the CLKin pins listed in the

Electrical Characteristics table. CLKinX_TYPE in Register 11 is recommended to be set to

bipolar mode (CLKinX_TYPE = 0).

Submit Documentation Feedback

55

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

0.1 mF

50W Trace

CLKinX

LMK040XX

Clock Source

CLKinX*

0.1 mF

Figure 30. CLKinX/X* Single-ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC

coupling may be used. If DC coupling is used, the CLKinX_TYPE should be set to MOS buffer mode

(CLKinX_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-

mode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_TYPE

should be set to the bipolar buffer mode (CLKinX_TYPE = 0). The voltage swing at the input pins must meet the

specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this

case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC

coupling capacitor is sufficient.

Figure 31. DC Coupled LVCMOS/LVTTL Reference Clock

Additional Outputs with an LMK04000 Family Device

The number of outputs on a LMK04000 family device can be expanded in many ways. The first method is to use

the differential outputs as two single-ended outputs. For CMOS outputs, both the positive and negative outputs

can be programmed to be in phase, or 180 degrees out of phase. LVDS/LVPECL positive and negative outputs

are always 180 degrees out of phase. LVDS single-ended is not recommended.

In addition to this technique, the number of outputs can be expanded with a LMK01000 family device. To do this,

one of the clock outputs of a LMK04000 can drive the LMK01000 device.

For more information on phase synchronization with multiple devices, please refer to application note AN-1864:

http://www.national.com/an/AN/AN-1864.pdf.

Output Clock Phase Noise Performance VS. VCXO Phase Noise

The jitter cleaning capability of the LMK04000 family is highly dependent on the phase noise performance of the

VCXO (or crystal) that is integrated with PLL1. The VCXO is the reference for PLL2 which provides the clock for

the output distribution path. Consequently, the designer must choose a VCXO (or crystal) that supports the

required performance at the clock outputs.

An example of the difference in performance that can be obtained from various VCXOs is illustrated in the

following plots. Figure 32 compares the phase noise of two different VCXOs: VCXO “A” and VCXO “B”. Both

VCXOs have a center frequency of 100 MHz. The figure of merit, RMS jitter, is measured over the bandwidth

100 Hz to 200 kHz. This is the most relevant integration bandwidth for the VCXO because it will have the most

impact inside the loop bandwidth of PLL2.

56

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

www.ti.com

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

ë/óh ^!_

ë/óh ^._

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 32. VCXO Phase Noise Comparison, 100 MHz

This plot shows that VCXO “B” exhibits superior phase noise when compared to VCXO “A”. Both VCXOs offer

excellent jitter performance from 100 Hz to 200 kHz. VCXO “A” exhibits RMS jitter of 151 femtoseconds (fs),

while VCXO “B” has RMS jitter of 90 fs.

Figure 33 Figure 34 Figure 35 present a side-by-side comparison of clock output phase noise at 250 MHz,

organized by output format and associated VCXO. The total RMS jitter listed on the plots is integrated from 100

Hz to 20 MHz. Examining these plots, the clock output phase noise associated with VCXO “B” is superior in all

cases. The average improvement in RMS jitter due to VCXO “B” is approximately 47 fs. The plots show the

primary difference in clock output phase noise is in the band from 100 Hz to approximately 4 kHz. Across this

range, the VCXO phase noise dominates that of the PLL, given the loop bandwidth of this design, which is 152

kHz. Above 4 kHz, the PLL noise dominates (inside the loop bandwidth), so it is basically the same for either

VCXO. Comparing the jitter of two VCXOs in the 100 Hz to 4 kHz band, it can be shown that VCXO “A” exhibits

jitter of 142 fs, and VCXO “B” exhibits jitter of 90 fs. The difference, 52 fs, accounts for the majority of the

average difference in RMS jitter at the clock outputs when comparing VCXOs.

The PLL configurations listed below were the same for both VCXOs/LMK040xx pair:

•

PLL1 loop filter components: C1 = 100 nF, C2 = 680 nF, R2 = 39 kΩ

PLL1 f_PD= 1 MHz, CP gain = 100 µA, loop BW = 20 Hz

PLL2 loop filter components: C1 = 0, C2 = 12 nF, R2 = 1.8 kΩ

PLL2 f_PD= 25 MHz, CP gain = 3200 µA, loop BW = 152 kHz

-80

-90

ë/óh ^!_, RMS jitter = 224 fs

-100

-110

-120

-130

-140

-150

-160

-170

ë/óh ^._, RMS jitter = 167 fs

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 33. LVDS Clock Output Phase Noise Comparison, 250 MHz

Submit Documentation Feedback

57

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

LMK04000, LMK04001, LMK04002, LMK04010

LMK04011, LMK04031, LMK04033

SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011

www.ti.com

-80

-90

ë/óh ^!_, RMS jitter = 211 fs

-100

-110

-120

-130

-140

-150

-160

-170

ë/óh ^._, RMS jitter = 171 fs

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 34. LVPECL Clock Output Phase Noise Comparison, 250 MHz

-80

-90

ë/óh ^!_, RMS jitter = 209 fs

-100

-110

-120

-130

-140

-150

-160

-170

ë/óh ^._, RMS jitter = 166 fs

100

1000

10000

100000

1000000

10000000

100000000

OFFSET (Hz)

Figure 35. LVCMOS Clock Output Phase Noise Comparison, 250 MHz

58

Submit Documentation Feedback

Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMK04002BISQ/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有 1600MHz 至 1750MHz VCO 的低噪声抖动消除器：3 路输出用于 2VPEC/LVPEC+4 路输出用于 LVCMOS \| RHS \| 48 \| -40 to 85
文件：	总66页 (文件大小：1150K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK04002BISQ/NOPB [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E